target-arm/cpu.h

   1 /*
   2  * ARM virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_ARM_H
  20 #define CPU_ARM_H
  21
  22 #define TARGET_LONG_BITS 32
  23
  24 #define ELF_MACHINE     EM_ARM
  25
  26 #define CPUArchState struct CPUARMState
  27
  28 #include "config.h"
  29 #include "qemu-common.h"
  30 #include "exec/cpu-defs.h"
  31
  32 #include "fpu/softfloat.h"
  33
  34 #define TARGET_HAS_ICE 1
  35
  36 #define EXCP_UDEF            1   /* undefined instruction */
  37 #define EXCP_SWI             2   /* software interrupt */
  38 #define EXCP_PREFETCH_ABORT  3
  39 #define EXCP_DATA_ABORT      4
  40 #define EXCP_IRQ             5
  41 #define EXCP_FIQ             6
  42 #define EXCP_BKPT            7
  43 #define EXCP_EXCEPTION_EXIT  8   /* Return from v7M exception.  */
  44 #define EXCP_KERNEL_TRAP     9   /* Jumped to kernel code page.  */
  45 #define EXCP_STREX          10
  46
  47 #define ARMV7M_EXCP_RESET   1
  48 #define ARMV7M_EXCP_NMI     2
  49 #define ARMV7M_EXCP_HARD    3
  50 #define ARMV7M_EXCP_MEM     4
  51 #define ARMV7M_EXCP_BUS     5
  52 #define ARMV7M_EXCP_USAGE   6
  53 #define ARMV7M_EXCP_SVC     11
  54 #define ARMV7M_EXCP_DEBUG   12
  55 #define ARMV7M_EXCP_PENDSV  14
  56 #define ARMV7M_EXCP_SYSTICK 15
  57
  58 /* ARM-specific interrupt pending bits.  */
  59 #define CPU_INTERRUPT_FIQ   CPU_INTERRUPT_TGT_EXT_1
  60
  61 /* Meanings of the ARMCPU object's two inbound GPIO lines */
  62 #define ARM_CPU_IRQ 0
  63 #define ARM_CPU_FIQ 1
  64
  65 typedef void ARMWriteCPFunc(void *opaque, int cp_info,
  66                             int srcreg, int operand, uint32_t value);
  67 typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
  68                                int dstreg, int operand);
  69
  70 struct arm_boot_info;
  71
  72 #define NB_MMU_MODES 2
  73
  74 /* We currently assume float and double are IEEE single and double
  75    precision respectively.
  76    Doing runtime conversions is tricky because VFP registers may contain
  77    integer values (eg. as the result of a FTOSI instruction).
  78    s<2n> maps to the least significant half of d<n>
  79    s<2n+1> maps to the most significant half of d<n>
  80  */
  81
  82 /* CPU state for each instance of a generic timer (in cp15 c14) */
  83 typedef struct ARMGenericTimer {
  84     uint64_t cval; /* Timer CompareValue register */
  85     uint32_t ctl; /* Timer Control register */
  86 } ARMGenericTimer;
  87
  88 #define GTIMER_PHYS 0
  89 #define GTIMER_VIRT 1
  90 #define NUM_GTIMERS 2
  91
  92 /* Scale factor for generic timers, ie number of ns per tick.
  93  * This gives a 62.5MHz timer.
  94  */
  95 #define GTIMER_SCALE 16
  96
  97 typedef struct CPUARMState {
  98     /* Regs for current mode.  */
  99     uint32_t regs[16];
 100     /* Frequently accessed CPSR bits are stored separately for efficiency.
 101        This contains all the other bits.  Use cpsr_{read,write} to access
 102        the whole CPSR.  */
 103     uint32_t uncached_cpsr;
 104     uint32_t spsr;
 105
 106     /* Banked registers.  */
 107     uint32_t banked_spsr[6];
 108     uint32_t banked_r13[6];
 109     uint32_t banked_r14[6];
 110
 111     /* These hold r8-r12.  */
 112     uint32_t usr_regs[5];
 113     uint32_t fiq_regs[5];
 114
 115     /* cpsr flag cache for faster execution */
 116     uint32_t CF; /* 0 or 1 */
 117     uint32_t VF; /* V is the bit 31. All other bits are undefined */
 118     uint32_t NF; /* N is bit 31. All other bits are undefined.  */
 119     uint32_t ZF; /* Z set if zero.  */
 120     uint32_t QF; /* 0 or 1 */
 121     uint32_t GE; /* cpsr[19:16] */
 122     uint32_t thumb; /* cpsr[5]. 0 = arm mode, 1 = thumb mode. */
 123     uint32_t condexec_bits; /* IT bits.  cpsr[15:10,26:25].  */
 124
 125     /* System control coprocessor (cp15) */
 126     struct {
 127         uint32_t c0_cpuid;
 128         uint32_t c0_cssel; /* Cache size selection.  */
 129         uint32_t c1_sys; /* System control register.  */
 130         uint32_t c1_coproc; /* Coprocessor access register.  */
 131         uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
 132         uint32_t c1_scr; /* secure config register.  */
 133         uint32_t c2_base0; /* MMU translation table base 0.  */
 134         uint32_t c2_base0_hi; /* MMU translation table base 0, high 32 bits */
 135         uint32_t c2_base1; /* MMU translation table base 0.  */
 136         uint32_t c2_base1_hi; /* MMU translation table base 1, high 32 bits */
 137         uint32_t c2_control; /* MMU translation table base control.  */
 138         uint32_t c2_mask; /* MMU translation table base selection mask.  */
 139         uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
 140         uint32_t c2_data; /* MPU data cachable bits.  */
 141         uint32_t c2_insn; /* MPU instruction cachable bits.  */
 142         uint32_t c3; /* MMU domain access control register
 143                         MPU write buffer control.  */
 144         uint32_t c5_insn; /* Fault status registers.  */
 145         uint32_t c5_data;
 146         uint32_t c6_region[8]; /* MPU base/size registers.  */
 147         uint32_t c6_insn; /* Fault address registers.  */
 148         uint32_t c6_data;
 149         uint32_t c7_par;  /* Translation result. */
 150         uint32_t c7_par_hi;  /* Translation result, high 32 bits */
 151         uint32_t c9_insn; /* Cache lockdown registers.  */
 152         uint32_t c9_data;
 153         uint32_t c9_pmcr; /* performance monitor control register */
 154         uint32_t c9_pmcnten; /* perf monitor counter enables */
 155         uint32_t c9_pmovsr; /* perf monitor overflow status */
 156         uint32_t c9_pmxevtyper; /* perf monitor event type */
 157         uint32_t c9_pmuserenr; /* perf monitor user enable */
 158         uint32_t c9_pminten; /* perf monitor interrupt enables */
 159         uint32_t c13_fcse; /* FCSE PID.  */
 160         uint32_t c13_context; /* Context ID.  */
 161         uint32_t c13_tls1; /* User RW Thread register.  */
 162         uint32_t c13_tls2; /* User RO Thread register.  */
 163         uint32_t c13_tls3; /* Privileged Thread register.  */
 164         uint32_t c14_cntfrq; /* Counter Frequency register */
 165         uint32_t c14_cntkctl; /* Timer Control register */
 166         ARMGenericTimer c14_timer[NUM_GTIMERS];
 167         uint32_t c15_cpar; /* XScale Coprocessor Access Register */
 168         uint32_t c15_ticonfig; /* TI925T configuration byte.  */
 169         uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
 170         uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
 171         uint32_t c15_threadid; /* TI debugger thread-ID.  */
 172         uint32_t c15_config_base_address; /* SCU base address.  */
 173         uint32_t c15_diagnostic; /* diagnostic register */
 174         uint32_t c15_power_diagnostic;
 175         uint32_t c15_power_control; /* power control */
 176     } cp15;
 177
 178     struct {
 179         uint32_t other_sp;
 180         uint32_t vecbase;
 181         uint32_t basepri;
 182         uint32_t control;
 183         int current_sp;
 184         int exception;
 185         int pending_exception;
 186     } v7m;
 187
 188     /* Thumb-2 EE state.  */
 189     uint32_t teecr;
 190     uint32_t teehbr;
 191
 192     /* VFP coprocessor state.  */
 193     struct {
 194         float64 regs[32];
 195
 196         uint32_t xregs[16];
 197         /* We store these fpcsr fields separately for convenience.  */
 198         int vec_len;
 199         int vec_stride;
 200
 201         /* scratch space when Tn are not sufficient.  */
 202         uint32_t scratch[8];
 203
 204         /* fp_status is the "normal" fp status. standard_fp_status retains
 205          * values corresponding to the ARM "Standard FPSCR Value", ie
 206          * default-NaN, flush-to-zero, round-to-nearest and is used by
 207          * any operations (generally Neon) which the architecture defines
 208          * as controlled by the standard FPSCR value rather than the FPSCR.
 209          *
 210          * To avoid having to transfer exception bits around, we simply
 211          * say that the FPSCR cumulative exception flags are the logical
 212          * OR of the flags in the two fp statuses. This relies on the
 213          * only thing which needs to read the exception flags being
 214          * an explicit FPSCR read.
 215          */
 216         float_status fp_status;
 217         float_status standard_fp_status;
 218     } vfp;
 219     uint32_t exclusive_addr;
 220     uint32_t exclusive_val;
 221     uint32_t exclusive_high;
 222 #if defined(CONFIG_USER_ONLY)
 223     uint32_t exclusive_test;
 224     uint32_t exclusive_info;
 225 #endif
 226
 227     /* iwMMXt coprocessor state.  */
 228     struct {
 229         uint64_t regs[16];
 230         uint64_t val;
 231
 232         uint32_t cregs[16];
 233     } iwmmxt;
 234
 235     /* For mixed endian mode.  */
 236     bool bswap_code;
 237
 238 #if defined(CONFIG_USER_ONLY)
 239     /* For usermode syscall translation.  */
 240     int eabi;
 241 #endif
 242
 243     CPU_COMMON
 244
 245     /* These fields after the common ones so they are preserved on reset.  */
 246
 247     /* Internal CPU feature flags.  */
 248     uint64_t features;
 249
 250     void *nvic;
 251     const struct arm_boot_info *boot_info;
 252 } CPUARMState;
 253
 254 #include "cpu-qom.h"
 255
 256 ARMCPU *cpu_arm_init(const char *cpu_model);
 257 void arm_translate_init(void);
 258 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
 259 int cpu_arm_exec(CPUARMState *s);
 260 int bank_number(int mode);
 261 void switch_mode(CPUARMState *, int);
 262 uint32_t do_arm_semihosting(CPUARMState *env);
 263
 264 /* you can call this signal handler from your SIGBUS and SIGSEGV
 265    signal handlers to inform the virtual CPU of exceptions. non zero
 266    is returned if the signal was handled by the virtual CPU.  */
 267 int cpu_arm_signal_handler(int host_signum, void *pinfo,
 268                            void *puc);
 269 int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
 270                               int mmu_idx);
 271 #define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
 272
 273 #define CPSR_M (0x1f)
 274 #define CPSR_T (1 << 5)
 275 #define CPSR_F (1 << 6)
 276 #define CPSR_I (1 << 7)
 277 #define CPSR_A (1 << 8)
 278 #define CPSR_E (1 << 9)
 279 #define CPSR_IT_2_7 (0xfc00)
 280 #define CPSR_GE (0xf << 16)
 281 #define CPSR_RESERVED (0xf << 20)
 282 #define CPSR_J (1 << 24)
 283 #define CPSR_IT_0_1 (3 << 25)
 284 #define CPSR_Q (1 << 27)
 285 #define CPSR_V (1 << 28)
 286 #define CPSR_C (1 << 29)
 287 #define CPSR_Z (1 << 30)
 288 #define CPSR_N (1 << 31)
 289 #define CPSR_NZCV (CPSR_N | CPSR_Z | CPSR_C | CPSR_V)
 290
 291 #define CPSR_IT (CPSR_IT_0_1 | CPSR_IT_2_7)
 292 #define CACHED_CPSR_BITS (CPSR_T | CPSR_GE | CPSR_IT | CPSR_Q | CPSR_NZCV)
 293 /* Bits writable in user mode.  */
 294 #define CPSR_USER (CPSR_NZCV | CPSR_Q | CPSR_GE)
 295 /* Execution state bits.  MRS read as zero, MSR writes ignored.  */
 296 #define CPSR_EXEC (CPSR_T | CPSR_IT | CPSR_J)
 297
 298 /* Return the current CPSR value.  */
 299 uint32_t cpsr_read(CPUARMState *env);
 300 /* Set the CPSR.  Note that some bits of mask must be all-set or all-clear.  */
 301 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask);
 302
 303 /* Return the current xPSR value.  */
 304 static inline uint32_t xpsr_read(CPUARMState *env)
 305 {
 306     int ZF;
 307     ZF = (env->ZF == 0);
 308     return (env->NF & 0x80000000) | (ZF << 30)
 309         | (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
 310         | (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
 311         | ((env->condexec_bits & 0xfc) << 8)
 312         | env->v7m.exception;
 313 }
 314
 315 /* Set the xPSR.  Note that some bits of mask must be all-set or all-clear.  */
 316 static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
 317 {
 318     if (mask & CPSR_NZCV) {
 319         env->ZF = (~val) & CPSR_Z;
 320         env->NF = val;
 321         env->CF = (val >> 29) & 1;
 322         env->VF = (val << 3) & 0x80000000;
 323     }
 324     if (mask & CPSR_Q)
 325         env->QF = ((val & CPSR_Q) != 0);
 326     if (mask & (1 << 24))
 327         env->thumb = ((val & (1 << 24)) != 0);
 328     if (mask & CPSR_IT_0_1) {
 329         env->condexec_bits &= ~3;
 330         env->condexec_bits |= (val >> 25) & 3;
 331     }
 332     if (mask & CPSR_IT_2_7) {
 333         env->condexec_bits &= 3;
 334         env->condexec_bits |= (val >> 8) & 0xfc;
 335     }
 336     if (mask & 0x1ff) {
 337         env->v7m.exception = val & 0x1ff;
 338     }
 339 }
 340
 341 /* Return the current FPSCR value.  */
 342 uint32_t vfp_get_fpscr(CPUARMState *env);
 343 void vfp_set_fpscr(CPUARMState *env, uint32_t val);
 344
 345 enum arm_cpu_mode {
 346   ARM_CPU_MODE_USR = 0x10,
 347   ARM_CPU_MODE_FIQ = 0x11,
 348   ARM_CPU_MODE_IRQ = 0x12,
 349   ARM_CPU_MODE_SVC = 0x13,
 350   ARM_CPU_MODE_ABT = 0x17,
 351   ARM_CPU_MODE_UND = 0x1b,
 352   ARM_CPU_MODE_SYS = 0x1f
 353 };
 354
 355 /* VFP system registers.  */
 356 #define ARM_VFP_FPSID   0
 357 #define ARM_VFP_FPSCR   1
 358 #define ARM_VFP_MVFR1   6
 359 #define ARM_VFP_MVFR0   7
 360 #define ARM_VFP_FPEXC   8
 361 #define ARM_VFP_FPINST  9
 362 #define ARM_VFP_FPINST2 10
 363
 364 /* iwMMXt coprocessor control registers.  */
 365 #define ARM_IWMMXT_wCID         0
 366 #define ARM_IWMMXT_wCon         1
 367 #define ARM_IWMMXT_wCSSF        2
 368 #define ARM_IWMMXT_wCASF        3
 369 #define ARM_IWMMXT_wCGR0        8
 370 #define ARM_IWMMXT_wCGR1        9
 371 #define ARM_IWMMXT_wCGR2        10
 372 #define ARM_IWMMXT_wCGR3        11
 373
 374 /* If adding a feature bit which corresponds to a Linux ELF
 375  * HWCAP bit, remember to update the feature-bit-to-hwcap
 376  * mapping in linux-user/elfload.c:get_elf_hwcap().
 377  */
 378 enum arm_features {
 379     ARM_FEATURE_VFP,
 380     ARM_FEATURE_AUXCR,  /* ARM1026 Auxiliary control register.  */
 381     ARM_FEATURE_XSCALE, /* Intel XScale extensions.  */
 382     ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension.  */
 383     ARM_FEATURE_V6,
 384     ARM_FEATURE_V6K,
 385     ARM_FEATURE_V7,
 386     ARM_FEATURE_THUMB2,
 387     ARM_FEATURE_MPU,    /* Only has Memory Protection Unit, not full MMU.  */
 388     ARM_FEATURE_VFP3,
 389     ARM_FEATURE_VFP_FP16,
 390     ARM_FEATURE_NEON,
 391     ARM_FEATURE_THUMB_DIV, /* divide supported in Thumb encoding */
 392     ARM_FEATURE_M, /* Microcontroller profile.  */
 393     ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
 394     ARM_FEATURE_THUMB2EE,
 395     ARM_FEATURE_V7MP,    /* v7 Multiprocessing Extensions */
 396     ARM_FEATURE_V4T,
 397     ARM_FEATURE_V5,
 398     ARM_FEATURE_STRONGARM,
 399     ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
 400     ARM_FEATURE_ARM_DIV, /* divide supported in ARM encoding */
 401     ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */
 402     ARM_FEATURE_GENERIC_TIMER,
 403     ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
 404     ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
 405     ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
 406     ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
 407     ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
 408     ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
 409     ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
 410     ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
 411     ARM_FEATURE_V8,
 412 };
 413
 414 static inline int arm_feature(CPUARMState *env, int feature)
 415 {
 416     return (env->features & (1ULL << feature)) != 0;
 417 }
 418
 419 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 420
 421 /* Interface between CPU and Interrupt controller.  */
 422 void armv7m_nvic_set_pending(void *opaque, int irq);
 423 int armv7m_nvic_acknowledge_irq(void *opaque);
 424 void armv7m_nvic_complete_irq(void *opaque, int irq);
 425
 426 /* Interface for defining coprocessor registers.
 427  * Registers are defined in tables of arm_cp_reginfo structs
 428  * which are passed to define_arm_cp_regs().
 429  */
 430
 431 /* When looking up a coprocessor register we look for it
 432  * via an integer which encodes all of:
 433  *  coprocessor number
 434  *  Crn, Crm, opc1, opc2 fields
 435  *  32 or 64 bit register (ie is it accessed via MRC/MCR
 436  *    or via MRRC/MCRR?)
 437  * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field.
 438  * (In this case crn and opc2 should be zero.)
 439  */
 440 #define ENCODE_CP_REG(cp, is64, crn, crm, opc1, opc2)   \
 441     (((cp) << 16) | ((is64) << 15) | ((crn) << 11) |    \
 442      ((crm) << 7) | ((opc1) << 3) | (opc2))
 443
 444 /* Note that these must line up with the KVM/ARM register
 445  * ID field definitions (kvm.c will check this, but we
 446  * can't just use the KVM defines here as the kvm headers
 447  * are unavailable to non-KVM-specific files)
 448  */
 449 #define CP_REG_SIZE_SHIFT 52
 450 #define CP_REG_SIZE_MASK       0x00f0000000000000ULL
 451 #define CP_REG_SIZE_U32        0x0020000000000000ULL
 452 #define CP_REG_SIZE_U64        0x0030000000000000ULL
 453 #define CP_REG_ARM             0x4000000000000000ULL
 454
 455 /* Convert a full 64 bit KVM register ID to the truncated 32 bit
 456  * version used as a key for the coprocessor register hashtable
 457  */
 458 static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid)
 459 {
 460     uint32_t cpregid = kvmid;
 461     if ((kvmid & CP_REG_SIZE_MASK) == CP_REG_SIZE_U64) {
 462         cpregid |= (1 << 15);
 463     }
 464     return cpregid;
 465 }
 466
 467 /* Convert a truncated 32 bit hashtable key into the full
 468  * 64 bit KVM register ID.
 469  */
 470 static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
 471 {
 472     uint64_t kvmid = cpregid & ~(1 << 15);
 473     if (cpregid & (1 << 15)) {
 474         kvmid |= CP_REG_SIZE_U64 | CP_REG_ARM;
 475     } else {
 476         kvmid |= CP_REG_SIZE_U32 | CP_REG_ARM;
 477     }
 478     return kvmid;
 479 }
 480
 481 /* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
 482  * special-behaviour cp reg and bits [15..8] indicate what behaviour
 483  * it has. Otherwise it is a simple cp reg, where CONST indicates that
 484  * TCG can assume the value to be constant (ie load at translate time)
 485  * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
 486  * indicates that the TB should not be ended after a write to this register
 487  * (the default is that the TB ends after cp writes). OVERRIDE permits
 488  * a register definition to override a previous definition for the
 489  * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the
 490  * old must have the OVERRIDE bit set.
 491  * NO_MIGRATE indicates that this register should be ignored for migration;
 492  * (eg because any state is accessed via some other coprocessor register).
 493  * IO indicates that this register does I/O and therefore its accesses
 494  * need to be surrounded by gen_io_start()/gen_io_end(). In particular,
 495  * registers which implement clocks or timers require this.
 496  */
 497 #define ARM_CP_SPECIAL 1
 498 #define ARM_CP_CONST 2
 499 #define ARM_CP_64BIT 4
 500 #define ARM_CP_SUPPRESS_TB_END 8
 501 #define ARM_CP_OVERRIDE 16
 502 #define ARM_CP_NO_MIGRATE 32
 503 #define ARM_CP_IO 64
 504 #define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
 505 #define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
 506 #define ARM_LAST_SPECIAL ARM_CP_WFI
 507 /* Used only as a terminator for ARMCPRegInfo lists */
 508 #define ARM_CP_SENTINEL 0xffff
 509 /* Mask of only the flag bits in a type field */
 510 #define ARM_CP_FLAG_MASK 0x7f
 511
 512 /* Return true if cptype is a valid type field. This is used to try to
 513  * catch errors where the sentinel has been accidentally left off the end
 514  * of a list of registers.
 515  */
 516 static inline bool cptype_valid(int cptype)
 517 {
 518     return ((cptype & ~ARM_CP_FLAG_MASK) == 0)
 519         || ((cptype & ARM_CP_SPECIAL) &&
 520             ((cptype & ~ARM_CP_FLAG_MASK) <= ARM_LAST_SPECIAL));
 521 }
 522
 523 /* Access rights:
 524  * We define bits for Read and Write access for what rev C of the v7-AR ARM ARM
 525  * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and
 526  * PL2 (hyp). The other level which has Read and Write bits is Secure PL1
 527  * (ie any of the privileged modes in Secure state, or Monitor mode).
 528  * If a register is accessible in one privilege level it's always accessible
 529  * in higher privilege levels too. Since "Secure PL1" also follows this rule
 530  * (ie anything visible in PL2 is visible in S-PL1, some things are only
 531  * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the
 532  * terminology a little and call this PL3.
 533  *
 534  * If access permissions for a register are more complex than can be
 535  * described with these bits, then use a laxer set of restrictions, and
 536  * do the more restrictive/complex check inside a helper function.
 537  */
 538 #define PL3_R 0x80
 539 #define PL3_W 0x40
 540 #define PL2_R (0x20 | PL3_R)
 541 #define PL2_W (0x10 | PL3_W)
 542 #define PL1_R (0x08 | PL2_R)
 543 #define PL1_W (0x04 | PL2_W)
 544 #define PL0_R (0x02 | PL1_R)
 545 #define PL0_W (0x01 | PL1_W)
 546
 547 #define PL3_RW (PL3_R | PL3_W)
 548 #define PL2_RW (PL2_R | PL2_W)
 549 #define PL1_RW (PL1_R | PL1_W)
 550 #define PL0_RW (PL0_R | PL0_W)
 551
 552 static inline int arm_current_pl(CPUARMState *env)
 553 {
 554     if ((env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_USR) {
 555         return 0;
 556     }
 557     /* We don't currently implement the Virtualization or TrustZone
 558      * extensions, so PL2 and PL3 don't exist for us.
 559      */
 560     return 1;
 561 }
 562
 563 typedef struct ARMCPRegInfo ARMCPRegInfo;
 564
 565 /* Access functions for coprocessor registers. These should return
 566  * 0 on success, or one of the EXCP_* constants if access should cause
 567  * an exception (in which case *value is not written).
 568  */
 569 typedef int CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque,
 570                      uint64_t *value);
 571 typedef int CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque,
 572                       uint64_t value);
 573 /* Hook function for register reset */
 574 typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque);
 575
 576 #define CP_ANY 0xff
 577
 578 /* Definition of an ARM coprocessor register */
 579 struct ARMCPRegInfo {
 580     /* Name of register (useful mainly for debugging, need not be unique) */
 581     const char *name;
 582     /* Location of register: coprocessor number and (crn,crm,opc1,opc2)
 583      * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a
 584      * 'wildcard' field -- any value of that field in the MRC/MCR insn
 585      * will be decoded to this register. The register read and write
 586      * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2
 587      * used by the program, so it is possible to register a wildcard and
 588      * then behave differently on read/write if necessary.
 589      * For 64 bit registers, only crm and opc1 are relevant; crn and opc2
 590      * must both be zero.
 591      */
 592     uint8_t cp;
 593     uint8_t crn;
 594     uint8_t crm;
 595     uint8_t opc1;
 596     uint8_t opc2;
 597     /* Register type: ARM_CP_* bits/values */
 598     int type;
 599     /* Access rights: PL*_[RW] */
 600     int access;
 601     /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when
 602      * this register was defined: can be used to hand data through to the
 603      * register read/write functions, since they are passed the ARMCPRegInfo*.
 604      */
 605     void *opaque;
 606     /* Value of this register, if it is ARM_CP_CONST. Otherwise, if
 607      * fieldoffset is non-zero, the reset value of the register.
 608      */
 609     uint64_t resetvalue;
 610     /* Offset of the field in CPUARMState for this register. This is not
 611      * needed if either:
 612      *  1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs
 613      *  2. both readfn and writefn are specified
 614      */
 615     ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */
 616     /* Function for handling reads of this register. If NULL, then reads
 617      * will be done by loading from the offset into CPUARMState specified
 618      * by fieldoffset.
 619      */
 620     CPReadFn *readfn;
 621     /* Function for handling writes of this register. If NULL, then writes
 622      * will be done by writing to the offset into CPUARMState specified
 623      * by fieldoffset.
 624      */
 625     CPWriteFn *writefn;
 626     /* Function for doing a "raw" read; used when we need to copy
 627      * coprocessor state to the kernel for KVM or out for
 628      * migration. This only needs to be provided if there is also a
 629      * readfn and it makes an access permission check.
 630      */
 631     CPReadFn *raw_readfn;
 632     /* Function for doing a "raw" write; used when we need to copy KVM
 633      * kernel coprocessor state into userspace, or for inbound
 634      * migration. This only needs to be provided if there is also a
 635      * writefn and it makes an access permission check or masks out
 636      * "unwritable" bits or has write-one-to-clear or similar behaviour.
 637      */
 638     CPWriteFn *raw_writefn;
 639     /* Function for resetting the register. If NULL, then reset will be done
 640      * by writing resetvalue to the field specified in fieldoffset. If
 641      * fieldoffset is 0 then no reset will be done.
 642      */
 643     CPResetFn *resetfn;
 644 };
 645
 646 /* Macros which are lvalues for the field in CPUARMState for the
 647  * ARMCPRegInfo *ri.
 648  */
 649 #define CPREG_FIELD32(env, ri) \
 650     (*(uint32_t *)((char *)(env) + (ri)->fieldoffset))
 651 #define CPREG_FIELD64(env, ri) \
 652     (*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
 653
 654 #define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
 655
 656 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
 657                                     const ARMCPRegInfo *regs, void *opaque);
 658 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
 659                                        const ARMCPRegInfo *regs, void *opaque);
 660 static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *regs)
 661 {
 662     define_arm_cp_regs_with_opaque(cpu, regs, 0);
 663 }
 664 static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs)
 665 {
 666     define_one_arm_cp_reg_with_opaque(cpu, regs, 0);
 667 }
 668 const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp);
 669
 670 /* CPWriteFn that can be used to implement writes-ignored behaviour */
 671 int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
 672                         uint64_t value);
 673 /* CPReadFn that can be used for read-as-zero behaviour */
 674 int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value);
 675
 676 static inline bool cp_access_ok(CPUARMState *env,
 677                                 const ARMCPRegInfo *ri, int isread)
 678 {
 679     return (ri->access >> ((arm_current_pl(env) * 2) + isread)) & 1;
 680 }
 681
 682 /**
 683  * write_list_to_cpustate
 684  * @cpu: ARMCPU
 685  *
 686  * For each register listed in the ARMCPU cpreg_indexes list, write
 687  * its value from the cpreg_values list into the ARMCPUState structure.
 688  * This updates TCG's working data structures from KVM data or
 689  * from incoming migration state.
 690  *
 691  * Returns: true if all register values were updated correctly,
 692  * false if some register was unknown or could not be written.
 693  * Note that we do not stop early on failure -- we will attempt
 694  * writing all registers in the list.
 695  */
 696 bool write_list_to_cpustate(ARMCPU *cpu);
 697
 698 /**
 699  * write_cpustate_to_list:
 700  * @cpu: ARMCPU
 701  *
 702  * For each register listed in the ARMCPU cpreg_indexes list, write
 703  * its value from the ARMCPUState structure into the cpreg_values list.
 704  * This is used to copy info from TCG's working data structures into
 705  * KVM or for outbound migration.
 706  *
 707  * Returns: true if all register values were read correctly,
 708  * false if some register was unknown or could not be read.
 709  * Note that we do not stop early on failure -- we will attempt
 710  * reading all registers in the list.
 711  */
 712 bool write_cpustate_to_list(ARMCPU *cpu);
 713
 714 /* Does the core conform to the the "MicroController" profile. e.g. Cortex-M3.
 715    Note the M in older cores (eg. ARM7TDMI) stands for Multiply. These are
 716    conventional cores (ie. Application or Realtime profile).  */
 717
 718 #define IS_M(env) arm_feature(env, ARM_FEATURE_M)
 719
 720 #define ARM_CPUID_TI915T      0x54029152
 721 #define ARM_CPUID_TI925T      0x54029252
 722
 723 #if defined(CONFIG_USER_ONLY)
 724 #define TARGET_PAGE_BITS 12
 725 #else
 726 /* The ARM MMU allows 1k pages.  */
 727 /* ??? Linux doesn't actually use these, and they're deprecated in recent
 728    architecture revisions.  Maybe a configure option to disable them.  */
 729 #define TARGET_PAGE_BITS 10
 730 #endif
 731
 732 #define TARGET_PHYS_ADDR_SPACE_BITS 40
 733 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 734
 735 static inline CPUARMState *cpu_init(const char *cpu_model)
 736 {
 737     ARMCPU *cpu = cpu_arm_init(cpu_model);
 738     if (cpu) {
 739         return &cpu->env;
 740     }
 741     return NULL;
 742 }
 743
 744 #define cpu_exec cpu_arm_exec
 745 #define cpu_gen_code cpu_arm_gen_code
 746 #define cpu_signal_handler cpu_arm_signal_handler
 747 #define cpu_list arm_cpu_list
 748
 749 /* MMU modes definitions */
 750 #define MMU_MODE0_SUFFIX _kernel
 751 #define MMU_MODE1_SUFFIX _user
 752 #define MMU_USER_IDX 1
 753 static inline int cpu_mmu_index (CPUARMState *env)
 754 {
 755     return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
 756 }
 757
 758 #include "exec/cpu-all.h"
 759
 760 /* Bit usage in the TB flags field: */
 761 #define ARM_TBFLAG_THUMB_SHIFT      0
 762 #define ARM_TBFLAG_THUMB_MASK       (1 << ARM_TBFLAG_THUMB_SHIFT)
 763 #define ARM_TBFLAG_VECLEN_SHIFT     1
 764 #define ARM_TBFLAG_VECLEN_MASK      (0x7 << ARM_TBFLAG_VECLEN_SHIFT)
 765 #define ARM_TBFLAG_VECSTRIDE_SHIFT  4
 766 #define ARM_TBFLAG_VECSTRIDE_MASK   (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT)
 767 #define ARM_TBFLAG_PRIV_SHIFT       6
 768 #define ARM_TBFLAG_PRIV_MASK        (1 << ARM_TBFLAG_PRIV_SHIFT)
 769 #define ARM_TBFLAG_VFPEN_SHIFT      7
 770 #define ARM_TBFLAG_VFPEN_MASK       (1 << ARM_TBFLAG_VFPEN_SHIFT)
 771 #define ARM_TBFLAG_CONDEXEC_SHIFT   8
 772 #define ARM_TBFLAG_CONDEXEC_MASK    (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
 773 #define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
 774 #define ARM_TBFLAG_BSWAP_CODE_MASK  (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
 775 /* Bits 31..17 are currently unused. */
 776
 777 /* some convenience accessor macros */
 778 #define ARM_TBFLAG_THUMB(F) \
 779     (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT)
 780 #define ARM_TBFLAG_VECLEN(F) \
 781     (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT)
 782 #define ARM_TBFLAG_VECSTRIDE(F) \
 783     (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT)
 784 #define ARM_TBFLAG_PRIV(F) \
 785     (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT)
 786 #define ARM_TBFLAG_VFPEN(F) \
 787     (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT)
 788 #define ARM_TBFLAG_CONDEXEC(F) \
 789     (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
 790 #define ARM_TBFLAG_BSWAP_CODE(F) \
 791     (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
 792
 793 static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
 794                                         target_ulong *cs_base, int *flags)
 795 {
 796     int privmode;
 797     *pc = env->regs[15];
 798     *cs_base = 0;
 799     *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
 800         | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
 801         | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
 802         | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
 803         | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT);
 804     if (arm_feature(env, ARM_FEATURE_M)) {
 805         privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
 806     } else {
 807         privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
 808     }
 809     if (privmode) {
 810         *flags |= ARM_TBFLAG_PRIV_MASK;
 811     }
 812     if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
 813         *flags |= ARM_TBFLAG_VFPEN_MASK;
 814     }
 815 }
 816
 817 static inline bool cpu_has_work(CPUState *cpu)
 818 {
 819     return cpu->interrupt_request &
 820         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
 821 }
 822
 823 #include "exec/exec-all.h"
 824
 825 /* Load an instruction and return it in the standard little-endian order */
 826 static inline uint32_t arm_ldl_code(CPUARMState *env, uint32_t addr,
 827                                     bool do_swap)
 828 {
 829     uint32_t insn = cpu_ldl_code(env, addr);
 830     if (do_swap) {
 831         return bswap32(insn);
 832     }
 833     return insn;
 834 }
 835
 836 /* Ditto, for a halfword (Thumb) instruction */
 837 static inline uint16_t arm_lduw_code(CPUARMState *env, uint32_t addr,
 838                                      bool do_swap)
 839 {
 840     uint16_t insn = cpu_lduw_code(env, addr);
 841     if (do_swap) {
 842         return bswap16(insn);
 843     }
 844     return insn;
 845 }
 846
 847 #endif