hw/sd/milkymist-memcard.c

   1 /*
   2  *  QEMU model of the Milkymist SD Card Controller.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   http://milkymist.walle.cc/socdoc/memcard.pdf
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "qemu/log.h"
  26 #include "qemu/module.h"
  27 #include "hw/sysbus.h"
  28 #include "migration/vmstate.h"
  29 #include "trace.h"
  30 #include "qapi/error.h"
  31 #include "sysemu/block-backend.h"
  32 #include "sysemu/blockdev.h"
  33 #include "hw/qdev-properties.h"
  34 #include "hw/sd/sd.h"
  35 #include "qom/object.h"
  36
  37 enum {
  38     ENABLE_CMD_TX   = (1<<0),
  39     ENABLE_CMD_RX   = (1<<1),
  40     ENABLE_DAT_TX   = (1<<2),
  41     ENABLE_DAT_RX   = (1<<3),
  42 };
  43
  44 enum {
  45     PENDING_CMD_TX   = (1<<0),
  46     PENDING_CMD_RX   = (1<<1),
  47     PENDING_DAT_TX   = (1<<2),
  48     PENDING_DAT_RX   = (1<<3),
  49 };
  50
  51 enum {
  52     START_CMD_TX    = (1<<0),
  53     START_DAT_RX    = (1<<1),
  54 };
  55
  56 enum {
  57     R_CLK2XDIV = 0,
  58     R_ENABLE,
  59     R_PENDING,
  60     R_START,
  61     R_CMD,
  62     R_DAT,
  63     R_MAX
  64 };
  65
  66 #define TYPE_MILKYMIST_MEMCARD "milkymist-memcard"
  67 OBJECT_DECLARE_SIMPLE_TYPE(MilkymistMemcardState, MILKYMIST_MEMCARD)
  68
  69 #define TYPE_MILKYMIST_SDBUS "milkymist-sdbus"
  70
  71 struct MilkymistMemcardState {
  72     SysBusDevice parent_obj;
  73
  74     MemoryRegion regs_region;
  75     SDBus sdbus;
  76
  77     int command_write_ptr;
  78     int response_read_ptr;
  79     int response_len;
  80     int ignore_next_cmd;
  81     int enabled;
  82     uint8_t command[6];
  83     uint8_t response[17];
  84     uint32_t regs[R_MAX];
  85 };
  86
  87 static void update_pending_bits(MilkymistMemcardState *s)
  88 {
  89     /* transmits are instantaneous, thus tx pending bits are never set */
  90     s->regs[R_PENDING] = 0;
  91     /* if rx is enabled the corresponding pending bits are always set */
  92     if (s->regs[R_ENABLE] & ENABLE_CMD_RX) {
  93         s->regs[R_PENDING] |= PENDING_CMD_RX;
  94     }
  95     if (s->regs[R_ENABLE] & ENABLE_DAT_RX) {
  96         s->regs[R_PENDING] |= PENDING_DAT_RX;
  97     }
  98 }
  99
 100 static void memcard_sd_command(MilkymistMemcardState *s)
 101 {
 102     SDRequest req;
 103
 104     req.cmd = s->command[0] & 0x3f;
 105     req.arg = ldl_be_p(s->command + 1);
 106     req.crc = s->command[5];
 107
 108     s->response[0] = req.cmd;
 109     s->response_len = sdbus_do_command(&s->sdbus, &req, s->response + 1);
 110     s->response_read_ptr = 0;
 111
 112     if (s->response_len == 16) {
 113         /* R2 response */
 114         s->response[0] = 0x3f;
 115         s->response_len += 1;
 116     } else if (s->response_len == 4) {
 117         /* no crc calculation, insert dummy byte */
 118         s->response[5] = 0;
 119         s->response_len += 2;
 120     }
 121
 122     if (req.cmd == 0) {
 123         /* next write is a dummy byte to clock the initialization of the sd
 124          * card */
 125         s->ignore_next_cmd = 1;
 126     }
 127 }
 128
 129 static uint64_t memcard_read(void *opaque, hwaddr addr,
 130                              unsigned size)
 131 {
 132     MilkymistMemcardState *s = opaque;
 133     uint32_t r = 0;
 134
 135     addr >>= 2;
 136     switch (addr) {
 137     case R_CMD:
 138         if (!s->enabled) {
 139             r = 0xff;
 140         } else {
 141             r = s->response[s->response_read_ptr++];
 142             if (s->response_read_ptr > s->response_len) {
 143                 qemu_log_mask(LOG_GUEST_ERROR, "milkymist_memcard: "
 144                               "read more cmd bytes than available: clipping\n");
 145                 s->response_read_ptr = 0;
 146             }
 147         }
 148         break;
 149     case R_DAT:
 150         if (!s->enabled) {
 151             r = 0xffffffff;
 152         } else {
 153             sdbus_read_data(&s->sdbus, &r, sizeof(r));
 154             be32_to_cpus(&r);
 155         }
 156         break;
 157     case R_CLK2XDIV:
 158     case R_ENABLE:
 159     case R_PENDING:
 160     case R_START:
 161         r = s->regs[addr];
 162         break;
 163
 164     default:
 165         qemu_log_mask(LOG_UNIMP, "milkymist_memcard: "
 166                       "read access to unknown register 0x%" HWADDR_PRIx "\n",
 167                       addr << 2);
 168         break;
 169     }
 170
 171     trace_milkymist_memcard_memory_read(addr << 2, r);
 172
 173     return r;
 174 }
 175
 176 static void memcard_write(void *opaque, hwaddr addr, uint64_t value,
 177                           unsigned size)
 178 {
 179     MilkymistMemcardState *s = opaque;
 180     uint32_t val32;
 181
 182     trace_milkymist_memcard_memory_write(addr, value);
 183
 184     addr >>= 2;
 185     switch (addr) {
 186     case R_PENDING:
 187         /* clear rx pending bits */
 188         s->regs[R_PENDING] &= ~(value & (PENDING_CMD_RX | PENDING_DAT_RX));
 189         update_pending_bits(s);
 190         break;
 191     case R_CMD:
 192         if (!s->enabled) {
 193             break;
 194         }
 195         if (s->ignore_next_cmd) {
 196             s->ignore_next_cmd = 0;
 197             break;
 198         }
 199         s->command[s->command_write_ptr] = value & 0xff;
 200         s->command_write_ptr = (s->command_write_ptr + 1) % 6;
 201         if (s->command_write_ptr == 0) {
 202             memcard_sd_command(s);
 203         }
 204         break;
 205     case R_DAT:
 206         if (!s->enabled) {
 207             break;
 208         }
 209         val32 = cpu_to_be32(value);
 210         sdbus_write_data(&s->sdbus, &val32, sizeof(val32));
 211         break;
 212     case R_ENABLE:
 213         s->regs[addr] = value;
 214         update_pending_bits(s);
 215         break;
 216     case R_CLK2XDIV:
 217     case R_START:
 218         s->regs[addr] = value;
 219         break;
 220
 221     default:
 222         qemu_log_mask(LOG_UNIMP, "milkymist_memcard: "
 223                       "write access to unknown register 0x%" HWADDR_PRIx " "
 224                       "(value 0x%" PRIx64 ")\n", addr << 2, value);
 225         break;
 226     }
 227 }
 228
 229 static const MemoryRegionOps memcard_mmio_ops = {
 230     .read = memcard_read,
 231     .write = memcard_write,
 232     .valid = {
 233         .min_access_size = 4,
 234         .max_access_size = 4,
 235     },
 236     .endianness = DEVICE_NATIVE_ENDIAN,
 237 };
 238
 239 static void milkymist_memcard_reset(DeviceState *d)
 240 {
 241     MilkymistMemcardState *s = MILKYMIST_MEMCARD(d);
 242     int i;
 243
 244     s->command_write_ptr = 0;
 245     s->response_read_ptr = 0;
 246     s->response_len = 0;
 247
 248     for (i = 0; i < R_MAX; i++) {
 249         s->regs[i] = 0;
 250     }
 251 }
 252
 253 static void milkymist_memcard_set_readonly(DeviceState *dev, bool level)
 254 {
 255     qemu_log_mask(LOG_UNIMP,
 256                   "milkymist_memcard: read-only mode not supported\n");
 257 }
 258
 259 static void milkymist_memcard_set_inserted(DeviceState *dev, bool level)
 260 {
 261     MilkymistMemcardState *s = MILKYMIST_MEMCARD(dev);
 262
 263     s->enabled = !!level;
 264 }
 265
 266 static void milkymist_memcard_init(Object *obj)
 267 {
 268     MilkymistMemcardState *s = MILKYMIST_MEMCARD(obj);
 269     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 270
 271     memory_region_init_io(&s->regs_region, OBJECT(s), &memcard_mmio_ops, s,
 272             "milkymist-memcard", R_MAX * 4);
 273     sysbus_init_mmio(dev, &s->regs_region);
 274
 275     qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS,
 276                         DEVICE(obj), "sd-bus");
 277 }
 278
 279 static const VMStateDescription vmstate_milkymist_memcard = {
 280     .name = "milkymist-memcard",
 281     .version_id = 1,
 282     .minimum_version_id = 1,
 283     .fields = (VMStateField[]) {
 284         VMSTATE_INT32(command_write_ptr, MilkymistMemcardState),
 285         VMSTATE_INT32(response_read_ptr, MilkymistMemcardState),
 286         VMSTATE_INT32(response_len, MilkymistMemcardState),
 287         VMSTATE_INT32(ignore_next_cmd, MilkymistMemcardState),
 288         VMSTATE_INT32(enabled, MilkymistMemcardState),
 289         VMSTATE_UINT8_ARRAY(command, MilkymistMemcardState, 6),
 290         VMSTATE_UINT8_ARRAY(response, MilkymistMemcardState, 17),
 291         VMSTATE_UINT32_ARRAY(regs, MilkymistMemcardState, R_MAX),
 292         VMSTATE_END_OF_LIST()
 293     }
 294 };
 295
 296 static void milkymist_memcard_class_init(ObjectClass *klass, void *data)
 297 {
 298     DeviceClass *dc = DEVICE_CLASS(klass);
 299
 300     dc->reset = milkymist_memcard_reset;
 301     dc->vmsd = &vmstate_milkymist_memcard;
 302     /* Reason: output IRQs should be wired up */
 303     dc->user_creatable = false;
 304 }
 305
 306 static const TypeInfo milkymist_memcard_info = {
 307     .name          = TYPE_MILKYMIST_MEMCARD,
 308     .parent        = TYPE_SYS_BUS_DEVICE,
 309     .instance_size = sizeof(MilkymistMemcardState),
 310     .instance_init = milkymist_memcard_init,
 311     .class_init    = milkymist_memcard_class_init,
 312 };
 313
 314 static void milkymist_sdbus_class_init(ObjectClass *klass, void *data)
 315 {
 316     SDBusClass *sbc = SD_BUS_CLASS(klass);
 317
 318     sbc->set_inserted = milkymist_memcard_set_inserted;
 319     sbc->set_readonly = milkymist_memcard_set_readonly;
 320 }
 321
 322 static const TypeInfo milkymist_sdbus_info = {
 323     .name = TYPE_MILKYMIST_SDBUS,
 324     .parent = TYPE_SD_BUS,
 325     .instance_size = sizeof(SDBus),
 326     .class_init = milkymist_sdbus_class_init,
 327 };
 328
 329 static void milkymist_memcard_register_types(void)
 330 {
 331     type_register_static(&milkymist_memcard_info);
 332     type_register_static(&milkymist_sdbus_info);
 333 }
 334
 335 type_init(milkymist_memcard_register_types)