hw/char/ibex_uart.c

   1 /*
   2  * QEMU lowRISC Ibex UART device
   3  *
   4  * Copyright (c) 2020 Western Digital
   5  *
   6  * For details check the documentation here:
   7  *    https://docs.opentitan.org/hw/ip/uart/doc/
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a copy
  10  * of this software and associated documentation files (the "Software"), to deal
  11  * in the Software without restriction, including without limitation the rights
  12  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  13  * copies of the Software, and to permit persons to whom the Software is
  14  * furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice shall be included in
  17  * all copies or substantial portions of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  25  * THE SOFTWARE.
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "hw/char/ibex_uart.h"
  30 #include "hw/irq.h"
  31 #include "hw/qdev-clock.h"
  32 #include "hw/qdev-properties.h"
  33 #include "migration/vmstate.h"
  34 #include "qemu/log.h"
  35 #include "qemu/module.h"
  36
  37 static void ibex_uart_update_irqs(IbexUartState *s)
  38 {
  39     if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_WATERMARK_MASK) {
  40         qemu_set_irq(s->tx_watermark, 1);
  41     } else {
  42         qemu_set_irq(s->tx_watermark, 0);
  43     }
  44
  45     if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_RX_WATERMARK_MASK) {
  46         qemu_set_irq(s->rx_watermark, 1);
  47     } else {
  48         qemu_set_irq(s->rx_watermark, 0);
  49     }
  50
  51     if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_TX_EMPTY_MASK) {
  52         qemu_set_irq(s->tx_empty, 1);
  53     } else {
  54         qemu_set_irq(s->tx_empty, 0);
  55     }
  56
  57     if (s->uart_intr_state & s->uart_intr_enable & R_INTR_STATE_RX_OVERFLOW_MASK) {
  58         qemu_set_irq(s->rx_overflow, 1);
  59     } else {
  60         qemu_set_irq(s->rx_overflow, 0);
  61     }
  62 }
  63
  64 static int ibex_uart_can_receive(void *opaque)
  65 {
  66     IbexUartState *s = opaque;
  67
  68     if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
  69         return 1;
  70     }
  71
  72     return 0;
  73 }
  74
  75 static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size)
  76 {
  77     IbexUartState *s = opaque;
  78     uint8_t rx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_RXILVL_MASK)
  79                             >> R_FIFO_CTRL_RXILVL_SHIFT;
  80
  81     s->uart_rdata = *buf;
  82
  83     s->uart_status &= ~R_STATUS_RXIDLE_MASK;
  84     s->uart_status &= ~R_STATUS_RXEMPTY_MASK;
  85
  86     if (size > rx_fifo_level) {
  87         s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK;
  88     }
  89
  90     ibex_uart_update_irqs(s);
  91 }
  92
  93 static gboolean ibex_uart_xmit(GIOChannel *chan, GIOCondition cond,
  94                                void *opaque)
  95 {
  96     IbexUartState *s = opaque;
  97     uint8_t tx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_TXILVL_MASK)
  98                             >> R_FIFO_CTRL_TXILVL_SHIFT;
  99     int ret;
 100
 101     /* instant drain the fifo when there's no back-end */
 102     if (!qemu_chr_fe_backend_connected(&s->chr)) {
 103         s->tx_level = 0;
 104         return FALSE;
 105     }
 106
 107     if (!s->tx_level) {
 108         s->uart_status &= ~R_STATUS_TXFULL_MASK;
 109         s->uart_status |= R_STATUS_TXEMPTY_MASK;
 110         s->uart_intr_state |= R_INTR_STATE_TX_EMPTY_MASK;
 111         s->uart_intr_state &= ~R_INTR_STATE_TX_WATERMARK_MASK;
 112         ibex_uart_update_irqs(s);
 113         return FALSE;
 114     }
 115
 116     ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_level);
 117
 118     if (ret >= 0) {
 119         s->tx_level -= ret;
 120         memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_level);
 121     }
 122
 123     if (s->tx_level) {
 124         guint r = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
 125                                         ibex_uart_xmit, s);
 126         if (!r) {
 127             s->tx_level = 0;
 128             return FALSE;
 129         }
 130     }
 131
 132     /* Clear the TX Full bit */
 133     if (s->tx_level != IBEX_UART_TX_FIFO_SIZE) {
 134         s->uart_status &= ~R_STATUS_TXFULL_MASK;
 135     }
 136
 137     /* Disable the TX_WATERMARK IRQ */
 138     if (s->tx_level < tx_fifo_level) {
 139         s->uart_intr_state &= ~R_INTR_STATE_TX_WATERMARK_MASK;
 140     }
 141
 142     /* Set TX empty */
 143     if (s->tx_level == 0) {
 144         s->uart_status |= R_STATUS_TXEMPTY_MASK;
 145         s->uart_intr_state |= R_INTR_STATE_TX_EMPTY_MASK;
 146     }
 147
 148     ibex_uart_update_irqs(s);
 149     return FALSE;
 150 }
 151
 152 static void uart_write_tx_fifo(IbexUartState *s, const uint8_t *buf,
 153                                int size)
 154 {
 155     uint64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 156     uint8_t tx_fifo_level = (s->uart_fifo_ctrl & R_FIFO_CTRL_TXILVL_MASK)
 157                             >> R_FIFO_CTRL_TXILVL_SHIFT;
 158
 159     if (size > IBEX_UART_TX_FIFO_SIZE - s->tx_level) {
 160         size = IBEX_UART_TX_FIFO_SIZE - s->tx_level;
 161         qemu_log_mask(LOG_GUEST_ERROR, "ibex_uart: TX FIFO overflow");
 162     }
 163
 164     memcpy(s->tx_fifo + s->tx_level, buf, size);
 165     s->tx_level += size;
 166
 167     if (s->tx_level > 0) {
 168         s->uart_status &= ~R_STATUS_TXEMPTY_MASK;
 169     }
 170
 171     if (s->tx_level >= tx_fifo_level) {
 172         s->uart_intr_state |= R_INTR_STATE_TX_WATERMARK_MASK;
 173         ibex_uart_update_irqs(s);
 174     }
 175
 176     if (s->tx_level == IBEX_UART_TX_FIFO_SIZE) {
 177         s->uart_status |= R_STATUS_TXFULL_MASK;
 178     }
 179
 180     timer_mod(s->fifo_trigger_handle, current_time +
 181               (s->char_tx_time * 4));
 182 }
 183
 184 static void ibex_uart_reset(DeviceState *dev)
 185 {
 186     IbexUartState *s = IBEX_UART(dev);
 187
 188     s->uart_intr_state = 0x00000000;
 189     s->uart_intr_state = 0x00000000;
 190     s->uart_intr_enable = 0x00000000;
 191     s->uart_ctrl = 0x00000000;
 192     s->uart_status = 0x0000003c;
 193     s->uart_rdata = 0x00000000;
 194     s->uart_fifo_ctrl = 0x00000000;
 195     s->uart_fifo_status = 0x00000000;
 196     s->uart_ovrd = 0x00000000;
 197     s->uart_val = 0x00000000;
 198     s->uart_timeout_ctrl = 0x00000000;
 199
 200     s->tx_level = 0;
 201
 202     s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10;
 203
 204     ibex_uart_update_irqs(s);
 205 }
 206
 207 static uint64_t ibex_uart_get_baud(IbexUartState *s)
 208 {
 209     uint64_t baud;
 210
 211     baud = ((s->uart_ctrl & R_CTRL_NCO_MASK) >> 16);
 212     baud *= clock_get_hz(s->f_clk);
 213     baud >>= 20;
 214
 215     return baud;
 216 }
 217
 218 static uint64_t ibex_uart_read(void *opaque, hwaddr addr,
 219                                        unsigned int size)
 220 {
 221     IbexUartState *s = opaque;
 222     uint64_t retvalue = 0;
 223
 224     switch (addr >> 2) {
 225     case R_INTR_STATE:
 226         retvalue = s->uart_intr_state;
 227         break;
 228     case R_INTR_ENABLE:
 229         retvalue = s->uart_intr_enable;
 230         break;
 231     case R_INTR_TEST:
 232         qemu_log_mask(LOG_GUEST_ERROR,
 233                       "%s: wdata is write only\n", __func__);
 234         break;
 235
 236     case R_CTRL:
 237         retvalue = s->uart_ctrl;
 238         break;
 239     case R_STATUS:
 240         retvalue = s->uart_status;
 241         break;
 242
 243     case R_RDATA:
 244         retvalue = s->uart_rdata;
 245         if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) {
 246             qemu_chr_fe_accept_input(&s->chr);
 247
 248             s->uart_status |= R_STATUS_RXIDLE_MASK;
 249             s->uart_status |= R_STATUS_RXEMPTY_MASK;
 250         }
 251         break;
 252     case R_WDATA:
 253         qemu_log_mask(LOG_GUEST_ERROR,
 254                       "%s: wdata is write only\n", __func__);
 255         break;
 256
 257     case R_FIFO_CTRL:
 258         retvalue = s->uart_fifo_ctrl;
 259         break;
 260     case R_FIFO_STATUS:
 261         retvalue = s->uart_fifo_status;
 262
 263         retvalue |= s->tx_level & 0x1F;
 264
 265         qemu_log_mask(LOG_UNIMP,
 266                       "%s: RX fifos are not supported\n", __func__);
 267         break;
 268
 269     case R_OVRD:
 270         retvalue = s->uart_ovrd;
 271         qemu_log_mask(LOG_UNIMP,
 272                       "%s: ovrd is not supported\n", __func__);
 273         break;
 274     case R_VAL:
 275         retvalue = s->uart_val;
 276         qemu_log_mask(LOG_UNIMP,
 277                       "%s: val is not supported\n", __func__);
 278         break;
 279     case R_TIMEOUT_CTRL:
 280         retvalue = s->uart_timeout_ctrl;
 281         qemu_log_mask(LOG_UNIMP,
 282                       "%s: timeout_ctrl is not supported\n", __func__);
 283         break;
 284     default:
 285         qemu_log_mask(LOG_GUEST_ERROR,
 286                       "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
 287         return 0;
 288     }
 289
 290     return retvalue;
 291 }
 292
 293 static void ibex_uart_write(void *opaque, hwaddr addr,
 294                                   uint64_t val64, unsigned int size)
 295 {
 296     IbexUartState *s = opaque;
 297     uint32_t value = val64;
 298
 299     switch (addr >> 2) {
 300     case R_INTR_STATE:
 301         /* Write 1 clear */
 302         s->uart_intr_state &= ~value;
 303         ibex_uart_update_irqs(s);
 304         break;
 305     case R_INTR_ENABLE:
 306         s->uart_intr_enable = value;
 307         ibex_uart_update_irqs(s);
 308         break;
 309     case R_INTR_TEST:
 310         s->uart_intr_state |= value;
 311         ibex_uart_update_irqs(s);
 312         break;
 313
 314     case R_CTRL:
 315         s->uart_ctrl = value;
 316
 317         if (value & R_CTRL_NF_MASK) {
 318             qemu_log_mask(LOG_UNIMP,
 319                           "%s: UART_CTRL_NF is not supported\n", __func__);
 320         }
 321         if (value & R_CTRL_SLPBK_MASK) {
 322             qemu_log_mask(LOG_UNIMP,
 323                           "%s: UART_CTRL_SLPBK is not supported\n", __func__);
 324         }
 325         if (value & R_CTRL_LLPBK_MASK) {
 326             qemu_log_mask(LOG_UNIMP,
 327                           "%s: UART_CTRL_LLPBK is not supported\n", __func__);
 328         }
 329         if (value & R_CTRL_PARITY_EN_MASK) {
 330             qemu_log_mask(LOG_UNIMP,
 331                           "%s: UART_CTRL_PARITY_EN is not supported\n",
 332                           __func__);
 333         }
 334         if (value & R_CTRL_PARITY_ODD_MASK) {
 335             qemu_log_mask(LOG_UNIMP,
 336                           "%s: UART_CTRL_PARITY_ODD is not supported\n",
 337                           __func__);
 338         }
 339         if (value & R_CTRL_RXBLVL_MASK) {
 340             qemu_log_mask(LOG_UNIMP,
 341                           "%s: UART_CTRL_RXBLVL is not supported\n", __func__);
 342         }
 343         if (value & R_CTRL_NCO_MASK) {
 344             uint64_t baud = ibex_uart_get_baud(s);
 345
 346             s->char_tx_time = (NANOSECONDS_PER_SECOND / baud) * 10;
 347         }
 348         break;
 349     case R_STATUS:
 350         qemu_log_mask(LOG_GUEST_ERROR,
 351                       "%s: status is read only\n", __func__);
 352         break;
 353
 354     case R_RDATA:
 355         qemu_log_mask(LOG_GUEST_ERROR,
 356                       "%s: rdata is read only\n", __func__);
 357         break;
 358     case R_WDATA:
 359         uart_write_tx_fifo(s, (uint8_t *) &value, 1);
 360         break;
 361
 362     case R_FIFO_CTRL:
 363         s->uart_fifo_ctrl = value;
 364
 365         if (value & R_FIFO_CTRL_RXRST_MASK) {
 366             qemu_log_mask(LOG_UNIMP,
 367                           "%s: RX fifos are not supported\n", __func__);
 368         }
 369         if (value & R_FIFO_CTRL_TXRST_MASK) {
 370             s->tx_level = 0;
 371         }
 372         break;
 373     case R_FIFO_STATUS:
 374         qemu_log_mask(LOG_GUEST_ERROR,
 375                       "%s: fifo_status is read only\n", __func__);
 376         break;
 377
 378     case R_OVRD:
 379         s->uart_ovrd = value;
 380         qemu_log_mask(LOG_UNIMP,
 381                       "%s: ovrd is not supported\n", __func__);
 382         break;
 383     case R_VAL:
 384         qemu_log_mask(LOG_GUEST_ERROR,
 385                       "%s: val is read only\n", __func__);
 386         break;
 387     case R_TIMEOUT_CTRL:
 388         s->uart_timeout_ctrl = value;
 389         qemu_log_mask(LOG_UNIMP,
 390                       "%s: timeout_ctrl is not supported\n", __func__);
 391         break;
 392     default:
 393         qemu_log_mask(LOG_GUEST_ERROR,
 394                       "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
 395     }
 396 }
 397
 398 static void ibex_uart_clk_update(void *opaque)
 399 {
 400     IbexUartState *s = opaque;
 401
 402     /* recompute uart's speed on clock change */
 403     uint64_t baud = ibex_uart_get_baud(s);
 404
 405     s->char_tx_time = (NANOSECONDS_PER_SECOND / baud) * 10;
 406 }
 407
 408 static void fifo_trigger_update(void *opaque)
 409 {
 410     IbexUartState *s = opaque;
 411
 412     if (s->uart_ctrl & R_CTRL_TX_ENABLE_MASK) {
 413         ibex_uart_xmit(NULL, G_IO_OUT, s);
 414     }
 415 }
 416
 417 static const MemoryRegionOps ibex_uart_ops = {
 418     .read = ibex_uart_read,
 419     .write = ibex_uart_write,
 420     .endianness = DEVICE_NATIVE_ENDIAN,
 421     .impl.min_access_size = 4,
 422     .impl.max_access_size = 4,
 423 };
 424
 425 static int ibex_uart_post_load(void *opaque, int version_id)
 426 {
 427     IbexUartState *s = opaque;
 428
 429     ibex_uart_update_irqs(s);
 430     return 0;
 431 }
 432
 433 static const VMStateDescription vmstate_ibex_uart = {
 434     .name = TYPE_IBEX_UART,
 435     .version_id = 1,
 436     .minimum_version_id = 1,
 437     .post_load = ibex_uart_post_load,
 438     .fields = (VMStateField[]) {
 439         VMSTATE_UINT8_ARRAY(tx_fifo, IbexUartState,
 440                             IBEX_UART_TX_FIFO_SIZE),
 441         VMSTATE_UINT32(tx_level, IbexUartState),
 442         VMSTATE_UINT64(char_tx_time, IbexUartState),
 443         VMSTATE_TIMER_PTR(fifo_trigger_handle, IbexUartState),
 444         VMSTATE_UINT32(uart_intr_state, IbexUartState),
 445         VMSTATE_UINT32(uart_intr_enable, IbexUartState),
 446         VMSTATE_UINT32(uart_ctrl, IbexUartState),
 447         VMSTATE_UINT32(uart_status, IbexUartState),
 448         VMSTATE_UINT32(uart_rdata, IbexUartState),
 449         VMSTATE_UINT32(uart_fifo_ctrl, IbexUartState),
 450         VMSTATE_UINT32(uart_fifo_status, IbexUartState),
 451         VMSTATE_UINT32(uart_ovrd, IbexUartState),
 452         VMSTATE_UINT32(uart_val, IbexUartState),
 453         VMSTATE_UINT32(uart_timeout_ctrl, IbexUartState),
 454         VMSTATE_END_OF_LIST()
 455     }
 456 };
 457
 458 static Property ibex_uart_properties[] = {
 459     DEFINE_PROP_CHR("chardev", IbexUartState, chr),
 460     DEFINE_PROP_END_OF_LIST(),
 461 };
 462
 463 static void ibex_uart_init(Object *obj)
 464 {
 465     IbexUartState *s = IBEX_UART(obj);
 466
 467     s->f_clk = qdev_init_clock_in(DEVICE(obj), "f_clock",
 468                                   ibex_uart_clk_update, s);
 469     clock_set_hz(s->f_clk, IBEX_UART_CLOCK);
 470
 471     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_watermark);
 472     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rx_watermark);
 473     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->tx_empty);
 474     sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->rx_overflow);
 475
 476     memory_region_init_io(&s->mmio, obj, &ibex_uart_ops, s,
 477                           TYPE_IBEX_UART, 0x400);
 478     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 479 }
 480
 481 static void ibex_uart_realize(DeviceState *dev, Error **errp)
 482 {
 483     IbexUartState *s = IBEX_UART(dev);
 484
 485     s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 486                                           fifo_trigger_update, s);
 487
 488     qemu_chr_fe_set_handlers(&s->chr, ibex_uart_can_receive,
 489                              ibex_uart_receive, NULL, NULL,
 490                              s, NULL, true);
 491 }
 492
 493 static void ibex_uart_class_init(ObjectClass *klass, void *data)
 494 {
 495     DeviceClass *dc = DEVICE_CLASS(klass);
 496
 497     dc->reset = ibex_uart_reset;
 498     dc->realize = ibex_uart_realize;
 499     dc->vmsd = &vmstate_ibex_uart;
 500     device_class_set_props(dc, ibex_uart_properties);
 501 }
 502
 503 static const TypeInfo ibex_uart_info = {
 504     .name          = TYPE_IBEX_UART,
 505     .parent        = TYPE_SYS_BUS_DEVICE,
 506     .instance_size = sizeof(IbexUartState),
 507     .instance_init = ibex_uart_init,
 508     .class_init    = ibex_uart_class_init,
 509 };
 510
 511 static void ibex_uart_register_types(void)
 512 {
 513     type_register_static(&ibex_uart_info);
 514 }
 515
 516 type_init(ibex_uart_register_types)