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hw: arm: Convert the RSDP build to the buid_append_foo() API
[qemu/ar7.git] / hw / arm / virt-acpi-build.c
blob4a6b53fbfcb4b838eda8a4e1405c236f8929b94b
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * ARM virt ACPI generation
4 *
5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
6 * Copyright (C) 2006 Fabrice Bellard
7 * Copyright (C) 2013 Red Hat Inc
8 *
9 * Author: Michael S. Tsirkin <mst@redhat.com>
10 *
11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
12 *
13 * Author: Shannon Zhao <zhaoshenglong@huawei.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, see <http://www.gnu.org/licenses/>.
27 */
28
29 #include "qemu/osdep.h"
30 #include "qapi/error.h"
31 #include "qemu-common.h"
32 #include "qemu/bitmap.h"
33 #include "trace.h"
34 #include "qom/cpu.h"
35 #include "target/arm/cpu.h"
36 #include "hw/acpi/acpi-defs.h"
37 #include "hw/acpi/acpi.h"
38 #include "hw/nvram/fw_cfg.h"
39 #include "hw/acpi/bios-linker-loader.h"
40 #include "hw/loader.h"
41 #include "hw/hw.h"
42 #include "hw/acpi/aml-build.h"
43 #include "hw/pci/pcie_host.h"
44 #include "hw/pci/pci.h"
45 #include "hw/arm/virt.h"
46 #include "sysemu/numa.h"
47 #include "kvm_arm.h"
48
49 #define ARM_SPI_BASE 32
50 #define ACPI_POWER_BUTTON_DEVICE "PWRB"
51
52 static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)
53 {
54 uint16_t i;
55
56 for (i = 0; i < smp_cpus; i++) {
57 Aml *dev = aml_device("C%.03X", i);
58 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
59 aml_append(dev, aml_name_decl("_UID", aml_int(i)));
60 aml_append(scope, dev);
61 }
62 }
63
64 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
65 uint32_t uart_irq)
66 {
67 Aml *dev = aml_device("COM0");
68 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011")));
69 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
70
71 Aml *crs = aml_resource_template();
72 aml_append(crs, aml_memory32_fixed(uart_memmap->base,
73 uart_memmap->size, AML_READ_WRITE));
74 aml_append(crs,
75 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
76 AML_EXCLUSIVE, &uart_irq, 1));
77 aml_append(dev, aml_name_decl("_CRS", crs));
78
79 /* The _ADR entry is used to link this device to the UART described
80 * in the SPCR table, i.e. SPCR.base_address.address == _ADR.
81 */
82 aml_append(dev, aml_name_decl("_ADR", aml_int(uart_memmap->base)));
83
84 aml_append(scope, dev);
85 }
86
87 static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap)
88 {
89 Aml *dev = aml_device("FWCF");
90 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
91 /* device present, functioning, decoding, not shown in UI */
92 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
93 aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
94
95 Aml *crs = aml_resource_template();
96 aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base,
97 fw_cfg_memmap->size, AML_READ_WRITE));
98 aml_append(dev, aml_name_decl("_CRS", crs));
99 aml_append(scope, dev);
100 }
101
102 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap)
103 {
104 Aml *dev, *crs;
105 hwaddr base = flash_memmap->base;
106 hwaddr size = flash_memmap->size / 2;
107
108 dev = aml_device("FLS0");
109 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
110 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
111
112 crs = aml_resource_template();
113 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
114 aml_append(dev, aml_name_decl("_CRS", crs));
115 aml_append(scope, dev);
116
117 dev = aml_device("FLS1");
118 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
119 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
120 crs = aml_resource_template();
121 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE));
122 aml_append(dev, aml_name_decl("_CRS", crs));
123 aml_append(scope, dev);
124 }
125
126 static void acpi_dsdt_add_virtio(Aml *scope,
127 const MemMapEntry *virtio_mmio_memmap,
128 uint32_t mmio_irq, int num)
129 {
130 hwaddr base = virtio_mmio_memmap->base;
131 hwaddr size = virtio_mmio_memmap->size;
132 int i;
133
134 for (i = 0; i < num; i++) {
135 uint32_t irq = mmio_irq + i;
136 Aml *dev = aml_device("VR%02u", i);
137 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
138 aml_append(dev, aml_name_decl("_UID", aml_int(i)));
139 aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
140
141 Aml *crs = aml_resource_template();
142 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
143 aml_append(crs,
144 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
145 AML_EXCLUSIVE, &irq, 1));
146 aml_append(dev, aml_name_decl("_CRS", crs));
147 aml_append(scope, dev);
148 base += size;
149 }
150 }
151
152 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
153 uint32_t irq, bool use_highmem, bool highmem_ecam)
154 {
155 int ecam_id = VIRT_ECAM_ID(highmem_ecam);
156 Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf;
157 int i, bus_no;
158 hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base;
159 hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size;
160 hwaddr base_pio = memmap[VIRT_PCIE_PIO].base;
161 hwaddr size_pio = memmap[VIRT_PCIE_PIO].size;
162 hwaddr base_ecam = memmap[ecam_id].base;
163 hwaddr size_ecam = memmap[ecam_id].size;
164 int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
165
166 Aml *dev = aml_device("%s", "PCI0");
167 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
168 aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
169 aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
170 aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
171 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
172 aml_append(dev, aml_name_decl("_UID", aml_string("PCI0")));
173 aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
174 aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
175
176 /* Declare the PCI Routing Table. */
177 Aml *rt_pkg = aml_varpackage(nr_pcie_buses * PCI_NUM_PINS);
178 for (bus_no = 0; bus_no < nr_pcie_buses; bus_no++) {
179 for (i = 0; i < PCI_NUM_PINS; i++) {
180 int gsi = (i + bus_no) % PCI_NUM_PINS;
181 Aml *pkg = aml_package(4);
182 aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF));
183 aml_append(pkg, aml_int(i));
184 aml_append(pkg, aml_name("GSI%d", gsi));
185 aml_append(pkg, aml_int(0));
186 aml_append(rt_pkg, pkg);
187 }
188 }
189 aml_append(dev, aml_name_decl("_PRT", rt_pkg));
190
191 /* Create GSI link device */
192 for (i = 0; i < PCI_NUM_PINS; i++) {
193 uint32_t irqs = irq + i;
194 Aml *dev_gsi = aml_device("GSI%d", i);
195 aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
196 aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0)));
197 crs = aml_resource_template();
198 aml_append(crs,
199 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
200 AML_EXCLUSIVE, &irqs, 1));
201 aml_append(dev_gsi, aml_name_decl("_PRS", crs));
202 crs = aml_resource_template();
203 aml_append(crs,
204 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
205 AML_EXCLUSIVE, &irqs, 1));
206 aml_append(dev_gsi, aml_name_decl("_CRS", crs));
207 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
208 aml_append(dev_gsi, method);
209 aml_append(dev, dev_gsi);
210 }
211
212 method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
213 aml_append(method, aml_return(aml_int(base_ecam)));
214 aml_append(dev, method);
215
216 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
217 Aml *rbuf = aml_resource_template();
218 aml_append(rbuf,
219 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
220 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
221 nr_pcie_buses));
222 aml_append(rbuf,
223 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
224 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio,
225 base_mmio + size_mmio - 1, 0x0000, size_mmio));
226 aml_append(rbuf,
227 aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
228 AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio,
229 size_pio));
230
231 if (use_highmem) {
232 hwaddr base_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].base;
233 hwaddr size_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].size;
234
235 aml_append(rbuf,
236 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
237 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
238 base_mmio_high,
239 base_mmio_high + size_mmio_high - 1, 0x0000,
240 size_mmio_high));
241 }
242
243 aml_append(method, aml_name_decl("RBUF", rbuf));
244 aml_append(method, aml_return(rbuf));
245 aml_append(dev, method);
246
247 /* Declare an _OSC (OS Control Handoff) method */
248 aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
249 aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
250 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
251 aml_append(method,
252 aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
253
254 /* PCI Firmware Specification 3.0
255 * 4.5.1. _OSC Interface for PCI Host Bridge Devices
256 * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
257 * identified by the Universal Unique IDentifier (UUID)
258 * 33DB4D5B-1FF7-401C-9657-7441C03DD766
259 */
260 UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
261 ifctx = aml_if(aml_equal(aml_arg(0), UUID));
262 aml_append(ifctx,
263 aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
264 aml_append(ifctx,
265 aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
266 aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
267 aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
268 aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D), NULL),
269 aml_name("CTRL")));
270
271 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
272 aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08), NULL),
273 aml_name("CDW1")));
274 aml_append(ifctx, ifctx1);
275
276 ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
277 aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10), NULL),
278 aml_name("CDW1")));
279 aml_append(ifctx, ifctx1);
280
281 aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
282 aml_append(ifctx, aml_return(aml_arg(3)));
283 aml_append(method, ifctx);
284
285 elsectx = aml_else();
286 aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4), NULL),
287 aml_name("CDW1")));
288 aml_append(elsectx, aml_return(aml_arg(3)));
289 aml_append(method, elsectx);
290 aml_append(dev, method);
291
292 method = aml_method("_DSM", 4, AML_NOTSERIALIZED);
293
294 /* PCI Firmware Specification 3.0
295 * 4.6.1. _DSM for PCI Express Slot Information
296 * The UUID in _DSM in this context is
297 * {E5C937D0-3553-4D7A-9117-EA4D19C3434D}
298 */
299 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
300 ifctx = aml_if(aml_equal(aml_arg(0), UUID));
301 ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
302 uint8_t byte_list[1] = {1};
303 buf = aml_buffer(1, byte_list);
304 aml_append(ifctx1, aml_return(buf));
305 aml_append(ifctx, ifctx1);
306 aml_append(method, ifctx);
307
308 byte_list[0] = 0;
309 buf = aml_buffer(1, byte_list);
310 aml_append(method, aml_return(buf));
311 aml_append(dev, method);
312
313 Aml *dev_rp0 = aml_device("%s", "RP0");
314 aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
315 aml_append(dev, dev_rp0);
316
317 Aml *dev_res0 = aml_device("%s", "RES0");
318 aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02")));
319 crs = aml_resource_template();
320 aml_append(crs,
321 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
322 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_ecam,
323 base_ecam + size_ecam - 1, 0x0000, size_ecam));
324 aml_append(dev_res0, aml_name_decl("_CRS", crs));
325 aml_append(dev, dev_res0);
326 aml_append(scope, dev);
327 }
328
329 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap,
330 uint32_t gpio_irq)
331 {
332 Aml *dev = aml_device("GPO0");
333 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061")));
334 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
335 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
336
337 Aml *crs = aml_resource_template();
338 aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size,
339 AML_READ_WRITE));
340 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
341 AML_EXCLUSIVE, &gpio_irq, 1));
342 aml_append(dev, aml_name_decl("_CRS", crs));
343
344 Aml *aei = aml_resource_template();
345 /* Pin 3 for power button */
346 const uint32_t pin_list[1] = {3};
347 aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH,
348 AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1,
349 "GPO0", NULL, 0));
350 aml_append(dev, aml_name_decl("_AEI", aei));
351
352 /* _E03 is handle for power button */
353 Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED);
354 aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE),
355 aml_int(0x80)));
356 aml_append(dev, method);
357 aml_append(scope, dev);
358 }
359
360 static void acpi_dsdt_add_power_button(Aml *scope)
361 {
362 Aml *dev = aml_device(ACPI_POWER_BUTTON_DEVICE);
363 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C0C")));
364 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
365 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
366 aml_append(scope, dev);
367 }
368
369 /* RSDP */
370 static void
371 build_rsdp(GArray *tbl, BIOSLinker *linker, AcpiRsdpData *rsdp_data)
372 {
373 int tbl_off = tbl->len; /* Table offset in the RSDP file */
374
375 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, tbl, 16,
376 true /* fseg memory */);
377
378 g_array_append_vals(tbl, "RSD PTR ", 8); /* Signature */
379 build_append_int_noprefix(tbl, 0, 1); /* Checksum */
380 g_array_append_vals(tbl, rsdp_data->oem_id, 6); /* OEMID */
381 build_append_int_noprefix(tbl, rsdp_data->revision, 1); /* Revision */
382 build_append_int_noprefix(tbl, 0, 4); /* RsdtAddress */
383 build_append_int_noprefix(tbl, 36, 4); /* Length */
384
385 /* XSDT address to be filled by guest linker */
386 build_append_int_noprefix(tbl, 0, 8); /* XsdtAddress */
387 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE,
388 tbl_off + 24, 8,
389 ACPI_BUILD_TABLE_FILE,
390 *rsdp_data->xsdt_tbl_offset);
391
392 build_append_int_noprefix(tbl, 0, 1); /* Extended Checksum */
393 build_append_int_noprefix(tbl, 0, 3); /* Reserved */
394
395 /* Checksum to be filled by guest linker */
396 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
397 tbl_off, 20, /* ACPI rev 1.0 RSDP size */
398 8);
399
400 /* Extended checksum to be filled by Guest linker */
401 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
402 tbl_off, 36, /* ACPI rev 2.0 RSDP size */
403 32);
404 }
405
406 static void
407 build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
408 {
409 int nb_nodes, iort_start = table_data->len;
410 AcpiIortIdMapping *idmap;
411 AcpiIortItsGroup *its;
412 AcpiIortTable *iort;
413 AcpiIortSmmu3 *smmu;
414 size_t node_size, iort_node_offset, iort_length, smmu_offset = 0;
415 AcpiIortRC *rc;
416
417 iort = acpi_data_push(table_data, sizeof(*iort));
418
419 if (vms->iommu == VIRT_IOMMU_SMMUV3) {
420 nb_nodes = 3; /* RC, ITS, SMMUv3 */
421 } else {
422 nb_nodes = 2; /* RC, ITS */
423 }
424
425 iort_length = sizeof(*iort);
426 iort->node_count = cpu_to_le32(nb_nodes);
427 /*
428 * Use a copy in case table_data->data moves during acpi_data_push
429 * operations.
430 */
431 iort_node_offset = sizeof(*iort);
432 iort->node_offset = cpu_to_le32(iort_node_offset);
433
434 /* ITS group node */
435 node_size = sizeof(*its) + sizeof(uint32_t);
436 iort_length += node_size;
437 its = acpi_data_push(table_data, node_size);
438
439 its->type = ACPI_IORT_NODE_ITS_GROUP;
440 its->length = cpu_to_le16(node_size);
441 its->its_count = cpu_to_le32(1);
442 its->identifiers[0] = 0; /* MADT translation_id */
443
444 if (vms->iommu == VIRT_IOMMU_SMMUV3) {
445 int irq = vms->irqmap[VIRT_SMMU];
446
447 /* SMMUv3 node */
448 smmu_offset = iort_node_offset + node_size;
449 node_size = sizeof(*smmu) + sizeof(*idmap);
450 iort_length += node_size;
451 smmu = acpi_data_push(table_data, node_size);
452
453 smmu->type = ACPI_IORT_NODE_SMMU_V3;
454 smmu->length = cpu_to_le16(node_size);
455 smmu->mapping_count = cpu_to_le32(1);
456 smmu->mapping_offset = cpu_to_le32(sizeof(*smmu));
457 smmu->base_address = cpu_to_le64(vms->memmap[VIRT_SMMU].base);
458 smmu->event_gsiv = cpu_to_le32(irq);
459 smmu->pri_gsiv = cpu_to_le32(irq + 1);
460 smmu->gerr_gsiv = cpu_to_le32(irq + 2);
461 smmu->sync_gsiv = cpu_to_le32(irq + 3);
462
463 /* Identity RID mapping covering the whole input RID range */
464 idmap = &smmu->id_mapping_array[0];
465 idmap->input_base = 0;
466 idmap->id_count = cpu_to_le32(0xFFFF);
467 idmap->output_base = 0;
468 /* output IORT node is the ITS group node (the first node) */
469 idmap->output_reference = cpu_to_le32(iort_node_offset);
470 }
471
472 /* Root Complex Node */
473 node_size = sizeof(*rc) + sizeof(*idmap);
474 iort_length += node_size;
475 rc = acpi_data_push(table_data, node_size);
476
477 rc->type = ACPI_IORT_NODE_PCI_ROOT_COMPLEX;
478 rc->length = cpu_to_le16(node_size);
479 rc->mapping_count = cpu_to_le32(1);
480 rc->mapping_offset = cpu_to_le32(sizeof(*rc));
481
482 /* fully coherent device */
483 rc->memory_properties.cache_coherency = cpu_to_le32(1);
484 rc->memory_properties.memory_flags = 0x3; /* CCA = CPM = DCAS = 1 */
485 rc->pci_segment_number = 0; /* MCFG pci_segment */
486
487 /* Identity RID mapping covering the whole input RID range */
488 idmap = &rc->id_mapping_array[0];
489 idmap->input_base = 0;
490 idmap->id_count = cpu_to_le32(0xFFFF);
491 idmap->output_base = 0;
492
493 if (vms->iommu == VIRT_IOMMU_SMMUV3) {
494 /* output IORT node is the smmuv3 node */
495 idmap->output_reference = cpu_to_le32(smmu_offset);
496 } else {
497 /* output IORT node is the ITS group node (the first node) */
498 idmap->output_reference = cpu_to_le32(iort_node_offset);
499 }
500
501 /*
502 * Update the pointer address in case table_data->data moves during above
503 * acpi_data_push operations.
504 */
505 iort = (AcpiIortTable *)(table_data->data + iort_start);
506 iort->length = cpu_to_le32(iort_length);
507
508 build_header(linker, table_data, (void *)(table_data->data + iort_start),
509 "IORT", table_data->len - iort_start, 0, NULL, NULL);
510 }
511
512 static void
513 build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
514 {
515 AcpiSerialPortConsoleRedirection *spcr;
516 const MemMapEntry *uart_memmap = &vms->memmap[VIRT_UART];
517 int irq = vms->irqmap[VIRT_UART] + ARM_SPI_BASE;
518 int spcr_start = table_data->len;
519
520 spcr = acpi_data_push(table_data, sizeof(*spcr));
521
522 spcr->interface_type = 0x3; /* ARM PL011 UART */
523
524 spcr->base_address.space_id = AML_SYSTEM_MEMORY;
525 spcr->base_address.bit_width = 8;
526 spcr->base_address.bit_offset = 0;
527 spcr->base_address.access_width = 1;
528 spcr->base_address.address = cpu_to_le64(uart_memmap->base);
529
530 spcr->interrupt_types = (1 << 3); /* Bit[3] ARMH GIC interrupt */
531 spcr->gsi = cpu_to_le32(irq); /* Global System Interrupt */
532
533 spcr->baud = 3; /* Baud Rate: 3 = 9600 */
534 spcr->parity = 0; /* No Parity */
535 spcr->stopbits = 1; /* 1 Stop bit */
536 spcr->flowctrl = (1 << 1); /* Bit[1] = RTS/CTS hardware flow control */
537 spcr->term_type = 0; /* Terminal Type: 0 = VT100 */
538
539 spcr->pci_device_id = 0xffff; /* PCI Device ID: not a PCI device */
540 spcr->pci_vendor_id = 0xffff; /* PCI Vendor ID: not a PCI device */
541
542 build_header(linker, table_data, (void *)(table_data->data + spcr_start),
543 "SPCR", table_data->len - spcr_start, 2, NULL, NULL);
544 }
545
546 static void
547 build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
548 {
549 AcpiSystemResourceAffinityTable *srat;
550 AcpiSratProcessorGiccAffinity *core;
551 AcpiSratMemoryAffinity *numamem;
552 int i, srat_start;
553 uint64_t mem_base;
554 MachineClass *mc = MACHINE_GET_CLASS(vms);
555 const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(MACHINE(vms));
556
557 srat_start = table_data->len;
558 srat = acpi_data_push(table_data, sizeof(*srat));
559 srat->reserved1 = cpu_to_le32(1);
560
561 for (i = 0; i < cpu_list->len; ++i) {
562 core = acpi_data_push(table_data, sizeof(*core));
563 core->type = ACPI_SRAT_PROCESSOR_GICC;
564 core->length = sizeof(*core);
565 core->proximity = cpu_to_le32(cpu_list->cpus[i].props.node_id);
566 core->acpi_processor_uid = cpu_to_le32(i);
567 core->flags = cpu_to_le32(1);
568 }
569
570 mem_base = vms->memmap[VIRT_MEM].base;
571 for (i = 0; i < nb_numa_nodes; ++i) {
572 if (numa_info[i].node_mem > 0) {
573 numamem = acpi_data_push(table_data, sizeof(*numamem));
574 build_srat_memory(numamem, mem_base, numa_info[i].node_mem, i,
575 MEM_AFFINITY_ENABLED);
576 mem_base += numa_info[i].node_mem;
577 }
578 }
579
580 build_header(linker, table_data, (void *)(table_data->data + srat_start),
581 "SRAT", table_data->len - srat_start, 3, NULL, NULL);
582 }
583
584 static void
585 build_mcfg(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
586 {
587 AcpiTableMcfg *mcfg;
588 const MemMapEntry *memmap = vms->memmap;
589 int ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
590 int len = sizeof(*mcfg) + sizeof(mcfg->allocation[0]);
591 int mcfg_start = table_data->len;
592
593 mcfg = acpi_data_push(table_data, len);
594 mcfg->allocation[0].address = cpu_to_le64(memmap[ecam_id].base);
595
596 /* Only a single allocation so no need to play with segments */
597 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
598 mcfg->allocation[0].start_bus_number = 0;
599 mcfg->allocation[0].end_bus_number = (memmap[ecam_id].size
600 / PCIE_MMCFG_SIZE_MIN) - 1;
601
602 build_header(linker, table_data, (void *)(table_data->data + mcfg_start),
603 "MCFG", table_data->len - mcfg_start, 1, NULL, NULL);
604 }
605
606 /* GTDT */
607 static void
608 build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
609 {
610 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
611 int gtdt_start = table_data->len;
612 AcpiGenericTimerTable *gtdt;
613 uint32_t irqflags;
614
615 if (vmc->claim_edge_triggered_timers) {
616 irqflags = ACPI_GTDT_INTERRUPT_MODE_EDGE;
617 } else {
618 irqflags = ACPI_GTDT_INTERRUPT_MODE_LEVEL;
619 }
620
621 gtdt = acpi_data_push(table_data, sizeof *gtdt);
622 /* The interrupt values are the same with the device tree when adding 16 */
623 gtdt->secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_S_EL1_IRQ + 16);
624 gtdt->secure_el1_flags = cpu_to_le32(irqflags);
625
626 gtdt->non_secure_el1_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL1_IRQ + 16);
627 gtdt->non_secure_el1_flags = cpu_to_le32(irqflags |
628 ACPI_GTDT_CAP_ALWAYS_ON);
629
630 gtdt->virtual_timer_interrupt = cpu_to_le32(ARCH_TIMER_VIRT_IRQ + 16);
631 gtdt->virtual_timer_flags = cpu_to_le32(irqflags);
632
633 gtdt->non_secure_el2_interrupt = cpu_to_le32(ARCH_TIMER_NS_EL2_IRQ + 16);
634 gtdt->non_secure_el2_flags = cpu_to_le32(irqflags);
635
636 build_header(linker, table_data,
637 (void *)(table_data->data + gtdt_start), "GTDT",
638 table_data->len - gtdt_start, 2, NULL, NULL);
639 }
640
641 /* MADT */
642 static void
643 build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
644 {
645 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
646 int madt_start = table_data->len;
647 const MemMapEntry *memmap = vms->memmap;
648 const int *irqmap = vms->irqmap;
649 AcpiMultipleApicTable *madt;
650 AcpiMadtGenericDistributor *gicd;
651 AcpiMadtGenericMsiFrame *gic_msi;
652 int i;
653
654 madt = acpi_data_push(table_data, sizeof *madt);
655
656 gicd = acpi_data_push(table_data, sizeof *gicd);
657 gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR;
658 gicd->length = sizeof(*gicd);
659 gicd->base_address = cpu_to_le64(memmap[VIRT_GIC_DIST].base);
660 gicd->version = vms->gic_version;
661
662 for (i = 0; i < vms->smp_cpus; i++) {
663 AcpiMadtGenericCpuInterface *gicc = acpi_data_push(table_data,
664 sizeof(*gicc));
665 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
666
667 gicc->type = ACPI_APIC_GENERIC_CPU_INTERFACE;
668 gicc->length = sizeof(*gicc);
669 if (vms->gic_version == 2) {
670 gicc->base_address = cpu_to_le64(memmap[VIRT_GIC_CPU].base);
671 gicc->gich_base_address = cpu_to_le64(memmap[VIRT_GIC_HYP].base);
672 gicc->gicv_base_address = cpu_to_le64(memmap[VIRT_GIC_VCPU].base);
673 }
674 gicc->cpu_interface_number = cpu_to_le32(i);
675 gicc->arm_mpidr = cpu_to_le64(armcpu->mp_affinity);
676 gicc->uid = cpu_to_le32(i);
677 gicc->flags = cpu_to_le32(ACPI_MADT_GICC_ENABLED);
678
679 if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
680 gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ));
681 }
682 if (vms->virt) {
683 gicc->vgic_interrupt = cpu_to_le32(PPI(ARCH_GIC_MAINT_IRQ));
684 }
685 }
686
687 if (vms->gic_version == 3) {
688 AcpiMadtGenericTranslator *gic_its;
689 int nb_redist_regions = virt_gicv3_redist_region_count(vms);
690 AcpiMadtGenericRedistributor *gicr = acpi_data_push(table_data,
691 sizeof *gicr);
692
693 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR;
694 gicr->length = sizeof(*gicr);
695 gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST].base);
696 gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST].size);
697
698 if (nb_redist_regions == 2) {
699 gicr = acpi_data_push(table_data, sizeof(*gicr));
700 gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR;
701 gicr->length = sizeof(*gicr);
702 gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST2].base);
703 gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST2].size);
704 }
705
706 if (its_class_name() && !vmc->no_its) {
707 gic_its = acpi_data_push(table_data, sizeof *gic_its);
708 gic_its->type = ACPI_APIC_GENERIC_TRANSLATOR;
709 gic_its->length = sizeof(*gic_its);
710 gic_its->translation_id = 0;
711 gic_its->base_address = cpu_to_le64(memmap[VIRT_GIC_ITS].base);
712 }
713 } else {
714 gic_msi = acpi_data_push(table_data, sizeof *gic_msi);
715 gic_msi->type = ACPI_APIC_GENERIC_MSI_FRAME;
716 gic_msi->length = sizeof(*gic_msi);
717 gic_msi->gic_msi_frame_id = 0;
718 gic_msi->base_address = cpu_to_le64(memmap[VIRT_GIC_V2M].base);
719 gic_msi->flags = cpu_to_le32(1);
720 gic_msi->spi_count = cpu_to_le16(NUM_GICV2M_SPIS);
721 gic_msi->spi_base = cpu_to_le16(irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE);
722 }
723
724 build_header(linker, table_data,
725 (void *)(table_data->data + madt_start), "APIC",
726 table_data->len - madt_start, 3, NULL, NULL);
727 }
728
729 /* FADT */
730 static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker,
731 VirtMachineState *vms, unsigned dsdt_tbl_offset)
732 {
733 /* ACPI v5.1 */
734 AcpiFadtData fadt = {
735 .rev = 5,
736 .minor_ver = 1,
737 .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI,
738 .xdsdt_tbl_offset = &dsdt_tbl_offset,
739 };
740
741 switch (vms->psci_conduit) {
742 case QEMU_PSCI_CONDUIT_DISABLED:
743 fadt.arm_boot_arch = 0;
744 break;
745 case QEMU_PSCI_CONDUIT_HVC:
746 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT |
747 ACPI_FADT_ARM_PSCI_USE_HVC;
748 break;
749 case QEMU_PSCI_CONDUIT_SMC:
750 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT;
751 break;
752 default:
753 g_assert_not_reached();
754 }
755
756 build_fadt(table_data, linker, &fadt, NULL, NULL);
757 }
758
759 /* DSDT */
760 static void
761 build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
762 {
763 Aml *scope, *dsdt;
764 const MemMapEntry *memmap = vms->memmap;
765 const int *irqmap = vms->irqmap;
766
767 dsdt = init_aml_allocator();
768 /* Reserve space for header */
769 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
770
771 /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware.
772 * While UEFI can use libfdt to disable the RTC device node in the DTB that
773 * it passes to the OS, it cannot modify AML. Therefore, we won't generate
774 * the RTC ACPI device at all when using UEFI.
775 */
776 scope = aml_scope("\\_SB");
777 acpi_dsdt_add_cpus(scope, vms->smp_cpus);
778 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART],
779 (irqmap[VIRT_UART] + ARM_SPI_BASE));
780 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
781 acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]);
782 acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
783 (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
784 acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE),
785 vms->highmem, vms->highmem_ecam);
786 acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO],
787 (irqmap[VIRT_GPIO] + ARM_SPI_BASE));
788 acpi_dsdt_add_power_button(scope);
789
790 aml_append(dsdt, scope);
791
792 /* copy AML table into ACPI tables blob and patch header there */
793 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
794 build_header(linker, table_data,
795 (void *)(table_data->data + table_data->len - dsdt->buf->len),
796 "DSDT", dsdt->buf->len, 2, NULL, NULL);
797 free_aml_allocator();
798 }
799
800 typedef
801 struct AcpiBuildState {
802 /* Copy of table in RAM (for patching). */
803 MemoryRegion *table_mr;
804 MemoryRegion *rsdp_mr;
805 MemoryRegion *linker_mr;
806 /* Is table patched? */
807 bool patched;
808 } AcpiBuildState;
809
810 static
811 void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
812 {
813 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
814 GArray *table_offsets;
815 unsigned dsdt, xsdt;
816 GArray *tables_blob = tables->table_data;
817
818 table_offsets = g_array_new(false, true /* clear */,
819 sizeof(uint32_t));
820
821 bios_linker_loader_alloc(tables->linker,
822 ACPI_BUILD_TABLE_FILE, tables_blob,
823 64, false /* high memory */);
824
825 /* DSDT is pointed to by FADT */
826 dsdt = tables_blob->len;
827 build_dsdt(tables_blob, tables->linker, vms);
828
829 /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */
830 acpi_add_table(table_offsets, tables_blob);
831 build_fadt_rev5(tables_blob, tables->linker, vms, dsdt);
832
833 acpi_add_table(table_offsets, tables_blob);
834 build_madt(tables_blob, tables->linker, vms);
835
836 acpi_add_table(table_offsets, tables_blob);
837 build_gtdt(tables_blob, tables->linker, vms);
838
839 acpi_add_table(table_offsets, tables_blob);
840 build_mcfg(tables_blob, tables->linker, vms);
841
842 acpi_add_table(table_offsets, tables_blob);
843 build_spcr(tables_blob, tables->linker, vms);
844
845 if (nb_numa_nodes > 0) {
846 acpi_add_table(table_offsets, tables_blob);
847 build_srat(tables_blob, tables->linker, vms);
848 if (have_numa_distance) {
849 acpi_add_table(table_offsets, tables_blob);
850 build_slit(tables_blob, tables->linker);
851 }
852 }
853
854 if (its_class_name() && !vmc->no_its) {
855 acpi_add_table(table_offsets, tables_blob);
856 build_iort(tables_blob, tables->linker, vms);
857 }
858
859 /* XSDT is pointed to by RSDP */
860 xsdt = tables_blob->len;
861 build_xsdt(tables_blob, tables->linker, table_offsets, NULL, NULL);
862
863 /* RSDP is in FSEG memory, so allocate it separately */
864 {
865 AcpiRsdpData rsdp_data = {
866 .revision = 2,
867 .oem_id = ACPI_BUILD_APPNAME6,
868 .xsdt_tbl_offset = &xsdt,
869 .rsdt_tbl_offset = NULL,
870 };
871 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
872 }
873
874 /* Cleanup memory that's no longer used. */
875 g_array_free(table_offsets, true);
876 }
877
878 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
879 {
880 uint32_t size = acpi_data_len(data);
881
882 /* Make sure RAM size is correct - in case it got changed
883 * e.g. by migration */
884 memory_region_ram_resize(mr, size, &error_abort);
885
886 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
887 memory_region_set_dirty(mr, 0, size);
888 }
889
890 static void virt_acpi_build_update(void *build_opaque)
891 {
892 AcpiBuildState *build_state = build_opaque;
893 AcpiBuildTables tables;
894
895 /* No state to update or already patched? Nothing to do. */
896 if (!build_state || build_state->patched) {
897 return;
898 }
899 build_state->patched = true;
900
901 acpi_build_tables_init(&tables);
902
903 virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables);
904
905 acpi_ram_update(build_state->table_mr, tables.table_data);
906 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
907 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
908
909 acpi_build_tables_cleanup(&tables, true);
910 }
911
912 static void virt_acpi_build_reset(void *build_opaque)
913 {
914 AcpiBuildState *build_state = build_opaque;
915 build_state->patched = false;
916 }
917
918 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
919 GArray *blob, const char *name,
920 uint64_t max_size)
921 {
922 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
923 name, virt_acpi_build_update, build_state, NULL, true);
924 }
925
926 static const VMStateDescription vmstate_virt_acpi_build = {
927 .name = "virt_acpi_build",
928 .version_id = 1,
929 .minimum_version_id = 1,
930 .fields = (VMStateField[]) {
931 VMSTATE_BOOL(patched, AcpiBuildState),
932 VMSTATE_END_OF_LIST()
933 },
934 };
935
936 void virt_acpi_setup(VirtMachineState *vms)
937 {
938 AcpiBuildTables tables;
939 AcpiBuildState *build_state;
940
941 if (!vms->fw_cfg) {
942 trace_virt_acpi_setup();
943 return;
944 }
945
946 if (!acpi_enabled) {
947 trace_virt_acpi_setup();
948 return;
949 }
950
951 build_state = g_malloc0(sizeof *build_state);
952
953 acpi_build_tables_init(&tables);
954 virt_acpi_build(vms, &tables);
955
956 /* Now expose it all to Guest */
957 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
958 ACPI_BUILD_TABLE_FILE,
959 ACPI_BUILD_TABLE_MAX_SIZE);
960 assert(build_state->table_mr != NULL);
961
962 build_state->linker_mr =
963 acpi_add_rom_blob(build_state, tables.linker->cmd_blob,
964 "etc/table-loader", 0);
965
966 fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data,
967 acpi_data_len(tables.tcpalog));
968
969 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
970 ACPI_BUILD_RSDP_FILE, 0);
971
972 qemu_register_reset(virt_acpi_build_reset, build_state);
973 virt_acpi_build_reset(build_state);
974 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state);
975
976 /* Cleanup tables but don't free the memory: we track it
977 * in build_state.
978 */
979 acpi_build_tables_cleanup(&tables, false);
980 }
AR7 emulation for QEMU