4 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
21 #include "qemu/osdep.h"
22 #include "qemu/qemu-print.h"
23 #include "qemu-common.h"
24 #include "target/arm/idau.h"
25 #include "qemu/module.h"
26 #include "qapi/error.h"
27 #include "qapi/visitor.h"
29 #include "internals.h"
30 #include "exec/exec-all.h"
31 #include "hw/qdev-properties.h"
32 #if !defined(CONFIG_USER_ONLY)
33 #include "hw/loader.h"
34 #include "hw/boards.h"
36 #include "sysemu/sysemu.h"
37 #include "sysemu/tcg.h"
38 #include "sysemu/hw_accel.h"
40 #include "disas/capstone.h"
41 #include "fpu/softfloat.h"
43 static void arm_cpu_set_pc(CPUState
*cs
, vaddr value
)
45 ARMCPU
*cpu
= ARM_CPU(cs
);
46 CPUARMState
*env
= &cpu
->env
;
52 env
->regs
[15] = value
& ~1;
53 env
->thumb
= value
& 1;
57 static void arm_cpu_synchronize_from_tb(CPUState
*cs
, TranslationBlock
*tb
)
59 ARMCPU
*cpu
= ARM_CPU(cs
);
60 CPUARMState
*env
= &cpu
->env
;
63 * It's OK to look at env for the current mode here, because it's
64 * never possible for an AArch64 TB to chain to an AArch32 TB.
69 env
->regs
[15] = tb
->pc
;
73 static bool arm_cpu_has_work(CPUState
*cs
)
75 ARMCPU
*cpu
= ARM_CPU(cs
);
77 return (cpu
->power_state
!= PSCI_OFF
)
78 && cs
->interrupt_request
&
79 (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
80 | CPU_INTERRUPT_VFIQ
| CPU_INTERRUPT_VIRQ
81 | CPU_INTERRUPT_EXITTB
);
84 void arm_register_pre_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
87 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
90 entry
->opaque
= opaque
;
92 QLIST_INSERT_HEAD(&cpu
->pre_el_change_hooks
, entry
, node
);
95 void arm_register_el_change_hook(ARMCPU
*cpu
, ARMELChangeHookFn
*hook
,
98 ARMELChangeHook
*entry
= g_new0(ARMELChangeHook
, 1);
101 entry
->opaque
= opaque
;
103 QLIST_INSERT_HEAD(&cpu
->el_change_hooks
, entry
, node
);
106 static void cp_reg_reset(gpointer key
, gpointer value
, gpointer opaque
)
108 /* Reset a single ARMCPRegInfo register */
109 ARMCPRegInfo
*ri
= value
;
110 ARMCPU
*cpu
= opaque
;
112 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
)) {
117 ri
->resetfn(&cpu
->env
, ri
);
121 /* A zero offset is never possible as it would be regs[0]
122 * so we use it to indicate that reset is being handled elsewhere.
123 * This is basically only used for fields in non-core coprocessors
124 * (like the pxa2xx ones).
126 if (!ri
->fieldoffset
) {
130 if (cpreg_field_is_64bit(ri
)) {
131 CPREG_FIELD64(&cpu
->env
, ri
) = ri
->resetvalue
;
133 CPREG_FIELD32(&cpu
->env
, ri
) = ri
->resetvalue
;
137 static void cp_reg_check_reset(gpointer key
, gpointer value
, gpointer opaque
)
139 /* Purely an assertion check: we've already done reset once,
140 * so now check that running the reset for the cpreg doesn't
141 * change its value. This traps bugs where two different cpregs
142 * both try to reset the same state field but to different values.
144 ARMCPRegInfo
*ri
= value
;
145 ARMCPU
*cpu
= opaque
;
146 uint64_t oldvalue
, newvalue
;
148 if (ri
->type
& (ARM_CP_SPECIAL
| ARM_CP_ALIAS
| ARM_CP_NO_RAW
)) {
152 oldvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
153 cp_reg_reset(key
, value
, opaque
);
154 newvalue
= read_raw_cp_reg(&cpu
->env
, ri
);
155 assert(oldvalue
== newvalue
);
158 static void arm_cpu_reset(DeviceState
*dev
)
160 CPUState
*s
= CPU(dev
);
161 ARMCPU
*cpu
= ARM_CPU(s
);
162 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(cpu
);
163 CPUARMState
*env
= &cpu
->env
;
165 acc
->parent_reset(dev
);
167 memset(env
, 0, offsetof(CPUARMState
, end_reset_fields
));
169 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_reset
, cpu
);
170 g_hash_table_foreach(cpu
->cp_regs
, cp_reg_check_reset
, cpu
);
172 env
->vfp
.xregs
[ARM_VFP_FPSID
] = cpu
->reset_fpsid
;
173 env
->vfp
.xregs
[ARM_VFP_MVFR0
] = cpu
->isar
.mvfr0
;
174 env
->vfp
.xregs
[ARM_VFP_MVFR1
] = cpu
->isar
.mvfr1
;
175 env
->vfp
.xregs
[ARM_VFP_MVFR2
] = cpu
->isar
.mvfr2
;
177 cpu
->power_state
= cpu
->start_powered_off
? PSCI_OFF
: PSCI_ON
;
178 s
->halted
= cpu
->start_powered_off
;
180 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
181 env
->iwmmxt
.cregs
[ARM_IWMMXT_wCID
] = 0x69051000 | 'Q';
184 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
185 /* 64 bit CPUs always start in 64 bit mode */
187 #if defined(CONFIG_USER_ONLY)
188 env
->pstate
= PSTATE_MODE_EL0t
;
189 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
190 env
->cp15
.sctlr_el
[1] |= SCTLR_UCT
| SCTLR_UCI
| SCTLR_DZE
;
191 /* Enable all PAC keys. */
192 env
->cp15
.sctlr_el
[1] |= (SCTLR_EnIA
| SCTLR_EnIB
|
193 SCTLR_EnDA
| SCTLR_EnDB
);
194 /* and to the FP/Neon instructions */
195 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 2, 3);
196 /* and to the SVE instructions */
197 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 16, 2, 3);
198 /* with reasonable vector length */
199 if (cpu_isar_feature(aa64_sve
, cpu
)) {
200 env
->vfp
.zcr_el
[1] = MIN(cpu
->sve_max_vq
- 1, 3);
203 * Enable TBI0 and TBI1. While the real kernel only enables TBI0,
204 * turning on both here will produce smaller code and otherwise
205 * make no difference to the user-level emulation.
207 env
->cp15
.tcr_el
[1].raw_tcr
= (3ULL << 37);
209 /* Reset into the highest available EL */
210 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
211 env
->pstate
= PSTATE_MODE_EL3h
;
212 } else if (arm_feature(env
, ARM_FEATURE_EL2
)) {
213 env
->pstate
= PSTATE_MODE_EL2h
;
215 env
->pstate
= PSTATE_MODE_EL1h
;
217 env
->pc
= cpu
->rvbar
;
220 #if defined(CONFIG_USER_ONLY)
221 /* Userspace expects access to cp10 and cp11 for FP/Neon */
222 env
->cp15
.cpacr_el1
= deposit64(env
->cp15
.cpacr_el1
, 20, 4, 0xf);
226 #if defined(CONFIG_USER_ONLY)
227 env
->uncached_cpsr
= ARM_CPU_MODE_USR
;
228 /* For user mode we must enable access to coprocessors */
229 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 1 << 30;
230 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
231 env
->cp15
.c15_cpar
= 3;
232 } else if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
233 env
->cp15
.c15_cpar
= 1;
238 * If the highest available EL is EL2, AArch32 will start in Hyp
239 * mode; otherwise it starts in SVC. Note that if we start in
240 * AArch64 then these values in the uncached_cpsr will be ignored.
242 if (arm_feature(env
, ARM_FEATURE_EL2
) &&
243 !arm_feature(env
, ARM_FEATURE_EL3
)) {
244 env
->uncached_cpsr
= ARM_CPU_MODE_HYP
;
246 env
->uncached_cpsr
= ARM_CPU_MODE_SVC
;
248 env
->daif
= PSTATE_D
| PSTATE_A
| PSTATE_I
| PSTATE_F
;
250 if (arm_feature(env
, ARM_FEATURE_M
)) {
251 uint32_t initial_msp
; /* Loaded from 0x0 */
252 uint32_t initial_pc
; /* Loaded from 0x4 */
256 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
257 env
->v7m
.secure
= true;
259 /* This bit resets to 0 if security is supported, but 1 if
260 * it is not. The bit is not present in v7M, but we set it
261 * here so we can avoid having to make checks on it conditional
262 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
264 env
->v7m
.aircr
= R_V7M_AIRCR_BFHFNMINS_MASK
;
266 * Set NSACR to indicate "NS access permitted to everything";
267 * this avoids having to have all the tests of it being
268 * conditional on ARM_FEATURE_M_SECURITY. Note also that from
269 * v8.1M the guest-visible value of NSACR in a CPU without the
270 * Security Extension is 0xcff.
272 env
->v7m
.nsacr
= 0xcff;
275 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
276 * that it resets to 1, so QEMU always does that rather than making
277 * it dependent on CPU model. In v8M it is RES1.
279 env
->v7m
.ccr
[M_REG_NS
] = R_V7M_CCR_STKALIGN_MASK
;
280 env
->v7m
.ccr
[M_REG_S
] = R_V7M_CCR_STKALIGN_MASK
;
281 if (arm_feature(env
, ARM_FEATURE_V8
)) {
282 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
283 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
284 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_NONBASETHRDENA_MASK
;
286 if (!arm_feature(env
, ARM_FEATURE_M_MAIN
)) {
287 env
->v7m
.ccr
[M_REG_NS
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
288 env
->v7m
.ccr
[M_REG_S
] |= R_V7M_CCR_UNALIGN_TRP_MASK
;
291 if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
292 env
->v7m
.fpccr
[M_REG_NS
] = R_V7M_FPCCR_ASPEN_MASK
;
293 env
->v7m
.fpccr
[M_REG_S
] = R_V7M_FPCCR_ASPEN_MASK
|
294 R_V7M_FPCCR_LSPEN_MASK
| R_V7M_FPCCR_S_MASK
;
296 /* Unlike A/R profile, M profile defines the reset LR value */
297 env
->regs
[14] = 0xffffffff;
299 env
->v7m
.vecbase
[M_REG_S
] = cpu
->init_svtor
& 0xffffff80;
301 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
302 vecbase
= env
->v7m
.vecbase
[env
->v7m
.secure
];
303 rom
= rom_ptr(vecbase
, 8);
305 /* Address zero is covered by ROM which hasn't yet been
306 * copied into physical memory.
308 initial_msp
= ldl_p(rom
);
309 initial_pc
= ldl_p(rom
+ 4);
311 /* Address zero not covered by a ROM blob, or the ROM blob
312 * is in non-modifiable memory and this is a second reset after
313 * it got copied into memory. In the latter case, rom_ptr
314 * will return a NULL pointer and we should use ldl_phys instead.
316 initial_msp
= ldl_phys(s
->as
, vecbase
);
317 initial_pc
= ldl_phys(s
->as
, vecbase
+ 4);
320 env
->regs
[13] = initial_msp
& 0xFFFFFFFC;
321 env
->regs
[15] = initial_pc
& ~1;
322 env
->thumb
= initial_pc
& 1;
325 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
326 * executing as AArch32 then check if highvecs are enabled and
327 * adjust the PC accordingly.
329 if (A32_BANKED_CURRENT_REG_GET(env
, sctlr
) & SCTLR_V
) {
330 env
->regs
[15] = 0xFFFF0000;
333 /* M profile requires that reset clears the exclusive monitor;
334 * A profile does not, but clearing it makes more sense than having it
335 * set with an exclusive access on address zero.
337 arm_clear_exclusive(env
);
339 env
->vfp
.xregs
[ARM_VFP_FPEXC
] = 0;
342 if (arm_feature(env
, ARM_FEATURE_PMSA
)) {
343 if (cpu
->pmsav7_dregion
> 0) {
344 if (arm_feature(env
, ARM_FEATURE_V8
)) {
345 memset(env
->pmsav8
.rbar
[M_REG_NS
], 0,
346 sizeof(*env
->pmsav8
.rbar
[M_REG_NS
])
347 * cpu
->pmsav7_dregion
);
348 memset(env
->pmsav8
.rlar
[M_REG_NS
], 0,
349 sizeof(*env
->pmsav8
.rlar
[M_REG_NS
])
350 * cpu
->pmsav7_dregion
);
351 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
352 memset(env
->pmsav8
.rbar
[M_REG_S
], 0,
353 sizeof(*env
->pmsav8
.rbar
[M_REG_S
])
354 * cpu
->pmsav7_dregion
);
355 memset(env
->pmsav8
.rlar
[M_REG_S
], 0,
356 sizeof(*env
->pmsav8
.rlar
[M_REG_S
])
357 * cpu
->pmsav7_dregion
);
359 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
360 memset(env
->pmsav7
.drbar
, 0,
361 sizeof(*env
->pmsav7
.drbar
) * cpu
->pmsav7_dregion
);
362 memset(env
->pmsav7
.drsr
, 0,
363 sizeof(*env
->pmsav7
.drsr
) * cpu
->pmsav7_dregion
);
364 memset(env
->pmsav7
.dracr
, 0,
365 sizeof(*env
->pmsav7
.dracr
) * cpu
->pmsav7_dregion
);
368 env
->pmsav7
.rnr
[M_REG_NS
] = 0;
369 env
->pmsav7
.rnr
[M_REG_S
] = 0;
370 env
->pmsav8
.mair0
[M_REG_NS
] = 0;
371 env
->pmsav8
.mair0
[M_REG_S
] = 0;
372 env
->pmsav8
.mair1
[M_REG_NS
] = 0;
373 env
->pmsav8
.mair1
[M_REG_S
] = 0;
376 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
377 if (cpu
->sau_sregion
> 0) {
378 memset(env
->sau
.rbar
, 0, sizeof(*env
->sau
.rbar
) * cpu
->sau_sregion
);
379 memset(env
->sau
.rlar
, 0, sizeof(*env
->sau
.rlar
) * cpu
->sau_sregion
);
382 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
383 * the Cortex-M33 does.
388 set_flush_to_zero(1, &env
->vfp
.standard_fp_status
);
389 set_flush_inputs_to_zero(1, &env
->vfp
.standard_fp_status
);
390 set_default_nan_mode(1, &env
->vfp
.standard_fp_status
);
391 set_float_detect_tininess(float_tininess_before_rounding
,
392 &env
->vfp
.fp_status
);
393 set_float_detect_tininess(float_tininess_before_rounding
,
394 &env
->vfp
.standard_fp_status
);
395 set_float_detect_tininess(float_tininess_before_rounding
,
396 &env
->vfp
.fp_status_f16
);
397 #ifndef CONFIG_USER_ONLY
399 kvm_arm_reset_vcpu(cpu
);
403 hw_breakpoint_update_all(cpu
);
404 hw_watchpoint_update_all(cpu
);
405 arm_rebuild_hflags(env
);
408 static inline bool arm_excp_unmasked(CPUState
*cs
, unsigned int excp_idx
,
409 unsigned int target_el
,
410 unsigned int cur_el
, bool secure
,
413 CPUARMState
*env
= cs
->env_ptr
;
414 bool pstate_unmasked
;
415 bool unmasked
= false;
418 * Don't take exceptions if they target a lower EL.
419 * This check should catch any exceptions that would not be taken
422 if (cur_el
> target_el
) {
428 pstate_unmasked
= !(env
->daif
& PSTATE_F
);
432 pstate_unmasked
= !(env
->daif
& PSTATE_I
);
436 if (secure
|| !(hcr_el2
& HCR_FMO
) || (hcr_el2
& HCR_TGE
)) {
437 /* VFIQs are only taken when hypervized and non-secure. */
440 return !(env
->daif
& PSTATE_F
);
442 if (secure
|| !(hcr_el2
& HCR_IMO
) || (hcr_el2
& HCR_TGE
)) {
443 /* VIRQs are only taken when hypervized and non-secure. */
446 return !(env
->daif
& PSTATE_I
);
448 g_assert_not_reached();
452 * Use the target EL, current execution state and SCR/HCR settings to
453 * determine whether the corresponding CPSR bit is used to mask the
456 if ((target_el
> cur_el
) && (target_el
!= 1)) {
457 /* Exceptions targeting a higher EL may not be maskable */
458 if (arm_feature(env
, ARM_FEATURE_AARCH64
)) {
460 * 64-bit masking rules are simple: exceptions to EL3
461 * can't be masked, and exceptions to EL2 can only be
462 * masked from Secure state. The HCR and SCR settings
463 * don't affect the masking logic, only the interrupt routing.
465 if (target_el
== 3 || !secure
) {
470 * The old 32-bit-only environment has a more complicated
471 * masking setup. HCR and SCR bits not only affect interrupt
472 * routing but also change the behaviour of masking.
479 * If FIQs are routed to EL3 or EL2 then there are cases where
480 * we override the CPSR.F in determining if the exception is
481 * masked or not. If neither of these are set then we fall back
482 * to the CPSR.F setting otherwise we further assess the state
485 hcr
= hcr_el2
& HCR_FMO
;
486 scr
= (env
->cp15
.scr_el3
& SCR_FIQ
);
489 * When EL3 is 32-bit, the SCR.FW bit controls whether the
490 * CPSR.F bit masks FIQ interrupts when taken in non-secure
491 * state. If SCR.FW is set then FIQs can be masked by CPSR.F
492 * when non-secure but only when FIQs are only routed to EL3.
494 scr
= scr
&& !((env
->cp15
.scr_el3
& SCR_FW
) && !hcr
);
498 * When EL3 execution state is 32-bit, if HCR.IMO is set then
499 * we may override the CPSR.I masking when in non-secure state.
500 * The SCR.IRQ setting has already been taken into consideration
501 * when setting the target EL, so it does not have a further
504 hcr
= hcr_el2
& HCR_IMO
;
508 g_assert_not_reached();
511 if ((scr
|| hcr
) && !secure
) {
518 * The PSTATE bits only mask the interrupt if we have not overriden the
521 return unmasked
|| pstate_unmasked
;
524 bool arm_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
526 CPUClass
*cc
= CPU_GET_CLASS(cs
);
527 CPUARMState
*env
= cs
->env_ptr
;
528 uint32_t cur_el
= arm_current_el(env
);
529 bool secure
= arm_is_secure(env
);
530 uint64_t hcr_el2
= arm_hcr_el2_eff(env
);
534 /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */
536 if (interrupt_request
& CPU_INTERRUPT_FIQ
) {
538 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
539 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
540 cur_el
, secure
, hcr_el2
)) {
544 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
546 target_el
= arm_phys_excp_target_el(cs
, excp_idx
, cur_el
, secure
);
547 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
548 cur_el
, secure
, hcr_el2
)) {
552 if (interrupt_request
& CPU_INTERRUPT_VIRQ
) {
553 excp_idx
= EXCP_VIRQ
;
555 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
556 cur_el
, secure
, hcr_el2
)) {
560 if (interrupt_request
& CPU_INTERRUPT_VFIQ
) {
561 excp_idx
= EXCP_VFIQ
;
563 if (arm_excp_unmasked(cs
, excp_idx
, target_el
,
564 cur_el
, secure
, hcr_el2
)) {
571 cs
->exception_index
= excp_idx
;
572 env
->exception
.target_el
= target_el
;
573 cc
->do_interrupt(cs
);
577 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
578 static bool arm_v7m_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
580 CPUClass
*cc
= CPU_GET_CLASS(cs
);
581 ARMCPU
*cpu
= ARM_CPU(cs
);
582 CPUARMState
*env
= &cpu
->env
;
585 /* ARMv7-M interrupt masking works differently than -A or -R.
586 * There is no FIQ/IRQ distinction. Instead of I and F bits
587 * masking FIQ and IRQ interrupts, an exception is taken only
588 * if it is higher priority than the current execution priority
589 * (which depends on state like BASEPRI, FAULTMASK and the
590 * currently active exception).
592 if (interrupt_request
& CPU_INTERRUPT_HARD
593 && (armv7m_nvic_can_take_pending_exception(env
->nvic
))) {
594 cs
->exception_index
= EXCP_IRQ
;
595 cc
->do_interrupt(cs
);
602 void arm_cpu_update_virq(ARMCPU
*cpu
)
605 * Update the interrupt level for VIRQ, which is the logical OR of
606 * the HCR_EL2.VI bit and the input line level from the GIC.
608 CPUARMState
*env
= &cpu
->env
;
609 CPUState
*cs
= CPU(cpu
);
611 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VI
) ||
612 (env
->irq_line_state
& CPU_INTERRUPT_VIRQ
);
614 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VIRQ
) != 0)) {
616 cpu_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
618 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VIRQ
);
623 void arm_cpu_update_vfiq(ARMCPU
*cpu
)
626 * Update the interrupt level for VFIQ, which is the logical OR of
627 * the HCR_EL2.VF bit and the input line level from the GIC.
629 CPUARMState
*env
= &cpu
->env
;
630 CPUState
*cs
= CPU(cpu
);
632 bool new_state
= (env
->cp15
.hcr_el2
& HCR_VF
) ||
633 (env
->irq_line_state
& CPU_INTERRUPT_VFIQ
);
635 if (new_state
!= ((cs
->interrupt_request
& CPU_INTERRUPT_VFIQ
) != 0)) {
637 cpu_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
639 cpu_reset_interrupt(cs
, CPU_INTERRUPT_VFIQ
);
644 #ifndef CONFIG_USER_ONLY
645 static void arm_cpu_set_irq(void *opaque
, int irq
, int level
)
647 ARMCPU
*cpu
= opaque
;
648 CPUARMState
*env
= &cpu
->env
;
649 CPUState
*cs
= CPU(cpu
);
650 static const int mask
[] = {
651 [ARM_CPU_IRQ
] = CPU_INTERRUPT_HARD
,
652 [ARM_CPU_FIQ
] = CPU_INTERRUPT_FIQ
,
653 [ARM_CPU_VIRQ
] = CPU_INTERRUPT_VIRQ
,
654 [ARM_CPU_VFIQ
] = CPU_INTERRUPT_VFIQ
658 env
->irq_line_state
|= mask
[irq
];
660 env
->irq_line_state
&= ~mask
[irq
];
665 assert(arm_feature(env
, ARM_FEATURE_EL2
));
666 arm_cpu_update_virq(cpu
);
669 assert(arm_feature(env
, ARM_FEATURE_EL2
));
670 arm_cpu_update_vfiq(cpu
);
675 cpu_interrupt(cs
, mask
[irq
]);
677 cpu_reset_interrupt(cs
, mask
[irq
]);
681 g_assert_not_reached();
685 static void arm_cpu_kvm_set_irq(void *opaque
, int irq
, int level
)
688 ARMCPU
*cpu
= opaque
;
689 CPUARMState
*env
= &cpu
->env
;
690 CPUState
*cs
= CPU(cpu
);
691 uint32_t linestate_bit
;
696 irq_id
= KVM_ARM_IRQ_CPU_IRQ
;
697 linestate_bit
= CPU_INTERRUPT_HARD
;
700 irq_id
= KVM_ARM_IRQ_CPU_FIQ
;
701 linestate_bit
= CPU_INTERRUPT_FIQ
;
704 g_assert_not_reached();
708 env
->irq_line_state
|= linestate_bit
;
710 env
->irq_line_state
&= ~linestate_bit
;
712 kvm_arm_set_irq(cs
->cpu_index
, KVM_ARM_IRQ_TYPE_CPU
, irq_id
, !!level
);
716 static bool arm_cpu_virtio_is_big_endian(CPUState
*cs
)
718 ARMCPU
*cpu
= ARM_CPU(cs
);
719 CPUARMState
*env
= &cpu
->env
;
721 cpu_synchronize_state(cs
);
722 return arm_cpu_data_is_big_endian(env
);
727 static inline void set_feature(CPUARMState
*env
, int feature
)
729 env
->features
|= 1ULL << feature
;
732 static inline void unset_feature(CPUARMState
*env
, int feature
)
734 env
->features
&= ~(1ULL << feature
);
738 print_insn_thumb1(bfd_vma pc
, disassemble_info
*info
)
740 return print_insn_arm(pc
| 1, info
);
743 static void arm_disas_set_info(CPUState
*cpu
, disassemble_info
*info
)
745 ARMCPU
*ac
= ARM_CPU(cpu
);
746 CPUARMState
*env
= &ac
->env
;
750 /* We might not be compiled with the A64 disassembler
751 * because it needs a C++ compiler. Leave print_insn
752 * unset in this case to use the caller default behaviour.
754 #if defined(CONFIG_ARM_A64_DIS)
755 info
->print_insn
= print_insn_arm_a64
;
757 info
->cap_arch
= CS_ARCH_ARM64
;
758 info
->cap_insn_unit
= 4;
759 info
->cap_insn_split
= 4;
763 info
->print_insn
= print_insn_thumb1
;
764 info
->cap_insn_unit
= 2;
765 info
->cap_insn_split
= 4;
766 cap_mode
= CS_MODE_THUMB
;
768 info
->print_insn
= print_insn_arm
;
769 info
->cap_insn_unit
= 4;
770 info
->cap_insn_split
= 4;
771 cap_mode
= CS_MODE_ARM
;
773 if (arm_feature(env
, ARM_FEATURE_V8
)) {
774 cap_mode
|= CS_MODE_V8
;
776 if (arm_feature(env
, ARM_FEATURE_M
)) {
777 cap_mode
|= CS_MODE_MCLASS
;
779 info
->cap_arch
= CS_ARCH_ARM
;
780 info
->cap_mode
= cap_mode
;
783 sctlr_b
= arm_sctlr_b(env
);
784 if (bswap_code(sctlr_b
)) {
785 #ifdef TARGET_WORDS_BIGENDIAN
786 info
->endian
= BFD_ENDIAN_LITTLE
;
788 info
->endian
= BFD_ENDIAN_BIG
;
791 info
->flags
&= ~INSN_ARM_BE32
;
792 #ifndef CONFIG_USER_ONLY
794 info
->flags
|= INSN_ARM_BE32
;
799 #ifdef TARGET_AARCH64
801 static void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
803 ARMCPU
*cpu
= ARM_CPU(cs
);
804 CPUARMState
*env
= &cpu
->env
;
805 uint32_t psr
= pstate_read(env
);
807 int el
= arm_current_el(env
);
808 const char *ns_status
;
810 qemu_fprintf(f
, " PC=%016" PRIx64
" ", env
->pc
);
811 for (i
= 0; i
< 32; i
++) {
813 qemu_fprintf(f
, " SP=%016" PRIx64
"\n", env
->xregs
[i
]);
815 qemu_fprintf(f
, "X%02d=%016" PRIx64
"%s", i
, env
->xregs
[i
],
816 (i
+ 2) % 3 ? " " : "\n");
820 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
821 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
825 qemu_fprintf(f
, "PSTATE=%08x %c%c%c%c %sEL%d%c",
827 psr
& PSTATE_N
? 'N' : '-',
828 psr
& PSTATE_Z
? 'Z' : '-',
829 psr
& PSTATE_C
? 'C' : '-',
830 psr
& PSTATE_V
? 'V' : '-',
833 psr
& PSTATE_SP
? 'h' : 't');
835 if (cpu_isar_feature(aa64_bti
, cpu
)) {
836 qemu_fprintf(f
, " BTYPE=%d", (psr
& PSTATE_BTYPE
) >> 10);
838 if (!(flags
& CPU_DUMP_FPU
)) {
839 qemu_fprintf(f
, "\n");
842 if (fp_exception_el(env
, el
) != 0) {
843 qemu_fprintf(f
, " FPU disabled\n");
846 qemu_fprintf(f
, " FPCR=%08x FPSR=%08x\n",
847 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
849 if (cpu_isar_feature(aa64_sve
, cpu
) && sve_exception_el(env
, el
) == 0) {
850 int j
, zcr_len
= sve_zcr_len_for_el(env
, el
);
852 for (i
= 0; i
<= FFR_PRED_NUM
; i
++) {
854 if (i
== FFR_PRED_NUM
) {
855 qemu_fprintf(f
, "FFR=");
856 /* It's last, so end the line. */
859 qemu_fprintf(f
, "P%02d=", i
);
872 /* More than one quadword per predicate. */
877 for (j
= zcr_len
/ 4; j
>= 0; j
--) {
879 if (j
* 4 + 4 <= zcr_len
+ 1) {
882 digits
= (zcr_len
% 4 + 1) * 4;
884 qemu_fprintf(f
, "%0*" PRIx64
"%s", digits
,
885 env
->vfp
.pregs
[i
].p
[j
],
886 j
? ":" : eol
? "\n" : " ");
890 for (i
= 0; i
< 32; i
++) {
892 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
"%s",
893 i
, env
->vfp
.zregs
[i
].d
[1],
894 env
->vfp
.zregs
[i
].d
[0], i
& 1 ? "\n" : " ");
895 } else if (zcr_len
== 1) {
896 qemu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
897 ":%016" PRIx64
":%016" PRIx64
"\n",
898 i
, env
->vfp
.zregs
[i
].d
[3], env
->vfp
.zregs
[i
].d
[2],
899 env
->vfp
.zregs
[i
].d
[1], env
->vfp
.zregs
[i
].d
[0]);
901 for (j
= zcr_len
; j
>= 0; j
--) {
902 bool odd
= (zcr_len
- j
) % 2 != 0;
904 qemu_fprintf(f
, "Z%02d[%x-%x]=", i
, j
, j
- 1);
907 qemu_fprintf(f
, " [%x-%x]=", j
, j
- 1);
909 qemu_fprintf(f
, " [%x]=", j
);
912 qemu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%s",
913 env
->vfp
.zregs
[i
].d
[j
* 2 + 1],
914 env
->vfp
.zregs
[i
].d
[j
* 2],
915 odd
|| j
== 0 ? "\n" : ":");
920 for (i
= 0; i
< 32; i
++) {
921 uint64_t *q
= aa64_vfp_qreg(env
, i
);
922 qemu_fprintf(f
, "Q%02d=%016" PRIx64
":%016" PRIx64
"%s",
923 i
, q
[1], q
[0], (i
& 1 ? "\n" : " "));
930 static inline void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
932 g_assert_not_reached();
937 static void arm_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
939 ARMCPU
*cpu
= ARM_CPU(cs
);
940 CPUARMState
*env
= &cpu
->env
;
944 aarch64_cpu_dump_state(cs
, f
, flags
);
948 for (i
= 0; i
< 16; i
++) {
949 qemu_fprintf(f
, "R%02d=%08x", i
, env
->regs
[i
]);
951 qemu_fprintf(f
, "\n");
953 qemu_fprintf(f
, " ");
957 if (arm_feature(env
, ARM_FEATURE_M
)) {
958 uint32_t xpsr
= xpsr_read(env
);
960 const char *ns_status
= "";
962 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
963 ns_status
= env
->v7m
.secure
? "S " : "NS ";
966 if (xpsr
& XPSR_EXCP
) {
969 if (env
->v7m
.control
[env
->v7m
.secure
] & R_V7M_CONTROL_NPRIV_MASK
) {
970 mode
= "unpriv-thread";
972 mode
= "priv-thread";
976 qemu_fprintf(f
, "XPSR=%08x %c%c%c%c %c %s%s\n",
978 xpsr
& XPSR_N
? 'N' : '-',
979 xpsr
& XPSR_Z
? 'Z' : '-',
980 xpsr
& XPSR_C
? 'C' : '-',
981 xpsr
& XPSR_V
? 'V' : '-',
982 xpsr
& XPSR_T
? 'T' : 'A',
986 uint32_t psr
= cpsr_read(env
);
987 const char *ns_status
= "";
989 if (arm_feature(env
, ARM_FEATURE_EL3
) &&
990 (psr
& CPSR_M
) != ARM_CPU_MODE_MON
) {
991 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
994 qemu_fprintf(f
, "PSR=%08x %c%c%c%c %c %s%s%d\n",
996 psr
& CPSR_N
? 'N' : '-',
997 psr
& CPSR_Z
? 'Z' : '-',
998 psr
& CPSR_C
? 'C' : '-',
999 psr
& CPSR_V
? 'V' : '-',
1000 psr
& CPSR_T
? 'T' : 'A',
1002 aarch32_mode_name(psr
), (psr
& 0x10) ? 32 : 26);
1005 if (flags
& CPU_DUMP_FPU
) {
1007 if (cpu_isar_feature(aa32_simd_r32
, cpu
)) {
1009 } else if (cpu_isar_feature(aa32_vfp_simd
, cpu
)) {
1012 for (i
= 0; i
< numvfpregs
; i
++) {
1013 uint64_t v
= *aa32_vfp_dreg(env
, i
);
1014 qemu_fprintf(f
, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64
"\n",
1016 i
* 2 + 1, (uint32_t)(v
>> 32),
1019 qemu_fprintf(f
, "FPSCR: %08x\n", vfp_get_fpscr(env
));
1023 uint64_t arm_cpu_mp_affinity(int idx
, uint8_t clustersz
)
1025 uint32_t Aff1
= idx
/ clustersz
;
1026 uint32_t Aff0
= idx
% clustersz
;
1027 return (Aff1
<< ARM_AFF1_SHIFT
) | Aff0
;
1030 static void cpreg_hashtable_data_destroy(gpointer data
)
1033 * Destroy function for cpu->cp_regs hashtable data entries.
1034 * We must free the name string because it was g_strdup()ed in
1035 * add_cpreg_to_hashtable(). It's OK to cast away the 'const'
1036 * from r->name because we know we definitely allocated it.
1038 ARMCPRegInfo
*r
= data
;
1040 g_free((void *)r
->name
);
1044 static void arm_cpu_initfn(Object
*obj
)
1046 ARMCPU
*cpu
= ARM_CPU(obj
);
1048 cpu_set_cpustate_pointers(cpu
);
1049 cpu
->cp_regs
= g_hash_table_new_full(g_int_hash
, g_int_equal
,
1050 g_free
, cpreg_hashtable_data_destroy
);
1052 QLIST_INIT(&cpu
->pre_el_change_hooks
);
1053 QLIST_INIT(&cpu
->el_change_hooks
);
1055 #ifndef CONFIG_USER_ONLY
1056 /* Our inbound IRQ and FIQ lines */
1057 if (kvm_enabled()) {
1058 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
1059 * the same interface as non-KVM CPUs.
1061 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_kvm_set_irq
, 4);
1063 qdev_init_gpio_in(DEVICE(cpu
), arm_cpu_set_irq
, 4);
1066 qdev_init_gpio_out(DEVICE(cpu
), cpu
->gt_timer_outputs
,
1067 ARRAY_SIZE(cpu
->gt_timer_outputs
));
1069 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->gicv3_maintenance_interrupt
,
1070 "gicv3-maintenance-interrupt", 1);
1071 qdev_init_gpio_out_named(DEVICE(cpu
), &cpu
->pmu_interrupt
,
1072 "pmu-interrupt", 1);
1075 /* DTB consumers generally don't in fact care what the 'compatible'
1076 * string is, so always provide some string and trust that a hypothetical
1077 * picky DTB consumer will also provide a helpful error message.
1079 cpu
->dtb_compatible
= "qemu,unknown";
1080 cpu
->psci_version
= 1; /* By default assume PSCI v0.1 */
1081 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_NONE
;
1083 if (tcg_enabled()) {
1084 cpu
->psci_version
= 2; /* TCG implements PSCI 0.2 */
1088 static Property arm_cpu_gt_cntfrq_property
=
1089 DEFINE_PROP_UINT64("cntfrq", ARMCPU
, gt_cntfrq_hz
,
1090 NANOSECONDS_PER_SECOND
/ GTIMER_SCALE
);
1092 static Property arm_cpu_reset_cbar_property
=
1093 DEFINE_PROP_UINT64("reset-cbar", ARMCPU
, reset_cbar
, 0);
1095 static Property arm_cpu_reset_hivecs_property
=
1096 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU
, reset_hivecs
, false);
1098 static Property arm_cpu_rvbar_property
=
1099 DEFINE_PROP_UINT64("rvbar", ARMCPU
, rvbar
, 0);
1101 #ifndef CONFIG_USER_ONLY
1102 static Property arm_cpu_has_el2_property
=
1103 DEFINE_PROP_BOOL("has_el2", ARMCPU
, has_el2
, true);
1105 static Property arm_cpu_has_el3_property
=
1106 DEFINE_PROP_BOOL("has_el3", ARMCPU
, has_el3
, true);
1109 static Property arm_cpu_cfgend_property
=
1110 DEFINE_PROP_BOOL("cfgend", ARMCPU
, cfgend
, false);
1112 static Property arm_cpu_has_vfp_property
=
1113 DEFINE_PROP_BOOL("vfp", ARMCPU
, has_vfp
, true);
1115 static Property arm_cpu_has_neon_property
=
1116 DEFINE_PROP_BOOL("neon", ARMCPU
, has_neon
, true);
1118 static Property arm_cpu_has_dsp_property
=
1119 DEFINE_PROP_BOOL("dsp", ARMCPU
, has_dsp
, true);
1121 static Property arm_cpu_has_mpu_property
=
1122 DEFINE_PROP_BOOL("has-mpu", ARMCPU
, has_mpu
, true);
1124 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
1125 * because the CPU initfn will have already set cpu->pmsav7_dregion to
1126 * the right value for that particular CPU type, and we don't want
1127 * to override that with an incorrect constant value.
1129 static Property arm_cpu_pmsav7_dregion_property
=
1130 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU
,
1132 qdev_prop_uint32
, uint32_t);
1134 static bool arm_get_pmu(Object
*obj
, Error
**errp
)
1136 ARMCPU
*cpu
= ARM_CPU(obj
);
1138 return cpu
->has_pmu
;
1141 static void arm_set_pmu(Object
*obj
, bool value
, Error
**errp
)
1143 ARMCPU
*cpu
= ARM_CPU(obj
);
1146 if (kvm_enabled() && !kvm_arm_pmu_supported(CPU(cpu
))) {
1147 error_setg(errp
, "'pmu' feature not supported by KVM on this host");
1150 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1152 unset_feature(&cpu
->env
, ARM_FEATURE_PMU
);
1154 cpu
->has_pmu
= value
;
1157 unsigned int gt_cntfrq_period_ns(ARMCPU
*cpu
)
1160 * The exact approach to calculating guest ticks is:
1162 * muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), cpu->gt_cntfrq_hz,
1163 * NANOSECONDS_PER_SECOND);
1165 * We don't do that. Rather we intentionally use integer division
1166 * truncation below and in the caller for the conversion of host monotonic
1167 * time to guest ticks to provide the exact inverse for the semantics of
1168 * the QEMUTimer scale factor. QEMUTimer's scale facter is an integer, so
1169 * it loses precision when representing frequencies where
1170 * `(NANOSECONDS_PER_SECOND % cpu->gt_cntfrq) > 0` holds. Failing to
1171 * provide an exact inverse leads to scheduling timers with negative
1172 * periods, which in turn leads to sticky behaviour in the guest.
1174 * Finally, CNTFRQ is effectively capped at 1GHz to ensure our scale factor
1175 * cannot become zero.
1177 return NANOSECONDS_PER_SECOND
> cpu
->gt_cntfrq_hz
?
1178 NANOSECONDS_PER_SECOND
/ cpu
->gt_cntfrq_hz
: 1;
1181 void arm_cpu_post_init(Object
*obj
)
1183 ARMCPU
*cpu
= ARM_CPU(obj
);
1185 /* M profile implies PMSA. We have to do this here rather than
1186 * in realize with the other feature-implication checks because
1187 * we look at the PMSA bit to see if we should add some properties.
1189 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1190 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
1193 if (arm_feature(&cpu
->env
, ARM_FEATURE_CBAR
) ||
1194 arm_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
)) {
1195 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_cbar_property
);
1198 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M
)) {
1199 qdev_property_add_static(DEVICE(obj
), &arm_cpu_reset_hivecs_property
);
1202 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1203 qdev_property_add_static(DEVICE(obj
), &arm_cpu_rvbar_property
);
1206 #ifndef CONFIG_USER_ONLY
1207 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL3
)) {
1208 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
1209 * prevent "has_el3" from existing on CPUs which cannot support EL3.
1211 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el3_property
);
1213 object_property_add_link(obj
, "secure-memory",
1215 (Object
**)&cpu
->secure_memory
,
1216 qdev_prop_allow_set_link_before_realize
,
1217 OBJ_PROP_LINK_STRONG
,
1221 if (arm_feature(&cpu
->env
, ARM_FEATURE_EL2
)) {
1222 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_el2_property
);
1226 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMU
)) {
1227 cpu
->has_pmu
= true;
1228 object_property_add_bool(obj
, "pmu", arm_get_pmu
, arm_set_pmu
,
1233 * Allow user to turn off VFP and Neon support, but only for TCG --
1234 * KVM does not currently allow us to lie to the guest about its
1235 * ID/feature registers, so the guest always sees what the host has.
1237 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)
1238 ? cpu_isar_feature(aa64_fp_simd
, cpu
)
1239 : cpu_isar_feature(aa32_vfp
, cpu
)) {
1240 cpu
->has_vfp
= true;
1241 if (!kvm_enabled()) {
1242 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_vfp_property
);
1246 if (arm_feature(&cpu
->env
, ARM_FEATURE_NEON
)) {
1247 cpu
->has_neon
= true;
1248 if (!kvm_enabled()) {
1249 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_neon_property
);
1253 if (arm_feature(&cpu
->env
, ARM_FEATURE_M
) &&
1254 arm_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
)) {
1255 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_dsp_property
);
1258 if (arm_feature(&cpu
->env
, ARM_FEATURE_PMSA
)) {
1259 qdev_property_add_static(DEVICE(obj
), &arm_cpu_has_mpu_property
);
1260 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1261 qdev_property_add_static(DEVICE(obj
),
1262 &arm_cpu_pmsav7_dregion_property
);
1266 if (arm_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
1267 object_property_add_link(obj
, "idau", TYPE_IDAU_INTERFACE
, &cpu
->idau
,
1268 qdev_prop_allow_set_link_before_realize
,
1269 OBJ_PROP_LINK_STRONG
,
1272 * M profile: initial value of the Secure VTOR. We can't just use
1273 * a simple DEFINE_PROP_UINT32 for this because we want to permit
1274 * the property to be set after realize.
1276 object_property_add_uint32_ptr(obj
, "init-svtor",
1278 OBJ_PROP_FLAG_READWRITE
, &error_abort
);
1281 qdev_property_add_static(DEVICE(obj
), &arm_cpu_cfgend_property
);
1283 if (arm_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
)) {
1284 qdev_property_add_static(DEVICE(cpu
), &arm_cpu_gt_cntfrq_property
);
1288 static void arm_cpu_finalizefn(Object
*obj
)
1290 ARMCPU
*cpu
= ARM_CPU(obj
);
1291 ARMELChangeHook
*hook
, *next
;
1293 g_hash_table_destroy(cpu
->cp_regs
);
1295 QLIST_FOREACH_SAFE(hook
, &cpu
->pre_el_change_hooks
, node
, next
) {
1296 QLIST_REMOVE(hook
, node
);
1299 QLIST_FOREACH_SAFE(hook
, &cpu
->el_change_hooks
, node
, next
) {
1300 QLIST_REMOVE(hook
, node
);
1303 #ifndef CONFIG_USER_ONLY
1304 if (cpu
->pmu_timer
) {
1305 timer_del(cpu
->pmu_timer
);
1306 timer_deinit(cpu
->pmu_timer
);
1307 timer_free(cpu
->pmu_timer
);
1312 void arm_cpu_finalize_features(ARMCPU
*cpu
, Error
**errp
)
1314 Error
*local_err
= NULL
;
1316 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1317 arm_cpu_sve_finalize(cpu
, &local_err
);
1318 if (local_err
!= NULL
) {
1319 error_propagate(errp
, local_err
);
1325 static void arm_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
1327 CPUState
*cs
= CPU(dev
);
1328 ARMCPU
*cpu
= ARM_CPU(dev
);
1329 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(dev
);
1330 CPUARMState
*env
= &cpu
->env
;
1332 Error
*local_err
= NULL
;
1333 bool no_aa32
= false;
1335 /* If we needed to query the host kernel for the CPU features
1336 * then it's possible that might have failed in the initfn, but
1337 * this is the first point where we can report it.
1339 if (cpu
->host_cpu_probe_failed
) {
1340 if (!kvm_enabled()) {
1341 error_setg(errp
, "The 'host' CPU type can only be used with KVM");
1343 error_setg(errp
, "Failed to retrieve host CPU features");
1348 #ifndef CONFIG_USER_ONLY
1349 /* The NVIC and M-profile CPU are two halves of a single piece of
1350 * hardware; trying to use one without the other is a command line
1351 * error and will result in segfaults if not caught here.
1353 if (arm_feature(env
, ARM_FEATURE_M
)) {
1355 error_setg(errp
, "This board cannot be used with Cortex-M CPUs");
1360 error_setg(errp
, "This board can only be used with Cortex-M CPUs");
1368 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
1369 if (!cpu
->gt_cntfrq_hz
) {
1370 error_setg(errp
, "Invalid CNTFRQ: %"PRId64
"Hz",
1374 scale
= gt_cntfrq_period_ns(cpu
);
1376 scale
= GTIMER_SCALE
;
1379 cpu
->gt_timer
[GTIMER_PHYS
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1380 arm_gt_ptimer_cb
, cpu
);
1381 cpu
->gt_timer
[GTIMER_VIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1382 arm_gt_vtimer_cb
, cpu
);
1383 cpu
->gt_timer
[GTIMER_HYP
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1384 arm_gt_htimer_cb
, cpu
);
1385 cpu
->gt_timer
[GTIMER_SEC
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1386 arm_gt_stimer_cb
, cpu
);
1387 cpu
->gt_timer
[GTIMER_HYPVIRT
] = timer_new(QEMU_CLOCK_VIRTUAL
, scale
,
1388 arm_gt_hvtimer_cb
, cpu
);
1392 cpu_exec_realizefn(cs
, &local_err
);
1393 if (local_err
!= NULL
) {
1394 error_propagate(errp
, local_err
);
1398 arm_cpu_finalize_features(cpu
, &local_err
);
1399 if (local_err
!= NULL
) {
1400 error_propagate(errp
, local_err
);
1404 if (arm_feature(env
, ARM_FEATURE_AARCH64
) &&
1405 cpu
->has_vfp
!= cpu
->has_neon
) {
1407 * This is an architectural requirement for AArch64; AArch32 is
1408 * more flexible and permits VFP-no-Neon and Neon-no-VFP.
1411 "AArch64 CPUs must have both VFP and Neon or neither");
1415 if (!cpu
->has_vfp
) {
1419 t
= cpu
->isar
.id_aa64isar1
;
1420 t
= FIELD_DP64(t
, ID_AA64ISAR1
, JSCVT
, 0);
1421 cpu
->isar
.id_aa64isar1
= t
;
1423 t
= cpu
->isar
.id_aa64pfr0
;
1424 t
= FIELD_DP64(t
, ID_AA64PFR0
, FP
, 0xf);
1425 cpu
->isar
.id_aa64pfr0
= t
;
1427 u
= cpu
->isar
.id_isar6
;
1428 u
= FIELD_DP32(u
, ID_ISAR6
, JSCVT
, 0);
1429 cpu
->isar
.id_isar6
= u
;
1431 u
= cpu
->isar
.mvfr0
;
1432 u
= FIELD_DP32(u
, MVFR0
, FPSP
, 0);
1433 u
= FIELD_DP32(u
, MVFR0
, FPDP
, 0);
1434 u
= FIELD_DP32(u
, MVFR0
, FPTRAP
, 0);
1435 u
= FIELD_DP32(u
, MVFR0
, FPDIVIDE
, 0);
1436 u
= FIELD_DP32(u
, MVFR0
, FPSQRT
, 0);
1437 u
= FIELD_DP32(u
, MVFR0
, FPSHVEC
, 0);
1438 u
= FIELD_DP32(u
, MVFR0
, FPROUND
, 0);
1439 cpu
->isar
.mvfr0
= u
;
1441 u
= cpu
->isar
.mvfr1
;
1442 u
= FIELD_DP32(u
, MVFR1
, FPFTZ
, 0);
1443 u
= FIELD_DP32(u
, MVFR1
, FPDNAN
, 0);
1444 u
= FIELD_DP32(u
, MVFR1
, FPHP
, 0);
1445 cpu
->isar
.mvfr1
= u
;
1447 u
= cpu
->isar
.mvfr2
;
1448 u
= FIELD_DP32(u
, MVFR2
, FPMISC
, 0);
1449 cpu
->isar
.mvfr2
= u
;
1452 if (!cpu
->has_neon
) {
1456 unset_feature(env
, ARM_FEATURE_NEON
);
1458 t
= cpu
->isar
.id_aa64isar0
;
1459 t
= FIELD_DP64(t
, ID_AA64ISAR0
, DP
, 0);
1460 cpu
->isar
.id_aa64isar0
= t
;
1462 t
= cpu
->isar
.id_aa64isar1
;
1463 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FCMA
, 0);
1464 cpu
->isar
.id_aa64isar1
= t
;
1466 t
= cpu
->isar
.id_aa64pfr0
;
1467 t
= FIELD_DP64(t
, ID_AA64PFR0
, ADVSIMD
, 0xf);
1468 cpu
->isar
.id_aa64pfr0
= t
;
1470 u
= cpu
->isar
.id_isar5
;
1471 u
= FIELD_DP32(u
, ID_ISAR5
, RDM
, 0);
1472 u
= FIELD_DP32(u
, ID_ISAR5
, VCMA
, 0);
1473 cpu
->isar
.id_isar5
= u
;
1475 u
= cpu
->isar
.id_isar6
;
1476 u
= FIELD_DP32(u
, ID_ISAR6
, DP
, 0);
1477 u
= FIELD_DP32(u
, ID_ISAR6
, FHM
, 0);
1478 cpu
->isar
.id_isar6
= u
;
1480 u
= cpu
->isar
.mvfr1
;
1481 u
= FIELD_DP32(u
, MVFR1
, SIMDLS
, 0);
1482 u
= FIELD_DP32(u
, MVFR1
, SIMDINT
, 0);
1483 u
= FIELD_DP32(u
, MVFR1
, SIMDSP
, 0);
1484 u
= FIELD_DP32(u
, MVFR1
, SIMDHP
, 0);
1485 cpu
->isar
.mvfr1
= u
;
1487 u
= cpu
->isar
.mvfr2
;
1488 u
= FIELD_DP32(u
, MVFR2
, SIMDMISC
, 0);
1489 cpu
->isar
.mvfr2
= u
;
1492 if (!cpu
->has_neon
&& !cpu
->has_vfp
) {
1496 t
= cpu
->isar
.id_aa64isar0
;
1497 t
= FIELD_DP64(t
, ID_AA64ISAR0
, FHM
, 0);
1498 cpu
->isar
.id_aa64isar0
= t
;
1500 t
= cpu
->isar
.id_aa64isar1
;
1501 t
= FIELD_DP64(t
, ID_AA64ISAR1
, FRINTTS
, 0);
1502 cpu
->isar
.id_aa64isar1
= t
;
1504 u
= cpu
->isar
.mvfr0
;
1505 u
= FIELD_DP32(u
, MVFR0
, SIMDREG
, 0);
1506 cpu
->isar
.mvfr0
= u
;
1508 /* Despite the name, this field covers both VFP and Neon */
1509 u
= cpu
->isar
.mvfr1
;
1510 u
= FIELD_DP32(u
, MVFR1
, SIMDFMAC
, 0);
1511 cpu
->isar
.mvfr1
= u
;
1514 if (arm_feature(env
, ARM_FEATURE_M
) && !cpu
->has_dsp
) {
1517 unset_feature(env
, ARM_FEATURE_THUMB_DSP
);
1519 u
= cpu
->isar
.id_isar1
;
1520 u
= FIELD_DP32(u
, ID_ISAR1
, EXTEND
, 1);
1521 cpu
->isar
.id_isar1
= u
;
1523 u
= cpu
->isar
.id_isar2
;
1524 u
= FIELD_DP32(u
, ID_ISAR2
, MULTU
, 1);
1525 u
= FIELD_DP32(u
, ID_ISAR2
, MULTS
, 1);
1526 cpu
->isar
.id_isar2
= u
;
1528 u
= cpu
->isar
.id_isar3
;
1529 u
= FIELD_DP32(u
, ID_ISAR3
, SIMD
, 1);
1530 u
= FIELD_DP32(u
, ID_ISAR3
, SATURATE
, 0);
1531 cpu
->isar
.id_isar3
= u
;
1534 /* Some features automatically imply others: */
1535 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1536 if (arm_feature(env
, ARM_FEATURE_M
)) {
1537 set_feature(env
, ARM_FEATURE_V7
);
1539 set_feature(env
, ARM_FEATURE_V7VE
);
1544 * There exist AArch64 cpus without AArch32 support. When KVM
1545 * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
1546 * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
1547 * As a general principle, we also do not make ID register
1548 * consistency checks anywhere unless using TCG, because only
1549 * for TCG would a consistency-check failure be a QEMU bug.
1551 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
1552 no_aa32
= !cpu_isar_feature(aa64_aa32
, cpu
);
1555 if (arm_feature(env
, ARM_FEATURE_V7VE
)) {
1556 /* v7 Virtualization Extensions. In real hardware this implies
1557 * EL2 and also the presence of the Security Extensions.
1558 * For QEMU, for backwards-compatibility we implement some
1559 * CPUs or CPU configs which have no actual EL2 or EL3 but do
1560 * include the various other features that V7VE implies.
1561 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
1562 * Security Extensions is ARM_FEATURE_EL3.
1564 assert(!tcg_enabled() || no_aa32
||
1565 cpu_isar_feature(aa32_arm_div
, cpu
));
1566 set_feature(env
, ARM_FEATURE_LPAE
);
1567 set_feature(env
, ARM_FEATURE_V7
);
1569 if (arm_feature(env
, ARM_FEATURE_V7
)) {
1570 set_feature(env
, ARM_FEATURE_VAPA
);
1571 set_feature(env
, ARM_FEATURE_THUMB2
);
1572 set_feature(env
, ARM_FEATURE_MPIDR
);
1573 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1574 set_feature(env
, ARM_FEATURE_V6K
);
1576 set_feature(env
, ARM_FEATURE_V6
);
1579 /* Always define VBAR for V7 CPUs even if it doesn't exist in
1580 * non-EL3 configs. This is needed by some legacy boards.
1582 set_feature(env
, ARM_FEATURE_VBAR
);
1584 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
1585 set_feature(env
, ARM_FEATURE_V6
);
1586 set_feature(env
, ARM_FEATURE_MVFR
);
1588 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1589 set_feature(env
, ARM_FEATURE_V5
);
1590 if (!arm_feature(env
, ARM_FEATURE_M
)) {
1591 assert(!tcg_enabled() || no_aa32
||
1592 cpu_isar_feature(aa32_jazelle
, cpu
));
1593 set_feature(env
, ARM_FEATURE_AUXCR
);
1596 if (arm_feature(env
, ARM_FEATURE_V5
)) {
1597 set_feature(env
, ARM_FEATURE_V4T
);
1599 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1600 set_feature(env
, ARM_FEATURE_V7MP
);
1601 set_feature(env
, ARM_FEATURE_PXN
);
1603 if (arm_feature(env
, ARM_FEATURE_CBAR_RO
)) {
1604 set_feature(env
, ARM_FEATURE_CBAR
);
1606 if (arm_feature(env
, ARM_FEATURE_THUMB2
) &&
1607 !arm_feature(env
, ARM_FEATURE_M
)) {
1608 set_feature(env
, ARM_FEATURE_THUMB_DSP
);
1612 * We rely on no XScale CPU having VFP so we can use the same bits in the
1613 * TB flags field for VECSTRIDE and XSCALE_CPAR.
1615 assert(arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
) ||
1616 !cpu_isar_feature(aa32_vfp_simd
, cpu
) ||
1617 !arm_feature(env
, ARM_FEATURE_XSCALE
));
1619 if (arm_feature(env
, ARM_FEATURE_V7
) &&
1620 !arm_feature(env
, ARM_FEATURE_M
) &&
1621 !arm_feature(env
, ARM_FEATURE_PMSA
)) {
1622 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
1627 /* For CPUs which might have tiny 1K pages, or which have an
1628 * MPU and might have small region sizes, stick with 1K pages.
1632 if (!set_preferred_target_page_bits(pagebits
)) {
1633 /* This can only ever happen for hotplugging a CPU, or if
1634 * the board code incorrectly creates a CPU which it has
1635 * promised via minimum_page_size that it will not.
1637 error_setg(errp
, "This CPU requires a smaller page size than the "
1642 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
1643 * We don't support setting cluster ID ([16..23]) (known as Aff2
1644 * in later ARM ARM versions), or any of the higher affinity level fields,
1645 * so these bits always RAZ.
1647 if (cpu
->mp_affinity
== ARM64_AFFINITY_INVALID
) {
1648 cpu
->mp_affinity
= arm_cpu_mp_affinity(cs
->cpu_index
,
1649 ARM_DEFAULT_CPUS_PER_CLUSTER
);
1652 if (cpu
->reset_hivecs
) {
1653 cpu
->reset_sctlr
|= (1 << 13);
1657 if (arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1658 cpu
->reset_sctlr
|= SCTLR_EE
;
1660 cpu
->reset_sctlr
|= SCTLR_B
;
1664 if (!cpu
->has_el3
) {
1665 /* If the has_el3 CPU property is disabled then we need to disable the
1668 unset_feature(env
, ARM_FEATURE_EL3
);
1670 /* Disable the security extension feature bits in the processor feature
1671 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
1673 cpu
->id_pfr1
&= ~0xf0;
1674 cpu
->isar
.id_aa64pfr0
&= ~0xf000;
1677 if (!cpu
->has_el2
) {
1678 unset_feature(env
, ARM_FEATURE_EL2
);
1681 if (!cpu
->has_pmu
) {
1682 unset_feature(env
, ARM_FEATURE_PMU
);
1684 if (arm_feature(env
, ARM_FEATURE_PMU
)) {
1687 if (!kvm_enabled()) {
1688 arm_register_pre_el_change_hook(cpu
, &pmu_pre_el_change
, 0);
1689 arm_register_el_change_hook(cpu
, &pmu_post_el_change
, 0);
1692 #ifndef CONFIG_USER_ONLY
1693 cpu
->pmu_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, arm_pmu_timer_cb
,
1697 cpu
->isar
.id_aa64dfr0
=
1698 FIELD_DP64(cpu
->isar
.id_aa64dfr0
, ID_AA64DFR0
, PMUVER
, 0);
1699 cpu
->isar
.id_dfr0
= FIELD_DP32(cpu
->isar
.id_dfr0
, ID_DFR0
, PERFMON
, 0);
1704 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
1705 /* Disable the hypervisor feature bits in the processor feature
1706 * registers if we don't have EL2. These are id_pfr1[15:12] and
1707 * id_aa64pfr0_el1[11:8].
1709 cpu
->isar
.id_aa64pfr0
&= ~0xf00;
1710 cpu
->id_pfr1
&= ~0xf000;
1713 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
1714 * to false or by setting pmsav7-dregion to 0.
1716 if (!cpu
->has_mpu
) {
1717 cpu
->pmsav7_dregion
= 0;
1719 if (cpu
->pmsav7_dregion
== 0) {
1720 cpu
->has_mpu
= false;
1723 if (arm_feature(env
, ARM_FEATURE_PMSA
) &&
1724 arm_feature(env
, ARM_FEATURE_V7
)) {
1725 uint32_t nr
= cpu
->pmsav7_dregion
;
1728 error_setg(errp
, "PMSAv7 MPU #regions invalid %" PRIu32
, nr
);
1733 if (arm_feature(env
, ARM_FEATURE_V8
)) {
1735 env
->pmsav8
.rbar
[M_REG_NS
] = g_new0(uint32_t, nr
);
1736 env
->pmsav8
.rlar
[M_REG_NS
] = g_new0(uint32_t, nr
);
1737 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1738 env
->pmsav8
.rbar
[M_REG_S
] = g_new0(uint32_t, nr
);
1739 env
->pmsav8
.rlar
[M_REG_S
] = g_new0(uint32_t, nr
);
1742 env
->pmsav7
.drbar
= g_new0(uint32_t, nr
);
1743 env
->pmsav7
.drsr
= g_new0(uint32_t, nr
);
1744 env
->pmsav7
.dracr
= g_new0(uint32_t, nr
);
1749 if (arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1750 uint32_t nr
= cpu
->sau_sregion
;
1753 error_setg(errp
, "v8M SAU #regions invalid %" PRIu32
, nr
);
1758 env
->sau
.rbar
= g_new0(uint32_t, nr
);
1759 env
->sau
.rlar
= g_new0(uint32_t, nr
);
1763 if (arm_feature(env
, ARM_FEATURE_EL3
)) {
1764 set_feature(env
, ARM_FEATURE_VBAR
);
1767 register_cp_regs_for_features(cpu
);
1768 arm_cpu_register_gdb_regs_for_features(cpu
);
1770 init_cpreg_list(cpu
);
1772 #ifndef CONFIG_USER_ONLY
1773 MachineState
*ms
= MACHINE(qdev_get_machine());
1774 unsigned int smp_cpus
= ms
->smp
.cpus
;
1776 if (cpu
->has_el3
|| arm_feature(env
, ARM_FEATURE_M_SECURITY
)) {
1779 if (!cpu
->secure_memory
) {
1780 cpu
->secure_memory
= cs
->memory
;
1782 cpu_address_space_init(cs
, ARMASIdx_S
, "cpu-secure-memory",
1783 cpu
->secure_memory
);
1787 cpu_address_space_init(cs
, ARMASIdx_NS
, "cpu-memory", cs
->memory
);
1789 /* No core_count specified, default to smp_cpus. */
1790 if (cpu
->core_count
== -1) {
1791 cpu
->core_count
= smp_cpus
;
1798 acc
->parent_realize(dev
, errp
);
1801 static ObjectClass
*arm_cpu_class_by_name(const char *cpu_model
)
1806 const char *cpunamestr
;
1808 cpuname
= g_strsplit(cpu_model
, ",", 1);
1809 cpunamestr
= cpuname
[0];
1810 #ifdef CONFIG_USER_ONLY
1811 /* For backwards compatibility usermode emulation allows "-cpu any",
1812 * which has the same semantics as "-cpu max".
1814 if (!strcmp(cpunamestr
, "any")) {
1818 typename
= g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr
);
1819 oc
= object_class_by_name(typename
);
1820 g_strfreev(cpuname
);
1822 if (!oc
|| !object_class_dynamic_cast(oc
, TYPE_ARM_CPU
) ||
1823 object_class_is_abstract(oc
)) {
1829 /* CPU models. These are not needed for the AArch64 linux-user build. */
1830 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1832 static void arm926_initfn(Object
*obj
)
1834 ARMCPU
*cpu
= ARM_CPU(obj
);
1836 cpu
->dtb_compatible
= "arm,arm926";
1837 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1838 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1839 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
1840 cpu
->midr
= 0x41069265;
1841 cpu
->reset_fpsid
= 0x41011090;
1842 cpu
->ctr
= 0x1dd20d2;
1843 cpu
->reset_sctlr
= 0x00090078;
1846 * ARMv5 does not have the ID_ISAR registers, but we can still
1847 * set the field to indicate Jazelle support within QEMU.
1849 cpu
->isar
.id_isar1
= FIELD_DP32(cpu
->isar
.id_isar1
, ID_ISAR1
, JAZELLE
, 1);
1851 * Similarly, we need to set MVFR0 fields to enable vfp and short vector
1852 * support even though ARMv5 doesn't have this register.
1854 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPSHVEC
, 1);
1855 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPSP
, 1);
1856 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPDP
, 1);
1859 static void arm946_initfn(Object
*obj
)
1861 ARMCPU
*cpu
= ARM_CPU(obj
);
1863 cpu
->dtb_compatible
= "arm,arm946";
1864 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1865 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
1866 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1867 cpu
->midr
= 0x41059461;
1868 cpu
->ctr
= 0x0f004006;
1869 cpu
->reset_sctlr
= 0x00000078;
1872 static void arm1026_initfn(Object
*obj
)
1874 ARMCPU
*cpu
= ARM_CPU(obj
);
1876 cpu
->dtb_compatible
= "arm,arm1026";
1877 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
1878 set_feature(&cpu
->env
, ARM_FEATURE_AUXCR
);
1879 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1880 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_TEST_CLEAN
);
1881 cpu
->midr
= 0x4106a262;
1882 cpu
->reset_fpsid
= 0x410110a0;
1883 cpu
->ctr
= 0x1dd20d2;
1884 cpu
->reset_sctlr
= 0x00090078;
1885 cpu
->reset_auxcr
= 1;
1888 * ARMv5 does not have the ID_ISAR registers, but we can still
1889 * set the field to indicate Jazelle support within QEMU.
1891 cpu
->isar
.id_isar1
= FIELD_DP32(cpu
->isar
.id_isar1
, ID_ISAR1
, JAZELLE
, 1);
1893 * Similarly, we need to set MVFR0 fields to enable vfp and short vector
1894 * support even though ARMv5 doesn't have this register.
1896 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPSHVEC
, 1);
1897 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPSP
, 1);
1898 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPDP
, 1);
1901 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
1902 ARMCPRegInfo ifar
= {
1903 .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
1905 .fieldoffset
= offsetof(CPUARMState
, cp15
.ifar_ns
),
1908 define_one_arm_cp_reg(cpu
, &ifar
);
1912 static void arm1136_r2_initfn(Object
*obj
)
1914 ARMCPU
*cpu
= ARM_CPU(obj
);
1915 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
1916 * older core than plain "arm1136". In particular this does not
1917 * have the v6K features.
1918 * These ID register values are correct for 1136 but may be wrong
1919 * for 1136_r2 (in particular r0p2 does not actually implement most
1920 * of the ID registers).
1923 cpu
->dtb_compatible
= "arm,arm1136";
1924 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
1925 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1926 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1927 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1928 cpu
->midr
= 0x4107b362;
1929 cpu
->reset_fpsid
= 0x410120b4;
1930 cpu
->isar
.mvfr0
= 0x11111111;
1931 cpu
->isar
.mvfr1
= 0x00000000;
1932 cpu
->ctr
= 0x1dd20d2;
1933 cpu
->reset_sctlr
= 0x00050078;
1934 cpu
->id_pfr0
= 0x111;
1936 cpu
->isar
.id_dfr0
= 0x2;
1938 cpu
->isar
.id_mmfr0
= 0x01130003;
1939 cpu
->isar
.id_mmfr1
= 0x10030302;
1940 cpu
->isar
.id_mmfr2
= 0x01222110;
1941 cpu
->isar
.id_isar0
= 0x00140011;
1942 cpu
->isar
.id_isar1
= 0x12002111;
1943 cpu
->isar
.id_isar2
= 0x11231111;
1944 cpu
->isar
.id_isar3
= 0x01102131;
1945 cpu
->isar
.id_isar4
= 0x141;
1946 cpu
->reset_auxcr
= 7;
1949 static void arm1136_initfn(Object
*obj
)
1951 ARMCPU
*cpu
= ARM_CPU(obj
);
1953 cpu
->dtb_compatible
= "arm,arm1136";
1954 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1955 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
1956 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1957 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1958 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1959 cpu
->midr
= 0x4117b363;
1960 cpu
->reset_fpsid
= 0x410120b4;
1961 cpu
->isar
.mvfr0
= 0x11111111;
1962 cpu
->isar
.mvfr1
= 0x00000000;
1963 cpu
->ctr
= 0x1dd20d2;
1964 cpu
->reset_sctlr
= 0x00050078;
1965 cpu
->id_pfr0
= 0x111;
1967 cpu
->isar
.id_dfr0
= 0x2;
1969 cpu
->isar
.id_mmfr0
= 0x01130003;
1970 cpu
->isar
.id_mmfr1
= 0x10030302;
1971 cpu
->isar
.id_mmfr2
= 0x01222110;
1972 cpu
->isar
.id_isar0
= 0x00140011;
1973 cpu
->isar
.id_isar1
= 0x12002111;
1974 cpu
->isar
.id_isar2
= 0x11231111;
1975 cpu
->isar
.id_isar3
= 0x01102131;
1976 cpu
->isar
.id_isar4
= 0x141;
1977 cpu
->reset_auxcr
= 7;
1980 static void arm1176_initfn(Object
*obj
)
1982 ARMCPU
*cpu
= ARM_CPU(obj
);
1984 cpu
->dtb_compatible
= "arm,arm1176";
1985 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
1986 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
1987 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
1988 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_DIRTY_REG
);
1989 set_feature(&cpu
->env
, ARM_FEATURE_CACHE_BLOCK_OPS
);
1990 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
1991 cpu
->midr
= 0x410fb767;
1992 cpu
->reset_fpsid
= 0x410120b5;
1993 cpu
->isar
.mvfr0
= 0x11111111;
1994 cpu
->isar
.mvfr1
= 0x00000000;
1995 cpu
->ctr
= 0x1dd20d2;
1996 cpu
->reset_sctlr
= 0x00050078;
1997 cpu
->id_pfr0
= 0x111;
1998 cpu
->id_pfr1
= 0x11;
1999 cpu
->isar
.id_dfr0
= 0x33;
2001 cpu
->isar
.id_mmfr0
= 0x01130003;
2002 cpu
->isar
.id_mmfr1
= 0x10030302;
2003 cpu
->isar
.id_mmfr2
= 0x01222100;
2004 cpu
->isar
.id_isar0
= 0x0140011;
2005 cpu
->isar
.id_isar1
= 0x12002111;
2006 cpu
->isar
.id_isar2
= 0x11231121;
2007 cpu
->isar
.id_isar3
= 0x01102131;
2008 cpu
->isar
.id_isar4
= 0x01141;
2009 cpu
->reset_auxcr
= 7;
2012 static void arm11mpcore_initfn(Object
*obj
)
2014 ARMCPU
*cpu
= ARM_CPU(obj
);
2016 cpu
->dtb_compatible
= "arm,arm11mpcore";
2017 set_feature(&cpu
->env
, ARM_FEATURE_V6K
);
2018 set_feature(&cpu
->env
, ARM_FEATURE_VAPA
);
2019 set_feature(&cpu
->env
, ARM_FEATURE_MPIDR
);
2020 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2021 cpu
->midr
= 0x410fb022;
2022 cpu
->reset_fpsid
= 0x410120b4;
2023 cpu
->isar
.mvfr0
= 0x11111111;
2024 cpu
->isar
.mvfr1
= 0x00000000;
2025 cpu
->ctr
= 0x1d192992; /* 32K icache 32K dcache */
2026 cpu
->id_pfr0
= 0x111;
2028 cpu
->isar
.id_dfr0
= 0;
2030 cpu
->isar
.id_mmfr0
= 0x01100103;
2031 cpu
->isar
.id_mmfr1
= 0x10020302;
2032 cpu
->isar
.id_mmfr2
= 0x01222000;
2033 cpu
->isar
.id_isar0
= 0x00100011;
2034 cpu
->isar
.id_isar1
= 0x12002111;
2035 cpu
->isar
.id_isar2
= 0x11221011;
2036 cpu
->isar
.id_isar3
= 0x01102131;
2037 cpu
->isar
.id_isar4
= 0x141;
2038 cpu
->reset_auxcr
= 1;
2041 static void cortex_m0_initfn(Object
*obj
)
2043 ARMCPU
*cpu
= ARM_CPU(obj
);
2044 set_feature(&cpu
->env
, ARM_FEATURE_V6
);
2045 set_feature(&cpu
->env
, ARM_FEATURE_M
);
2047 cpu
->midr
= 0x410cc200;
2050 static void cortex_m3_initfn(Object
*obj
)
2052 ARMCPU
*cpu
= ARM_CPU(obj
);
2053 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
2054 set_feature(&cpu
->env
, ARM_FEATURE_M
);
2055 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
2056 cpu
->midr
= 0x410fc231;
2057 cpu
->pmsav7_dregion
= 8;
2058 cpu
->id_pfr0
= 0x00000030;
2059 cpu
->id_pfr1
= 0x00000200;
2060 cpu
->isar
.id_dfr0
= 0x00100000;
2061 cpu
->id_afr0
= 0x00000000;
2062 cpu
->isar
.id_mmfr0
= 0x00000030;
2063 cpu
->isar
.id_mmfr1
= 0x00000000;
2064 cpu
->isar
.id_mmfr2
= 0x00000000;
2065 cpu
->isar
.id_mmfr3
= 0x00000000;
2066 cpu
->isar
.id_isar0
= 0x01141110;
2067 cpu
->isar
.id_isar1
= 0x02111000;
2068 cpu
->isar
.id_isar2
= 0x21112231;
2069 cpu
->isar
.id_isar3
= 0x01111110;
2070 cpu
->isar
.id_isar4
= 0x01310102;
2071 cpu
->isar
.id_isar5
= 0x00000000;
2072 cpu
->isar
.id_isar6
= 0x00000000;
2075 static void cortex_m4_initfn(Object
*obj
)
2077 ARMCPU
*cpu
= ARM_CPU(obj
);
2079 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
2080 set_feature(&cpu
->env
, ARM_FEATURE_M
);
2081 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
2082 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
2083 cpu
->midr
= 0x410fc240; /* r0p0 */
2084 cpu
->pmsav7_dregion
= 8;
2085 cpu
->isar
.mvfr0
= 0x10110021;
2086 cpu
->isar
.mvfr1
= 0x11000011;
2087 cpu
->isar
.mvfr2
= 0x00000000;
2088 cpu
->id_pfr0
= 0x00000030;
2089 cpu
->id_pfr1
= 0x00000200;
2090 cpu
->isar
.id_dfr0
= 0x00100000;
2091 cpu
->id_afr0
= 0x00000000;
2092 cpu
->isar
.id_mmfr0
= 0x00000030;
2093 cpu
->isar
.id_mmfr1
= 0x00000000;
2094 cpu
->isar
.id_mmfr2
= 0x00000000;
2095 cpu
->isar
.id_mmfr3
= 0x00000000;
2096 cpu
->isar
.id_isar0
= 0x01141110;
2097 cpu
->isar
.id_isar1
= 0x02111000;
2098 cpu
->isar
.id_isar2
= 0x21112231;
2099 cpu
->isar
.id_isar3
= 0x01111110;
2100 cpu
->isar
.id_isar4
= 0x01310102;
2101 cpu
->isar
.id_isar5
= 0x00000000;
2102 cpu
->isar
.id_isar6
= 0x00000000;
2105 static void cortex_m7_initfn(Object
*obj
)
2107 ARMCPU
*cpu
= ARM_CPU(obj
);
2109 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
2110 set_feature(&cpu
->env
, ARM_FEATURE_M
);
2111 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
2112 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
2113 cpu
->midr
= 0x411fc272; /* r1p2 */
2114 cpu
->pmsav7_dregion
= 8;
2115 cpu
->isar
.mvfr0
= 0x10110221;
2116 cpu
->isar
.mvfr1
= 0x12000011;
2117 cpu
->isar
.mvfr2
= 0x00000040;
2118 cpu
->id_pfr0
= 0x00000030;
2119 cpu
->id_pfr1
= 0x00000200;
2120 cpu
->isar
.id_dfr0
= 0x00100000;
2121 cpu
->id_afr0
= 0x00000000;
2122 cpu
->isar
.id_mmfr0
= 0x00100030;
2123 cpu
->isar
.id_mmfr1
= 0x00000000;
2124 cpu
->isar
.id_mmfr2
= 0x01000000;
2125 cpu
->isar
.id_mmfr3
= 0x00000000;
2126 cpu
->isar
.id_isar0
= 0x01101110;
2127 cpu
->isar
.id_isar1
= 0x02112000;
2128 cpu
->isar
.id_isar2
= 0x20232231;
2129 cpu
->isar
.id_isar3
= 0x01111131;
2130 cpu
->isar
.id_isar4
= 0x01310132;
2131 cpu
->isar
.id_isar5
= 0x00000000;
2132 cpu
->isar
.id_isar6
= 0x00000000;
2135 static void cortex_m33_initfn(Object
*obj
)
2137 ARMCPU
*cpu
= ARM_CPU(obj
);
2139 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
2140 set_feature(&cpu
->env
, ARM_FEATURE_M
);
2141 set_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
);
2142 set_feature(&cpu
->env
, ARM_FEATURE_M_SECURITY
);
2143 set_feature(&cpu
->env
, ARM_FEATURE_THUMB_DSP
);
2144 cpu
->midr
= 0x410fd213; /* r0p3 */
2145 cpu
->pmsav7_dregion
= 16;
2146 cpu
->sau_sregion
= 8;
2147 cpu
->isar
.mvfr0
= 0x10110021;
2148 cpu
->isar
.mvfr1
= 0x11000011;
2149 cpu
->isar
.mvfr2
= 0x00000040;
2150 cpu
->id_pfr0
= 0x00000030;
2151 cpu
->id_pfr1
= 0x00000210;
2152 cpu
->isar
.id_dfr0
= 0x00200000;
2153 cpu
->id_afr0
= 0x00000000;
2154 cpu
->isar
.id_mmfr0
= 0x00101F40;
2155 cpu
->isar
.id_mmfr1
= 0x00000000;
2156 cpu
->isar
.id_mmfr2
= 0x01000000;
2157 cpu
->isar
.id_mmfr3
= 0x00000000;
2158 cpu
->isar
.id_isar0
= 0x01101110;
2159 cpu
->isar
.id_isar1
= 0x02212000;
2160 cpu
->isar
.id_isar2
= 0x20232232;
2161 cpu
->isar
.id_isar3
= 0x01111131;
2162 cpu
->isar
.id_isar4
= 0x01310132;
2163 cpu
->isar
.id_isar5
= 0x00000000;
2164 cpu
->isar
.id_isar6
= 0x00000000;
2165 cpu
->clidr
= 0x00000000;
2166 cpu
->ctr
= 0x8000c000;
2169 static void arm_v7m_class_init(ObjectClass
*oc
, void *data
)
2171 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2172 CPUClass
*cc
= CPU_CLASS(oc
);
2175 #ifndef CONFIG_USER_ONLY
2176 cc
->do_interrupt
= arm_v7m_cpu_do_interrupt
;
2179 cc
->cpu_exec_interrupt
= arm_v7m_cpu_exec_interrupt
;
2182 static const ARMCPRegInfo cortexr5_cp_reginfo
[] = {
2183 /* Dummy the TCM region regs for the moment */
2184 { .name
= "ATCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 0,
2185 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
2186 { .name
= "BTCM", .cp
= 15, .opc1
= 0, .crn
= 9, .crm
= 1, .opc2
= 1,
2187 .access
= PL1_RW
, .type
= ARM_CP_CONST
},
2188 { .name
= "DCACHE_INVAL", .cp
= 15, .opc1
= 0, .crn
= 15, .crm
= 5,
2189 .opc2
= 0, .access
= PL1_W
, .type
= ARM_CP_NOP
},
2193 static void cortex_r5_initfn(Object
*obj
)
2195 ARMCPU
*cpu
= ARM_CPU(obj
);
2197 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
2198 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
2199 set_feature(&cpu
->env
, ARM_FEATURE_PMSA
);
2200 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
2201 cpu
->midr
= 0x411fc153; /* r1p3 */
2202 cpu
->id_pfr0
= 0x0131;
2203 cpu
->id_pfr1
= 0x001;
2204 cpu
->isar
.id_dfr0
= 0x010400;
2206 cpu
->isar
.id_mmfr0
= 0x0210030;
2207 cpu
->isar
.id_mmfr1
= 0x00000000;
2208 cpu
->isar
.id_mmfr2
= 0x01200000;
2209 cpu
->isar
.id_mmfr3
= 0x0211;
2210 cpu
->isar
.id_isar0
= 0x02101111;
2211 cpu
->isar
.id_isar1
= 0x13112111;
2212 cpu
->isar
.id_isar2
= 0x21232141;
2213 cpu
->isar
.id_isar3
= 0x01112131;
2214 cpu
->isar
.id_isar4
= 0x0010142;
2215 cpu
->isar
.id_isar5
= 0x0;
2216 cpu
->isar
.id_isar6
= 0x0;
2217 cpu
->mp_is_up
= true;
2218 cpu
->pmsav7_dregion
= 16;
2219 define_arm_cp_regs(cpu
, cortexr5_cp_reginfo
);
2222 static void cortex_r5f_initfn(Object
*obj
)
2224 ARMCPU
*cpu
= ARM_CPU(obj
);
2226 cortex_r5_initfn(obj
);
2227 cpu
->isar
.mvfr0
= 0x10110221;
2228 cpu
->isar
.mvfr1
= 0x00000011;
2231 static const ARMCPRegInfo cortexa8_cp_reginfo
[] = {
2232 { .name
= "L2LOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 0,
2233 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2234 { .name
= "L2AUXCR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
2235 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2239 static void cortex_a8_initfn(Object
*obj
)
2241 ARMCPU
*cpu
= ARM_CPU(obj
);
2243 cpu
->dtb_compatible
= "arm,cortex-a8";
2244 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
2245 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
2246 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
2247 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2248 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
2249 cpu
->midr
= 0x410fc080;
2250 cpu
->reset_fpsid
= 0x410330c0;
2251 cpu
->isar
.mvfr0
= 0x11110222;
2252 cpu
->isar
.mvfr1
= 0x00011111;
2253 cpu
->ctr
= 0x82048004;
2254 cpu
->reset_sctlr
= 0x00c50078;
2255 cpu
->id_pfr0
= 0x1031;
2256 cpu
->id_pfr1
= 0x11;
2257 cpu
->isar
.id_dfr0
= 0x400;
2259 cpu
->isar
.id_mmfr0
= 0x31100003;
2260 cpu
->isar
.id_mmfr1
= 0x20000000;
2261 cpu
->isar
.id_mmfr2
= 0x01202000;
2262 cpu
->isar
.id_mmfr3
= 0x11;
2263 cpu
->isar
.id_isar0
= 0x00101111;
2264 cpu
->isar
.id_isar1
= 0x12112111;
2265 cpu
->isar
.id_isar2
= 0x21232031;
2266 cpu
->isar
.id_isar3
= 0x11112131;
2267 cpu
->isar
.id_isar4
= 0x00111142;
2268 cpu
->isar
.dbgdidr
= 0x15141000;
2269 cpu
->clidr
= (1 << 27) | (2 << 24) | 3;
2270 cpu
->ccsidr
[0] = 0xe007e01a; /* 16k L1 dcache. */
2271 cpu
->ccsidr
[1] = 0x2007e01a; /* 16k L1 icache. */
2272 cpu
->ccsidr
[2] = 0xf0000000; /* No L2 icache. */
2273 cpu
->reset_auxcr
= 2;
2274 define_arm_cp_regs(cpu
, cortexa8_cp_reginfo
);
2277 static const ARMCPRegInfo cortexa9_cp_reginfo
[] = {
2278 /* power_control should be set to maximum latency. Again,
2279 * default to 0 and set by private hook
2281 { .name
= "A9_PWRCTL", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
2282 .access
= PL1_RW
, .resetvalue
= 0,
2283 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_control
) },
2284 { .name
= "A9_DIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 1,
2285 .access
= PL1_RW
, .resetvalue
= 0,
2286 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_diagnostic
) },
2287 { .name
= "A9_PWRDIAG", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 2,
2288 .access
= PL1_RW
, .resetvalue
= 0,
2289 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_power_diagnostic
) },
2290 { .name
= "NEONBUSY", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
2291 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
2292 /* TLB lockdown control */
2293 { .name
= "TLB_LOCKR", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 2,
2294 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
2295 { .name
= "TLB_LOCKW", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 5, .opc2
= 4,
2296 .access
= PL1_W
, .resetvalue
= 0, .type
= ARM_CP_NOP
},
2297 { .name
= "TLB_VA", .cp
= 15, .crn
= 15, .crm
= 5, .opc1
= 5, .opc2
= 2,
2298 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
2299 { .name
= "TLB_PA", .cp
= 15, .crn
= 15, .crm
= 6, .opc1
= 5, .opc2
= 2,
2300 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
2301 { .name
= "TLB_ATTR", .cp
= 15, .crn
= 15, .crm
= 7, .opc1
= 5, .opc2
= 2,
2302 .access
= PL1_RW
, .resetvalue
= 0, .type
= ARM_CP_CONST
},
2306 static void cortex_a9_initfn(Object
*obj
)
2308 ARMCPU
*cpu
= ARM_CPU(obj
);
2310 cpu
->dtb_compatible
= "arm,cortex-a9";
2311 set_feature(&cpu
->env
, ARM_FEATURE_V7
);
2312 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
2313 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
2314 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
2315 /* Note that A9 supports the MP extensions even for
2316 * A9UP and single-core A9MP (which are both different
2317 * and valid configurations; we don't model A9UP).
2319 set_feature(&cpu
->env
, ARM_FEATURE_V7MP
);
2320 set_feature(&cpu
->env
, ARM_FEATURE_CBAR
);
2321 cpu
->midr
= 0x410fc090;
2322 cpu
->reset_fpsid
= 0x41033090;
2323 cpu
->isar
.mvfr0
= 0x11110222;
2324 cpu
->isar
.mvfr1
= 0x01111111;
2325 cpu
->ctr
= 0x80038003;
2326 cpu
->reset_sctlr
= 0x00c50078;
2327 cpu
->id_pfr0
= 0x1031;
2328 cpu
->id_pfr1
= 0x11;
2329 cpu
->isar
.id_dfr0
= 0x000;
2331 cpu
->isar
.id_mmfr0
= 0x00100103;
2332 cpu
->isar
.id_mmfr1
= 0x20000000;
2333 cpu
->isar
.id_mmfr2
= 0x01230000;
2334 cpu
->isar
.id_mmfr3
= 0x00002111;
2335 cpu
->isar
.id_isar0
= 0x00101111;
2336 cpu
->isar
.id_isar1
= 0x13112111;
2337 cpu
->isar
.id_isar2
= 0x21232041;
2338 cpu
->isar
.id_isar3
= 0x11112131;
2339 cpu
->isar
.id_isar4
= 0x00111142;
2340 cpu
->isar
.dbgdidr
= 0x35141000;
2341 cpu
->clidr
= (1 << 27) | (1 << 24) | 3;
2342 cpu
->ccsidr
[0] = 0xe00fe019; /* 16k L1 dcache. */
2343 cpu
->ccsidr
[1] = 0x200fe019; /* 16k L1 icache. */
2344 define_arm_cp_regs(cpu
, cortexa9_cp_reginfo
);
2347 #ifndef CONFIG_USER_ONLY
2348 static uint64_t a15_l2ctlr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
2350 MachineState
*ms
= MACHINE(qdev_get_machine());
2352 /* Linux wants the number of processors from here.
2353 * Might as well set the interrupt-controller bit too.
2355 return ((ms
->smp
.cpus
- 1) << 24) | (1 << 23);
2359 static const ARMCPRegInfo cortexa15_cp_reginfo
[] = {
2360 #ifndef CONFIG_USER_ONLY
2361 { .name
= "L2CTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 2,
2362 .access
= PL1_RW
, .resetvalue
= 0, .readfn
= a15_l2ctlr_read
,
2363 .writefn
= arm_cp_write_ignore
, },
2365 { .name
= "L2ECTLR", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 1, .opc2
= 3,
2366 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
2370 static void cortex_a7_initfn(Object
*obj
)
2372 ARMCPU
*cpu
= ARM_CPU(obj
);
2374 cpu
->dtb_compatible
= "arm,cortex-a7";
2375 set_feature(&cpu
->env
, ARM_FEATURE_V7VE
);
2376 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
2377 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
2378 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
2379 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2380 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
2381 set_feature(&cpu
->env
, ARM_FEATURE_EL2
);
2382 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
2383 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
2384 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A7
;
2385 cpu
->midr
= 0x410fc075;
2386 cpu
->reset_fpsid
= 0x41023075;
2387 cpu
->isar
.mvfr0
= 0x10110222;
2388 cpu
->isar
.mvfr1
= 0x11111111;
2389 cpu
->ctr
= 0x84448003;
2390 cpu
->reset_sctlr
= 0x00c50078;
2391 cpu
->id_pfr0
= 0x00001131;
2392 cpu
->id_pfr1
= 0x00011011;
2393 cpu
->isar
.id_dfr0
= 0x02010555;
2394 cpu
->id_afr0
= 0x00000000;
2395 cpu
->isar
.id_mmfr0
= 0x10101105;
2396 cpu
->isar
.id_mmfr1
= 0x40000000;
2397 cpu
->isar
.id_mmfr2
= 0x01240000;
2398 cpu
->isar
.id_mmfr3
= 0x02102211;
2399 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
2400 * table 4-41 gives 0x02101110, which includes the arm div insns.
2402 cpu
->isar
.id_isar0
= 0x02101110;
2403 cpu
->isar
.id_isar1
= 0x13112111;
2404 cpu
->isar
.id_isar2
= 0x21232041;
2405 cpu
->isar
.id_isar3
= 0x11112131;
2406 cpu
->isar
.id_isar4
= 0x10011142;
2407 cpu
->isar
.dbgdidr
= 0x3515f005;
2408 cpu
->clidr
= 0x0a200023;
2409 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
2410 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
2411 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
2412 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
); /* Same as A15 */
2415 static void cortex_a15_initfn(Object
*obj
)
2417 ARMCPU
*cpu
= ARM_CPU(obj
);
2419 cpu
->dtb_compatible
= "arm,cortex-a15";
2420 set_feature(&cpu
->env
, ARM_FEATURE_V7VE
);
2421 set_feature(&cpu
->env
, ARM_FEATURE_NEON
);
2422 set_feature(&cpu
->env
, ARM_FEATURE_THUMB2EE
);
2423 set_feature(&cpu
->env
, ARM_FEATURE_GENERIC_TIMER
);
2424 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2425 set_feature(&cpu
->env
, ARM_FEATURE_CBAR_RO
);
2426 set_feature(&cpu
->env
, ARM_FEATURE_EL2
);
2427 set_feature(&cpu
->env
, ARM_FEATURE_EL3
);
2428 set_feature(&cpu
->env
, ARM_FEATURE_PMU
);
2429 cpu
->kvm_target
= QEMU_KVM_ARM_TARGET_CORTEX_A15
;
2430 cpu
->midr
= 0x412fc0f1;
2431 cpu
->reset_fpsid
= 0x410430f0;
2432 cpu
->isar
.mvfr0
= 0x10110222;
2433 cpu
->isar
.mvfr1
= 0x11111111;
2434 cpu
->ctr
= 0x8444c004;
2435 cpu
->reset_sctlr
= 0x00c50078;
2436 cpu
->id_pfr0
= 0x00001131;
2437 cpu
->id_pfr1
= 0x00011011;
2438 cpu
->isar
.id_dfr0
= 0x02010555;
2439 cpu
->id_afr0
= 0x00000000;
2440 cpu
->isar
.id_mmfr0
= 0x10201105;
2441 cpu
->isar
.id_mmfr1
= 0x20000000;
2442 cpu
->isar
.id_mmfr2
= 0x01240000;
2443 cpu
->isar
.id_mmfr3
= 0x02102211;
2444 cpu
->isar
.id_isar0
= 0x02101110;
2445 cpu
->isar
.id_isar1
= 0x13112111;
2446 cpu
->isar
.id_isar2
= 0x21232041;
2447 cpu
->isar
.id_isar3
= 0x11112131;
2448 cpu
->isar
.id_isar4
= 0x10011142;
2449 cpu
->isar
.dbgdidr
= 0x3515f021;
2450 cpu
->clidr
= 0x0a200023;
2451 cpu
->ccsidr
[0] = 0x701fe00a; /* 32K L1 dcache */
2452 cpu
->ccsidr
[1] = 0x201fe00a; /* 32K L1 icache */
2453 cpu
->ccsidr
[2] = 0x711fe07a; /* 4096K L2 unified cache */
2454 define_arm_cp_regs(cpu
, cortexa15_cp_reginfo
);
2457 static void ti925t_initfn(Object
*obj
)
2459 ARMCPU
*cpu
= ARM_CPU(obj
);
2460 set_feature(&cpu
->env
, ARM_FEATURE_V4T
);
2461 set_feature(&cpu
->env
, ARM_FEATURE_OMAPCP
);
2462 cpu
->midr
= ARM_CPUID_TI925T
;
2463 cpu
->ctr
= 0x5109149;
2464 cpu
->reset_sctlr
= 0x00000070;
2467 static void sa1100_initfn(Object
*obj
)
2469 ARMCPU
*cpu
= ARM_CPU(obj
);
2471 cpu
->dtb_compatible
= "intel,sa1100";
2472 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
2473 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2474 cpu
->midr
= 0x4401A11B;
2475 cpu
->reset_sctlr
= 0x00000070;
2478 static void sa1110_initfn(Object
*obj
)
2480 ARMCPU
*cpu
= ARM_CPU(obj
);
2481 set_feature(&cpu
->env
, ARM_FEATURE_STRONGARM
);
2482 set_feature(&cpu
->env
, ARM_FEATURE_DUMMY_C15_REGS
);
2483 cpu
->midr
= 0x6901B119;
2484 cpu
->reset_sctlr
= 0x00000070;
2487 static void pxa250_initfn(Object
*obj
)
2489 ARMCPU
*cpu
= ARM_CPU(obj
);
2491 cpu
->dtb_compatible
= "marvell,xscale";
2492 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2493 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2494 cpu
->midr
= 0x69052100;
2495 cpu
->ctr
= 0xd172172;
2496 cpu
->reset_sctlr
= 0x00000078;
2499 static void pxa255_initfn(Object
*obj
)
2501 ARMCPU
*cpu
= ARM_CPU(obj
);
2503 cpu
->dtb_compatible
= "marvell,xscale";
2504 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2505 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2506 cpu
->midr
= 0x69052d00;
2507 cpu
->ctr
= 0xd172172;
2508 cpu
->reset_sctlr
= 0x00000078;
2511 static void pxa260_initfn(Object
*obj
)
2513 ARMCPU
*cpu
= ARM_CPU(obj
);
2515 cpu
->dtb_compatible
= "marvell,xscale";
2516 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2517 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2518 cpu
->midr
= 0x69052903;
2519 cpu
->ctr
= 0xd172172;
2520 cpu
->reset_sctlr
= 0x00000078;
2523 static void pxa261_initfn(Object
*obj
)
2525 ARMCPU
*cpu
= ARM_CPU(obj
);
2527 cpu
->dtb_compatible
= "marvell,xscale";
2528 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2529 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2530 cpu
->midr
= 0x69052d05;
2531 cpu
->ctr
= 0xd172172;
2532 cpu
->reset_sctlr
= 0x00000078;
2535 static void pxa262_initfn(Object
*obj
)
2537 ARMCPU
*cpu
= ARM_CPU(obj
);
2539 cpu
->dtb_compatible
= "marvell,xscale";
2540 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2541 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2542 cpu
->midr
= 0x69052d06;
2543 cpu
->ctr
= 0xd172172;
2544 cpu
->reset_sctlr
= 0x00000078;
2547 static void pxa270a0_initfn(Object
*obj
)
2549 ARMCPU
*cpu
= ARM_CPU(obj
);
2551 cpu
->dtb_compatible
= "marvell,xscale";
2552 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2553 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2554 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2555 cpu
->midr
= 0x69054110;
2556 cpu
->ctr
= 0xd172172;
2557 cpu
->reset_sctlr
= 0x00000078;
2560 static void pxa270a1_initfn(Object
*obj
)
2562 ARMCPU
*cpu
= ARM_CPU(obj
);
2564 cpu
->dtb_compatible
= "marvell,xscale";
2565 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2566 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2567 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2568 cpu
->midr
= 0x69054111;
2569 cpu
->ctr
= 0xd172172;
2570 cpu
->reset_sctlr
= 0x00000078;
2573 static void pxa270b0_initfn(Object
*obj
)
2575 ARMCPU
*cpu
= ARM_CPU(obj
);
2577 cpu
->dtb_compatible
= "marvell,xscale";
2578 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2579 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2580 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2581 cpu
->midr
= 0x69054112;
2582 cpu
->ctr
= 0xd172172;
2583 cpu
->reset_sctlr
= 0x00000078;
2586 static void pxa270b1_initfn(Object
*obj
)
2588 ARMCPU
*cpu
= ARM_CPU(obj
);
2590 cpu
->dtb_compatible
= "marvell,xscale";
2591 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2592 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2593 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2594 cpu
->midr
= 0x69054113;
2595 cpu
->ctr
= 0xd172172;
2596 cpu
->reset_sctlr
= 0x00000078;
2599 static void pxa270c0_initfn(Object
*obj
)
2601 ARMCPU
*cpu
= ARM_CPU(obj
);
2603 cpu
->dtb_compatible
= "marvell,xscale";
2604 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2605 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2606 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2607 cpu
->midr
= 0x69054114;
2608 cpu
->ctr
= 0xd172172;
2609 cpu
->reset_sctlr
= 0x00000078;
2612 static void pxa270c5_initfn(Object
*obj
)
2614 ARMCPU
*cpu
= ARM_CPU(obj
);
2616 cpu
->dtb_compatible
= "marvell,xscale";
2617 set_feature(&cpu
->env
, ARM_FEATURE_V5
);
2618 set_feature(&cpu
->env
, ARM_FEATURE_XSCALE
);
2619 set_feature(&cpu
->env
, ARM_FEATURE_IWMMXT
);
2620 cpu
->midr
= 0x69054117;
2621 cpu
->ctr
= 0xd172172;
2622 cpu
->reset_sctlr
= 0x00000078;
2625 #ifndef TARGET_AARCH64
2626 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
2627 * otherwise, a CPU with as many features enabled as our emulation supports.
2628 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
2629 * this only needs to handle 32 bits.
2631 static void arm_max_initfn(Object
*obj
)
2633 ARMCPU
*cpu
= ARM_CPU(obj
);
2635 if (kvm_enabled()) {
2636 kvm_arm_set_cpu_features_from_host(cpu
);
2637 kvm_arm_add_vcpu_properties(obj
);
2639 cortex_a15_initfn(obj
);
2641 /* old-style VFP short-vector support */
2642 cpu
->isar
.mvfr0
= FIELD_DP32(cpu
->isar
.mvfr0
, MVFR0
, FPSHVEC
, 1);
2644 #ifdef CONFIG_USER_ONLY
2645 /* We don't set these in system emulation mode for the moment,
2646 * since we don't correctly set (all of) the ID registers to
2649 set_feature(&cpu
->env
, ARM_FEATURE_V8
);
2653 t
= cpu
->isar
.id_isar5
;
2654 t
= FIELD_DP32(t
, ID_ISAR5
, AES
, 2);
2655 t
= FIELD_DP32(t
, ID_ISAR5
, SHA1
, 1);
2656 t
= FIELD_DP32(t
, ID_ISAR5
, SHA2
, 1);
2657 t
= FIELD_DP32(t
, ID_ISAR5
, CRC32
, 1);
2658 t
= FIELD_DP32(t
, ID_ISAR5
, RDM
, 1);
2659 t
= FIELD_DP32(t
, ID_ISAR5
, VCMA
, 1);
2660 cpu
->isar
.id_isar5
= t
;
2662 t
= cpu
->isar
.id_isar6
;
2663 t
= FIELD_DP32(t
, ID_ISAR6
, JSCVT
, 1);
2664 t
= FIELD_DP32(t
, ID_ISAR6
, DP
, 1);
2665 t
= FIELD_DP32(t
, ID_ISAR6
, FHM
, 1);
2666 t
= FIELD_DP32(t
, ID_ISAR6
, SB
, 1);
2667 t
= FIELD_DP32(t
, ID_ISAR6
, SPECRES
, 1);
2668 cpu
->isar
.id_isar6
= t
;
2670 t
= cpu
->isar
.mvfr1
;
2671 t
= FIELD_DP32(t
, MVFR1
, FPHP
, 2); /* v8.0 FP support */
2672 cpu
->isar
.mvfr1
= t
;
2674 t
= cpu
->isar
.mvfr2
;
2675 t
= FIELD_DP32(t
, MVFR2
, SIMDMISC
, 3); /* SIMD MaxNum */
2676 t
= FIELD_DP32(t
, MVFR2
, FPMISC
, 4); /* FP MaxNum */
2677 cpu
->isar
.mvfr2
= t
;
2679 t
= cpu
->isar
.id_mmfr3
;
2680 t
= FIELD_DP32(t
, ID_MMFR3
, PAN
, 2); /* ATS1E1 */
2681 cpu
->isar
.id_mmfr3
= t
;
2683 t
= cpu
->isar
.id_mmfr4
;
2684 t
= FIELD_DP32(t
, ID_MMFR4
, HPDS
, 1); /* AA32HPD */
2685 t
= FIELD_DP32(t
, ID_MMFR4
, AC2
, 1); /* ACTLR2, HACTLR2 */
2686 t
= FIELD_DP32(t
, ID_MMFR4
, CNP
, 1); /* TTCNP */
2687 cpu
->isar
.id_mmfr4
= t
;
2694 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
2698 void (*initfn
)(Object
*obj
);
2699 void (*class_init
)(ObjectClass
*oc
, void *data
);
2702 static const ARMCPUInfo arm_cpus
[] = {
2703 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
2704 { .name
= "arm926", .initfn
= arm926_initfn
},
2705 { .name
= "arm946", .initfn
= arm946_initfn
},
2706 { .name
= "arm1026", .initfn
= arm1026_initfn
},
2707 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
2708 * older core than plain "arm1136". In particular this does not
2709 * have the v6K features.
2711 { .name
= "arm1136-r2", .initfn
= arm1136_r2_initfn
},
2712 { .name
= "arm1136", .initfn
= arm1136_initfn
},
2713 { .name
= "arm1176", .initfn
= arm1176_initfn
},
2714 { .name
= "arm11mpcore", .initfn
= arm11mpcore_initfn
},
2715 { .name
= "cortex-m0", .initfn
= cortex_m0_initfn
,
2716 .class_init
= arm_v7m_class_init
},
2717 { .name
= "cortex-m3", .initfn
= cortex_m3_initfn
,
2718 .class_init
= arm_v7m_class_init
},
2719 { .name
= "cortex-m4", .initfn
= cortex_m4_initfn
,
2720 .class_init
= arm_v7m_class_init
},
2721 { .name
= "cortex-m7", .initfn
= cortex_m7_initfn
,
2722 .class_init
= arm_v7m_class_init
},
2723 { .name
= "cortex-m33", .initfn
= cortex_m33_initfn
,
2724 .class_init
= arm_v7m_class_init
},
2725 { .name
= "cortex-r5", .initfn
= cortex_r5_initfn
},
2726 { .name
= "cortex-r5f", .initfn
= cortex_r5f_initfn
},
2727 { .name
= "cortex-a7", .initfn
= cortex_a7_initfn
},
2728 { .name
= "cortex-a8", .initfn
= cortex_a8_initfn
},
2729 { .name
= "cortex-a9", .initfn
= cortex_a9_initfn
},
2730 { .name
= "cortex-a15", .initfn
= cortex_a15_initfn
},
2731 { .name
= "ti925t", .initfn
= ti925t_initfn
},
2732 { .name
= "sa1100", .initfn
= sa1100_initfn
},
2733 { .name
= "sa1110", .initfn
= sa1110_initfn
},
2734 { .name
= "pxa250", .initfn
= pxa250_initfn
},
2735 { .name
= "pxa255", .initfn
= pxa255_initfn
},
2736 { .name
= "pxa260", .initfn
= pxa260_initfn
},
2737 { .name
= "pxa261", .initfn
= pxa261_initfn
},
2738 { .name
= "pxa262", .initfn
= pxa262_initfn
},
2739 /* "pxa270" is an alias for "pxa270-a0" */
2740 { .name
= "pxa270", .initfn
= pxa270a0_initfn
},
2741 { .name
= "pxa270-a0", .initfn
= pxa270a0_initfn
},
2742 { .name
= "pxa270-a1", .initfn
= pxa270a1_initfn
},
2743 { .name
= "pxa270-b0", .initfn
= pxa270b0_initfn
},
2744 { .name
= "pxa270-b1", .initfn
= pxa270b1_initfn
},
2745 { .name
= "pxa270-c0", .initfn
= pxa270c0_initfn
},
2746 { .name
= "pxa270-c5", .initfn
= pxa270c5_initfn
},
2747 #ifndef TARGET_AARCH64
2748 { .name
= "max", .initfn
= arm_max_initfn
},
2750 #ifdef CONFIG_USER_ONLY
2751 { .name
= "any", .initfn
= arm_max_initfn
},
2757 static Property arm_cpu_properties
[] = {
2758 DEFINE_PROP_BOOL("start-powered-off", ARMCPU
, start_powered_off
, false),
2759 DEFINE_PROP_UINT32("psci-conduit", ARMCPU
, psci_conduit
, 0),
2760 DEFINE_PROP_UINT32("midr", ARMCPU
, midr
, 0),
2761 DEFINE_PROP_UINT64("mp-affinity", ARMCPU
,
2762 mp_affinity
, ARM64_AFFINITY_INVALID
),
2763 DEFINE_PROP_INT32("node-id", ARMCPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
2764 DEFINE_PROP_INT32("core-count", ARMCPU
, core_count
, -1),
2765 DEFINE_PROP_END_OF_LIST()
2768 static gchar
*arm_gdb_arch_name(CPUState
*cs
)
2770 ARMCPU
*cpu
= ARM_CPU(cs
);
2771 CPUARMState
*env
= &cpu
->env
;
2773 if (arm_feature(env
, ARM_FEATURE_IWMMXT
)) {
2774 return g_strdup("iwmmxt");
2776 return g_strdup("arm");
2779 static void arm_cpu_class_init(ObjectClass
*oc
, void *data
)
2781 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2782 CPUClass
*cc
= CPU_CLASS(acc
);
2783 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2785 device_class_set_parent_realize(dc
, arm_cpu_realizefn
,
2786 &acc
->parent_realize
);
2788 device_class_set_props(dc
, arm_cpu_properties
);
2789 device_class_set_parent_reset(dc
, arm_cpu_reset
, &acc
->parent_reset
);
2791 cc
->class_by_name
= arm_cpu_class_by_name
;
2792 cc
->has_work
= arm_cpu_has_work
;
2793 cc
->cpu_exec_interrupt
= arm_cpu_exec_interrupt
;
2794 cc
->dump_state
= arm_cpu_dump_state
;
2795 cc
->set_pc
= arm_cpu_set_pc
;
2796 cc
->synchronize_from_tb
= arm_cpu_synchronize_from_tb
;
2797 cc
->gdb_read_register
= arm_cpu_gdb_read_register
;
2798 cc
->gdb_write_register
= arm_cpu_gdb_write_register
;
2799 #ifndef CONFIG_USER_ONLY
2800 cc
->do_interrupt
= arm_cpu_do_interrupt
;
2801 cc
->get_phys_page_attrs_debug
= arm_cpu_get_phys_page_attrs_debug
;
2802 cc
->asidx_from_attrs
= arm_asidx_from_attrs
;
2803 cc
->vmsd
= &vmstate_arm_cpu
;
2804 cc
->virtio_is_big_endian
= arm_cpu_virtio_is_big_endian
;
2805 cc
->write_elf64_note
= arm_cpu_write_elf64_note
;
2806 cc
->write_elf32_note
= arm_cpu_write_elf32_note
;
2808 cc
->gdb_num_core_regs
= 26;
2809 cc
->gdb_core_xml_file
= "arm-core.xml";
2810 cc
->gdb_arch_name
= arm_gdb_arch_name
;
2811 cc
->gdb_get_dynamic_xml
= arm_gdb_get_dynamic_xml
;
2812 cc
->gdb_stop_before_watchpoint
= true;
2813 cc
->disas_set_info
= arm_disas_set_info
;
2815 cc
->tcg_initialize
= arm_translate_init
;
2816 cc
->tlb_fill
= arm_cpu_tlb_fill
;
2817 cc
->debug_excp_handler
= arm_debug_excp_handler
;
2818 cc
->debug_check_watchpoint
= arm_debug_check_watchpoint
;
2819 #if !defined(CONFIG_USER_ONLY)
2820 cc
->do_unaligned_access
= arm_cpu_do_unaligned_access
;
2821 cc
->do_transaction_failed
= arm_cpu_do_transaction_failed
;
2822 cc
->adjust_watchpoint_address
= arm_adjust_watchpoint_address
;
2823 #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
2828 static void arm_host_initfn(Object
*obj
)
2830 ARMCPU
*cpu
= ARM_CPU(obj
);
2832 kvm_arm_set_cpu_features_from_host(cpu
);
2833 if (arm_feature(&cpu
->env
, ARM_FEATURE_AARCH64
)) {
2834 aarch64_add_sve_properties(obj
);
2836 kvm_arm_add_vcpu_properties(obj
);
2837 arm_cpu_post_init(obj
);
2840 static const TypeInfo host_arm_cpu_type_info
= {
2841 .name
= TYPE_ARM_HOST_CPU
,
2842 #ifdef TARGET_AARCH64
2843 .parent
= TYPE_AARCH64_CPU
,
2845 .parent
= TYPE_ARM_CPU
,
2847 .instance_init
= arm_host_initfn
,
2852 static void arm_cpu_instance_init(Object
*obj
)
2854 ARMCPUClass
*acc
= ARM_CPU_GET_CLASS(obj
);
2856 acc
->info
->initfn(obj
);
2857 arm_cpu_post_init(obj
);
2860 static void cpu_register_class_init(ObjectClass
*oc
, void *data
)
2862 ARMCPUClass
*acc
= ARM_CPU_CLASS(oc
);
2867 static void cpu_register(const ARMCPUInfo
*info
)
2869 TypeInfo type_info
= {
2870 .parent
= TYPE_ARM_CPU
,
2871 .instance_size
= sizeof(ARMCPU
),
2872 .instance_init
= arm_cpu_instance_init
,
2873 .class_size
= sizeof(ARMCPUClass
),
2874 .class_init
= info
->class_init
?: cpu_register_class_init
,
2875 .class_data
= (void *)info
,
2878 type_info
.name
= g_strdup_printf("%s-" TYPE_ARM_CPU
, info
->name
);
2879 type_register(&type_info
);
2880 g_free((void *)type_info
.name
);
2883 static const TypeInfo arm_cpu_type_info
= {
2884 .name
= TYPE_ARM_CPU
,
2886 .instance_size
= sizeof(ARMCPU
),
2887 .instance_init
= arm_cpu_initfn
,
2888 .instance_finalize
= arm_cpu_finalizefn
,
2890 .class_size
= sizeof(ARMCPUClass
),
2891 .class_init
= arm_cpu_class_init
,
2894 static const TypeInfo idau_interface_type_info
= {
2895 .name
= TYPE_IDAU_INTERFACE
,
2896 .parent
= TYPE_INTERFACE
,
2897 .class_size
= sizeof(IDAUInterfaceClass
),
2900 static void arm_cpu_register_types(void)
2902 const ARMCPUInfo
*info
= arm_cpus
;
2904 type_register_static(&arm_cpu_type_info
);
2905 type_register_static(&idau_interface_type_info
);
2907 while (info
->name
) {
2913 type_register_static(&host_arm_cpu_type_info
);
2917 type_init(arm_cpu_register_types
)