2 * Q35 chipset based pc system emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2009, 2010
6 * Isaku Yamahata <yamahata at valinux co jp>
7 * VA Linux Systems Japan K.K.
8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
10 * This is based on pc.c, but heavily modified.
12 * Permission is hereby granted, free of charge, to any person obtaining a copy
13 * of this software and associated documentation files (the "Software"), to deal
14 * in the Software without restriction, including without limitation the rights
15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16 * copies of the Software, and to permit persons to whom the Software is
17 * furnished to do so, subject to the following conditions:
19 * The above copyright notice and this permission notice shall be included in
20 * all copies or substantial portions of the Software.
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 #include "qemu/osdep.h"
32 #include "hw/loader.h"
33 #include "sysemu/arch_init.h"
34 #include "hw/i2c/smbus.h"
35 #include "hw/boards.h"
36 #include "hw/timer/mc146818rtc.h"
37 #include "hw/xen/xen.h"
38 #include "sysemu/kvm.h"
40 #include "hw/kvm/clock.h"
41 #include "hw/pci-host/q35.h"
42 #include "exec/address-spaces.h"
43 #include "hw/i386/pc.h"
44 #include "hw/i386/ich9.h"
45 #include "hw/smbios/smbios.h"
46 #include "hw/ide/pci.h"
47 #include "hw/ide/ahci.h"
49 #include "qemu/error-report.h"
50 #include "sysemu/numa.h"
52 /* ICH9 AHCI has 6 ports */
53 #define MAX_SATA_PORTS 6
55 /* PC hardware initialisation */
56 static void pc_q35_init(MachineState
*machine
)
58 PCMachineState
*pcms
= PC_MACHINE(machine
);
59 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
65 BusState
*idebus
[MAX_SATA_PORTS
];
67 MemoryRegion
*system_io
= get_system_io();
68 MemoryRegion
*pci_memory
;
69 MemoryRegion
*rom_memory
;
70 MemoryRegion
*ram_memory
;
75 ICH9LPCState
*ich9_lpc
;
78 DriveInfo
*hd
[MAX_SATA_PORTS
];
79 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
81 /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory
82 * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapping
83 * also known as MMCFG).
84 * If it doesn't, we need to split it in chunks below and above 4G.
85 * In any case, try to make sure that guest addresses aligned at
86 * 1G boundaries get mapped to host addresses aligned at 1G boundaries.
88 if (machine
->ram_size
>= 0xb0000000) {
94 /* Handle the machine opt max-ram-below-4g. It is basically doing
95 * min(qemu limit, user limit).
97 if (!pcms
->max_ram_below_4g
) {
98 pcms
->max_ram_below_4g
= 1ULL << 32; /* default: 4G */;
100 if (lowmem
> pcms
->max_ram_below_4g
) {
101 lowmem
= pcms
->max_ram_below_4g
;
102 if (machine
->ram_size
- lowmem
> lowmem
&&
103 lowmem
& ((1ULL << 30) - 1)) {
104 warn_report("There is possibly poor performance as the ram size "
105 " (0x%" PRIx64
") is more then twice the size of"
106 " max-ram-below-4g (%"PRIu64
") and"
107 " max-ram-below-4g is not a multiple of 1G.",
108 (uint64_t)machine
->ram_size
, pcms
->max_ram_below_4g
);
112 if (machine
->ram_size
>= lowmem
) {
113 pcms
->above_4g_mem_size
= machine
->ram_size
- lowmem
;
114 pcms
->below_4g_mem_size
= lowmem
;
116 pcms
->above_4g_mem_size
= 0;
117 pcms
->below_4g_mem_size
= machine
->ram_size
;
121 xen_hvm_init(pcms
, &ram_memory
);
129 if (pcmc
->pci_enabled
) {
130 pci_memory
= g_new(MemoryRegion
, 1);
131 memory_region_init(pci_memory
, NULL
, "pci", UINT64_MAX
);
132 rom_memory
= pci_memory
;
135 rom_memory
= get_system_memory();
138 pc_guest_info_init(pcms
);
140 if (pcmc
->smbios_defaults
) {
141 /* These values are guest ABI, do not change */
142 smbios_set_defaults("QEMU", "Standard PC (Q35 + ICH9, 2009)",
143 mc
->name
, pcmc
->smbios_legacy_mode
,
144 pcmc
->smbios_uuid_encoded
,
145 SMBIOS_ENTRY_POINT_21
);
148 /* allocate ram and load rom/bios */
149 if (!xen_enabled()) {
150 pc_memory_init(pcms
, get_system_memory(),
151 rom_memory
, &ram_memory
);
155 gsi_state
= g_malloc0(sizeof(*gsi_state
));
156 if (kvm_ioapic_in_kernel()) {
157 kvm_pc_setup_irq_routing(pcmc
->pci_enabled
);
158 pcms
->gsi
= qemu_allocate_irqs(kvm_pc_gsi_handler
, gsi_state
,
161 pcms
->gsi
= qemu_allocate_irqs(gsi_handler
, gsi_state
, GSI_NUM_PINS
);
164 /* create pci host bus */
165 q35_host
= Q35_HOST_DEVICE(qdev_create(NULL
, TYPE_Q35_HOST_DEVICE
));
167 object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host
), NULL
);
168 object_property_set_link(OBJECT(q35_host
), OBJECT(ram_memory
),
169 MCH_HOST_PROP_RAM_MEM
, NULL
);
170 object_property_set_link(OBJECT(q35_host
), OBJECT(pci_memory
),
171 MCH_HOST_PROP_PCI_MEM
, NULL
);
172 object_property_set_link(OBJECT(q35_host
), OBJECT(get_system_memory()),
173 MCH_HOST_PROP_SYSTEM_MEM
, NULL
);
174 object_property_set_link(OBJECT(q35_host
), OBJECT(system_io
),
175 MCH_HOST_PROP_IO_MEM
, NULL
);
176 object_property_set_int(OBJECT(q35_host
), pcms
->below_4g_mem_size
,
177 PCI_HOST_BELOW_4G_MEM_SIZE
, NULL
);
178 object_property_set_int(OBJECT(q35_host
), pcms
->above_4g_mem_size
,
179 PCI_HOST_ABOVE_4G_MEM_SIZE
, NULL
);
181 qdev_init_nofail(DEVICE(q35_host
));
182 phb
= PCI_HOST_BRIDGE(q35_host
);
185 lpc
= pci_create_simple_multifunction(host_bus
, PCI_DEVFN(ICH9_LPC_DEV
,
186 ICH9_LPC_FUNC
), true,
187 TYPE_ICH9_LPC_DEVICE
);
189 object_property_add_link(OBJECT(machine
), PC_MACHINE_ACPI_DEVICE_PROP
,
190 TYPE_HOTPLUG_HANDLER
,
191 (Object
**)&pcms
->acpi_dev
,
192 object_property_allow_set_link
,
193 OBJ_PROP_LINK_UNREF_ON_RELEASE
, &error_abort
);
194 object_property_set_link(OBJECT(machine
), OBJECT(lpc
),
195 PC_MACHINE_ACPI_DEVICE_PROP
, &error_abort
);
197 ich9_lpc
= ICH9_LPC_DEVICE(lpc
);
198 lpc_dev
= DEVICE(lpc
);
199 for (i
= 0; i
< GSI_NUM_PINS
; i
++) {
200 qdev_connect_gpio_out_named(lpc_dev
, ICH9_GPIO_GSI
, i
, pcms
->gsi
[i
]);
202 pci_bus_irqs(host_bus
, ich9_lpc_set_irq
, ich9_lpc_map_irq
, ich9_lpc
,
204 pci_bus_set_route_irq_fn(host_bus
, ich9_route_intx_pin_to_irq
);
205 isa_bus
= ich9_lpc
->isa_bus
;
207 if (kvm_pic_in_kernel()) {
208 i8259
= kvm_i8259_init(isa_bus
);
209 } else if (xen_enabled()) {
210 i8259
= xen_interrupt_controller_init();
212 i8259
= i8259_init(isa_bus
, pc_allocate_cpu_irq());
215 for (i
= 0; i
< ISA_NUM_IRQS
; i
++) {
216 gsi_state
->i8259_irq
[i
] = i8259
[i
];
220 if (pcmc
->pci_enabled
) {
221 ioapic_init_gsi(gsi_state
, "q35");
224 pc_register_ferr_irq(pcms
->gsi
[13]);
226 assert(pcms
->vmport
!= ON_OFF_AUTO__MAX
);
227 if (pcms
->vmport
== ON_OFF_AUTO_AUTO
) {
228 pcms
->vmport
= xen_enabled() ? ON_OFF_AUTO_OFF
: ON_OFF_AUTO_ON
;
231 /* init basic PC hardware */
232 pc_basic_device_init(isa_bus
, pcms
->gsi
, &rtc_state
, !mc
->no_floppy
,
233 (pcms
->vmport
!= ON_OFF_AUTO_ON
), pcms
->pit
,
236 /* connect pm stuff to lpc */
237 ich9_lpc_pm_init(lpc
, pc_machine_is_smm_enabled(pcms
));
240 /* ahci and SATA device, for q35 1 ahci controller is built-in */
241 ahci
= pci_create_simple_multifunction(host_bus
,
242 PCI_DEVFN(ICH9_SATA1_DEV
,
245 idebus
[0] = qdev_get_child_bus(&ahci
->qdev
, "ide.0");
246 idebus
[1] = qdev_get_child_bus(&ahci
->qdev
, "ide.1");
247 g_assert(MAX_SATA_PORTS
== ahci_get_num_ports(ahci
));
248 ide_drive_get(hd
, ahci_get_num_ports(ahci
));
249 ahci_ide_create_devs(ahci
, hd
);
251 idebus
[0] = idebus
[1] = NULL
;
254 if (machine_usb(machine
)) {
255 /* Should we create 6 UHCI according to ich9 spec? */
256 ehci_create_ich9_with_companions(host_bus
, 0x1d);
260 /* TODO: Populate SPD eeprom data. */
261 smbus_eeprom_init(ich9_smb_init(host_bus
,
262 PCI_DEVFN(ICH9_SMB_DEV
, ICH9_SMB_FUNC
),
267 pc_cmos_init(pcms
, idebus
[0], idebus
[1], rtc_state
);
269 /* the rest devices to which pci devfn is automatically assigned */
270 pc_vga_init(isa_bus
, host_bus
);
271 pc_nic_init(isa_bus
, host_bus
);
272 if (pcmc
->pci_enabled
) {
273 pc_pci_device_init(host_bus
);
276 if (pcms
->acpi_nvdimm_state
.is_enabled
) {
277 nvdimm_init_acpi_state(&pcms
->acpi_nvdimm_state
, system_io
,
278 pcms
->fw_cfg
, OBJECT(pcms
));
282 #define DEFINE_Q35_MACHINE(suffix, name, compatfn, optionfn) \
283 static void pc_init_##suffix(MachineState *machine) \
285 void (*compat)(MachineState *m) = (compatfn); \
289 pc_q35_init(machine); \
291 DEFINE_PC_MACHINE(suffix, name, pc_init_##suffix, optionfn)
294 static void pc_q35_machine_options(MachineClass
*m
)
296 m
->family
= "pc_q35";
297 m
->desc
= "Standard PC (Q35 + ICH9, 2009)";
298 m
->hot_add_cpu
= pc_hot_add_cpu
;
299 m
->units_per_default_bus
= 1;
300 m
->default_machine_opts
= "firmware=bios-256k.bin";
301 m
->default_display
= "std";
303 m
->has_dynamic_sysbus
= true;
307 static void pc_q35_2_11_machine_options(MachineClass
*m
)
309 pc_q35_machine_options(m
);
313 DEFINE_Q35_MACHINE(v2_11
, "pc-q35-2.11", NULL
,
314 pc_q35_2_11_machine_options
);
316 static void pc_q35_2_10_machine_options(MachineClass
*m
)
318 pc_q35_2_11_machine_options(m
);
320 SET_MACHINE_COMPAT(m
, PC_COMPAT_2_10
);
321 m
->numa_auto_assign_ram
= numa_legacy_auto_assign_ram
;
324 DEFINE_Q35_MACHINE(v2_10
, "pc-q35-2.10", NULL
,
325 pc_q35_2_10_machine_options
);
327 static void pc_q35_2_9_machine_options(MachineClass
*m
)
329 pc_q35_2_10_machine_options(m
);
330 SET_MACHINE_COMPAT(m
, PC_COMPAT_2_9
);
333 DEFINE_Q35_MACHINE(v2_9
, "pc-q35-2.9", NULL
,
334 pc_q35_2_9_machine_options
);
336 static void pc_q35_2_8_machine_options(MachineClass
*m
)
338 pc_q35_2_9_machine_options(m
);
339 SET_MACHINE_COMPAT(m
, PC_COMPAT_2_8
);
342 DEFINE_Q35_MACHINE(v2_8
, "pc-q35-2.8", NULL
,
343 pc_q35_2_8_machine_options
);
345 static void pc_q35_2_7_machine_options(MachineClass
*m
)
347 pc_q35_2_8_machine_options(m
);
349 SET_MACHINE_COMPAT(m
, PC_COMPAT_2_7
);
352 DEFINE_Q35_MACHINE(v2_7
, "pc-q35-2.7", NULL
,
353 pc_q35_2_7_machine_options
);
355 static void pc_q35_2_6_machine_options(MachineClass
*m
)
357 PCMachineClass
*pcmc
= PC_MACHINE_CLASS(m
);
358 pc_q35_2_7_machine_options(m
);
359 pcmc
->legacy_cpu_hotplug
= true;
360 pcmc
->linuxboot_dma_enabled
= false;
361 SET_MACHINE_COMPAT(m
, PC_COMPAT_2_6
);
364 DEFINE_Q35_MACHINE(v2_6
, "pc-q35-2.6", NULL
,
365 pc_q35_2_6_machine_options
);
367 static void pc_q35_2_5_machine_options(MachineClass
*m
)
369 PCMachineClass
*pcmc
= PC_MACHINE_CLASS(m
);
370 pc_q35_2_6_machine_options(m
);
371 pcmc
->save_tsc_khz
= false;
372 m
->legacy_fw_cfg_order
= 1;
373 SET_MACHINE_COMPAT(m
, PC_COMPAT_2_5
);
376 DEFINE_Q35_MACHINE(v2_5
, "pc-q35-2.5", NULL
,
377 pc_q35_2_5_machine_options
);
379 static void pc_q35_2_4_machine_options(MachineClass
*m
)
381 PCMachineClass
*pcmc
= PC_MACHINE_CLASS(m
);
382 pc_q35_2_5_machine_options(m
);
383 m
->hw_version
= "2.4.0";
384 pcmc
->broken_reserved_end
= true;
385 SET_MACHINE_COMPAT(m
, PC_COMPAT_2_4
);
388 DEFINE_Q35_MACHINE(v2_4
, "pc-q35-2.4", NULL
,
389 pc_q35_2_4_machine_options
);