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mc146818rtc: put it into the 'misc' category
[qemu/ar7.git] / hw / riscv / virt.c
blob95a11adaa2f229fd0c3df34c1a9e82711f38ff96
1 /*
2 * QEMU RISC-V VirtIO Board
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * RISC-V machine with 16550a UART and VirtIO MMIO
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/units.h"
23 #include "qemu/error-report.h"
24 #include "qapi/error.h"
25 #include "hw/boards.h"
26 #include "hw/loader.h"
27 #include "hw/sysbus.h"
28 #include "hw/qdev-properties.h"
29 #include "hw/char/serial.h"
30 #include "target/riscv/cpu.h"
31 #include "hw/riscv/riscv_hart.h"
32 #include "hw/riscv/virt.h"
33 #include "hw/riscv/boot.h"
34 #include "hw/riscv/numa.h"
35 #include "hw/intc/sifive_clint.h"
36 #include "hw/intc/sifive_plic.h"
37 #include "hw/misc/sifive_test.h"
38 #include "chardev/char.h"
39 #include "sysemu/arch_init.h"
40 #include "sysemu/device_tree.h"
41 #include "sysemu/sysemu.h"
42 #include "hw/pci/pci.h"
43 #include "hw/pci-host/gpex.h"
44 #include "hw/display/ramfb.h"
45
46 static const MemMapEntry virt_memmap[] = {
47 [VIRT_DEBUG] = { 0x0, 0x100 },
48 [VIRT_MROM] = { 0x1000, 0xf000 },
49 [VIRT_TEST] = { 0x100000, 0x1000 },
50 [VIRT_RTC] = { 0x101000, 0x1000 },
51 [VIRT_CLINT] = { 0x2000000, 0x10000 },
52 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 },
53 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
54 [VIRT_UART0] = { 0x10000000, 0x100 },
55 [VIRT_VIRTIO] = { 0x10001000, 0x1000 },
56 [VIRT_FW_CFG] = { 0x10100000, 0x18 },
57 [VIRT_FLASH] = { 0x20000000, 0x4000000 },
58 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 },
59 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 },
60 [VIRT_DRAM] = { 0x80000000, 0x0 },
61 };
62
63 /* PCIe high mmio is fixed for RV32 */
64 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL
65 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB)
66
67 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */
68 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB)
69
70 static MemMapEntry virt_high_pcie_memmap;
71
72 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
73
74 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s,
75 const char *name,
76 const char *alias_prop_name)
77 {
78 /*
79 * Create a single flash device. We use the same parameters as
80 * the flash devices on the ARM virt board.
81 */
82 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
83
84 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
85 qdev_prop_set_uint8(dev, "width", 4);
86 qdev_prop_set_uint8(dev, "device-width", 2);
87 qdev_prop_set_bit(dev, "big-endian", false);
88 qdev_prop_set_uint16(dev, "id0", 0x89);
89 qdev_prop_set_uint16(dev, "id1", 0x18);
90 qdev_prop_set_uint16(dev, "id2", 0x00);
91 qdev_prop_set_uint16(dev, "id3", 0x00);
92 qdev_prop_set_string(dev, "name", name);
93
94 object_property_add_child(OBJECT(s), name, OBJECT(dev));
95 object_property_add_alias(OBJECT(s), alias_prop_name,
96 OBJECT(dev), "drive");
97
98 return PFLASH_CFI01(dev);
99 }
100
101 static void virt_flash_create(RISCVVirtState *s)
102 {
103 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0");
104 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1");
105 }
106
107 static void virt_flash_map1(PFlashCFI01 *flash,
108 hwaddr base, hwaddr size,
109 MemoryRegion *sysmem)
110 {
111 DeviceState *dev = DEVICE(flash);
112
113 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
114 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
115 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
116 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
117
118 memory_region_add_subregion(sysmem, base,
119 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
120 0));
121 }
122
123 static void virt_flash_map(RISCVVirtState *s,
124 MemoryRegion *sysmem)
125 {
126 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
127 hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
128
129 virt_flash_map1(s->flash[0], flashbase, flashsize,
130 sysmem);
131 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize,
132 sysmem);
133 }
134
135 static void create_pcie_irq_map(void *fdt, char *nodename,
136 uint32_t plic_phandle)
137 {
138 int pin, dev;
139 uint32_t
140 full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {};
141 uint32_t *irq_map = full_irq_map;
142
143 /* This code creates a standard swizzle of interrupts such that
144 * each device's first interrupt is based on it's PCI_SLOT number.
145 * (See pci_swizzle_map_irq_fn())
146 *
147 * We only need one entry per interrupt in the table (not one per
148 * possible slot) seeing the interrupt-map-mask will allow the table
149 * to wrap to any number of devices.
150 */
151 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
152 int devfn = dev * 0x8;
153
154 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
155 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
156 int i = 0;
157
158 irq_map[i] = cpu_to_be32(devfn << 8);
159
160 i += FDT_PCI_ADDR_CELLS;
161 irq_map[i] = cpu_to_be32(pin + 1);
162
163 i += FDT_PCI_INT_CELLS;
164 irq_map[i++] = cpu_to_be32(plic_phandle);
165
166 i += FDT_PLIC_ADDR_CELLS;
167 irq_map[i] = cpu_to_be32(irq_nr);
168
169 irq_map += FDT_INT_MAP_WIDTH;
170 }
171 }
172
173 qemu_fdt_setprop(fdt, nodename, "interrupt-map",
174 full_irq_map, sizeof(full_irq_map));
175
176 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
177 0x1800, 0, 0, 0x7);
178 }
179
180 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
181 uint64_t mem_size, const char *cmdline, bool is_32_bit)
182 {
183 void *fdt;
184 int i, cpu, socket;
185 MachineState *mc = MACHINE(s);
186 uint64_t addr, size;
187 uint32_t *clint_cells, *plic_cells;
188 unsigned long clint_addr, plic_addr;
189 uint32_t plic_phandle[MAX_NODES];
190 uint32_t cpu_phandle, intc_phandle, test_phandle;
191 uint32_t phandle = 1, plic_mmio_phandle = 1;
192 uint32_t plic_pcie_phandle = 1, plic_virtio_phandle = 1;
193 char *mem_name, *cpu_name, *core_name, *intc_name;
194 char *name, *clint_name, *plic_name, *clust_name;
195 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
196 hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
197
198 if (mc->dtb) {
199 fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
200 if (!fdt) {
201 error_report("load_device_tree() failed");
202 exit(1);
203 }
204 goto update_bootargs;
205 } else {
206 fdt = mc->fdt = create_device_tree(&s->fdt_size);
207 if (!fdt) {
208 error_report("create_device_tree() failed");
209 exit(1);
210 }
211 }
212
213 qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu");
214 qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio");
215 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
216 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
217
218 qemu_fdt_add_subnode(fdt, "/soc");
219 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
220 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
221 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
222 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
223
224 qemu_fdt_add_subnode(fdt, "/cpus");
225 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
226 SIFIVE_CLINT_TIMEBASE_FREQ);
227 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
228 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
229 qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
230
231 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) {
232 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket);
233 qemu_fdt_add_subnode(fdt, clust_name);
234
235 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
236 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4);
237
238 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
239 cpu_phandle = phandle++;
240
241 cpu_name = g_strdup_printf("/cpus/cpu@%d",
242 s->soc[socket].hartid_base + cpu);
243 qemu_fdt_add_subnode(fdt, cpu_name);
244 if (is_32_bit) {
245 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32");
246 } else {
247 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48");
248 }
249 name = riscv_isa_string(&s->soc[socket].harts[cpu]);
250 qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name);
251 g_free(name);
252 qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv");
253 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
254 qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
255 s->soc[socket].hartid_base + cpu);
256 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
257 riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket);
258 qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle);
259
260 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name);
261 qemu_fdt_add_subnode(fdt, intc_name);
262 intc_phandle = phandle++;
263 qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle);
264 qemu_fdt_setprop_string(fdt, intc_name, "compatible",
265 "riscv,cpu-intc");
266 qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0);
267 qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1);
268
269 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
270 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
271 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
272 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
273
274 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
275 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
276 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
277 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
278
279 core_name = g_strdup_printf("%s/core%d", clust_name, cpu);
280 qemu_fdt_add_subnode(fdt, core_name);
281 qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle);
282
283 g_free(core_name);
284 g_free(intc_name);
285 g_free(cpu_name);
286 }
287
288 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket);
289 size = riscv_socket_mem_size(mc, socket);
290 mem_name = g_strdup_printf("/memory@%lx", (long)addr);
291 qemu_fdt_add_subnode(fdt, mem_name);
292 qemu_fdt_setprop_cells(fdt, mem_name, "reg",
293 addr >> 32, addr, size >> 32, size);
294 qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory");
295 riscv_socket_fdt_write_id(mc, fdt, mem_name, socket);
296 g_free(mem_name);
297
298 clint_addr = memmap[VIRT_CLINT].base +
299 (memmap[VIRT_CLINT].size * socket);
300 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
301 qemu_fdt_add_subnode(fdt, clint_name);
302 qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0");
303 qemu_fdt_setprop_cells(fdt, clint_name, "reg",
304 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
305 qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
306 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
307 riscv_socket_fdt_write_id(mc, fdt, clint_name, socket);
308 g_free(clint_name);
309
310 plic_phandle[socket] = phandle++;
311 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket);
312 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr);
313 qemu_fdt_add_subnode(fdt, plic_name);
314 qemu_fdt_setprop_cell(fdt, plic_name,
315 "#address-cells", FDT_PLIC_ADDR_CELLS);
316 qemu_fdt_setprop_cell(fdt, plic_name,
317 "#interrupt-cells", FDT_PLIC_INT_CELLS);
318 qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0");
319 qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0);
320 qemu_fdt_setprop(fdt, plic_name, "interrupts-extended",
321 plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
322 qemu_fdt_setprop_cells(fdt, plic_name, "reg",
323 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size);
324 qemu_fdt_setprop_cell(fdt, plic_name, "riscv,ndev", VIRTIO_NDEV);
325 riscv_socket_fdt_write_id(mc, fdt, plic_name, socket);
326 qemu_fdt_setprop_cell(fdt, plic_name, "phandle", plic_phandle[socket]);
327 g_free(plic_name);
328
329 g_free(clint_cells);
330 g_free(plic_cells);
331 g_free(clust_name);
332 }
333
334 for (socket = 0; socket < riscv_socket_count(mc); socket++) {
335 if (socket == 0) {
336 plic_mmio_phandle = plic_phandle[socket];
337 plic_virtio_phandle = plic_phandle[socket];
338 plic_pcie_phandle = plic_phandle[socket];
339 }
340 if (socket == 1) {
341 plic_virtio_phandle = plic_phandle[socket];
342 plic_pcie_phandle = plic_phandle[socket];
343 }
344 if (socket == 2) {
345 plic_pcie_phandle = plic_phandle[socket];
346 }
347 }
348
349 riscv_socket_fdt_write_distance_matrix(mc, fdt);
350
351 for (i = 0; i < VIRTIO_COUNT; i++) {
352 name = g_strdup_printf("/soc/virtio_mmio@%lx",
353 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
354 qemu_fdt_add_subnode(fdt, name);
355 qemu_fdt_setprop_string(fdt, name, "compatible", "virtio,mmio");
356 qemu_fdt_setprop_cells(fdt, name, "reg",
357 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
358 0x0, memmap[VIRT_VIRTIO].size);
359 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent",
360 plic_virtio_phandle);
361 qemu_fdt_setprop_cell(fdt, name, "interrupts", VIRTIO_IRQ + i);
362 g_free(name);
363 }
364
365 name = g_strdup_printf("/soc/pci@%lx",
366 (long) memmap[VIRT_PCIE_ECAM].base);
367 qemu_fdt_add_subnode(fdt, name);
368 qemu_fdt_setprop_cell(fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS);
369 qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS);
370 qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0x2);
371 qemu_fdt_setprop_string(fdt, name, "compatible", "pci-host-ecam-generic");
372 qemu_fdt_setprop_string(fdt, name, "device_type", "pci");
373 qemu_fdt_setprop_cell(fdt, name, "linux,pci-domain", 0);
374 qemu_fdt_setprop_cells(fdt, name, "bus-range", 0,
375 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1);
376 qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0);
377 qemu_fdt_setprop_cells(fdt, name, "reg", 0,
378 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size);
379 qemu_fdt_setprop_sized_cells(fdt, name, "ranges",
380 1, FDT_PCI_RANGE_IOPORT, 2, 0,
381 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
382 1, FDT_PCI_RANGE_MMIO,
383 2, memmap[VIRT_PCIE_MMIO].base,
384 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size,
385 1, FDT_PCI_RANGE_MMIO_64BIT,
386 2, virt_high_pcie_memmap.base,
387 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size);
388
389 create_pcie_irq_map(fdt, name, plic_pcie_phandle);
390 g_free(name);
391
392 test_phandle = phandle++;
393 name = g_strdup_printf("/soc/test@%lx",
394 (long)memmap[VIRT_TEST].base);
395 qemu_fdt_add_subnode(fdt, name);
396 {
397 const char compat[] = "sifive,test1\0sifive,test0\0syscon";
398 qemu_fdt_setprop(fdt, name, "compatible", compat, sizeof(compat));
399 }
400 qemu_fdt_setprop_cells(fdt, name, "reg",
401 0x0, memmap[VIRT_TEST].base,
402 0x0, memmap[VIRT_TEST].size);
403 qemu_fdt_setprop_cell(fdt, name, "phandle", test_phandle);
404 test_phandle = qemu_fdt_get_phandle(fdt, name);
405 g_free(name);
406
407 name = g_strdup_printf("/soc/reboot");
408 qemu_fdt_add_subnode(fdt, name);
409 qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot");
410 qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle);
411 qemu_fdt_setprop_cell(fdt, name, "offset", 0x0);
412 qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_RESET);
413 g_free(name);
414
415 name = g_strdup_printf("/soc/poweroff");
416 qemu_fdt_add_subnode(fdt, name);
417 qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-poweroff");
418 qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle);
419 qemu_fdt_setprop_cell(fdt, name, "offset", 0x0);
420 qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_PASS);
421 g_free(name);
422
423 name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base);
424 qemu_fdt_add_subnode(fdt, name);
425 qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a");
426 qemu_fdt_setprop_cells(fdt, name, "reg",
427 0x0, memmap[VIRT_UART0].base,
428 0x0, memmap[VIRT_UART0].size);
429 qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 3686400);
430 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle);
431 qemu_fdt_setprop_cell(fdt, name, "interrupts", UART0_IRQ);
432
433 qemu_fdt_add_subnode(fdt, "/chosen");
434 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name);
435 g_free(name);
436
437 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base);
438 qemu_fdt_add_subnode(fdt, name);
439 qemu_fdt_setprop_string(fdt, name, "compatible", "google,goldfish-rtc");
440 qemu_fdt_setprop_cells(fdt, name, "reg",
441 0x0, memmap[VIRT_RTC].base,
442 0x0, memmap[VIRT_RTC].size);
443 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle);
444 qemu_fdt_setprop_cell(fdt, name, "interrupts", RTC_IRQ);
445 g_free(name);
446
447 name = g_strdup_printf("/soc/flash@%" PRIx64, flashbase);
448 qemu_fdt_add_subnode(mc->fdt, name);
449 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash");
450 qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg",
451 2, flashbase, 2, flashsize,
452 2, flashbase + flashsize, 2, flashsize);
453 qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4);
454 g_free(name);
455
456 update_bootargs:
457 if (cmdline) {
458 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
459 }
460 }
461
462 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
463 hwaddr ecam_base, hwaddr ecam_size,
464 hwaddr mmio_base, hwaddr mmio_size,
465 hwaddr high_mmio_base,
466 hwaddr high_mmio_size,
467 hwaddr pio_base,
468 DeviceState *plic)
469 {
470 DeviceState *dev;
471 MemoryRegion *ecam_alias, *ecam_reg;
472 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg;
473 qemu_irq irq;
474 int i;
475
476 dev = qdev_new(TYPE_GPEX_HOST);
477
478 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
479
480 ecam_alias = g_new0(MemoryRegion, 1);
481 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
482 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
483 ecam_reg, 0, ecam_size);
484 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias);
485
486 mmio_alias = g_new0(MemoryRegion, 1);
487 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
488 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
489 mmio_reg, mmio_base, mmio_size);
490 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);
491
492 /* Map high MMIO space */
493 high_mmio_alias = g_new0(MemoryRegion, 1);
494 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
495 mmio_reg, high_mmio_base, high_mmio_size);
496 memory_region_add_subregion(get_system_memory(), high_mmio_base,
497 high_mmio_alias);
498
499 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
500
501 for (i = 0; i < GPEX_NUM_IRQS; i++) {
502 irq = qdev_get_gpio_in(plic, PCIE_IRQ + i);
503
504 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
505 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
506 }
507
508 return dev;
509 }
510
511 static FWCfgState *create_fw_cfg(const MachineState *mc)
512 {
513 hwaddr base = virt_memmap[VIRT_FW_CFG].base;
514 hwaddr size = virt_memmap[VIRT_FW_CFG].size;
515 FWCfgState *fw_cfg;
516 char *nodename;
517
518 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
519 &address_space_memory);
520 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
521
522 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
523 qemu_fdt_add_subnode(mc->fdt, nodename);
524 qemu_fdt_setprop_string(mc->fdt, nodename,
525 "compatible", "qemu,fw-cfg-mmio");
526 qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
527 2, base, 2, size);
528 qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
529 g_free(nodename);
530 return fw_cfg;
531 }
532
533 static void virt_machine_init(MachineState *machine)
534 {
535 const MemMapEntry *memmap = virt_memmap;
536 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine);
537 MemoryRegion *system_memory = get_system_memory();
538 MemoryRegion *main_mem = g_new(MemoryRegion, 1);
539 MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
540 char *plic_hart_config, *soc_name;
541 size_t plic_hart_config_len;
542 target_ulong start_addr = memmap[VIRT_DRAM].base;
543 target_ulong firmware_end_addr, kernel_start_addr;
544 uint32_t fdt_load_addr;
545 uint64_t kernel_entry;
546 DeviceState *mmio_plic, *virtio_plic, *pcie_plic;
547 int i, j, base_hartid, hart_count;
548
549 /* Check socket count limit */
550 if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) {
551 error_report("number of sockets/nodes should be less than %d",
552 VIRT_SOCKETS_MAX);
553 exit(1);
554 }
555
556 /* Initialize sockets */
557 mmio_plic = virtio_plic = pcie_plic = NULL;
558 for (i = 0; i < riscv_socket_count(machine); i++) {
559 if (!riscv_socket_check_hartids(machine, i)) {
560 error_report("discontinuous hartids in socket%d", i);
561 exit(1);
562 }
563
564 base_hartid = riscv_socket_first_hartid(machine, i);
565 if (base_hartid < 0) {
566 error_report("can't find hartid base for socket%d", i);
567 exit(1);
568 }
569
570 hart_count = riscv_socket_hart_count(machine, i);
571 if (hart_count < 0) {
572 error_report("can't find hart count for socket%d", i);
573 exit(1);
574 }
575
576 soc_name = g_strdup_printf("soc%d", i);
577 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i],
578 TYPE_RISCV_HART_ARRAY);
579 g_free(soc_name);
580 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type",
581 machine->cpu_type, &error_abort);
582 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base",
583 base_hartid, &error_abort);
584 object_property_set_int(OBJECT(&s->soc[i]), "num-harts",
585 hart_count, &error_abort);
586 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort);
587
588 /* Per-socket CLINT */
589 sifive_clint_create(
590 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size,
591 memmap[VIRT_CLINT].size, base_hartid, hart_count,
592 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
593 SIFIVE_CLINT_TIMEBASE_FREQ, true);
594
595 /* Per-socket PLIC hart topology configuration string */
596 plic_hart_config_len =
597 (strlen(VIRT_PLIC_HART_CONFIG) + 1) * hart_count;
598 plic_hart_config = g_malloc0(plic_hart_config_len);
599 for (j = 0; j < hart_count; j++) {
600 if (j != 0) {
601 strncat(plic_hart_config, ",", plic_hart_config_len);
602 }
603 strncat(plic_hart_config, VIRT_PLIC_HART_CONFIG,
604 plic_hart_config_len);
605 plic_hart_config_len -= (strlen(VIRT_PLIC_HART_CONFIG) + 1);
606 }
607
608 /* Per-socket PLIC */
609 s->plic[i] = sifive_plic_create(
610 memmap[VIRT_PLIC].base + i * memmap[VIRT_PLIC].size,
611 plic_hart_config, base_hartid,
612 VIRT_PLIC_NUM_SOURCES,
613 VIRT_PLIC_NUM_PRIORITIES,
614 VIRT_PLIC_PRIORITY_BASE,
615 VIRT_PLIC_PENDING_BASE,
616 VIRT_PLIC_ENABLE_BASE,
617 VIRT_PLIC_ENABLE_STRIDE,
618 VIRT_PLIC_CONTEXT_BASE,
619 VIRT_PLIC_CONTEXT_STRIDE,
620 memmap[VIRT_PLIC].size);
621 g_free(plic_hart_config);
622
623 /* Try to use different PLIC instance based device type */
624 if (i == 0) {
625 mmio_plic = s->plic[i];
626 virtio_plic = s->plic[i];
627 pcie_plic = s->plic[i];
628 }
629 if (i == 1) {
630 virtio_plic = s->plic[i];
631 pcie_plic = s->plic[i];
632 }
633 if (i == 2) {
634 pcie_plic = s->plic[i];
635 }
636 }
637
638 if (riscv_is_32bit(&s->soc[0])) {
639 #if HOST_LONG_BITS == 64
640 /* limit RAM size in a 32-bit system */
641 if (machine->ram_size > 10 * GiB) {
642 machine->ram_size = 10 * GiB;
643 error_report("Limiting RAM size to 10 GiB");
644 }
645 #endif
646 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE;
647 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE;
648 } else {
649 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE;
650 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size;
651 virt_high_pcie_memmap.base =
652 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size);
653 }
654
655 /* register system main memory (actual RAM) */
656 memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram",
657 machine->ram_size, &error_fatal);
658 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base,
659 main_mem);
660
661 /* create device tree */
662 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline,
663 riscv_is_32bit(&s->soc[0]));
664
665 /* boot rom */
666 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom",
667 memmap[VIRT_MROM].size, &error_fatal);
668 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base,
669 mask_rom);
670
671 if (riscv_is_32bit(&s->soc[0])) {
672 firmware_end_addr = riscv_find_and_load_firmware(machine,
673 "opensbi-riscv32-generic-fw_dynamic.bin",
674 start_addr, NULL);
675 } else {
676 firmware_end_addr = riscv_find_and_load_firmware(machine,
677 "opensbi-riscv64-generic-fw_dynamic.bin",
678 start_addr, NULL);
679 }
680
681 if (machine->kernel_filename) {
682 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0],
683 firmware_end_addr);
684
685 kernel_entry = riscv_load_kernel(machine->kernel_filename,
686 kernel_start_addr, NULL);
687
688 if (machine->initrd_filename) {
689 hwaddr start;
690 hwaddr end = riscv_load_initrd(machine->initrd_filename,
691 machine->ram_size, kernel_entry,
692 &start);
693 qemu_fdt_setprop_cell(machine->fdt, "/chosen",
694 "linux,initrd-start", start);
695 qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end",
696 end);
697 }
698 } else {
699 /*
700 * If dynamic firmware is used, it doesn't know where is the next mode
701 * if kernel argument is not set.
702 */
703 kernel_entry = 0;
704 }
705
706 if (drive_get(IF_PFLASH, 0, 0)) {
707 /*
708 * Pflash was supplied, let's overwrite the address we jump to after
709 * reset to the base of the flash.
710 */
711 start_addr = virt_memmap[VIRT_FLASH].base;
712 }
713
714 /*
715 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device
716 * tree cannot be altered and we get FDT_ERR_NOSPACE.
717 */
718 s->fw_cfg = create_fw_cfg(machine);
719 rom_set_fw(s->fw_cfg);
720
721 /* Compute the fdt load address in dram */
722 fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
723 machine->ram_size, machine->fdt);
724 /* load the reset vector */
725 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr,
726 virt_memmap[VIRT_MROM].base,
727 virt_memmap[VIRT_MROM].size, kernel_entry,
728 fdt_load_addr, machine->fdt);
729
730 /* SiFive Test MMIO device */
731 sifive_test_create(memmap[VIRT_TEST].base);
732
733 /* VirtIO MMIO devices */
734 for (i = 0; i < VIRTIO_COUNT; i++) {
735 sysbus_create_simple("virtio-mmio",
736 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
737 qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i));
738 }
739
740 gpex_pcie_init(system_memory,
741 memmap[VIRT_PCIE_ECAM].base,
742 memmap[VIRT_PCIE_ECAM].size,
743 memmap[VIRT_PCIE_MMIO].base,
744 memmap[VIRT_PCIE_MMIO].size,
745 virt_high_pcie_memmap.base,
746 virt_high_pcie_memmap.size,
747 memmap[VIRT_PCIE_PIO].base,
748 DEVICE(pcie_plic));
749
750 serial_mm_init(system_memory, memmap[VIRT_UART0].base,
751 0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193,
752 serial_hd(0), DEVICE_LITTLE_ENDIAN);
753
754 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
755 qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ));
756
757 virt_flash_create(s);
758
759 for (i = 0; i < ARRAY_SIZE(s->flash); i++) {
760 /* Map legacy -drive if=pflash to machine properties */
761 pflash_cfi01_legacy_drive(s->flash[i],
762 drive_get(IF_PFLASH, 0, i));
763 }
764 virt_flash_map(s, system_memory);
765 }
766
767 static void virt_machine_instance_init(Object *obj)
768 {
769 }
770
771 static void virt_machine_class_init(ObjectClass *oc, void *data)
772 {
773 MachineClass *mc = MACHINE_CLASS(oc);
774
775 mc->desc = "RISC-V VirtIO board";
776 mc->init = virt_machine_init;
777 mc->max_cpus = VIRT_CPUS_MAX;
778 mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
779 mc->pci_allow_0_address = true;
780 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
781 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
782 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
783 mc->numa_mem_supported = true;
784
785 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
786 }
787
788 static const TypeInfo virt_machine_typeinfo = {
789 .name = MACHINE_TYPE_NAME("virt"),
790 .parent = TYPE_MACHINE,
791 .class_init = virt_machine_class_init,
792 .instance_init = virt_machine_instance_init,
793 .instance_size = sizeof(RISCVVirtState),
794 };
795
796 static void virt_machine_init_register_types(void)
797 {
798 type_register_static(&virt_machine_typeinfo);
799 }
800
801 type_init(virt_machine_init_register_types)
AR7 emulation for QEMU