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target/xtensa: convert to do_transaction_failed
[qemu/ar7.git] / hw / audio / intel-hda.c
blob23a2cf6484ce5c4bb678b3e60986e4b27f5e2b87
1 /*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Gerd Hoffmann <kraxel@redhat.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "hw/hw.h"
22 #include "hw/pci/pci.h"
23 #include "hw/pci/msi.h"
24 #include "qemu/timer.h"
25 #include "qemu/bitops.h"
26 #include "hw/audio/soundhw.h"
27 #include "intel-hda.h"
28 #include "intel-hda-defs.h"
29 #include "sysemu/dma.h"
30 #include "qapi/error.h"
31
32 /* --------------------------------------------------------------------- */
33 /* hda bus */
34
35 static Property hda_props[] = {
36 DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1),
37 DEFINE_PROP_END_OF_LIST()
38 };
39
40 static const TypeInfo hda_codec_bus_info = {
41 .name = TYPE_HDA_BUS,
42 .parent = TYPE_BUS,
43 .instance_size = sizeof(HDACodecBus),
44 };
45
46 void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus, size_t bus_size,
47 hda_codec_response_func response,
48 hda_codec_xfer_func xfer)
49 {
50 qbus_create_inplace(bus, bus_size, TYPE_HDA_BUS, dev, NULL);
51 bus->response = response;
52 bus->xfer = xfer;
53 }
54
55 static void hda_codec_dev_realize(DeviceState *qdev, Error **errp)
56 {
57 HDACodecBus *bus = HDA_BUS(qdev->parent_bus);
58 HDACodecDevice *dev = HDA_CODEC_DEVICE(qdev);
59 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
60
61 if (dev->cad == -1) {
62 dev->cad = bus->next_cad;
63 }
64 if (dev->cad >= 15) {
65 error_setg(errp, "HDA audio codec address is full");
66 return;
67 }
68 bus->next_cad = dev->cad + 1;
69 if (cdc->init(dev) != 0) {
70 error_setg(errp, "HDA audio init failed");
71 }
72 }
73
74 static void hda_codec_dev_unrealize(DeviceState *qdev, Error **errp)
75 {
76 HDACodecDevice *dev = HDA_CODEC_DEVICE(qdev);
77 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
78
79 if (cdc->exit) {
80 cdc->exit(dev);
81 }
82 }
83
84 HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad)
85 {
86 BusChild *kid;
87 HDACodecDevice *cdev;
88
89 QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
90 DeviceState *qdev = kid->child;
91 cdev = HDA_CODEC_DEVICE(qdev);
92 if (cdev->cad == cad) {
93 return cdev;
94 }
95 }
96 return NULL;
97 }
98
99 void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response)
100 {
101 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
102 bus->response(dev, solicited, response);
103 }
104
105 bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
106 uint8_t *buf, uint32_t len)
107 {
108 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
109 return bus->xfer(dev, stnr, output, buf, len);
110 }
111
112 /* --------------------------------------------------------------------- */
113 /* intel hda emulation */
114
115 typedef struct IntelHDAStream IntelHDAStream;
116 typedef struct IntelHDAState IntelHDAState;
117 typedef struct IntelHDAReg IntelHDAReg;
118
119 typedef struct bpl {
120 uint64_t addr;
121 uint32_t len;
122 uint32_t flags;
123 } bpl;
124
125 struct IntelHDAStream {
126 /* registers */
127 uint32_t ctl;
128 uint32_t lpib;
129 uint32_t cbl;
130 uint32_t lvi;
131 uint32_t fmt;
132 uint32_t bdlp_lbase;
133 uint32_t bdlp_ubase;
134
135 /* state */
136 bpl *bpl;
137 uint32_t bentries;
138 uint32_t bsize, be, bp;
139 };
140
141 struct IntelHDAState {
142 PCIDevice pci;
143 const char *name;
144 HDACodecBus codecs;
145
146 /* registers */
147 uint32_t g_ctl;
148 uint32_t wake_en;
149 uint32_t state_sts;
150 uint32_t int_ctl;
151 uint32_t int_sts;
152 uint32_t wall_clk;
153
154 uint32_t corb_lbase;
155 uint32_t corb_ubase;
156 uint32_t corb_rp;
157 uint32_t corb_wp;
158 uint32_t corb_ctl;
159 uint32_t corb_sts;
160 uint32_t corb_size;
161
162 uint32_t rirb_lbase;
163 uint32_t rirb_ubase;
164 uint32_t rirb_wp;
165 uint32_t rirb_cnt;
166 uint32_t rirb_ctl;
167 uint32_t rirb_sts;
168 uint32_t rirb_size;
169
170 uint32_t dp_lbase;
171 uint32_t dp_ubase;
172
173 uint32_t icw;
174 uint32_t irr;
175 uint32_t ics;
176
177 /* streams */
178 IntelHDAStream st[8];
179
180 /* state */
181 MemoryRegion mmio;
182 uint32_t rirb_count;
183 int64_t wall_base_ns;
184
185 /* debug logging */
186 const IntelHDAReg *last_reg;
187 uint32_t last_val;
188 uint32_t last_write;
189 uint32_t last_sec;
190 uint32_t repeat_count;
191
192 /* properties */
193 uint32_t debug;
194 OnOffAuto msi;
195 bool old_msi_addr;
196 };
197
198 #define TYPE_INTEL_HDA_GENERIC "intel-hda-generic"
199
200 #define INTEL_HDA(obj) \
201 OBJECT_CHECK(IntelHDAState, (obj), TYPE_INTEL_HDA_GENERIC)
202
203 struct IntelHDAReg {
204 const char *name; /* register name */
205 uint32_t size; /* size in bytes */
206 uint32_t reset; /* reset value */
207 uint32_t wmask; /* write mask */
208 uint32_t wclear; /* write 1 to clear bits */
209 uint32_t offset; /* location in IntelHDAState */
210 uint32_t shift; /* byte access entries for dwords */
211 uint32_t stream;
212 void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old);
213 void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg);
214 };
215
216 static void intel_hda_reset(DeviceState *dev);
217
218 /* --------------------------------------------------------------------- */
219
220 static hwaddr intel_hda_addr(uint32_t lbase, uint32_t ubase)
221 {
222 return ((uint64_t)ubase << 32) | lbase;
223 }
224
225 static void intel_hda_update_int_sts(IntelHDAState *d)
226 {
227 uint32_t sts = 0;
228 uint32_t i;
229
230 /* update controller status */
231 if (d->rirb_sts & ICH6_RBSTS_IRQ) {
232 sts |= (1 << 30);
233 }
234 if (d->rirb_sts & ICH6_RBSTS_OVERRUN) {
235 sts |= (1 << 30);
236 }
237 if (d->state_sts & d->wake_en) {
238 sts |= (1 << 30);
239 }
240
241 /* update stream status */
242 for (i = 0; i < 8; i++) {
243 /* buffer completion interrupt */
244 if (d->st[i].ctl & (1 << 26)) {
245 sts |= (1 << i);
246 }
247 }
248
249 /* update global status */
250 if (sts & d->int_ctl) {
251 sts |= (1U << 31);
252 }
253
254 d->int_sts = sts;
255 }
256
257 static void intel_hda_update_irq(IntelHDAState *d)
258 {
259 bool msi = msi_enabled(&d->pci);
260 int level;
261
262 intel_hda_update_int_sts(d);
263 if (d->int_sts & (1U << 31) && d->int_ctl & (1U << 31)) {
264 level = 1;
265 } else {
266 level = 0;
267 }
268 dprint(d, 2, "%s: level %d [%s]\n", __func__,
269 level, msi ? "msi" : "intx");
270 if (msi) {
271 if (level) {
272 msi_notify(&d->pci, 0);
273 }
274 } else {
275 pci_set_irq(&d->pci, level);
276 }
277 }
278
279 static int intel_hda_send_command(IntelHDAState *d, uint32_t verb)
280 {
281 uint32_t cad, nid, data;
282 HDACodecDevice *codec;
283 HDACodecDeviceClass *cdc;
284
285 cad = (verb >> 28) & 0x0f;
286 if (verb & (1 << 27)) {
287 /* indirect node addressing, not specified in HDA 1.0 */
288 dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __func__);
289 return -1;
290 }
291 nid = (verb >> 20) & 0x7f;
292 data = verb & 0xfffff;
293
294 codec = hda_codec_find(&d->codecs, cad);
295 if (codec == NULL) {
296 dprint(d, 1, "%s: addressed non-existing codec\n", __func__);
297 return -1;
298 }
299 cdc = HDA_CODEC_DEVICE_GET_CLASS(codec);
300 cdc->command(codec, nid, data);
301 return 0;
302 }
303
304 static void intel_hda_corb_run(IntelHDAState *d)
305 {
306 hwaddr addr;
307 uint32_t rp, verb;
308
309 if (d->ics & ICH6_IRS_BUSY) {
310 dprint(d, 2, "%s: [icw] verb 0x%08x\n", __func__, d->icw);
311 intel_hda_send_command(d, d->icw);
312 return;
313 }
314
315 for (;;) {
316 if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) {
317 dprint(d, 2, "%s: !run\n", __func__);
318 return;
319 }
320 if ((d->corb_rp & 0xff) == d->corb_wp) {
321 dprint(d, 2, "%s: corb ring empty\n", __func__);
322 return;
323 }
324 if (d->rirb_count == d->rirb_cnt) {
325 dprint(d, 2, "%s: rirb count reached\n", __func__);
326 return;
327 }
328
329 rp = (d->corb_rp + 1) & 0xff;
330 addr = intel_hda_addr(d->corb_lbase, d->corb_ubase);
331 verb = ldl_le_pci_dma(&d->pci, addr + 4*rp);
332 d->corb_rp = rp;
333
334 dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __func__, rp, verb);
335 intel_hda_send_command(d, verb);
336 }
337 }
338
339 static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response)
340 {
341 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
342 IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
343 hwaddr addr;
344 uint32_t wp, ex;
345
346 if (d->ics & ICH6_IRS_BUSY) {
347 dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n",
348 __func__, response, dev->cad);
349 d->irr = response;
350 d->ics &= ~(ICH6_IRS_BUSY | 0xf0);
351 d->ics |= (ICH6_IRS_VALID | (dev->cad << 4));
352 return;
353 }
354
355 if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) {
356 dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __func__);
357 return;
358 }
359
360 ex = (solicited ? 0 : (1 << 4)) | dev->cad;
361 wp = (d->rirb_wp + 1) & 0xff;
362 addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase);
363 stl_le_pci_dma(&d->pci, addr + 8*wp, response);
364 stl_le_pci_dma(&d->pci, addr + 8*wp + 4, ex);
365 d->rirb_wp = wp;
366
367 dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n",
368 __func__, wp, response, ex);
369
370 d->rirb_count++;
371 if (d->rirb_count == d->rirb_cnt) {
372 dprint(d, 2, "%s: rirb count reached (%d)\n", __func__, d->rirb_count);
373 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
374 d->rirb_sts |= ICH6_RBSTS_IRQ;
375 intel_hda_update_irq(d);
376 }
377 } else if ((d->corb_rp & 0xff) == d->corb_wp) {
378 dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __func__,
379 d->rirb_count, d->rirb_cnt);
380 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
381 d->rirb_sts |= ICH6_RBSTS_IRQ;
382 intel_hda_update_irq(d);
383 }
384 }
385 }
386
387 static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
388 uint8_t *buf, uint32_t len)
389 {
390 HDACodecBus *bus = HDA_BUS(dev->qdev.parent_bus);
391 IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
392 hwaddr addr;
393 uint32_t s, copy, left;
394 IntelHDAStream *st;
395 bool irq = false;
396
397 st = output ? d->st + 4 : d->st;
398 for (s = 0; s < 4; s++) {
399 if (stnr == ((st[s].ctl >> 20) & 0x0f)) {
400 st = st + s;
401 break;
402 }
403 }
404 if (s == 4) {
405 return false;
406 }
407 if (st->bpl == NULL) {
408 return false;
409 }
410
411 left = len;
412 s = st->bentries;
413 while (left > 0 && s-- > 0) {
414 copy = left;
415 if (copy > st->bsize - st->lpib)
416 copy = st->bsize - st->lpib;
417 if (copy > st->bpl[st->be].len - st->bp)
418 copy = st->bpl[st->be].len - st->bp;
419
420 dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n",
421 st->be, st->bp, st->bpl[st->be].len, copy);
422
423 pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !output);
424 st->lpib += copy;
425 st->bp += copy;
426 buf += copy;
427 left -= copy;
428
429 if (st->bpl[st->be].len == st->bp) {
430 /* bpl entry filled */
431 if (st->bpl[st->be].flags & 0x01) {
432 irq = true;
433 }
434 st->bp = 0;
435 st->be++;
436 if (st->be == st->bentries) {
437 /* bpl wrap around */
438 st->be = 0;
439 st->lpib = 0;
440 }
441 }
442 }
443 if (d->dp_lbase & 0x01) {
444 s = st - d->st;
445 addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase);
446 stl_le_pci_dma(&d->pci, addr + 8*s, st->lpib);
447 }
448 dprint(d, 3, "dma: --\n");
449
450 if (irq) {
451 st->ctl |= (1 << 26); /* buffer completion interrupt */
452 intel_hda_update_irq(d);
453 }
454 return true;
455 }
456
457 static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st)
458 {
459 hwaddr addr;
460 uint8_t buf[16];
461 uint32_t i;
462
463 addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase);
464 st->bentries = st->lvi +1;
465 g_free(st->bpl);
466 st->bpl = g_malloc(sizeof(bpl) * st->bentries);
467 for (i = 0; i < st->bentries; i++, addr += 16) {
468 pci_dma_read(&d->pci, addr, buf, 16);
469 st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf);
470 st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8));
471 st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12));
472 dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n",
473 i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags);
474 }
475
476 st->bsize = st->cbl;
477 st->lpib = 0;
478 st->be = 0;
479 st->bp = 0;
480 }
481
482 static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running, bool output)
483 {
484 BusChild *kid;
485 HDACodecDevice *cdev;
486
487 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
488 DeviceState *qdev = kid->child;
489 HDACodecDeviceClass *cdc;
490
491 cdev = HDA_CODEC_DEVICE(qdev);
492 cdc = HDA_CODEC_DEVICE_GET_CLASS(cdev);
493 if (cdc->stream) {
494 cdc->stream(cdev, stream, running, output);
495 }
496 }
497 }
498
499 /* --------------------------------------------------------------------- */
500
501 static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
502 {
503 if ((d->g_ctl & ICH6_GCTL_RESET) == 0) {
504 intel_hda_reset(DEVICE(d));
505 }
506 }
507
508 static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
509 {
510 intel_hda_update_irq(d);
511 }
512
513 static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
514 {
515 intel_hda_update_irq(d);
516 }
517
518 static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
519 {
520 intel_hda_update_irq(d);
521 }
522
523 static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg)
524 {
525 int64_t ns;
526
527 ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - d->wall_base_ns;
528 d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */
529 }
530
531 static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
532 {
533 intel_hda_corb_run(d);
534 }
535
536 static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
537 {
538 intel_hda_corb_run(d);
539 }
540
541 static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
542 {
543 if (d->rirb_wp & ICH6_RIRBWP_RST) {
544 d->rirb_wp = 0;
545 }
546 }
547
548 static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
549 {
550 intel_hda_update_irq(d);
551
552 if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) {
553 /* cleared ICH6_RBSTS_IRQ */
554 d->rirb_count = 0;
555 intel_hda_corb_run(d);
556 }
557 }
558
559 static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
560 {
561 if (d->ics & ICH6_IRS_BUSY) {
562 intel_hda_corb_run(d);
563 }
564 }
565
566 static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
567 {
568 bool output = reg->stream >= 4;
569 IntelHDAStream *st = d->st + reg->stream;
570
571 if (st->ctl & 0x01) {
572 /* reset */
573 dprint(d, 1, "st #%d: reset\n", reg->stream);
574 st->ctl = SD_STS_FIFO_READY << 24;
575 }
576 if ((st->ctl & 0x02) != (old & 0x02)) {
577 uint32_t stnr = (st->ctl >> 20) & 0x0f;
578 /* run bit flipped */
579 if (st->ctl & 0x02) {
580 /* start */
581 dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n",
582 reg->stream, stnr, st->cbl);
583 intel_hda_parse_bdl(d, st);
584 intel_hda_notify_codecs(d, stnr, true, output);
585 } else {
586 /* stop */
587 dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr);
588 intel_hda_notify_codecs(d, stnr, false, output);
589 }
590 }
591 intel_hda_update_irq(d);
592 }
593
594 /* --------------------------------------------------------------------- */
595
596 #define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o))
597
598 static const struct IntelHDAReg regtab[] = {
599 /* global */
600 [ ICH6_REG_GCAP ] = {
601 .name = "GCAP",
602 .size = 2,
603 .reset = 0x4401,
604 },
605 [ ICH6_REG_VMIN ] = {
606 .name = "VMIN",
607 .size = 1,
608 },
609 [ ICH6_REG_VMAJ ] = {
610 .name = "VMAJ",
611 .size = 1,
612 .reset = 1,
613 },
614 [ ICH6_REG_OUTPAY ] = {
615 .name = "OUTPAY",
616 .size = 2,
617 .reset = 0x3c,
618 },
619 [ ICH6_REG_INPAY ] = {
620 .name = "INPAY",
621 .size = 2,
622 .reset = 0x1d,
623 },
624 [ ICH6_REG_GCTL ] = {
625 .name = "GCTL",
626 .size = 4,
627 .wmask = 0x0103,
628 .offset = offsetof(IntelHDAState, g_ctl),
629 .whandler = intel_hda_set_g_ctl,
630 },
631 [ ICH6_REG_WAKEEN ] = {
632 .name = "WAKEEN",
633 .size = 2,
634 .wmask = 0x7fff,
635 .offset = offsetof(IntelHDAState, wake_en),
636 .whandler = intel_hda_set_wake_en,
637 },
638 [ ICH6_REG_STATESTS ] = {
639 .name = "STATESTS",
640 .size = 2,
641 .wmask = 0x7fff,
642 .wclear = 0x7fff,
643 .offset = offsetof(IntelHDAState, state_sts),
644 .whandler = intel_hda_set_state_sts,
645 },
646
647 /* interrupts */
648 [ ICH6_REG_INTCTL ] = {
649 .name = "INTCTL",
650 .size = 4,
651 .wmask = 0xc00000ff,
652 .offset = offsetof(IntelHDAState, int_ctl),
653 .whandler = intel_hda_set_int_ctl,
654 },
655 [ ICH6_REG_INTSTS ] = {
656 .name = "INTSTS",
657 .size = 4,
658 .wmask = 0xc00000ff,
659 .wclear = 0xc00000ff,
660 .offset = offsetof(IntelHDAState, int_sts),
661 },
662
663 /* misc */
664 [ ICH6_REG_WALLCLK ] = {
665 .name = "WALLCLK",
666 .size = 4,
667 .offset = offsetof(IntelHDAState, wall_clk),
668 .rhandler = intel_hda_get_wall_clk,
669 },
670 [ ICH6_REG_WALLCLK + 0x2000 ] = {
671 .name = "WALLCLK(alias)",
672 .size = 4,
673 .offset = offsetof(IntelHDAState, wall_clk),
674 .rhandler = intel_hda_get_wall_clk,
675 },
676
677 /* dma engine */
678 [ ICH6_REG_CORBLBASE ] = {
679 .name = "CORBLBASE",
680 .size = 4,
681 .wmask = 0xffffff80,
682 .offset = offsetof(IntelHDAState, corb_lbase),
683 },
684 [ ICH6_REG_CORBUBASE ] = {
685 .name = "CORBUBASE",
686 .size = 4,
687 .wmask = 0xffffffff,
688 .offset = offsetof(IntelHDAState, corb_ubase),
689 },
690 [ ICH6_REG_CORBWP ] = {
691 .name = "CORBWP",
692 .size = 2,
693 .wmask = 0xff,
694 .offset = offsetof(IntelHDAState, corb_wp),
695 .whandler = intel_hda_set_corb_wp,
696 },
697 [ ICH6_REG_CORBRP ] = {
698 .name = "CORBRP",
699 .size = 2,
700 .wmask = 0x80ff,
701 .offset = offsetof(IntelHDAState, corb_rp),
702 },
703 [ ICH6_REG_CORBCTL ] = {
704 .name = "CORBCTL",
705 .size = 1,
706 .wmask = 0x03,
707 .offset = offsetof(IntelHDAState, corb_ctl),
708 .whandler = intel_hda_set_corb_ctl,
709 },
710 [ ICH6_REG_CORBSTS ] = {
711 .name = "CORBSTS",
712 .size = 1,
713 .wmask = 0x01,
714 .wclear = 0x01,
715 .offset = offsetof(IntelHDAState, corb_sts),
716 },
717 [ ICH6_REG_CORBSIZE ] = {
718 .name = "CORBSIZE",
719 .size = 1,
720 .reset = 0x42,
721 .offset = offsetof(IntelHDAState, corb_size),
722 },
723 [ ICH6_REG_RIRBLBASE ] = {
724 .name = "RIRBLBASE",
725 .size = 4,
726 .wmask = 0xffffff80,
727 .offset = offsetof(IntelHDAState, rirb_lbase),
728 },
729 [ ICH6_REG_RIRBUBASE ] = {
730 .name = "RIRBUBASE",
731 .size = 4,
732 .wmask = 0xffffffff,
733 .offset = offsetof(IntelHDAState, rirb_ubase),
734 },
735 [ ICH6_REG_RIRBWP ] = {
736 .name = "RIRBWP",
737 .size = 2,
738 .wmask = 0x8000,
739 .offset = offsetof(IntelHDAState, rirb_wp),
740 .whandler = intel_hda_set_rirb_wp,
741 },
742 [ ICH6_REG_RINTCNT ] = {
743 .name = "RINTCNT",
744 .size = 2,
745 .wmask = 0xff,
746 .offset = offsetof(IntelHDAState, rirb_cnt),
747 },
748 [ ICH6_REG_RIRBCTL ] = {
749 .name = "RIRBCTL",
750 .size = 1,
751 .wmask = 0x07,
752 .offset = offsetof(IntelHDAState, rirb_ctl),
753 },
754 [ ICH6_REG_RIRBSTS ] = {
755 .name = "RIRBSTS",
756 .size = 1,
757 .wmask = 0x05,
758 .wclear = 0x05,
759 .offset = offsetof(IntelHDAState, rirb_sts),
760 .whandler = intel_hda_set_rirb_sts,
761 },
762 [ ICH6_REG_RIRBSIZE ] = {
763 .name = "RIRBSIZE",
764 .size = 1,
765 .reset = 0x42,
766 .offset = offsetof(IntelHDAState, rirb_size),
767 },
768
769 [ ICH6_REG_DPLBASE ] = {
770 .name = "DPLBASE",
771 .size = 4,
772 .wmask = 0xffffff81,
773 .offset = offsetof(IntelHDAState, dp_lbase),
774 },
775 [ ICH6_REG_DPUBASE ] = {
776 .name = "DPUBASE",
777 .size = 4,
778 .wmask = 0xffffffff,
779 .offset = offsetof(IntelHDAState, dp_ubase),
780 },
781
782 [ ICH6_REG_IC ] = {
783 .name = "ICW",
784 .size = 4,
785 .wmask = 0xffffffff,
786 .offset = offsetof(IntelHDAState, icw),
787 },
788 [ ICH6_REG_IR ] = {
789 .name = "IRR",
790 .size = 4,
791 .offset = offsetof(IntelHDAState, irr),
792 },
793 [ ICH6_REG_IRS ] = {
794 .name = "ICS",
795 .size = 2,
796 .wmask = 0x0003,
797 .wclear = 0x0002,
798 .offset = offsetof(IntelHDAState, ics),
799 .whandler = intel_hda_set_ics,
800 },
801
802 #define HDA_STREAM(_t, _i) \
803 [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \
804 .stream = _i, \
805 .name = _t stringify(_i) " CTL", \
806 .size = 4, \
807 .wmask = 0x1cff001f, \
808 .offset = offsetof(IntelHDAState, st[_i].ctl), \
809 .whandler = intel_hda_set_st_ctl, \
810 }, \
811 [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \
812 .stream = _i, \
813 .name = _t stringify(_i) " CTL(stnr)", \
814 .size = 1, \
815 .shift = 16, \
816 .wmask = 0x00ff0000, \
817 .offset = offsetof(IntelHDAState, st[_i].ctl), \
818 .whandler = intel_hda_set_st_ctl, \
819 }, \
820 [ ST_REG(_i, ICH6_REG_SD_STS)] = { \
821 .stream = _i, \
822 .name = _t stringify(_i) " CTL(sts)", \
823 .size = 1, \
824 .shift = 24, \
825 .wmask = 0x1c000000, \
826 .wclear = 0x1c000000, \
827 .offset = offsetof(IntelHDAState, st[_i].ctl), \
828 .whandler = intel_hda_set_st_ctl, \
829 .reset = SD_STS_FIFO_READY << 24 \
830 }, \
831 [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \
832 .stream = _i, \
833 .name = _t stringify(_i) " LPIB", \
834 .size = 4, \
835 .offset = offsetof(IntelHDAState, st[_i].lpib), \
836 }, \
837 [ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = { \
838 .stream = _i, \
839 .name = _t stringify(_i) " LPIB(alias)", \
840 .size = 4, \
841 .offset = offsetof(IntelHDAState, st[_i].lpib), \
842 }, \
843 [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \
844 .stream = _i, \
845 .name = _t stringify(_i) " CBL", \
846 .size = 4, \
847 .wmask = 0xffffffff, \
848 .offset = offsetof(IntelHDAState, st[_i].cbl), \
849 }, \
850 [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \
851 .stream = _i, \
852 .name = _t stringify(_i) " LVI", \
853 .size = 2, \
854 .wmask = 0x00ff, \
855 .offset = offsetof(IntelHDAState, st[_i].lvi), \
856 }, \
857 [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \
858 .stream = _i, \
859 .name = _t stringify(_i) " FIFOS", \
860 .size = 2, \
861 .reset = HDA_BUFFER_SIZE, \
862 }, \
863 [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \
864 .stream = _i, \
865 .name = _t stringify(_i) " FMT", \
866 .size = 2, \
867 .wmask = 0x7f7f, \
868 .offset = offsetof(IntelHDAState, st[_i].fmt), \
869 }, \
870 [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \
871 .stream = _i, \
872 .name = _t stringify(_i) " BDLPL", \
873 .size = 4, \
874 .wmask = 0xffffff80, \
875 .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \
876 }, \
877 [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \
878 .stream = _i, \
879 .name = _t stringify(_i) " BDLPU", \
880 .size = 4, \
881 .wmask = 0xffffffff, \
882 .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \
883 }, \
884
885 HDA_STREAM("IN", 0)
886 HDA_STREAM("IN", 1)
887 HDA_STREAM("IN", 2)
888 HDA_STREAM("IN", 3)
889
890 HDA_STREAM("OUT", 4)
891 HDA_STREAM("OUT", 5)
892 HDA_STREAM("OUT", 6)
893 HDA_STREAM("OUT", 7)
894
895 };
896
897 static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, hwaddr addr)
898 {
899 const IntelHDAReg *reg;
900
901 if (addr >= ARRAY_SIZE(regtab)) {
902 goto noreg;
903 }
904 reg = regtab+addr;
905 if (reg->name == NULL) {
906 goto noreg;
907 }
908 return reg;
909
910 noreg:
911 dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr);
912 return NULL;
913 }
914
915 static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg)
916 {
917 uint8_t *addr = (void*)d;
918
919 addr += reg->offset;
920 return (uint32_t*)addr;
921 }
922
923 static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val,
924 uint32_t wmask)
925 {
926 uint32_t *addr;
927 uint32_t old;
928
929 if (!reg) {
930 return;
931 }
932
933 if (d->debug) {
934 time_t now = time(NULL);
935 if (d->last_write && d->last_reg == reg && d->last_val == val) {
936 d->repeat_count++;
937 if (d->last_sec != now) {
938 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
939 d->last_sec = now;
940 d->repeat_count = 0;
941 }
942 } else {
943 if (d->repeat_count) {
944 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
945 }
946 dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask);
947 d->last_write = 1;
948 d->last_reg = reg;
949 d->last_val = val;
950 d->last_sec = now;
951 d->repeat_count = 0;
952 }
953 }
954 assert(reg->offset != 0);
955
956 addr = intel_hda_reg_addr(d, reg);
957 old = *addr;
958
959 if (reg->shift) {
960 val <<= reg->shift;
961 wmask <<= reg->shift;
962 }
963 wmask &= reg->wmask;
964 *addr &= ~wmask;
965 *addr |= wmask & val;
966 *addr &= ~(val & reg->wclear);
967
968 if (reg->whandler) {
969 reg->whandler(d, reg, old);
970 }
971 }
972
973 static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg,
974 uint32_t rmask)
975 {
976 uint32_t *addr, ret;
977
978 if (!reg) {
979 return 0;
980 }
981
982 if (reg->rhandler) {
983 reg->rhandler(d, reg);
984 }
985
986 if (reg->offset == 0) {
987 /* constant read-only register */
988 ret = reg->reset;
989 } else {
990 addr = intel_hda_reg_addr(d, reg);
991 ret = *addr;
992 if (reg->shift) {
993 ret >>= reg->shift;
994 }
995 ret &= rmask;
996 }
997 if (d->debug) {
998 time_t now = time(NULL);
999 if (!d->last_write && d->last_reg == reg && d->last_val == ret) {
1000 d->repeat_count++;
1001 if (d->last_sec != now) {
1002 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1003 d->last_sec = now;
1004 d->repeat_count = 0;
1005 }
1006 } else {
1007 if (d->repeat_count) {
1008 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1009 }
1010 dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask);
1011 d->last_write = 0;
1012 d->last_reg = reg;
1013 d->last_val = ret;
1014 d->last_sec = now;
1015 d->repeat_count = 0;
1016 }
1017 }
1018 return ret;
1019 }
1020
1021 static void intel_hda_regs_reset(IntelHDAState *d)
1022 {
1023 uint32_t *addr;
1024 int i;
1025
1026 for (i = 0; i < ARRAY_SIZE(regtab); i++) {
1027 if (regtab[i].name == NULL) {
1028 continue;
1029 }
1030 if (regtab[i].offset == 0) {
1031 continue;
1032 }
1033 addr = intel_hda_reg_addr(d, regtab + i);
1034 *addr = regtab[i].reset;
1035 }
1036 }
1037
1038 /* --------------------------------------------------------------------- */
1039
1040 static void intel_hda_mmio_write(void *opaque, hwaddr addr, uint64_t val,
1041 unsigned size)
1042 {
1043 IntelHDAState *d = opaque;
1044 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1045
1046 intel_hda_reg_write(d, reg, val, MAKE_64BIT_MASK(0, size * 8));
1047 }
1048
1049 static uint64_t intel_hda_mmio_read(void *opaque, hwaddr addr, unsigned size)
1050 {
1051 IntelHDAState *d = opaque;
1052 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1053
1054 return intel_hda_reg_read(d, reg, MAKE_64BIT_MASK(0, size * 8));
1055 }
1056
1057 static const MemoryRegionOps intel_hda_mmio_ops = {
1058 .read = intel_hda_mmio_read,
1059 .write = intel_hda_mmio_write,
1060 .impl = {
1061 .min_access_size = 1,
1062 .max_access_size = 4,
1063 },
1064 .endianness = DEVICE_NATIVE_ENDIAN,
1065 };
1066
1067 /* --------------------------------------------------------------------- */
1068
1069 static void intel_hda_reset(DeviceState *dev)
1070 {
1071 BusChild *kid;
1072 IntelHDAState *d = INTEL_HDA(dev);
1073 HDACodecDevice *cdev;
1074
1075 intel_hda_regs_reset(d);
1076 d->wall_base_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1077
1078 /* reset codecs */
1079 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
1080 DeviceState *qdev = kid->child;
1081 cdev = HDA_CODEC_DEVICE(qdev);
1082 device_reset(DEVICE(cdev));
1083 d->state_sts |= (1 << cdev->cad);
1084 }
1085 intel_hda_update_irq(d);
1086 }
1087
1088 static void intel_hda_realize(PCIDevice *pci, Error **errp)
1089 {
1090 IntelHDAState *d = INTEL_HDA(pci);
1091 uint8_t *conf = d->pci.config;
1092 Error *err = NULL;
1093 int ret;
1094
1095 d->name = object_get_typename(OBJECT(d));
1096
1097 pci_config_set_interrupt_pin(conf, 1);
1098
1099 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
1100 conf[0x40] = 0x01;
1101
1102 if (d->msi != ON_OFF_AUTO_OFF) {
1103 ret = msi_init(&d->pci, d->old_msi_addr ? 0x50 : 0x60,
1104 1, true, false, &err);
1105 /* Any error other than -ENOTSUP(board's MSI support is broken)
1106 * is a programming error */
1107 assert(!ret || ret == -ENOTSUP);
1108 if (ret && d->msi == ON_OFF_AUTO_ON) {
1109 /* Can't satisfy user's explicit msi=on request, fail */
1110 error_append_hint(&err, "You have to use msi=auto (default) or "
1111 "msi=off with this machine type.\n");
1112 error_propagate(errp, err);
1113 return;
1114 }
1115 assert(!err || d->msi == ON_OFF_AUTO_AUTO);
1116 /* With msi=auto, we fall back to MSI off silently */
1117 error_free(err);
1118 }
1119
1120 memory_region_init_io(&d->mmio, OBJECT(d), &intel_hda_mmio_ops, d,
1121 "intel-hda", 0x4000);
1122 pci_register_bar(&d->pci, 0, 0, &d->mmio);
1123
1124 hda_codec_bus_init(DEVICE(pci), &d->codecs, sizeof(d->codecs),
1125 intel_hda_response, intel_hda_xfer);
1126 }
1127
1128 static void intel_hda_exit(PCIDevice *pci)
1129 {
1130 IntelHDAState *d = INTEL_HDA(pci);
1131
1132 msi_uninit(&d->pci);
1133 }
1134
1135 static int intel_hda_post_load(void *opaque, int version)
1136 {
1137 IntelHDAState* d = opaque;
1138 int i;
1139
1140 dprint(d, 1, "%s\n", __func__);
1141 for (i = 0; i < ARRAY_SIZE(d->st); i++) {
1142 if (d->st[i].ctl & 0x02) {
1143 intel_hda_parse_bdl(d, &d->st[i]);
1144 }
1145 }
1146 intel_hda_update_irq(d);
1147 return 0;
1148 }
1149
1150 static const VMStateDescription vmstate_intel_hda_stream = {
1151 .name = "intel-hda-stream",
1152 .version_id = 1,
1153 .fields = (VMStateField[]) {
1154 VMSTATE_UINT32(ctl, IntelHDAStream),
1155 VMSTATE_UINT32(lpib, IntelHDAStream),
1156 VMSTATE_UINT32(cbl, IntelHDAStream),
1157 VMSTATE_UINT32(lvi, IntelHDAStream),
1158 VMSTATE_UINT32(fmt, IntelHDAStream),
1159 VMSTATE_UINT32(bdlp_lbase, IntelHDAStream),
1160 VMSTATE_UINT32(bdlp_ubase, IntelHDAStream),
1161 VMSTATE_END_OF_LIST()
1162 }
1163 };
1164
1165 static const VMStateDescription vmstate_intel_hda = {
1166 .name = "intel-hda",
1167 .version_id = 1,
1168 .post_load = intel_hda_post_load,
1169 .fields = (VMStateField[]) {
1170 VMSTATE_PCI_DEVICE(pci, IntelHDAState),
1171
1172 /* registers */
1173 VMSTATE_UINT32(g_ctl, IntelHDAState),
1174 VMSTATE_UINT32(wake_en, IntelHDAState),
1175 VMSTATE_UINT32(state_sts, IntelHDAState),
1176 VMSTATE_UINT32(int_ctl, IntelHDAState),
1177 VMSTATE_UINT32(int_sts, IntelHDAState),
1178 VMSTATE_UINT32(wall_clk, IntelHDAState),
1179 VMSTATE_UINT32(corb_lbase, IntelHDAState),
1180 VMSTATE_UINT32(corb_ubase, IntelHDAState),
1181 VMSTATE_UINT32(corb_rp, IntelHDAState),
1182 VMSTATE_UINT32(corb_wp, IntelHDAState),
1183 VMSTATE_UINT32(corb_ctl, IntelHDAState),
1184 VMSTATE_UINT32(corb_sts, IntelHDAState),
1185 VMSTATE_UINT32(corb_size, IntelHDAState),
1186 VMSTATE_UINT32(rirb_lbase, IntelHDAState),
1187 VMSTATE_UINT32(rirb_ubase, IntelHDAState),
1188 VMSTATE_UINT32(rirb_wp, IntelHDAState),
1189 VMSTATE_UINT32(rirb_cnt, IntelHDAState),
1190 VMSTATE_UINT32(rirb_ctl, IntelHDAState),
1191 VMSTATE_UINT32(rirb_sts, IntelHDAState),
1192 VMSTATE_UINT32(rirb_size, IntelHDAState),
1193 VMSTATE_UINT32(dp_lbase, IntelHDAState),
1194 VMSTATE_UINT32(dp_ubase, IntelHDAState),
1195 VMSTATE_UINT32(icw, IntelHDAState),
1196 VMSTATE_UINT32(irr, IntelHDAState),
1197 VMSTATE_UINT32(ics, IntelHDAState),
1198 VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0,
1199 vmstate_intel_hda_stream,
1200 IntelHDAStream),
1201
1202 /* additional state info */
1203 VMSTATE_UINT32(rirb_count, IntelHDAState),
1204 VMSTATE_INT64(wall_base_ns, IntelHDAState),
1205
1206 VMSTATE_END_OF_LIST()
1207 }
1208 };
1209
1210 static Property intel_hda_properties[] = {
1211 DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0),
1212 DEFINE_PROP_ON_OFF_AUTO("msi", IntelHDAState, msi, ON_OFF_AUTO_AUTO),
1213 DEFINE_PROP_BOOL("old_msi_addr", IntelHDAState, old_msi_addr, false),
1214 DEFINE_PROP_END_OF_LIST(),
1215 };
1216
1217 static void intel_hda_class_init(ObjectClass *klass, void *data)
1218 {
1219 DeviceClass *dc = DEVICE_CLASS(klass);
1220 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1221
1222 k->realize = intel_hda_realize;
1223 k->exit = intel_hda_exit;
1224 k->vendor_id = PCI_VENDOR_ID_INTEL;
1225 k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO;
1226 dc->reset = intel_hda_reset;
1227 dc->vmsd = &vmstate_intel_hda;
1228 dc->props = intel_hda_properties;
1229 }
1230
1231 static void intel_hda_class_init_ich6(ObjectClass *klass, void *data)
1232 {
1233 DeviceClass *dc = DEVICE_CLASS(klass);
1234 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1235
1236 k->device_id = 0x2668;
1237 k->revision = 1;
1238 set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
1239 dc->desc = "Intel HD Audio Controller (ich6)";
1240 }
1241
1242 static void intel_hda_class_init_ich9(ObjectClass *klass, void *data)
1243 {
1244 DeviceClass *dc = DEVICE_CLASS(klass);
1245 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1246
1247 k->device_id = 0x293e;
1248 k->revision = 3;
1249 set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
1250 dc->desc = "Intel HD Audio Controller (ich9)";
1251 }
1252
1253 static const TypeInfo intel_hda_info = {
1254 .name = TYPE_INTEL_HDA_GENERIC,
1255 .parent = TYPE_PCI_DEVICE,
1256 .instance_size = sizeof(IntelHDAState),
1257 .class_init = intel_hda_class_init,
1258 .abstract = true,
1259 .interfaces = (InterfaceInfo[]) {
1260 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
1261 { },
1262 },
1263 };
1264
1265 static const TypeInfo intel_hda_info_ich6 = {
1266 .name = "intel-hda",
1267 .parent = TYPE_INTEL_HDA_GENERIC,
1268 .class_init = intel_hda_class_init_ich6,
1269 };
1270
1271 static const TypeInfo intel_hda_info_ich9 = {
1272 .name = "ich9-intel-hda",
1273 .parent = TYPE_INTEL_HDA_GENERIC,
1274 .class_init = intel_hda_class_init_ich9,
1275 };
1276
1277 static void hda_codec_device_class_init(ObjectClass *klass, void *data)
1278 {
1279 DeviceClass *k = DEVICE_CLASS(klass);
1280 k->realize = hda_codec_dev_realize;
1281 k->unrealize = hda_codec_dev_unrealize;
1282 set_bit(DEVICE_CATEGORY_SOUND, k->categories);
1283 k->bus_type = TYPE_HDA_BUS;
1284 k->props = hda_props;
1285 }
1286
1287 static const TypeInfo hda_codec_device_type_info = {
1288 .name = TYPE_HDA_CODEC_DEVICE,
1289 .parent = TYPE_DEVICE,
1290 .instance_size = sizeof(HDACodecDevice),
1291 .abstract = true,
1292 .class_size = sizeof(HDACodecDeviceClass),
1293 .class_init = hda_codec_device_class_init,
1294 };
1295
1296 /*
1297 * create intel hda controller with codec attached to it,
1298 * so '-soundhw hda' works.
1299 */
1300 static int intel_hda_and_codec_init(PCIBus *bus)
1301 {
1302 DeviceState *controller;
1303 BusState *hdabus;
1304 DeviceState *codec;
1305
1306 controller = DEVICE(pci_create_simple(bus, -1, "intel-hda"));
1307 hdabus = QLIST_FIRST(&controller->child_bus);
1308 codec = qdev_create(hdabus, "hda-duplex");
1309 qdev_init_nofail(codec);
1310 return 0;
1311 }
1312
1313 static void intel_hda_register_types(void)
1314 {
1315 type_register_static(&hda_codec_bus_info);
1316 type_register_static(&intel_hda_info);
1317 type_register_static(&intel_hda_info_ich6);
1318 type_register_static(&intel_hda_info_ich9);
1319 type_register_static(&hda_codec_device_type_info);
1320 pci_register_soundhw("hda", "Intel HD Audio", intel_hda_and_codec_init);
1321 }
1322
1323 type_init(intel_hda_register_types)
AR7 emulation for QEMU