?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
target-ppc: MSR_POW not supported on POWER7/7+/8
[qemu/ar7.git] / target-ppc / translate_init.c
blobd07e186416fe20313fa80bd0c3b24e71719320a1
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "disas/bfd.h"
22 #include "exec/gdbstub.h"
23 #include <sysemu/kvm.h>
24 #include "kvm_ppc.h"
25 #include "sysemu/arch_init.h"
26 #include "sysemu/cpus.h"
27 #include "cpu-models.h"
28 #include "mmu-hash32.h"
29 #include "mmu-hash64.h"
30 #include "qemu/error-report.h"
31
32 //#define PPC_DUMP_CPU
33 //#define PPC_DEBUG_SPR
34 //#define PPC_DUMP_SPR_ACCESSES
35
36 /* For user-mode emulation, we don't emulate any IRQ controller */
37 #if defined(CONFIG_USER_ONLY)
38 #define PPC_IRQ_INIT_FN(name) \
39 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
40 { \
41 }
42 #else
43 #define PPC_IRQ_INIT_FN(name) \
44 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
45 #endif
46
47 PPC_IRQ_INIT_FN(40x);
48 PPC_IRQ_INIT_FN(6xx);
49 PPC_IRQ_INIT_FN(970);
50 PPC_IRQ_INIT_FN(POWER7);
51 PPC_IRQ_INIT_FN(e500);
52
53 /* Generic callbacks:
54 * do nothing but store/retrieve spr value
55 */
56 static void spr_load_dump_spr(int sprn)
57 {
58 #ifdef PPC_DUMP_SPR_ACCESSES
59 TCGv_i32 t0 = tcg_const_i32(sprn);
60 gen_helper_load_dump_spr(cpu_env, t0);
61 tcg_temp_free_i32(t0);
62 #endif
63 }
64
65 static void spr_read_generic (void *opaque, int gprn, int sprn)
66 {
67 gen_load_spr(cpu_gpr[gprn], sprn);
68 spr_load_dump_spr(sprn);
69 }
70
71 static void spr_store_dump_spr(int sprn)
72 {
73 #ifdef PPC_DUMP_SPR_ACCESSES
74 TCGv_i32 t0 = tcg_const_i32(sprn);
75 gen_helper_store_dump_spr(cpu_env, t0);
76 tcg_temp_free_i32(t0);
77 #endif
78 }
79
80 static void spr_write_generic (void *opaque, int sprn, int gprn)
81 {
82 gen_store_spr(sprn, cpu_gpr[gprn]);
83 spr_store_dump_spr(sprn);
84 }
85
86 #if !defined(CONFIG_USER_ONLY)
87 static void spr_write_generic32(void *opaque, int sprn, int gprn)
88 {
89 #ifdef TARGET_PPC64
90 TCGv t0 = tcg_temp_new();
91 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
92 gen_store_spr(sprn, t0);
93 tcg_temp_free(t0);
94 spr_store_dump_spr(sprn);
95 #else
96 spr_write_generic(opaque, sprn, gprn);
97 #endif
98 }
99
100 static void spr_write_clear (void *opaque, int sprn, int gprn)
101 {
102 TCGv t0 = tcg_temp_new();
103 TCGv t1 = tcg_temp_new();
104 gen_load_spr(t0, sprn);
105 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
106 tcg_gen_and_tl(t0, t0, t1);
107 gen_store_spr(sprn, t0);
108 tcg_temp_free(t0);
109 tcg_temp_free(t1);
110 }
111
112 static void spr_access_nop(void *opaque, int sprn, int gprn)
113 {
114 }
115
116 #endif
117
118 /* SPR common to all PowerPC */
119 /* XER */
120 static void spr_read_xer (void *opaque, int gprn, int sprn)
121 {
122 gen_read_xer(cpu_gpr[gprn]);
123 }
124
125 static void spr_write_xer (void *opaque, int sprn, int gprn)
126 {
127 gen_write_xer(cpu_gpr[gprn]);
128 }
129
130 /* LR */
131 static void spr_read_lr (void *opaque, int gprn, int sprn)
132 {
133 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
134 }
135
136 static void spr_write_lr (void *opaque, int sprn, int gprn)
137 {
138 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
139 }
140
141 /* CFAR */
142 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
143 static void spr_read_cfar (void *opaque, int gprn, int sprn)
144 {
145 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
146 }
147
148 static void spr_write_cfar (void *opaque, int sprn, int gprn)
149 {
150 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
151 }
152 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
153
154 /* CTR */
155 static void spr_read_ctr (void *opaque, int gprn, int sprn)
156 {
157 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
158 }
159
160 static void spr_write_ctr (void *opaque, int sprn, int gprn)
161 {
162 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
163 }
164
165 /* User read access to SPR */
166 /* USPRx */
167 /* UMMCRx */
168 /* UPMCx */
169 /* USIA */
170 /* UDECR */
171 static void spr_read_ureg (void *opaque, int gprn, int sprn)
172 {
173 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
174 }
175
176 /* SPR common to all non-embedded PowerPC */
177 /* DECR */
178 #if !defined(CONFIG_USER_ONLY)
179 static void spr_read_decr (void *opaque, int gprn, int sprn)
180 {
181 if (use_icount) {
182 gen_io_start();
183 }
184 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
185 if (use_icount) {
186 gen_io_end();
187 gen_stop_exception(opaque);
188 }
189 }
190
191 static void spr_write_decr (void *opaque, int sprn, int gprn)
192 {
193 if (use_icount) {
194 gen_io_start();
195 }
196 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
197 if (use_icount) {
198 gen_io_end();
199 gen_stop_exception(opaque);
200 }
201 }
202 #endif
203
204 /* SPR common to all non-embedded PowerPC, except 601 */
205 /* Time base */
206 static void spr_read_tbl (void *opaque, int gprn, int sprn)
207 {
208 if (use_icount) {
209 gen_io_start();
210 }
211 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
212 if (use_icount) {
213 gen_io_end();
214 gen_stop_exception(opaque);
215 }
216 }
217
218 static void spr_read_tbu (void *opaque, int gprn, int sprn)
219 {
220 if (use_icount) {
221 gen_io_start();
222 }
223 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
224 if (use_icount) {
225 gen_io_end();
226 gen_stop_exception(opaque);
227 }
228 }
229
230 __attribute__ (( unused ))
231 static void spr_read_atbl (void *opaque, int gprn, int sprn)
232 {
233 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
234 }
235
236 __attribute__ (( unused ))
237 static void spr_read_atbu (void *opaque, int gprn, int sprn)
238 {
239 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
240 }
241
242 #if !defined(CONFIG_USER_ONLY)
243 static void spr_write_tbl (void *opaque, int sprn, int gprn)
244 {
245 if (use_icount) {
246 gen_io_start();
247 }
248 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
249 if (use_icount) {
250 gen_io_end();
251 gen_stop_exception(opaque);
252 }
253 }
254
255 static void spr_write_tbu (void *opaque, int sprn, int gprn)
256 {
257 if (use_icount) {
258 gen_io_start();
259 }
260 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
261 if (use_icount) {
262 gen_io_end();
263 gen_stop_exception(opaque);
264 }
265 }
266
267 __attribute__ (( unused ))
268 static void spr_write_atbl (void *opaque, int sprn, int gprn)
269 {
270 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
271 }
272
273 __attribute__ (( unused ))
274 static void spr_write_atbu (void *opaque, int sprn, int gprn)
275 {
276 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
277 }
278
279 #if defined(TARGET_PPC64)
280 __attribute__ (( unused ))
281 static void spr_read_purr (void *opaque, int gprn, int sprn)
282 {
283 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
284 }
285 #endif
286 #endif
287
288 #if !defined(CONFIG_USER_ONLY)
289 /* IBAT0U...IBAT0U */
290 /* IBAT0L...IBAT7L */
291 static void spr_read_ibat (void *opaque, int gprn, int sprn)
292 {
293 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
294 }
295
296 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
297 {
298 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
299 }
300
301 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
302 {
303 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
304 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
305 tcg_temp_free_i32(t0);
306 }
307
308 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
309 {
310 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
311 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
312 tcg_temp_free_i32(t0);
313 }
314
315 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
316 {
317 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
318 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
319 tcg_temp_free_i32(t0);
320 }
321
322 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
323 {
324 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
325 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
326 tcg_temp_free_i32(t0);
327 }
328
329 /* DBAT0U...DBAT7U */
330 /* DBAT0L...DBAT7L */
331 static void spr_read_dbat (void *opaque, int gprn, int sprn)
332 {
333 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
334 }
335
336 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
337 {
338 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
339 }
340
341 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
342 {
343 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
344 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
345 tcg_temp_free_i32(t0);
346 }
347
348 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
349 {
350 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
351 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
352 tcg_temp_free_i32(t0);
353 }
354
355 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
356 {
357 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
358 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
359 tcg_temp_free_i32(t0);
360 }
361
362 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
363 {
364 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
365 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
366 tcg_temp_free_i32(t0);
367 }
368
369 /* SDR1 */
370 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
371 {
372 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
373 }
374
375 /* 64 bits PowerPC specific SPRs */
376 #if defined(TARGET_PPC64)
377 static void spr_read_hior (void *opaque, int gprn, int sprn)
378 {
379 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
380 }
381
382 static void spr_write_hior (void *opaque, int sprn, int gprn)
383 {
384 TCGv t0 = tcg_temp_new();
385 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
386 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
387 tcg_temp_free(t0);
388 }
389 #endif
390 #endif
391
392 /* PowerPC 601 specific registers */
393 /* RTC */
394 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
395 {
396 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
397 }
398
399 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
400 {
401 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
402 }
403
404 #if !defined(CONFIG_USER_ONLY)
405 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
406 {
407 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
408 }
409
410 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
411 {
412 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
413 }
414
415 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
416 {
417 DisasContext *ctx = opaque;
418
419 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
420 /* Must stop the translation as endianness may have changed */
421 gen_stop_exception(ctx);
422 }
423 #endif
424
425 /* Unified bats */
426 #if !defined(CONFIG_USER_ONLY)
427 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
428 {
429 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
430 }
431
432 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
433 {
434 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
435 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
436 tcg_temp_free_i32(t0);
437 }
438
439 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
440 {
441 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
442 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
443 tcg_temp_free_i32(t0);
444 }
445 #endif
446
447 /* PowerPC 40x specific registers */
448 #if !defined(CONFIG_USER_ONLY)
449 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
450 {
451 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
452 }
453
454 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
455 {
456 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
457 }
458
459 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
460 {
461 DisasContext *ctx = opaque;
462
463 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
464 /* We must stop translation as we may have rebooted */
465 gen_stop_exception(ctx);
466 }
467
468 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
469 {
470 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
471 }
472
473 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
474 {
475 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
476 }
477
478 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
479 {
480 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
481 }
482 #endif
483
484 /* PowerPC 403 specific registers */
485 /* PBL1 / PBU1 / PBL2 / PBU2 */
486 #if !defined(CONFIG_USER_ONLY)
487 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
488 {
489 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
490 }
491
492 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
493 {
494 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
495 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
496 tcg_temp_free_i32(t0);
497 }
498
499 static void spr_write_pir (void *opaque, int sprn, int gprn)
500 {
501 TCGv t0 = tcg_temp_new();
502 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
503 gen_store_spr(SPR_PIR, t0);
504 tcg_temp_free(t0);
505 }
506 #endif
507
508 /* SPE specific registers */
509 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
510 {
511 TCGv_i32 t0 = tcg_temp_new_i32();
512 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
513 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
514 tcg_temp_free_i32(t0);
515 }
516
517 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
518 {
519 TCGv_i32 t0 = tcg_temp_new_i32();
520 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
521 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
522 tcg_temp_free_i32(t0);
523 }
524
525 #if !defined(CONFIG_USER_ONLY)
526 /* Callback used to write the exception vector base */
527 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
528 {
529 TCGv t0 = tcg_temp_new();
530 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
531 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
532 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
533 gen_store_spr(sprn, t0);
534 tcg_temp_free(t0);
535 }
536
537 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
538 {
539 DisasContext *ctx = opaque;
540 int sprn_offs;
541
542 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
543 sprn_offs = sprn - SPR_BOOKE_IVOR0;
544 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
545 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
546 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
547 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
548 } else {
549 printf("Trying to write an unknown exception vector %d %03x\n",
550 sprn, sprn);
551 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
552 return;
553 }
554
555 TCGv t0 = tcg_temp_new();
556 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
557 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
558 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
559 gen_store_spr(sprn, t0);
560 tcg_temp_free(t0);
561 }
562 #endif
563
564 static inline void vscr_init (CPUPPCState *env, uint32_t val)
565 {
566 env->vscr = val;
567 /* Altivec always uses round-to-nearest */
568 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
569 set_flush_to_zero(vscr_nj, &env->vec_status);
570 }
571
572 #ifdef CONFIG_USER_ONLY
573 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
574 oea_read, oea_write, one_reg_id, initial_value) \
575 _spr_register(env, num, name, uea_read, uea_write, initial_value)
576 #else
577 #if !defined(CONFIG_KVM)
578 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
579 oea_read, oea_write, one_reg_id, initial_value) \
580 _spr_register(env, num, name, uea_read, uea_write, \
581 oea_read, oea_write, initial_value)
582 #else
583 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
584 oea_read, oea_write, one_reg_id, initial_value) \
585 _spr_register(env, num, name, uea_read, uea_write, \
586 oea_read, oea_write, one_reg_id, initial_value)
587 #endif
588 #endif
589
590 #define spr_register(env, num, name, uea_read, uea_write, \
591 oea_read, oea_write, initial_value) \
592 spr_register_kvm(env, num, name, uea_read, uea_write, \
593 oea_read, oea_write, 0, initial_value)
594
595 static inline void _spr_register(CPUPPCState *env, int num,
596 const char *name,
597 void (*uea_read)(void *opaque, int gprn, int sprn),
598 void (*uea_write)(void *opaque, int sprn, int gprn),
599 #if !defined(CONFIG_USER_ONLY)
600
601 void (*oea_read)(void *opaque, int gprn, int sprn),
602 void (*oea_write)(void *opaque, int sprn, int gprn),
603 #endif
604 #if defined(CONFIG_KVM)
605 uint64_t one_reg_id,
606 #endif
607 target_ulong initial_value)
608 {
609 ppc_spr_t *spr;
610
611 spr = &env->spr_cb[num];
612 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
613 #if !defined(CONFIG_USER_ONLY)
614 spr->oea_read != NULL || spr->oea_write != NULL ||
615 #endif
616 spr->uea_read != NULL || spr->uea_write != NULL) {
617 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
618 exit(1);
619 }
620 #if defined(PPC_DEBUG_SPR)
621 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
622 name, initial_value);
623 #endif
624 spr->name = name;
625 spr->uea_read = uea_read;
626 spr->uea_write = uea_write;
627 #if !defined(CONFIG_USER_ONLY)
628 spr->oea_read = oea_read;
629 spr->oea_write = oea_write;
630 #endif
631 #if defined(CONFIG_KVM)
632 spr->one_reg_id = one_reg_id,
633 #endif
634 env->spr[num] = spr->default_value = initial_value;
635 }
636
637 /* Generic PowerPC SPRs */
638 static void gen_spr_generic (CPUPPCState *env)
639 {
640 /* Integer processing */
641 spr_register(env, SPR_XER, "XER",
642 &spr_read_xer, &spr_write_xer,
643 &spr_read_xer, &spr_write_xer,
644 0x00000000);
645 /* Branch contol */
646 spr_register(env, SPR_LR, "LR",
647 &spr_read_lr, &spr_write_lr,
648 &spr_read_lr, &spr_write_lr,
649 0x00000000);
650 spr_register(env, SPR_CTR, "CTR",
651 &spr_read_ctr, &spr_write_ctr,
652 &spr_read_ctr, &spr_write_ctr,
653 0x00000000);
654 /* Interrupt processing */
655 spr_register(env, SPR_SRR0, "SRR0",
656 SPR_NOACCESS, SPR_NOACCESS,
657 &spr_read_generic, &spr_write_generic,
658 0x00000000);
659 spr_register(env, SPR_SRR1, "SRR1",
660 SPR_NOACCESS, SPR_NOACCESS,
661 &spr_read_generic, &spr_write_generic,
662 0x00000000);
663 /* Processor control */
664 spr_register(env, SPR_SPRG0, "SPRG0",
665 SPR_NOACCESS, SPR_NOACCESS,
666 &spr_read_generic, &spr_write_generic,
667 0x00000000);
668 spr_register(env, SPR_SPRG1, "SPRG1",
669 SPR_NOACCESS, SPR_NOACCESS,
670 &spr_read_generic, &spr_write_generic,
671 0x00000000);
672 spr_register(env, SPR_SPRG2, "SPRG2",
673 SPR_NOACCESS, SPR_NOACCESS,
674 &spr_read_generic, &spr_write_generic,
675 0x00000000);
676 spr_register(env, SPR_SPRG3, "SPRG3",
677 SPR_NOACCESS, SPR_NOACCESS,
678 &spr_read_generic, &spr_write_generic,
679 0x00000000);
680 }
681
682 /* SPR common to all non-embedded PowerPC, including 601 */
683 static void gen_spr_ne_601 (CPUPPCState *env)
684 {
685 /* Exception processing */
686 spr_register_kvm(env, SPR_DSISR, "DSISR",
687 SPR_NOACCESS, SPR_NOACCESS,
688 &spr_read_generic, &spr_write_generic,
689 KVM_REG_PPC_DSISR, 0x00000000);
690 spr_register_kvm(env, SPR_DAR, "DAR",
691 SPR_NOACCESS, SPR_NOACCESS,
692 &spr_read_generic, &spr_write_generic,
693 KVM_REG_PPC_DAR, 0x00000000);
694 /* Timer */
695 spr_register(env, SPR_DECR, "DECR",
696 SPR_NOACCESS, SPR_NOACCESS,
697 &spr_read_decr, &spr_write_decr,
698 0x00000000);
699 /* Memory management */
700 spr_register(env, SPR_SDR1, "SDR1",
701 SPR_NOACCESS, SPR_NOACCESS,
702 &spr_read_generic, &spr_write_sdr1,
703 0x00000000);
704 }
705
706 /* BATs 0-3 */
707 static void gen_low_BATs (CPUPPCState *env)
708 {
709 #if !defined(CONFIG_USER_ONLY)
710 spr_register(env, SPR_IBAT0U, "IBAT0U",
711 SPR_NOACCESS, SPR_NOACCESS,
712 &spr_read_ibat, &spr_write_ibatu,
713 0x00000000);
714 spr_register(env, SPR_IBAT0L, "IBAT0L",
715 SPR_NOACCESS, SPR_NOACCESS,
716 &spr_read_ibat, &spr_write_ibatl,
717 0x00000000);
718 spr_register(env, SPR_IBAT1U, "IBAT1U",
719 SPR_NOACCESS, SPR_NOACCESS,
720 &spr_read_ibat, &spr_write_ibatu,
721 0x00000000);
722 spr_register(env, SPR_IBAT1L, "IBAT1L",
723 SPR_NOACCESS, SPR_NOACCESS,
724 &spr_read_ibat, &spr_write_ibatl,
725 0x00000000);
726 spr_register(env, SPR_IBAT2U, "IBAT2U",
727 SPR_NOACCESS, SPR_NOACCESS,
728 &spr_read_ibat, &spr_write_ibatu,
729 0x00000000);
730 spr_register(env, SPR_IBAT2L, "IBAT2L",
731 SPR_NOACCESS, SPR_NOACCESS,
732 &spr_read_ibat, &spr_write_ibatl,
733 0x00000000);
734 spr_register(env, SPR_IBAT3U, "IBAT3U",
735 SPR_NOACCESS, SPR_NOACCESS,
736 &spr_read_ibat, &spr_write_ibatu,
737 0x00000000);
738 spr_register(env, SPR_IBAT3L, "IBAT3L",
739 SPR_NOACCESS, SPR_NOACCESS,
740 &spr_read_ibat, &spr_write_ibatl,
741 0x00000000);
742 spr_register(env, SPR_DBAT0U, "DBAT0U",
743 SPR_NOACCESS, SPR_NOACCESS,
744 &spr_read_dbat, &spr_write_dbatu,
745 0x00000000);
746 spr_register(env, SPR_DBAT0L, "DBAT0L",
747 SPR_NOACCESS, SPR_NOACCESS,
748 &spr_read_dbat, &spr_write_dbatl,
749 0x00000000);
750 spr_register(env, SPR_DBAT1U, "DBAT1U",
751 SPR_NOACCESS, SPR_NOACCESS,
752 &spr_read_dbat, &spr_write_dbatu,
753 0x00000000);
754 spr_register(env, SPR_DBAT1L, "DBAT1L",
755 SPR_NOACCESS, SPR_NOACCESS,
756 &spr_read_dbat, &spr_write_dbatl,
757 0x00000000);
758 spr_register(env, SPR_DBAT2U, "DBAT2U",
759 SPR_NOACCESS, SPR_NOACCESS,
760 &spr_read_dbat, &spr_write_dbatu,
761 0x00000000);
762 spr_register(env, SPR_DBAT2L, "DBAT2L",
763 SPR_NOACCESS, SPR_NOACCESS,
764 &spr_read_dbat, &spr_write_dbatl,
765 0x00000000);
766 spr_register(env, SPR_DBAT3U, "DBAT3U",
767 SPR_NOACCESS, SPR_NOACCESS,
768 &spr_read_dbat, &spr_write_dbatu,
769 0x00000000);
770 spr_register(env, SPR_DBAT3L, "DBAT3L",
771 SPR_NOACCESS, SPR_NOACCESS,
772 &spr_read_dbat, &spr_write_dbatl,
773 0x00000000);
774 env->nb_BATs += 4;
775 #endif
776 }
777
778 /* BATs 4-7 */
779 static void gen_high_BATs (CPUPPCState *env)
780 {
781 #if !defined(CONFIG_USER_ONLY)
782 spr_register(env, SPR_IBAT4U, "IBAT4U",
783 SPR_NOACCESS, SPR_NOACCESS,
784 &spr_read_ibat_h, &spr_write_ibatu_h,
785 0x00000000);
786 spr_register(env, SPR_IBAT4L, "IBAT4L",
787 SPR_NOACCESS, SPR_NOACCESS,
788 &spr_read_ibat_h, &spr_write_ibatl_h,
789 0x00000000);
790 spr_register(env, SPR_IBAT5U, "IBAT5U",
791 SPR_NOACCESS, SPR_NOACCESS,
792 &spr_read_ibat_h, &spr_write_ibatu_h,
793 0x00000000);
794 spr_register(env, SPR_IBAT5L, "IBAT5L",
795 SPR_NOACCESS, SPR_NOACCESS,
796 &spr_read_ibat_h, &spr_write_ibatl_h,
797 0x00000000);
798 spr_register(env, SPR_IBAT6U, "IBAT6U",
799 SPR_NOACCESS, SPR_NOACCESS,
800 &spr_read_ibat_h, &spr_write_ibatu_h,
801 0x00000000);
802 spr_register(env, SPR_IBAT6L, "IBAT6L",
803 SPR_NOACCESS, SPR_NOACCESS,
804 &spr_read_ibat_h, &spr_write_ibatl_h,
805 0x00000000);
806 spr_register(env, SPR_IBAT7U, "IBAT7U",
807 SPR_NOACCESS, SPR_NOACCESS,
808 &spr_read_ibat_h, &spr_write_ibatu_h,
809 0x00000000);
810 spr_register(env, SPR_IBAT7L, "IBAT7L",
811 SPR_NOACCESS, SPR_NOACCESS,
812 &spr_read_ibat_h, &spr_write_ibatl_h,
813 0x00000000);
814 spr_register(env, SPR_DBAT4U, "DBAT4U",
815 SPR_NOACCESS, SPR_NOACCESS,
816 &spr_read_dbat_h, &spr_write_dbatu_h,
817 0x00000000);
818 spr_register(env, SPR_DBAT4L, "DBAT4L",
819 SPR_NOACCESS, SPR_NOACCESS,
820 &spr_read_dbat_h, &spr_write_dbatl_h,
821 0x00000000);
822 spr_register(env, SPR_DBAT5U, "DBAT5U",
823 SPR_NOACCESS, SPR_NOACCESS,
824 &spr_read_dbat_h, &spr_write_dbatu_h,
825 0x00000000);
826 spr_register(env, SPR_DBAT5L, "DBAT5L",
827 SPR_NOACCESS, SPR_NOACCESS,
828 &spr_read_dbat_h, &spr_write_dbatl_h,
829 0x00000000);
830 spr_register(env, SPR_DBAT6U, "DBAT6U",
831 SPR_NOACCESS, SPR_NOACCESS,
832 &spr_read_dbat_h, &spr_write_dbatu_h,
833 0x00000000);
834 spr_register(env, SPR_DBAT6L, "DBAT6L",
835 SPR_NOACCESS, SPR_NOACCESS,
836 &spr_read_dbat_h, &spr_write_dbatl_h,
837 0x00000000);
838 spr_register(env, SPR_DBAT7U, "DBAT7U",
839 SPR_NOACCESS, SPR_NOACCESS,
840 &spr_read_dbat_h, &spr_write_dbatu_h,
841 0x00000000);
842 spr_register(env, SPR_DBAT7L, "DBAT7L",
843 SPR_NOACCESS, SPR_NOACCESS,
844 &spr_read_dbat_h, &spr_write_dbatl_h,
845 0x00000000);
846 env->nb_BATs += 4;
847 #endif
848 }
849
850 /* Generic PowerPC time base */
851 static void gen_tbl (CPUPPCState *env)
852 {
853 spr_register(env, SPR_VTBL, "TBL",
854 &spr_read_tbl, SPR_NOACCESS,
855 &spr_read_tbl, SPR_NOACCESS,
856 0x00000000);
857 spr_register(env, SPR_TBL, "TBL",
858 &spr_read_tbl, SPR_NOACCESS,
859 &spr_read_tbl, &spr_write_tbl,
860 0x00000000);
861 spr_register(env, SPR_VTBU, "TBU",
862 &spr_read_tbu, SPR_NOACCESS,
863 &spr_read_tbu, SPR_NOACCESS,
864 0x00000000);
865 spr_register(env, SPR_TBU, "TBU",
866 &spr_read_tbu, SPR_NOACCESS,
867 &spr_read_tbu, &spr_write_tbu,
868 0x00000000);
869 }
870
871 /* Softare table search registers */
872 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
873 {
874 #if !defined(CONFIG_USER_ONLY)
875 env->nb_tlb = nb_tlbs;
876 env->nb_ways = nb_ways;
877 env->id_tlbs = 1;
878 env->tlb_type = TLB_6XX;
879 spr_register(env, SPR_DMISS, "DMISS",
880 SPR_NOACCESS, SPR_NOACCESS,
881 &spr_read_generic, SPR_NOACCESS,
882 0x00000000);
883 spr_register(env, SPR_DCMP, "DCMP",
884 SPR_NOACCESS, SPR_NOACCESS,
885 &spr_read_generic, SPR_NOACCESS,
886 0x00000000);
887 spr_register(env, SPR_HASH1, "HASH1",
888 SPR_NOACCESS, SPR_NOACCESS,
889 &spr_read_generic, SPR_NOACCESS,
890 0x00000000);
891 spr_register(env, SPR_HASH2, "HASH2",
892 SPR_NOACCESS, SPR_NOACCESS,
893 &spr_read_generic, SPR_NOACCESS,
894 0x00000000);
895 spr_register(env, SPR_IMISS, "IMISS",
896 SPR_NOACCESS, SPR_NOACCESS,
897 &spr_read_generic, SPR_NOACCESS,
898 0x00000000);
899 spr_register(env, SPR_ICMP, "ICMP",
900 SPR_NOACCESS, SPR_NOACCESS,
901 &spr_read_generic, SPR_NOACCESS,
902 0x00000000);
903 spr_register(env, SPR_RPA, "RPA",
904 SPR_NOACCESS, SPR_NOACCESS,
905 &spr_read_generic, &spr_write_generic,
906 0x00000000);
907 #endif
908 }
909
910 /* SPR common to MPC755 and G2 */
911 static void gen_spr_G2_755 (CPUPPCState *env)
912 {
913 /* SGPRs */
914 spr_register(env, SPR_SPRG4, "SPRG4",
915 SPR_NOACCESS, SPR_NOACCESS,
916 &spr_read_generic, &spr_write_generic,
917 0x00000000);
918 spr_register(env, SPR_SPRG5, "SPRG5",
919 SPR_NOACCESS, SPR_NOACCESS,
920 &spr_read_generic, &spr_write_generic,
921 0x00000000);
922 spr_register(env, SPR_SPRG6, "SPRG6",
923 SPR_NOACCESS, SPR_NOACCESS,
924 &spr_read_generic, &spr_write_generic,
925 0x00000000);
926 spr_register(env, SPR_SPRG7, "SPRG7",
927 SPR_NOACCESS, SPR_NOACCESS,
928 &spr_read_generic, &spr_write_generic,
929 0x00000000);
930 }
931
932 /* SPR common to all 7xx PowerPC implementations */
933 static void gen_spr_7xx (CPUPPCState *env)
934 {
935 /* Breakpoints */
936 /* XXX : not implemented */
937 spr_register_kvm(env, SPR_DABR, "DABR",
938 SPR_NOACCESS, SPR_NOACCESS,
939 &spr_read_generic, &spr_write_generic,
940 KVM_REG_PPC_DABR, 0x00000000);
941 /* XXX : not implemented */
942 spr_register(env, SPR_IABR, "IABR",
943 SPR_NOACCESS, SPR_NOACCESS,
944 &spr_read_generic, &spr_write_generic,
945 0x00000000);
946 /* Cache management */
947 /* XXX : not implemented */
948 spr_register(env, SPR_ICTC, "ICTC",
949 SPR_NOACCESS, SPR_NOACCESS,
950 &spr_read_generic, &spr_write_generic,
951 0x00000000);
952 /* Performance monitors */
953 /* XXX : not implemented */
954 spr_register(env, SPR_MMCR0, "MMCR0",
955 SPR_NOACCESS, SPR_NOACCESS,
956 &spr_read_generic, &spr_write_generic,
957 0x00000000);
958 /* XXX : not implemented */
959 spr_register(env, SPR_MMCR1, "MMCR1",
960 SPR_NOACCESS, SPR_NOACCESS,
961 &spr_read_generic, &spr_write_generic,
962 0x00000000);
963 /* XXX : not implemented */
964 spr_register(env, SPR_PMC1, "PMC1",
965 SPR_NOACCESS, SPR_NOACCESS,
966 &spr_read_generic, &spr_write_generic,
967 0x00000000);
968 /* XXX : not implemented */
969 spr_register(env, SPR_PMC2, "PMC2",
970 SPR_NOACCESS, SPR_NOACCESS,
971 &spr_read_generic, &spr_write_generic,
972 0x00000000);
973 /* XXX : not implemented */
974 spr_register(env, SPR_PMC3, "PMC3",
975 SPR_NOACCESS, SPR_NOACCESS,
976 &spr_read_generic, &spr_write_generic,
977 0x00000000);
978 /* XXX : not implemented */
979 spr_register(env, SPR_PMC4, "PMC4",
980 SPR_NOACCESS, SPR_NOACCESS,
981 &spr_read_generic, &spr_write_generic,
982 0x00000000);
983 /* XXX : not implemented */
984 spr_register(env, SPR_SIAR, "SIAR",
985 SPR_NOACCESS, SPR_NOACCESS,
986 &spr_read_generic, SPR_NOACCESS,
987 0x00000000);
988 /* XXX : not implemented */
989 spr_register(env, SPR_UMMCR0, "UMMCR0",
990 &spr_read_ureg, SPR_NOACCESS,
991 &spr_read_ureg, SPR_NOACCESS,
992 0x00000000);
993 /* XXX : not implemented */
994 spr_register(env, SPR_UMMCR1, "UMMCR1",
995 &spr_read_ureg, SPR_NOACCESS,
996 &spr_read_ureg, SPR_NOACCESS,
997 0x00000000);
998 /* XXX : not implemented */
999 spr_register(env, SPR_UPMC1, "UPMC1",
1000 &spr_read_ureg, SPR_NOACCESS,
1001 &spr_read_ureg, SPR_NOACCESS,
1002 0x00000000);
1003 /* XXX : not implemented */
1004 spr_register(env, SPR_UPMC2, "UPMC2",
1005 &spr_read_ureg, SPR_NOACCESS,
1006 &spr_read_ureg, SPR_NOACCESS,
1007 0x00000000);
1008 /* XXX : not implemented */
1009 spr_register(env, SPR_UPMC3, "UPMC3",
1010 &spr_read_ureg, SPR_NOACCESS,
1011 &spr_read_ureg, SPR_NOACCESS,
1012 0x00000000);
1013 /* XXX : not implemented */
1014 spr_register(env, SPR_UPMC4, "UPMC4",
1015 &spr_read_ureg, SPR_NOACCESS,
1016 &spr_read_ureg, SPR_NOACCESS,
1017 0x00000000);
1018 /* XXX : not implemented */
1019 spr_register(env, SPR_USIAR, "USIAR",
1020 &spr_read_ureg, SPR_NOACCESS,
1021 &spr_read_ureg, SPR_NOACCESS,
1022 0x00000000);
1023 /* External access control */
1024 /* XXX : not implemented */
1025 spr_register(env, SPR_EAR, "EAR",
1026 SPR_NOACCESS, SPR_NOACCESS,
1027 &spr_read_generic, &spr_write_generic,
1028 0x00000000);
1029 }
1030
1031 #ifdef TARGET_PPC64
1032 #ifndef CONFIG_USER_ONLY
1033 static void spr_read_uamr (void *opaque, int gprn, int sprn)
1034 {
1035 gen_load_spr(cpu_gpr[gprn], SPR_AMR);
1036 spr_load_dump_spr(SPR_AMR);
1037 }
1038
1039 static void spr_write_uamr (void *opaque, int sprn, int gprn)
1040 {
1041 gen_store_spr(SPR_AMR, cpu_gpr[gprn]);
1042 spr_store_dump_spr(SPR_AMR);
1043 }
1044
1045 static void spr_write_uamr_pr (void *opaque, int sprn, int gprn)
1046 {
1047 TCGv t0 = tcg_temp_new();
1048
1049 gen_load_spr(t0, SPR_UAMOR);
1050 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1051 gen_store_spr(SPR_AMR, t0);
1052 spr_store_dump_spr(SPR_AMR);
1053 }
1054 #endif /* CONFIG_USER_ONLY */
1055
1056 static void gen_spr_amr (CPUPPCState *env)
1057 {
1058 #ifndef CONFIG_USER_ONLY
1059 /* Virtual Page Class Key protection */
1060 /* The AMR is accessible either via SPR 13 or SPR 29. 13 is
1061 * userspace accessible, 29 is privileged. So we only need to set
1062 * the kvm ONE_REG id on one of them, we use 29 */
1063 spr_register(env, SPR_UAMR, "UAMR",
1064 &spr_read_uamr, &spr_write_uamr_pr,
1065 &spr_read_uamr, &spr_write_uamr,
1066 0);
1067 spr_register_kvm(env, SPR_AMR, "AMR",
1068 SPR_NOACCESS, SPR_NOACCESS,
1069 &spr_read_generic, &spr_write_generic,
1070 KVM_REG_PPC_AMR, 0);
1071 spr_register_kvm(env, SPR_UAMOR, "UAMOR",
1072 SPR_NOACCESS, SPR_NOACCESS,
1073 &spr_read_generic, &spr_write_generic,
1074 KVM_REG_PPC_UAMOR, 0);
1075 #endif /* !CONFIG_USER_ONLY */
1076 }
1077 #endif /* TARGET_PPC64 */
1078
1079 static void gen_spr_thrm (CPUPPCState *env)
1080 {
1081 /* Thermal management */
1082 /* XXX : not implemented */
1083 spr_register(env, SPR_THRM1, "THRM1",
1084 SPR_NOACCESS, SPR_NOACCESS,
1085 &spr_read_generic, &spr_write_generic,
1086 0x00000000);
1087 /* XXX : not implemented */
1088 spr_register(env, SPR_THRM2, "THRM2",
1089 SPR_NOACCESS, SPR_NOACCESS,
1090 &spr_read_generic, &spr_write_generic,
1091 0x00000000);
1092 /* XXX : not implemented */
1093 spr_register(env, SPR_THRM3, "THRM3",
1094 SPR_NOACCESS, SPR_NOACCESS,
1095 &spr_read_generic, &spr_write_generic,
1096 0x00000000);
1097 }
1098
1099 /* SPR specific to PowerPC 604 implementation */
1100 static void gen_spr_604 (CPUPPCState *env)
1101 {
1102 /* Processor identification */
1103 spr_register(env, SPR_PIR, "PIR",
1104 SPR_NOACCESS, SPR_NOACCESS,
1105 &spr_read_generic, &spr_write_pir,
1106 0x00000000);
1107 /* Breakpoints */
1108 /* XXX : not implemented */
1109 spr_register(env, SPR_IABR, "IABR",
1110 SPR_NOACCESS, SPR_NOACCESS,
1111 &spr_read_generic, &spr_write_generic,
1112 0x00000000);
1113 /* XXX : not implemented */
1114 spr_register_kvm(env, SPR_DABR, "DABR",
1115 SPR_NOACCESS, SPR_NOACCESS,
1116 &spr_read_generic, &spr_write_generic,
1117 KVM_REG_PPC_DABR, 0x00000000);
1118 /* Performance counters */
1119 /* XXX : not implemented */
1120 spr_register(env, SPR_MMCR0, "MMCR0",
1121 SPR_NOACCESS, SPR_NOACCESS,
1122 &spr_read_generic, &spr_write_generic,
1123 0x00000000);
1124 /* XXX : not implemented */
1125 spr_register(env, SPR_PMC1, "PMC1",
1126 SPR_NOACCESS, SPR_NOACCESS,
1127 &spr_read_generic, &spr_write_generic,
1128 0x00000000);
1129 /* XXX : not implemented */
1130 spr_register(env, SPR_PMC2, "PMC2",
1131 SPR_NOACCESS, SPR_NOACCESS,
1132 &spr_read_generic, &spr_write_generic,
1133 0x00000000);
1134 /* XXX : not implemented */
1135 spr_register(env, SPR_SIAR, "SIAR",
1136 SPR_NOACCESS, SPR_NOACCESS,
1137 &spr_read_generic, SPR_NOACCESS,
1138 0x00000000);
1139 /* XXX : not implemented */
1140 spr_register(env, SPR_SDA, "SDA",
1141 SPR_NOACCESS, SPR_NOACCESS,
1142 &spr_read_generic, SPR_NOACCESS,
1143 0x00000000);
1144 /* External access control */
1145 /* XXX : not implemented */
1146 spr_register(env, SPR_EAR, "EAR",
1147 SPR_NOACCESS, SPR_NOACCESS,
1148 &spr_read_generic, &spr_write_generic,
1149 0x00000000);
1150 }
1151
1152 /* SPR specific to PowerPC 603 implementation */
1153 static void gen_spr_603 (CPUPPCState *env)
1154 {
1155 /* External access control */
1156 /* XXX : not implemented */
1157 spr_register(env, SPR_EAR, "EAR",
1158 SPR_NOACCESS, SPR_NOACCESS,
1159 &spr_read_generic, &spr_write_generic,
1160 0x00000000);
1161 /* Breakpoints */
1162 /* XXX : not implemented */
1163 spr_register(env, SPR_IABR, "IABR",
1164 SPR_NOACCESS, SPR_NOACCESS,
1165 &spr_read_generic, &spr_write_generic,
1166 0x00000000);
1167
1168 }
1169
1170 /* SPR specific to PowerPC G2 implementation */
1171 static void gen_spr_G2 (CPUPPCState *env)
1172 {
1173 /* Memory base address */
1174 /* MBAR */
1175 /* XXX : not implemented */
1176 spr_register(env, SPR_MBAR, "MBAR",
1177 SPR_NOACCESS, SPR_NOACCESS,
1178 &spr_read_generic, &spr_write_generic,
1179 0x00000000);
1180 /* Exception processing */
1181 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1182 SPR_NOACCESS, SPR_NOACCESS,
1183 &spr_read_generic, &spr_write_generic,
1184 0x00000000);
1185 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1186 SPR_NOACCESS, SPR_NOACCESS,
1187 &spr_read_generic, &spr_write_generic,
1188 0x00000000);
1189 /* Breakpoints */
1190 /* XXX : not implemented */
1191 spr_register(env, SPR_DABR, "DABR",
1192 SPR_NOACCESS, SPR_NOACCESS,
1193 &spr_read_generic, &spr_write_generic,
1194 0x00000000);
1195 /* XXX : not implemented */
1196 spr_register(env, SPR_DABR2, "DABR2",
1197 SPR_NOACCESS, SPR_NOACCESS,
1198 &spr_read_generic, &spr_write_generic,
1199 0x00000000);
1200 /* XXX : not implemented */
1201 spr_register(env, SPR_IABR, "IABR",
1202 SPR_NOACCESS, SPR_NOACCESS,
1203 &spr_read_generic, &spr_write_generic,
1204 0x00000000);
1205 /* XXX : not implemented */
1206 spr_register(env, SPR_IABR2, "IABR2",
1207 SPR_NOACCESS, SPR_NOACCESS,
1208 &spr_read_generic, &spr_write_generic,
1209 0x00000000);
1210 /* XXX : not implemented */
1211 spr_register(env, SPR_IBCR, "IBCR",
1212 SPR_NOACCESS, SPR_NOACCESS,
1213 &spr_read_generic, &spr_write_generic,
1214 0x00000000);
1215 /* XXX : not implemented */
1216 spr_register(env, SPR_DBCR, "DBCR",
1217 SPR_NOACCESS, SPR_NOACCESS,
1218 &spr_read_generic, &spr_write_generic,
1219 0x00000000);
1220 }
1221
1222 /* SPR specific to PowerPC 602 implementation */
1223 static void gen_spr_602 (CPUPPCState *env)
1224 {
1225 /* ESA registers */
1226 /* XXX : not implemented */
1227 spr_register(env, SPR_SER, "SER",
1228 SPR_NOACCESS, SPR_NOACCESS,
1229 &spr_read_generic, &spr_write_generic,
1230 0x00000000);
1231 /* XXX : not implemented */
1232 spr_register(env, SPR_SEBR, "SEBR",
1233 SPR_NOACCESS, SPR_NOACCESS,
1234 &spr_read_generic, &spr_write_generic,
1235 0x00000000);
1236 /* XXX : not implemented */
1237 spr_register(env, SPR_ESASRR, "ESASRR",
1238 SPR_NOACCESS, SPR_NOACCESS,
1239 &spr_read_generic, &spr_write_generic,
1240 0x00000000);
1241 /* Floating point status */
1242 /* XXX : not implemented */
1243 spr_register(env, SPR_SP, "SP",
1244 SPR_NOACCESS, SPR_NOACCESS,
1245 &spr_read_generic, &spr_write_generic,
1246 0x00000000);
1247 /* XXX : not implemented */
1248 spr_register(env, SPR_LT, "LT",
1249 SPR_NOACCESS, SPR_NOACCESS,
1250 &spr_read_generic, &spr_write_generic,
1251 0x00000000);
1252 /* Watchdog timer */
1253 /* XXX : not implemented */
1254 spr_register(env, SPR_TCR, "TCR",
1255 SPR_NOACCESS, SPR_NOACCESS,
1256 &spr_read_generic, &spr_write_generic,
1257 0x00000000);
1258 /* Interrupt base */
1259 spr_register(env, SPR_IBR, "IBR",
1260 SPR_NOACCESS, SPR_NOACCESS,
1261 &spr_read_generic, &spr_write_generic,
1262 0x00000000);
1263 /* XXX : not implemented */
1264 spr_register(env, SPR_IABR, "IABR",
1265 SPR_NOACCESS, SPR_NOACCESS,
1266 &spr_read_generic, &spr_write_generic,
1267 0x00000000);
1268 }
1269
1270 /* SPR specific to PowerPC 601 implementation */
1271 static void gen_spr_601 (CPUPPCState *env)
1272 {
1273 /* Multiplication/division register */
1274 /* MQ */
1275 spr_register(env, SPR_MQ, "MQ",
1276 &spr_read_generic, &spr_write_generic,
1277 &spr_read_generic, &spr_write_generic,
1278 0x00000000);
1279 /* RTC registers */
1280 spr_register(env, SPR_601_RTCU, "RTCU",
1281 SPR_NOACCESS, SPR_NOACCESS,
1282 SPR_NOACCESS, &spr_write_601_rtcu,
1283 0x00000000);
1284 spr_register(env, SPR_601_VRTCU, "RTCU",
1285 &spr_read_601_rtcu, SPR_NOACCESS,
1286 &spr_read_601_rtcu, SPR_NOACCESS,
1287 0x00000000);
1288 spr_register(env, SPR_601_RTCL, "RTCL",
1289 SPR_NOACCESS, SPR_NOACCESS,
1290 SPR_NOACCESS, &spr_write_601_rtcl,
1291 0x00000000);
1292 spr_register(env, SPR_601_VRTCL, "RTCL",
1293 &spr_read_601_rtcl, SPR_NOACCESS,
1294 &spr_read_601_rtcl, SPR_NOACCESS,
1295 0x00000000);
1296 /* Timer */
1297 #if 0 /* ? */
1298 spr_register(env, SPR_601_UDECR, "UDECR",
1299 &spr_read_decr, SPR_NOACCESS,
1300 &spr_read_decr, SPR_NOACCESS,
1301 0x00000000);
1302 #endif
1303 /* External access control */
1304 /* XXX : not implemented */
1305 spr_register(env, SPR_EAR, "EAR",
1306 SPR_NOACCESS, SPR_NOACCESS,
1307 &spr_read_generic, &spr_write_generic,
1308 0x00000000);
1309 /* Memory management */
1310 #if !defined(CONFIG_USER_ONLY)
1311 spr_register(env, SPR_IBAT0U, "IBAT0U",
1312 SPR_NOACCESS, SPR_NOACCESS,
1313 &spr_read_601_ubat, &spr_write_601_ubatu,
1314 0x00000000);
1315 spr_register(env, SPR_IBAT0L, "IBAT0L",
1316 SPR_NOACCESS, SPR_NOACCESS,
1317 &spr_read_601_ubat, &spr_write_601_ubatl,
1318 0x00000000);
1319 spr_register(env, SPR_IBAT1U, "IBAT1U",
1320 SPR_NOACCESS, SPR_NOACCESS,
1321 &spr_read_601_ubat, &spr_write_601_ubatu,
1322 0x00000000);
1323 spr_register(env, SPR_IBAT1L, "IBAT1L",
1324 SPR_NOACCESS, SPR_NOACCESS,
1325 &spr_read_601_ubat, &spr_write_601_ubatl,
1326 0x00000000);
1327 spr_register(env, SPR_IBAT2U, "IBAT2U",
1328 SPR_NOACCESS, SPR_NOACCESS,
1329 &spr_read_601_ubat, &spr_write_601_ubatu,
1330 0x00000000);
1331 spr_register(env, SPR_IBAT2L, "IBAT2L",
1332 SPR_NOACCESS, SPR_NOACCESS,
1333 &spr_read_601_ubat, &spr_write_601_ubatl,
1334 0x00000000);
1335 spr_register(env, SPR_IBAT3U, "IBAT3U",
1336 SPR_NOACCESS, SPR_NOACCESS,
1337 &spr_read_601_ubat, &spr_write_601_ubatu,
1338 0x00000000);
1339 spr_register(env, SPR_IBAT3L, "IBAT3L",
1340 SPR_NOACCESS, SPR_NOACCESS,
1341 &spr_read_601_ubat, &spr_write_601_ubatl,
1342 0x00000000);
1343 env->nb_BATs = 4;
1344 #endif
1345 }
1346
1347 static void gen_spr_74xx (CPUPPCState *env)
1348 {
1349 /* Processor identification */
1350 spr_register(env, SPR_PIR, "PIR",
1351 SPR_NOACCESS, SPR_NOACCESS,
1352 &spr_read_generic, &spr_write_pir,
1353 0x00000000);
1354 /* XXX : not implemented */
1355 spr_register(env, SPR_MMCR2, "MMCR2",
1356 SPR_NOACCESS, SPR_NOACCESS,
1357 &spr_read_generic, &spr_write_generic,
1358 0x00000000);
1359 /* XXX : not implemented */
1360 spr_register(env, SPR_UMMCR2, "UMMCR2",
1361 &spr_read_ureg, SPR_NOACCESS,
1362 &spr_read_ureg, SPR_NOACCESS,
1363 0x00000000);
1364 /* XXX: not implemented */
1365 spr_register(env, SPR_BAMR, "BAMR",
1366 SPR_NOACCESS, SPR_NOACCESS,
1367 &spr_read_generic, &spr_write_generic,
1368 0x00000000);
1369 /* XXX : not implemented */
1370 spr_register(env, SPR_MSSCR0, "MSSCR0",
1371 SPR_NOACCESS, SPR_NOACCESS,
1372 &spr_read_generic, &spr_write_generic,
1373 0x00000000);
1374 /* Hardware implementation registers */
1375 /* XXX : not implemented */
1376 spr_register(env, SPR_HID0, "HID0",
1377 SPR_NOACCESS, SPR_NOACCESS,
1378 &spr_read_generic, &spr_write_generic,
1379 0x00000000);
1380 /* XXX : not implemented */
1381 spr_register(env, SPR_HID1, "HID1",
1382 SPR_NOACCESS, SPR_NOACCESS,
1383 &spr_read_generic, &spr_write_generic,
1384 0x00000000);
1385 /* Altivec */
1386 spr_register(env, SPR_VRSAVE, "VRSAVE",
1387 &spr_read_generic, &spr_write_generic,
1388 &spr_read_generic, &spr_write_generic,
1389 0x00000000);
1390 /* XXX : not implemented */
1391 spr_register(env, SPR_L2CR, "L2CR",
1392 SPR_NOACCESS, SPR_NOACCESS,
1393 &spr_read_generic, spr_access_nop,
1394 0x00000000);
1395 /* Not strictly an SPR */
1396 vscr_init(env, 0x00010000);
1397 }
1398
1399 static void gen_l3_ctrl (CPUPPCState *env)
1400 {
1401 /* L3CR */
1402 /* XXX : not implemented */
1403 spr_register(env, SPR_L3CR, "L3CR",
1404 SPR_NOACCESS, SPR_NOACCESS,
1405 &spr_read_generic, &spr_write_generic,
1406 0x00000000);
1407 /* L3ITCR0 */
1408 /* XXX : not implemented */
1409 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1410 SPR_NOACCESS, SPR_NOACCESS,
1411 &spr_read_generic, &spr_write_generic,
1412 0x00000000);
1413 /* L3PM */
1414 /* XXX : not implemented */
1415 spr_register(env, SPR_L3PM, "L3PM",
1416 SPR_NOACCESS, SPR_NOACCESS,
1417 &spr_read_generic, &spr_write_generic,
1418 0x00000000);
1419 }
1420
1421 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1422 {
1423 #if !defined(CONFIG_USER_ONLY)
1424 env->nb_tlb = nb_tlbs;
1425 env->nb_ways = nb_ways;
1426 env->id_tlbs = 1;
1427 env->tlb_type = TLB_6XX;
1428 /* XXX : not implemented */
1429 spr_register(env, SPR_PTEHI, "PTEHI",
1430 SPR_NOACCESS, SPR_NOACCESS,
1431 &spr_read_generic, &spr_write_generic,
1432 0x00000000);
1433 /* XXX : not implemented */
1434 spr_register(env, SPR_PTELO, "PTELO",
1435 SPR_NOACCESS, SPR_NOACCESS,
1436 &spr_read_generic, &spr_write_generic,
1437 0x00000000);
1438 /* XXX : not implemented */
1439 spr_register(env, SPR_TLBMISS, "TLBMISS",
1440 SPR_NOACCESS, SPR_NOACCESS,
1441 &spr_read_generic, &spr_write_generic,
1442 0x00000000);
1443 #endif
1444 }
1445
1446 #if !defined(CONFIG_USER_ONLY)
1447 static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1448 {
1449 TCGv t0 = tcg_temp_new();
1450
1451 tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256);
1452 gen_store_spr(sprn, t0);
1453 tcg_temp_free(t0);
1454 }
1455
1456 static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1457 {
1458 TCGv_i32 t0 = tcg_const_i32(sprn);
1459 gen_helper_booke206_tlbflush(cpu_env, t0);
1460 tcg_temp_free_i32(t0);
1461 }
1462
1463 static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1464 {
1465 TCGv_i32 t0 = tcg_const_i32(sprn);
1466 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1467 tcg_temp_free_i32(t0);
1468 }
1469 #endif
1470
1471 static void gen_spr_usprgh (CPUPPCState *env)
1472 {
1473 spr_register(env, SPR_USPRG4, "USPRG4",
1474 &spr_read_ureg, SPR_NOACCESS,
1475 &spr_read_ureg, SPR_NOACCESS,
1476 0x00000000);
1477 spr_register(env, SPR_USPRG5, "USPRG5",
1478 &spr_read_ureg, SPR_NOACCESS,
1479 &spr_read_ureg, SPR_NOACCESS,
1480 0x00000000);
1481 spr_register(env, SPR_USPRG6, "USPRG6",
1482 &spr_read_ureg, SPR_NOACCESS,
1483 &spr_read_ureg, SPR_NOACCESS,
1484 0x00000000);
1485 spr_register(env, SPR_USPRG7, "USPRG7",
1486 &spr_read_ureg, SPR_NOACCESS,
1487 &spr_read_ureg, SPR_NOACCESS,
1488 0x00000000);
1489 }
1490
1491 /* PowerPC BookE SPR */
1492 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1493 {
1494 const char *ivor_names[64] = {
1495 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1496 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1497 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1498 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1499 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1500 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1501 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1502 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1503 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1504 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1505 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1506 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1507 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1508 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1509 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1510 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1511 };
1512 #define SPR_BOOKE_IVORxx (-1)
1513 int ivor_sprn[64] = {
1514 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1515 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1516 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1517 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1518 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1519 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1520 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1521 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1522 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1523 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1524 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1525 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1526 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1527 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1528 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1529 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1530 };
1531 int i;
1532
1533 /* Interrupt processing */
1534 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1535 SPR_NOACCESS, SPR_NOACCESS,
1536 &spr_read_generic, &spr_write_generic,
1537 0x00000000);
1538 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1539 SPR_NOACCESS, SPR_NOACCESS,
1540 &spr_read_generic, &spr_write_generic,
1541 0x00000000);
1542 /* Debug */
1543 /* XXX : not implemented */
1544 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1545 SPR_NOACCESS, SPR_NOACCESS,
1546 &spr_read_generic, &spr_write_generic,
1547 0x00000000);
1548 /* XXX : not implemented */
1549 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1550 SPR_NOACCESS, SPR_NOACCESS,
1551 &spr_read_generic, &spr_write_generic,
1552 0x00000000);
1553 /* XXX : not implemented */
1554 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1555 SPR_NOACCESS, SPR_NOACCESS,
1556 &spr_read_generic, &spr_write_generic,
1557 0x00000000);
1558 /* XXX : not implemented */
1559 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1560 SPR_NOACCESS, SPR_NOACCESS,
1561 &spr_read_generic, &spr_write_generic,
1562 0x00000000);
1563 /* XXX : not implemented */
1564 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1565 SPR_NOACCESS, SPR_NOACCESS,
1566 &spr_read_generic, &spr_write_40x_dbcr0,
1567 0x00000000);
1568 /* XXX : not implemented */
1569 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1570 SPR_NOACCESS, SPR_NOACCESS,
1571 &spr_read_generic, &spr_write_generic,
1572 0x00000000);
1573 /* XXX : not implemented */
1574 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1575 SPR_NOACCESS, SPR_NOACCESS,
1576 &spr_read_generic, &spr_write_generic,
1577 0x00000000);
1578 /* XXX : not implemented */
1579 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1580 SPR_NOACCESS, SPR_NOACCESS,
1581 &spr_read_generic, &spr_write_clear,
1582 0x00000000);
1583 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1584 SPR_NOACCESS, SPR_NOACCESS,
1585 &spr_read_generic, &spr_write_generic,
1586 0x00000000);
1587 spr_register(env, SPR_BOOKE_ESR, "ESR",
1588 SPR_NOACCESS, SPR_NOACCESS,
1589 &spr_read_generic, &spr_write_generic,
1590 0x00000000);
1591 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1592 SPR_NOACCESS, SPR_NOACCESS,
1593 &spr_read_generic, &spr_write_excp_prefix,
1594 0x00000000);
1595 /* Exception vectors */
1596 for (i = 0; i < 64; i++) {
1597 if (ivor_mask & (1ULL << i)) {
1598 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1599 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1600 exit(1);
1601 }
1602 spr_register(env, ivor_sprn[i], ivor_names[i],
1603 SPR_NOACCESS, SPR_NOACCESS,
1604 &spr_read_generic, &spr_write_excp_vector,
1605 0x00000000);
1606 }
1607 }
1608 spr_register(env, SPR_BOOKE_PID, "PID",
1609 SPR_NOACCESS, SPR_NOACCESS,
1610 &spr_read_generic, &spr_write_booke_pid,
1611 0x00000000);
1612 spr_register(env, SPR_BOOKE_TCR, "TCR",
1613 SPR_NOACCESS, SPR_NOACCESS,
1614 &spr_read_generic, &spr_write_booke_tcr,
1615 0x00000000);
1616 spr_register(env, SPR_BOOKE_TSR, "TSR",
1617 SPR_NOACCESS, SPR_NOACCESS,
1618 &spr_read_generic, &spr_write_booke_tsr,
1619 0x00000000);
1620 /* Timer */
1621 spr_register(env, SPR_DECR, "DECR",
1622 SPR_NOACCESS, SPR_NOACCESS,
1623 &spr_read_decr, &spr_write_decr,
1624 0x00000000);
1625 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1626 SPR_NOACCESS, SPR_NOACCESS,
1627 SPR_NOACCESS, &spr_write_generic,
1628 0x00000000);
1629 /* SPRGs */
1630 spr_register(env, SPR_USPRG0, "USPRG0",
1631 &spr_read_generic, &spr_write_generic,
1632 &spr_read_generic, &spr_write_generic,
1633 0x00000000);
1634 spr_register(env, SPR_SPRG4, "SPRG4",
1635 SPR_NOACCESS, SPR_NOACCESS,
1636 &spr_read_generic, &spr_write_generic,
1637 0x00000000);
1638 spr_register(env, SPR_SPRG5, "SPRG5",
1639 SPR_NOACCESS, SPR_NOACCESS,
1640 &spr_read_generic, &spr_write_generic,
1641 0x00000000);
1642 spr_register(env, SPR_SPRG6, "SPRG6",
1643 SPR_NOACCESS, SPR_NOACCESS,
1644 &spr_read_generic, &spr_write_generic,
1645 0x00000000);
1646 spr_register(env, SPR_SPRG7, "SPRG7",
1647 SPR_NOACCESS, SPR_NOACCESS,
1648 &spr_read_generic, &spr_write_generic,
1649 0x00000000);
1650 }
1651
1652 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1653 uint32_t maxsize, uint32_t flags,
1654 uint32_t nentries)
1655 {
1656 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1657 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1658 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1659 flags | nentries;
1660 }
1661
1662 /* BookE 2.06 storage control registers */
1663 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1664 uint32_t *tlbncfg)
1665 {
1666 #if !defined(CONFIG_USER_ONLY)
1667 const char *mas_names[8] = {
1668 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1669 };
1670 int mas_sprn[8] = {
1671 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1672 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1673 };
1674 int i;
1675
1676 /* TLB assist registers */
1677 /* XXX : not implemented */
1678 for (i = 0; i < 8; i++) {
1679 void (*uea_write)(void *o, int sprn, int gprn) = &spr_write_generic32;
1680 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1681 uea_write = &spr_write_generic;
1682 }
1683 if (mas_mask & (1 << i)) {
1684 spr_register(env, mas_sprn[i], mas_names[i],
1685 SPR_NOACCESS, SPR_NOACCESS,
1686 &spr_read_generic, uea_write,
1687 0x00000000);
1688 }
1689 }
1690 if (env->nb_pids > 1) {
1691 /* XXX : not implemented */
1692 spr_register(env, SPR_BOOKE_PID1, "PID1",
1693 SPR_NOACCESS, SPR_NOACCESS,
1694 &spr_read_generic, &spr_write_booke_pid,
1695 0x00000000);
1696 }
1697 if (env->nb_pids > 2) {
1698 /* XXX : not implemented */
1699 spr_register(env, SPR_BOOKE_PID2, "PID2",
1700 SPR_NOACCESS, SPR_NOACCESS,
1701 &spr_read_generic, &spr_write_booke_pid,
1702 0x00000000);
1703 }
1704 /* XXX : not implemented */
1705 spr_register(env, SPR_MMUCFG, "MMUCFG",
1706 SPR_NOACCESS, SPR_NOACCESS,
1707 &spr_read_generic, SPR_NOACCESS,
1708 0x00000000); /* TOFIX */
1709 switch (env->nb_ways) {
1710 case 4:
1711 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1712 SPR_NOACCESS, SPR_NOACCESS,
1713 &spr_read_generic, SPR_NOACCESS,
1714 tlbncfg[3]);
1715 /* Fallthru */
1716 case 3:
1717 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1718 SPR_NOACCESS, SPR_NOACCESS,
1719 &spr_read_generic, SPR_NOACCESS,
1720 tlbncfg[2]);
1721 /* Fallthru */
1722 case 2:
1723 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1724 SPR_NOACCESS, SPR_NOACCESS,
1725 &spr_read_generic, SPR_NOACCESS,
1726 tlbncfg[1]);
1727 /* Fallthru */
1728 case 1:
1729 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1730 SPR_NOACCESS, SPR_NOACCESS,
1731 &spr_read_generic, SPR_NOACCESS,
1732 tlbncfg[0]);
1733 /* Fallthru */
1734 case 0:
1735 default:
1736 break;
1737 }
1738 #endif
1739
1740 gen_spr_usprgh(env);
1741 }
1742
1743 /* SPR specific to PowerPC 440 implementation */
1744 static void gen_spr_440 (CPUPPCState *env)
1745 {
1746 /* Cache control */
1747 /* XXX : not implemented */
1748 spr_register(env, SPR_440_DNV0, "DNV0",
1749 SPR_NOACCESS, SPR_NOACCESS,
1750 &spr_read_generic, &spr_write_generic,
1751 0x00000000);
1752 /* XXX : not implemented */
1753 spr_register(env, SPR_440_DNV1, "DNV1",
1754 SPR_NOACCESS, SPR_NOACCESS,
1755 &spr_read_generic, &spr_write_generic,
1756 0x00000000);
1757 /* XXX : not implemented */
1758 spr_register(env, SPR_440_DNV2, "DNV2",
1759 SPR_NOACCESS, SPR_NOACCESS,
1760 &spr_read_generic, &spr_write_generic,
1761 0x00000000);
1762 /* XXX : not implemented */
1763 spr_register(env, SPR_440_DNV3, "DNV3",
1764 SPR_NOACCESS, SPR_NOACCESS,
1765 &spr_read_generic, &spr_write_generic,
1766 0x00000000);
1767 /* XXX : not implemented */
1768 spr_register(env, SPR_440_DTV0, "DTV0",
1769 SPR_NOACCESS, SPR_NOACCESS,
1770 &spr_read_generic, &spr_write_generic,
1771 0x00000000);
1772 /* XXX : not implemented */
1773 spr_register(env, SPR_440_DTV1, "DTV1",
1774 SPR_NOACCESS, SPR_NOACCESS,
1775 &spr_read_generic, &spr_write_generic,
1776 0x00000000);
1777 /* XXX : not implemented */
1778 spr_register(env, SPR_440_DTV2, "DTV2",
1779 SPR_NOACCESS, SPR_NOACCESS,
1780 &spr_read_generic, &spr_write_generic,
1781 0x00000000);
1782 /* XXX : not implemented */
1783 spr_register(env, SPR_440_DTV3, "DTV3",
1784 SPR_NOACCESS, SPR_NOACCESS,
1785 &spr_read_generic, &spr_write_generic,
1786 0x00000000);
1787 /* XXX : not implemented */
1788 spr_register(env, SPR_440_DVLIM, "DVLIM",
1789 SPR_NOACCESS, SPR_NOACCESS,
1790 &spr_read_generic, &spr_write_generic,
1791 0x00000000);
1792 /* XXX : not implemented */
1793 spr_register(env, SPR_440_INV0, "INV0",
1794 SPR_NOACCESS, SPR_NOACCESS,
1795 &spr_read_generic, &spr_write_generic,
1796 0x00000000);
1797 /* XXX : not implemented */
1798 spr_register(env, SPR_440_INV1, "INV1",
1799 SPR_NOACCESS, SPR_NOACCESS,
1800 &spr_read_generic, &spr_write_generic,
1801 0x00000000);
1802 /* XXX : not implemented */
1803 spr_register(env, SPR_440_INV2, "INV2",
1804 SPR_NOACCESS, SPR_NOACCESS,
1805 &spr_read_generic, &spr_write_generic,
1806 0x00000000);
1807 /* XXX : not implemented */
1808 spr_register(env, SPR_440_INV3, "INV3",
1809 SPR_NOACCESS, SPR_NOACCESS,
1810 &spr_read_generic, &spr_write_generic,
1811 0x00000000);
1812 /* XXX : not implemented */
1813 spr_register(env, SPR_440_ITV0, "ITV0",
1814 SPR_NOACCESS, SPR_NOACCESS,
1815 &spr_read_generic, &spr_write_generic,
1816 0x00000000);
1817 /* XXX : not implemented */
1818 spr_register(env, SPR_440_ITV1, "ITV1",
1819 SPR_NOACCESS, SPR_NOACCESS,
1820 &spr_read_generic, &spr_write_generic,
1821 0x00000000);
1822 /* XXX : not implemented */
1823 spr_register(env, SPR_440_ITV2, "ITV2",
1824 SPR_NOACCESS, SPR_NOACCESS,
1825 &spr_read_generic, &spr_write_generic,
1826 0x00000000);
1827 /* XXX : not implemented */
1828 spr_register(env, SPR_440_ITV3, "ITV3",
1829 SPR_NOACCESS, SPR_NOACCESS,
1830 &spr_read_generic, &spr_write_generic,
1831 0x00000000);
1832 /* XXX : not implemented */
1833 spr_register(env, SPR_440_IVLIM, "IVLIM",
1834 SPR_NOACCESS, SPR_NOACCESS,
1835 &spr_read_generic, &spr_write_generic,
1836 0x00000000);
1837 /* Cache debug */
1838 /* XXX : not implemented */
1839 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1840 SPR_NOACCESS, SPR_NOACCESS,
1841 &spr_read_generic, SPR_NOACCESS,
1842 0x00000000);
1843 /* XXX : not implemented */
1844 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1845 SPR_NOACCESS, SPR_NOACCESS,
1846 &spr_read_generic, SPR_NOACCESS,
1847 0x00000000);
1848 /* XXX : not implemented */
1849 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1850 SPR_NOACCESS, SPR_NOACCESS,
1851 &spr_read_generic, SPR_NOACCESS,
1852 0x00000000);
1853 /* XXX : not implemented */
1854 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1855 SPR_NOACCESS, SPR_NOACCESS,
1856 &spr_read_generic, SPR_NOACCESS,
1857 0x00000000);
1858 /* XXX : not implemented */
1859 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1860 SPR_NOACCESS, SPR_NOACCESS,
1861 &spr_read_generic, SPR_NOACCESS,
1862 0x00000000);
1863 /* XXX : not implemented */
1864 spr_register(env, SPR_440_DBDR, "DBDR",
1865 SPR_NOACCESS, SPR_NOACCESS,
1866 &spr_read_generic, &spr_write_generic,
1867 0x00000000);
1868 /* Processor control */
1869 spr_register(env, SPR_4xx_CCR0, "CCR0",
1870 SPR_NOACCESS, SPR_NOACCESS,
1871 &spr_read_generic, &spr_write_generic,
1872 0x00000000);
1873 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1874 SPR_NOACCESS, SPR_NOACCESS,
1875 &spr_read_generic, SPR_NOACCESS,
1876 0x00000000);
1877 /* Storage control */
1878 spr_register(env, SPR_440_MMUCR, "MMUCR",
1879 SPR_NOACCESS, SPR_NOACCESS,
1880 &spr_read_generic, &spr_write_generic,
1881 0x00000000);
1882 }
1883
1884 /* SPR shared between PowerPC 40x implementations */
1885 static void gen_spr_40x (CPUPPCState *env)
1886 {
1887 /* Cache */
1888 /* not emulated, as QEMU do not emulate caches */
1889 spr_register(env, SPR_40x_DCCR, "DCCR",
1890 SPR_NOACCESS, SPR_NOACCESS,
1891 &spr_read_generic, &spr_write_generic,
1892 0x00000000);
1893 /* not emulated, as QEMU do not emulate caches */
1894 spr_register(env, SPR_40x_ICCR, "ICCR",
1895 SPR_NOACCESS, SPR_NOACCESS,
1896 &spr_read_generic, &spr_write_generic,
1897 0x00000000);
1898 /* not emulated, as QEMU do not emulate caches */
1899 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1900 SPR_NOACCESS, SPR_NOACCESS,
1901 &spr_read_generic, SPR_NOACCESS,
1902 0x00000000);
1903 /* Exception */
1904 spr_register(env, SPR_40x_DEAR, "DEAR",
1905 SPR_NOACCESS, SPR_NOACCESS,
1906 &spr_read_generic, &spr_write_generic,
1907 0x00000000);
1908 spr_register(env, SPR_40x_ESR, "ESR",
1909 SPR_NOACCESS, SPR_NOACCESS,
1910 &spr_read_generic, &spr_write_generic,
1911 0x00000000);
1912 spr_register(env, SPR_40x_EVPR, "EVPR",
1913 SPR_NOACCESS, SPR_NOACCESS,
1914 &spr_read_generic, &spr_write_excp_prefix,
1915 0x00000000);
1916 spr_register(env, SPR_40x_SRR2, "SRR2",
1917 &spr_read_generic, &spr_write_generic,
1918 &spr_read_generic, &spr_write_generic,
1919 0x00000000);
1920 spr_register(env, SPR_40x_SRR3, "SRR3",
1921 &spr_read_generic, &spr_write_generic,
1922 &spr_read_generic, &spr_write_generic,
1923 0x00000000);
1924 /* Timers */
1925 spr_register(env, SPR_40x_PIT, "PIT",
1926 SPR_NOACCESS, SPR_NOACCESS,
1927 &spr_read_40x_pit, &spr_write_40x_pit,
1928 0x00000000);
1929 spr_register(env, SPR_40x_TCR, "TCR",
1930 SPR_NOACCESS, SPR_NOACCESS,
1931 &spr_read_generic, &spr_write_booke_tcr,
1932 0x00000000);
1933 spr_register(env, SPR_40x_TSR, "TSR",
1934 SPR_NOACCESS, SPR_NOACCESS,
1935 &spr_read_generic, &spr_write_booke_tsr,
1936 0x00000000);
1937 }
1938
1939 /* SPR specific to PowerPC 405 implementation */
1940 static void gen_spr_405 (CPUPPCState *env)
1941 {
1942 /* MMU */
1943 spr_register(env, SPR_40x_PID, "PID",
1944 SPR_NOACCESS, SPR_NOACCESS,
1945 &spr_read_generic, &spr_write_generic,
1946 0x00000000);
1947 spr_register(env, SPR_4xx_CCR0, "CCR0",
1948 SPR_NOACCESS, SPR_NOACCESS,
1949 &spr_read_generic, &spr_write_generic,
1950 0x00700000);
1951 /* Debug interface */
1952 /* XXX : not implemented */
1953 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1954 SPR_NOACCESS, SPR_NOACCESS,
1955 &spr_read_generic, &spr_write_40x_dbcr0,
1956 0x00000000);
1957 /* XXX : not implemented */
1958 spr_register(env, SPR_405_DBCR1, "DBCR1",
1959 SPR_NOACCESS, SPR_NOACCESS,
1960 &spr_read_generic, &spr_write_generic,
1961 0x00000000);
1962 /* XXX : not implemented */
1963 spr_register(env, SPR_40x_DBSR, "DBSR",
1964 SPR_NOACCESS, SPR_NOACCESS,
1965 &spr_read_generic, &spr_write_clear,
1966 /* Last reset was system reset */
1967 0x00000300);
1968 /* XXX : not implemented */
1969 spr_register(env, SPR_40x_DAC1, "DAC1",
1970 SPR_NOACCESS, SPR_NOACCESS,
1971 &spr_read_generic, &spr_write_generic,
1972 0x00000000);
1973 spr_register(env, SPR_40x_DAC2, "DAC2",
1974 SPR_NOACCESS, SPR_NOACCESS,
1975 &spr_read_generic, &spr_write_generic,
1976 0x00000000);
1977 /* XXX : not implemented */
1978 spr_register(env, SPR_405_DVC1, "DVC1",
1979 SPR_NOACCESS, SPR_NOACCESS,
1980 &spr_read_generic, &spr_write_generic,
1981 0x00000000);
1982 /* XXX : not implemented */
1983 spr_register(env, SPR_405_DVC2, "DVC2",
1984 SPR_NOACCESS, SPR_NOACCESS,
1985 &spr_read_generic, &spr_write_generic,
1986 0x00000000);
1987 /* XXX : not implemented */
1988 spr_register(env, SPR_40x_IAC1, "IAC1",
1989 SPR_NOACCESS, SPR_NOACCESS,
1990 &spr_read_generic, &spr_write_generic,
1991 0x00000000);
1992 spr_register(env, SPR_40x_IAC2, "IAC2",
1993 SPR_NOACCESS, SPR_NOACCESS,
1994 &spr_read_generic, &spr_write_generic,
1995 0x00000000);
1996 /* XXX : not implemented */
1997 spr_register(env, SPR_405_IAC3, "IAC3",
1998 SPR_NOACCESS, SPR_NOACCESS,
1999 &spr_read_generic, &spr_write_generic,
2000 0x00000000);
2001 /* XXX : not implemented */
2002 spr_register(env, SPR_405_IAC4, "IAC4",
2003 SPR_NOACCESS, SPR_NOACCESS,
2004 &spr_read_generic, &spr_write_generic,
2005 0x00000000);
2006 /* Storage control */
2007 /* XXX: TODO: not implemented */
2008 spr_register(env, SPR_405_SLER, "SLER",
2009 SPR_NOACCESS, SPR_NOACCESS,
2010 &spr_read_generic, &spr_write_40x_sler,
2011 0x00000000);
2012 spr_register(env, SPR_40x_ZPR, "ZPR",
2013 SPR_NOACCESS, SPR_NOACCESS,
2014 &spr_read_generic, &spr_write_generic,
2015 0x00000000);
2016 /* XXX : not implemented */
2017 spr_register(env, SPR_405_SU0R, "SU0R",
2018 SPR_NOACCESS, SPR_NOACCESS,
2019 &spr_read_generic, &spr_write_generic,
2020 0x00000000);
2021 /* SPRG */
2022 spr_register(env, SPR_USPRG0, "USPRG0",
2023 &spr_read_ureg, SPR_NOACCESS,
2024 &spr_read_ureg, SPR_NOACCESS,
2025 0x00000000);
2026 spr_register(env, SPR_SPRG4, "SPRG4",
2027 SPR_NOACCESS, SPR_NOACCESS,
2028 &spr_read_generic, &spr_write_generic,
2029 0x00000000);
2030 spr_register(env, SPR_SPRG5, "SPRG5",
2031 SPR_NOACCESS, SPR_NOACCESS,
2032 spr_read_generic, &spr_write_generic,
2033 0x00000000);
2034 spr_register(env, SPR_SPRG6, "SPRG6",
2035 SPR_NOACCESS, SPR_NOACCESS,
2036 spr_read_generic, &spr_write_generic,
2037 0x00000000);
2038 spr_register(env, SPR_SPRG7, "SPRG7",
2039 SPR_NOACCESS, SPR_NOACCESS,
2040 spr_read_generic, &spr_write_generic,
2041 0x00000000);
2042 gen_spr_usprgh(env);
2043 }
2044
2045 /* SPR shared between PowerPC 401 & 403 implementations */
2046 static void gen_spr_401_403 (CPUPPCState *env)
2047 {
2048 /* Time base */
2049 spr_register(env, SPR_403_VTBL, "TBL",
2050 &spr_read_tbl, SPR_NOACCESS,
2051 &spr_read_tbl, SPR_NOACCESS,
2052 0x00000000);
2053 spr_register(env, SPR_403_TBL, "TBL",
2054 SPR_NOACCESS, SPR_NOACCESS,
2055 SPR_NOACCESS, &spr_write_tbl,
2056 0x00000000);
2057 spr_register(env, SPR_403_VTBU, "TBU",
2058 &spr_read_tbu, SPR_NOACCESS,
2059 &spr_read_tbu, SPR_NOACCESS,
2060 0x00000000);
2061 spr_register(env, SPR_403_TBU, "TBU",
2062 SPR_NOACCESS, SPR_NOACCESS,
2063 SPR_NOACCESS, &spr_write_tbu,
2064 0x00000000);
2065 /* Debug */
2066 /* not emulated, as QEMU do not emulate caches */
2067 spr_register(env, SPR_403_CDBCR, "CDBCR",
2068 SPR_NOACCESS, SPR_NOACCESS,
2069 &spr_read_generic, &spr_write_generic,
2070 0x00000000);
2071 }
2072
2073 /* SPR specific to PowerPC 401 implementation */
2074 static void gen_spr_401 (CPUPPCState *env)
2075 {
2076 /* Debug interface */
2077 /* XXX : not implemented */
2078 spr_register(env, SPR_40x_DBCR0, "DBCR",
2079 SPR_NOACCESS, SPR_NOACCESS,
2080 &spr_read_generic, &spr_write_40x_dbcr0,
2081 0x00000000);
2082 /* XXX : not implemented */
2083 spr_register(env, SPR_40x_DBSR, "DBSR",
2084 SPR_NOACCESS, SPR_NOACCESS,
2085 &spr_read_generic, &spr_write_clear,
2086 /* Last reset was system reset */
2087 0x00000300);
2088 /* XXX : not implemented */
2089 spr_register(env, SPR_40x_DAC1, "DAC",
2090 SPR_NOACCESS, SPR_NOACCESS,
2091 &spr_read_generic, &spr_write_generic,
2092 0x00000000);
2093 /* XXX : not implemented */
2094 spr_register(env, SPR_40x_IAC1, "IAC",
2095 SPR_NOACCESS, SPR_NOACCESS,
2096 &spr_read_generic, &spr_write_generic,
2097 0x00000000);
2098 /* Storage control */
2099 /* XXX: TODO: not implemented */
2100 spr_register(env, SPR_405_SLER, "SLER",
2101 SPR_NOACCESS, SPR_NOACCESS,
2102 &spr_read_generic, &spr_write_40x_sler,
2103 0x00000000);
2104 /* not emulated, as QEMU never does speculative access */
2105 spr_register(env, SPR_40x_SGR, "SGR",
2106 SPR_NOACCESS, SPR_NOACCESS,
2107 &spr_read_generic, &spr_write_generic,
2108 0xFFFFFFFF);
2109 /* not emulated, as QEMU do not emulate caches */
2110 spr_register(env, SPR_40x_DCWR, "DCWR",
2111 SPR_NOACCESS, SPR_NOACCESS,
2112 &spr_read_generic, &spr_write_generic,
2113 0x00000000);
2114 }
2115
2116 static void gen_spr_401x2 (CPUPPCState *env)
2117 {
2118 gen_spr_401(env);
2119 spr_register(env, SPR_40x_PID, "PID",
2120 SPR_NOACCESS, SPR_NOACCESS,
2121 &spr_read_generic, &spr_write_generic,
2122 0x00000000);
2123 spr_register(env, SPR_40x_ZPR, "ZPR",
2124 SPR_NOACCESS, SPR_NOACCESS,
2125 &spr_read_generic, &spr_write_generic,
2126 0x00000000);
2127 }
2128
2129 /* SPR specific to PowerPC 403 implementation */
2130 static void gen_spr_403 (CPUPPCState *env)
2131 {
2132 /* Debug interface */
2133 /* XXX : not implemented */
2134 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2135 SPR_NOACCESS, SPR_NOACCESS,
2136 &spr_read_generic, &spr_write_40x_dbcr0,
2137 0x00000000);
2138 /* XXX : not implemented */
2139 spr_register(env, SPR_40x_DBSR, "DBSR",
2140 SPR_NOACCESS, SPR_NOACCESS,
2141 &spr_read_generic, &spr_write_clear,
2142 /* Last reset was system reset */
2143 0x00000300);
2144 /* XXX : not implemented */
2145 spr_register(env, SPR_40x_DAC1, "DAC1",
2146 SPR_NOACCESS, SPR_NOACCESS,
2147 &spr_read_generic, &spr_write_generic,
2148 0x00000000);
2149 /* XXX : not implemented */
2150 spr_register(env, SPR_40x_DAC2, "DAC2",
2151 SPR_NOACCESS, SPR_NOACCESS,
2152 &spr_read_generic, &spr_write_generic,
2153 0x00000000);
2154 /* XXX : not implemented */
2155 spr_register(env, SPR_40x_IAC1, "IAC1",
2156 SPR_NOACCESS, SPR_NOACCESS,
2157 &spr_read_generic, &spr_write_generic,
2158 0x00000000);
2159 /* XXX : not implemented */
2160 spr_register(env, SPR_40x_IAC2, "IAC2",
2161 SPR_NOACCESS, SPR_NOACCESS,
2162 &spr_read_generic, &spr_write_generic,
2163 0x00000000);
2164 }
2165
2166 static void gen_spr_403_real (CPUPPCState *env)
2167 {
2168 spr_register(env, SPR_403_PBL1, "PBL1",
2169 SPR_NOACCESS, SPR_NOACCESS,
2170 &spr_read_403_pbr, &spr_write_403_pbr,
2171 0x00000000);
2172 spr_register(env, SPR_403_PBU1, "PBU1",
2173 SPR_NOACCESS, SPR_NOACCESS,
2174 &spr_read_403_pbr, &spr_write_403_pbr,
2175 0x00000000);
2176 spr_register(env, SPR_403_PBL2, "PBL2",
2177 SPR_NOACCESS, SPR_NOACCESS,
2178 &spr_read_403_pbr, &spr_write_403_pbr,
2179 0x00000000);
2180 spr_register(env, SPR_403_PBU2, "PBU2",
2181 SPR_NOACCESS, SPR_NOACCESS,
2182 &spr_read_403_pbr, &spr_write_403_pbr,
2183 0x00000000);
2184 }
2185
2186 static void gen_spr_403_mmu (CPUPPCState *env)
2187 {
2188 /* MMU */
2189 spr_register(env, SPR_40x_PID, "PID",
2190 SPR_NOACCESS, SPR_NOACCESS,
2191 &spr_read_generic, &spr_write_generic,
2192 0x00000000);
2193 spr_register(env, SPR_40x_ZPR, "ZPR",
2194 SPR_NOACCESS, SPR_NOACCESS,
2195 &spr_read_generic, &spr_write_generic,
2196 0x00000000);
2197 }
2198
2199 /* SPR specific to PowerPC compression coprocessor extension */
2200 static void gen_spr_compress (CPUPPCState *env)
2201 {
2202 /* XXX : not implemented */
2203 spr_register(env, SPR_401_SKR, "SKR",
2204 SPR_NOACCESS, SPR_NOACCESS,
2205 &spr_read_generic, &spr_write_generic,
2206 0x00000000);
2207 }
2208
2209 static void gen_spr_5xx_8xx (CPUPPCState *env)
2210 {
2211 /* Exception processing */
2212 spr_register_kvm(env, SPR_DSISR, "DSISR",
2213 SPR_NOACCESS, SPR_NOACCESS,
2214 &spr_read_generic, &spr_write_generic,
2215 KVM_REG_PPC_DSISR, 0x00000000);
2216 spr_register_kvm(env, SPR_DAR, "DAR",
2217 SPR_NOACCESS, SPR_NOACCESS,
2218 &spr_read_generic, &spr_write_generic,
2219 KVM_REG_PPC_DAR, 0x00000000);
2220 /* Timer */
2221 spr_register(env, SPR_DECR, "DECR",
2222 SPR_NOACCESS, SPR_NOACCESS,
2223 &spr_read_decr, &spr_write_decr,
2224 0x00000000);
2225 /* XXX : not implemented */
2226 spr_register(env, SPR_MPC_EIE, "EIE",
2227 SPR_NOACCESS, SPR_NOACCESS,
2228 &spr_read_generic, &spr_write_generic,
2229 0x00000000);
2230 /* XXX : not implemented */
2231 spr_register(env, SPR_MPC_EID, "EID",
2232 SPR_NOACCESS, SPR_NOACCESS,
2233 &spr_read_generic, &spr_write_generic,
2234 0x00000000);
2235 /* XXX : not implemented */
2236 spr_register(env, SPR_MPC_NRI, "NRI",
2237 SPR_NOACCESS, SPR_NOACCESS,
2238 &spr_read_generic, &spr_write_generic,
2239 0x00000000);
2240 /* XXX : not implemented */
2241 spr_register(env, SPR_MPC_CMPA, "CMPA",
2242 SPR_NOACCESS, SPR_NOACCESS,
2243 &spr_read_generic, &spr_write_generic,
2244 0x00000000);
2245 /* XXX : not implemented */
2246 spr_register(env, SPR_MPC_CMPB, "CMPB",
2247 SPR_NOACCESS, SPR_NOACCESS,
2248 &spr_read_generic, &spr_write_generic,
2249 0x00000000);
2250 /* XXX : not implemented */
2251 spr_register(env, SPR_MPC_CMPC, "CMPC",
2252 SPR_NOACCESS, SPR_NOACCESS,
2253 &spr_read_generic, &spr_write_generic,
2254 0x00000000);
2255 /* XXX : not implemented */
2256 spr_register(env, SPR_MPC_CMPD, "CMPD",
2257 SPR_NOACCESS, SPR_NOACCESS,
2258 &spr_read_generic, &spr_write_generic,
2259 0x00000000);
2260 /* XXX : not implemented */
2261 spr_register(env, SPR_MPC_ECR, "ECR",
2262 SPR_NOACCESS, SPR_NOACCESS,
2263 &spr_read_generic, &spr_write_generic,
2264 0x00000000);
2265 /* XXX : not implemented */
2266 spr_register(env, SPR_MPC_DER, "DER",
2267 SPR_NOACCESS, SPR_NOACCESS,
2268 &spr_read_generic, &spr_write_generic,
2269 0x00000000);
2270 /* XXX : not implemented */
2271 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2272 SPR_NOACCESS, SPR_NOACCESS,
2273 &spr_read_generic, &spr_write_generic,
2274 0x00000000);
2275 /* XXX : not implemented */
2276 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2277 SPR_NOACCESS, SPR_NOACCESS,
2278 &spr_read_generic, &spr_write_generic,
2279 0x00000000);
2280 /* XXX : not implemented */
2281 spr_register(env, SPR_MPC_CMPE, "CMPE",
2282 SPR_NOACCESS, SPR_NOACCESS,
2283 &spr_read_generic, &spr_write_generic,
2284 0x00000000);
2285 /* XXX : not implemented */
2286 spr_register(env, SPR_MPC_CMPF, "CMPF",
2287 SPR_NOACCESS, SPR_NOACCESS,
2288 &spr_read_generic, &spr_write_generic,
2289 0x00000000);
2290 /* XXX : not implemented */
2291 spr_register(env, SPR_MPC_CMPG, "CMPG",
2292 SPR_NOACCESS, SPR_NOACCESS,
2293 &spr_read_generic, &spr_write_generic,
2294 0x00000000);
2295 /* XXX : not implemented */
2296 spr_register(env, SPR_MPC_CMPH, "CMPH",
2297 SPR_NOACCESS, SPR_NOACCESS,
2298 &spr_read_generic, &spr_write_generic,
2299 0x00000000);
2300 /* XXX : not implemented */
2301 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2302 SPR_NOACCESS, SPR_NOACCESS,
2303 &spr_read_generic, &spr_write_generic,
2304 0x00000000);
2305 /* XXX : not implemented */
2306 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2307 SPR_NOACCESS, SPR_NOACCESS,
2308 &spr_read_generic, &spr_write_generic,
2309 0x00000000);
2310 /* XXX : not implemented */
2311 spr_register(env, SPR_MPC_BAR, "BAR",
2312 SPR_NOACCESS, SPR_NOACCESS,
2313 &spr_read_generic, &spr_write_generic,
2314 0x00000000);
2315 /* XXX : not implemented */
2316 spr_register(env, SPR_MPC_DPDR, "DPDR",
2317 SPR_NOACCESS, SPR_NOACCESS,
2318 &spr_read_generic, &spr_write_generic,
2319 0x00000000);
2320 /* XXX : not implemented */
2321 spr_register(env, SPR_MPC_IMMR, "IMMR",
2322 SPR_NOACCESS, SPR_NOACCESS,
2323 &spr_read_generic, &spr_write_generic,
2324 0x00000000);
2325 }
2326
2327 static void gen_spr_5xx (CPUPPCState *env)
2328 {
2329 /* XXX : not implemented */
2330 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2331 SPR_NOACCESS, SPR_NOACCESS,
2332 &spr_read_generic, &spr_write_generic,
2333 0x00000000);
2334 /* XXX : not implemented */
2335 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2336 SPR_NOACCESS, SPR_NOACCESS,
2337 &spr_read_generic, &spr_write_generic,
2338 0x00000000);
2339 /* XXX : not implemented */
2340 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2341 SPR_NOACCESS, SPR_NOACCESS,
2342 &spr_read_generic, &spr_write_generic,
2343 0x00000000);
2344 /* XXX : not implemented */
2345 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2346 SPR_NOACCESS, SPR_NOACCESS,
2347 &spr_read_generic, &spr_write_generic,
2348 0x00000000);
2349 /* XXX : not implemented */
2350 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2351 SPR_NOACCESS, SPR_NOACCESS,
2352 &spr_read_generic, &spr_write_generic,
2353 0x00000000);
2354 /* XXX : not implemented */
2355 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2356 SPR_NOACCESS, SPR_NOACCESS,
2357 &spr_read_generic, &spr_write_generic,
2358 0x00000000);
2359 /* XXX : not implemented */
2360 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2361 SPR_NOACCESS, SPR_NOACCESS,
2362 &spr_read_generic, &spr_write_generic,
2363 0x00000000);
2364 /* XXX : not implemented */
2365 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2366 SPR_NOACCESS, SPR_NOACCESS,
2367 &spr_read_generic, &spr_write_generic,
2368 0x00000000);
2369 /* XXX : not implemented */
2370 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2371 SPR_NOACCESS, SPR_NOACCESS,
2372 &spr_read_generic, &spr_write_generic,
2373 0x00000000);
2374 /* XXX : not implemented */
2375 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2376 SPR_NOACCESS, SPR_NOACCESS,
2377 &spr_read_generic, &spr_write_generic,
2378 0x00000000);
2379 /* XXX : not implemented */
2380 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2381 SPR_NOACCESS, SPR_NOACCESS,
2382 &spr_read_generic, &spr_write_generic,
2383 0x00000000);
2384 /* XXX : not implemented */
2385 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2386 SPR_NOACCESS, SPR_NOACCESS,
2387 &spr_read_generic, &spr_write_generic,
2388 0x00000000);
2389 /* XXX : not implemented */
2390 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2391 SPR_NOACCESS, SPR_NOACCESS,
2392 &spr_read_generic, &spr_write_generic,
2393 0x00000000);
2394 /* XXX : not implemented */
2395 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2396 SPR_NOACCESS, SPR_NOACCESS,
2397 &spr_read_generic, &spr_write_generic,
2398 0x00000000);
2399 /* XXX : not implemented */
2400 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2401 SPR_NOACCESS, SPR_NOACCESS,
2402 &spr_read_generic, &spr_write_generic,
2403 0x00000000);
2404 /* XXX : not implemented */
2405 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2406 SPR_NOACCESS, SPR_NOACCESS,
2407 &spr_read_generic, &spr_write_generic,
2408 0x00000000);
2409 /* XXX : not implemented */
2410 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2411 SPR_NOACCESS, SPR_NOACCESS,
2412 &spr_read_generic, &spr_write_generic,
2413 0x00000000);
2414 /* XXX : not implemented */
2415 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2416 SPR_NOACCESS, SPR_NOACCESS,
2417 &spr_read_generic, &spr_write_generic,
2418 0x00000000);
2419 /* XXX : not implemented */
2420 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2421 SPR_NOACCESS, SPR_NOACCESS,
2422 &spr_read_generic, &spr_write_generic,
2423 0x00000000);
2424 /* XXX : not implemented */
2425 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2426 SPR_NOACCESS, SPR_NOACCESS,
2427 &spr_read_generic, &spr_write_generic,
2428 0x00000000);
2429 /* XXX : not implemented */
2430 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2431 SPR_NOACCESS, SPR_NOACCESS,
2432 &spr_read_generic, &spr_write_generic,
2433 0x00000000);
2434 }
2435
2436 static void gen_spr_8xx (CPUPPCState *env)
2437 {
2438 /* XXX : not implemented */
2439 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2440 SPR_NOACCESS, SPR_NOACCESS,
2441 &spr_read_generic, &spr_write_generic,
2442 0x00000000);
2443 /* XXX : not implemented */
2444 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2445 SPR_NOACCESS, SPR_NOACCESS,
2446 &spr_read_generic, &spr_write_generic,
2447 0x00000000);
2448 /* XXX : not implemented */
2449 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2450 SPR_NOACCESS, SPR_NOACCESS,
2451 &spr_read_generic, &spr_write_generic,
2452 0x00000000);
2453 /* XXX : not implemented */
2454 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2455 SPR_NOACCESS, SPR_NOACCESS,
2456 &spr_read_generic, &spr_write_generic,
2457 0x00000000);
2458 /* XXX : not implemented */
2459 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2460 SPR_NOACCESS, SPR_NOACCESS,
2461 &spr_read_generic, &spr_write_generic,
2462 0x00000000);
2463 /* XXX : not implemented */
2464 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2465 SPR_NOACCESS, SPR_NOACCESS,
2466 &spr_read_generic, &spr_write_generic,
2467 0x00000000);
2468 /* XXX : not implemented */
2469 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2470 SPR_NOACCESS, SPR_NOACCESS,
2471 &spr_read_generic, &spr_write_generic,
2472 0x00000000);
2473 /* XXX : not implemented */
2474 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2475 SPR_NOACCESS, SPR_NOACCESS,
2476 &spr_read_generic, &spr_write_generic,
2477 0x00000000);
2478 /* XXX : not implemented */
2479 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2480 SPR_NOACCESS, SPR_NOACCESS,
2481 &spr_read_generic, &spr_write_generic,
2482 0x00000000);
2483 /* XXX : not implemented */
2484 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2485 SPR_NOACCESS, SPR_NOACCESS,
2486 &spr_read_generic, &spr_write_generic,
2487 0x00000000);
2488 /* XXX : not implemented */
2489 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2490 SPR_NOACCESS, SPR_NOACCESS,
2491 &spr_read_generic, &spr_write_generic,
2492 0x00000000);
2493 /* XXX : not implemented */
2494 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2495 SPR_NOACCESS, SPR_NOACCESS,
2496 &spr_read_generic, &spr_write_generic,
2497 0x00000000);
2498 /* XXX : not implemented */
2499 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2500 SPR_NOACCESS, SPR_NOACCESS,
2501 &spr_read_generic, &spr_write_generic,
2502 0x00000000);
2503 /* XXX : not implemented */
2504 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2505 SPR_NOACCESS, SPR_NOACCESS,
2506 &spr_read_generic, &spr_write_generic,
2507 0x00000000);
2508 /* XXX : not implemented */
2509 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2510 SPR_NOACCESS, SPR_NOACCESS,
2511 &spr_read_generic, &spr_write_generic,
2512 0x00000000);
2513 /* XXX : not implemented */
2514 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2515 SPR_NOACCESS, SPR_NOACCESS,
2516 &spr_read_generic, &spr_write_generic,
2517 0x00000000);
2518 /* XXX : not implemented */
2519 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2520 SPR_NOACCESS, SPR_NOACCESS,
2521 &spr_read_generic, &spr_write_generic,
2522 0x00000000);
2523 /* XXX : not implemented */
2524 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2525 SPR_NOACCESS, SPR_NOACCESS,
2526 &spr_read_generic, &spr_write_generic,
2527 0x00000000);
2528 /* XXX : not implemented */
2529 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2530 SPR_NOACCESS, SPR_NOACCESS,
2531 &spr_read_generic, &spr_write_generic,
2532 0x00000000);
2533 /* XXX : not implemented */
2534 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2535 SPR_NOACCESS, SPR_NOACCESS,
2536 &spr_read_generic, &spr_write_generic,
2537 0x00000000);
2538 /* XXX : not implemented */
2539 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2540 SPR_NOACCESS, SPR_NOACCESS,
2541 &spr_read_generic, &spr_write_generic,
2542 0x00000000);
2543 /* XXX : not implemented */
2544 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2545 SPR_NOACCESS, SPR_NOACCESS,
2546 &spr_read_generic, &spr_write_generic,
2547 0x00000000);
2548 /* XXX : not implemented */
2549 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2550 SPR_NOACCESS, SPR_NOACCESS,
2551 &spr_read_generic, &spr_write_generic,
2552 0x00000000);
2553 /* XXX : not implemented */
2554 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2555 SPR_NOACCESS, SPR_NOACCESS,
2556 &spr_read_generic, &spr_write_generic,
2557 0x00000000);
2558 /* XXX : not implemented */
2559 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2560 SPR_NOACCESS, SPR_NOACCESS,
2561 &spr_read_generic, &spr_write_generic,
2562 0x00000000);
2563 }
2564
2565 // XXX: TODO
2566 /*
2567 * AMR => SPR 29 (Power 2.04)
2568 * CTRL => SPR 136 (Power 2.04)
2569 * CTRL => SPR 152 (Power 2.04)
2570 * SCOMC => SPR 276 (64 bits ?)
2571 * SCOMD => SPR 277 (64 bits ?)
2572 * TBU40 => SPR 286 (Power 2.04 hypv)
2573 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2574 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2575 * HDSISR => SPR 306 (Power 2.04 hypv)
2576 * HDAR => SPR 307 (Power 2.04 hypv)
2577 * PURR => SPR 309 (Power 2.04 hypv)
2578 * HDEC => SPR 310 (Power 2.04 hypv)
2579 * HIOR => SPR 311 (hypv)
2580 * RMOR => SPR 312 (970)
2581 * HRMOR => SPR 313 (Power 2.04 hypv)
2582 * HSRR0 => SPR 314 (Power 2.04 hypv)
2583 * HSRR1 => SPR 315 (Power 2.04 hypv)
2584 * LPIDR => SPR 317 (970)
2585 * EPR => SPR 702 (Power 2.04 emb)
2586 * perf => 768-783 (Power 2.04)
2587 * perf => 784-799 (Power 2.04)
2588 * PPR => SPR 896 (Power 2.04)
2589 * EPLC => SPR 947 (Power 2.04 emb)
2590 * EPSC => SPR 948 (Power 2.04 emb)
2591 * DABRX => 1015 (Power 2.04 hypv)
2592 * FPECR => SPR 1022 (?)
2593 * ... and more (thermal management, performance counters, ...)
2594 */
2595
2596 /*****************************************************************************/
2597 /* Exception vectors models */
2598 static void init_excp_4xx_real (CPUPPCState *env)
2599 {
2600 #if !defined(CONFIG_USER_ONLY)
2601 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2602 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2603 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2604 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2605 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2606 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2607 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2608 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2609 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2610 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2611 env->ivor_mask = 0x0000FFF0UL;
2612 env->ivpr_mask = 0xFFFF0000UL;
2613 /* Hardware reset vector */
2614 env->hreset_vector = 0xFFFFFFFCUL;
2615 #endif
2616 }
2617
2618 static void init_excp_4xx_softmmu (CPUPPCState *env)
2619 {
2620 #if !defined(CONFIG_USER_ONLY)
2621 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2622 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2623 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2624 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2625 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2626 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2627 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2628 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2629 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2630 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2631 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2632 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2633 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2634 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2635 env->ivor_mask = 0x0000FFF0UL;
2636 env->ivpr_mask = 0xFFFF0000UL;
2637 /* Hardware reset vector */
2638 env->hreset_vector = 0xFFFFFFFCUL;
2639 #endif
2640 }
2641
2642 static void init_excp_MPC5xx (CPUPPCState *env)
2643 {
2644 #if !defined(CONFIG_USER_ONLY)
2645 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2646 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2647 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2648 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2649 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2650 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2651 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2652 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2653 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2654 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2655 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2656 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2657 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2658 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2659 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2660 env->ivor_mask = 0x0000FFF0UL;
2661 env->ivpr_mask = 0xFFFF0000UL;
2662 /* Hardware reset vector */
2663 env->hreset_vector = 0x00000100UL;
2664 #endif
2665 }
2666
2667 static void init_excp_MPC8xx (CPUPPCState *env)
2668 {
2669 #if !defined(CONFIG_USER_ONLY)
2670 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2671 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2672 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2673 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2674 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2675 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2676 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2677 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2678 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2679 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2680 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2681 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2682 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2683 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2684 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2685 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2686 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2687 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2688 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2689 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2690 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2691 env->ivor_mask = 0x0000FFF0UL;
2692 env->ivpr_mask = 0xFFFF0000UL;
2693 /* Hardware reset vector */
2694 env->hreset_vector = 0x00000100UL;
2695 #endif
2696 }
2697
2698 static void init_excp_G2 (CPUPPCState *env)
2699 {
2700 #if !defined(CONFIG_USER_ONLY)
2701 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2702 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2703 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2704 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2705 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2706 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2707 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2708 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2709 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2710 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2711 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2712 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2713 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2714 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2715 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2716 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2717 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2718 /* Hardware reset vector */
2719 env->hreset_vector = 0x00000100UL;
2720 #endif
2721 }
2722
2723 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2724 {
2725 #if !defined(CONFIG_USER_ONLY)
2726 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2727 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2728 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2729 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2730 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2731 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2732 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2733 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2734 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2735 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2736 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2737 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2738 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2739 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2740 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2741 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2742 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2743 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2744 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2745 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2746 env->ivor_mask = 0x0000FFF7UL;
2747 env->ivpr_mask = ivpr_mask;
2748 /* Hardware reset vector */
2749 env->hreset_vector = 0xFFFFFFFCUL;
2750 #endif
2751 }
2752
2753 static void init_excp_BookE (CPUPPCState *env)
2754 {
2755 #if !defined(CONFIG_USER_ONLY)
2756 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2757 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2758 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2759 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2760 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2761 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2762 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2763 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2764 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2765 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2766 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2767 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2768 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2769 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2770 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2771 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2772 env->ivor_mask = 0x0000FFE0UL;
2773 env->ivpr_mask = 0xFFFF0000UL;
2774 /* Hardware reset vector */
2775 env->hreset_vector = 0xFFFFFFFCUL;
2776 #endif
2777 }
2778
2779 static void init_excp_601 (CPUPPCState *env)
2780 {
2781 #if !defined(CONFIG_USER_ONLY)
2782 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2783 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2784 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2785 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2786 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2787 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2788 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2789 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2790 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2791 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2792 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2793 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2794 /* Hardware reset vector */
2795 env->hreset_vector = 0x00000100UL;
2796 #endif
2797 }
2798
2799 static void init_excp_602 (CPUPPCState *env)
2800 {
2801 #if !defined(CONFIG_USER_ONLY)
2802 /* XXX: exception prefix has a special behavior on 602 */
2803 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2804 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2805 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2806 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2807 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2808 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2809 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2810 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2811 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2812 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2813 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2814 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2815 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2816 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2817 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2818 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2819 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2820 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2821 /* Hardware reset vector */
2822 env->hreset_vector = 0x00000100UL;
2823 #endif
2824 }
2825
2826 static void init_excp_603 (CPUPPCState *env)
2827 {
2828 #if !defined(CONFIG_USER_ONLY)
2829 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2830 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2831 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2832 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2833 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2834 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2835 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2836 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2837 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2838 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2839 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2840 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2841 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2842 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2843 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2844 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2845 /* Hardware reset vector */
2846 env->hreset_vector = 0x00000100UL;
2847 #endif
2848 }
2849
2850 static void init_excp_604 (CPUPPCState *env)
2851 {
2852 #if !defined(CONFIG_USER_ONLY)
2853 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2854 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2855 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2856 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2857 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2858 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2859 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2860 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2861 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2862 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2863 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2864 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2865 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2866 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2867 /* Hardware reset vector */
2868 env->hreset_vector = 0x00000100UL;
2869 #endif
2870 }
2871
2872 static void init_excp_7x0 (CPUPPCState *env)
2873 {
2874 #if !defined(CONFIG_USER_ONLY)
2875 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2876 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2877 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2878 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2879 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2880 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2881 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2882 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2883 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2884 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2885 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2886 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2887 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2888 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2889 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2890 /* Hardware reset vector */
2891 env->hreset_vector = 0x00000100UL;
2892 #endif
2893 }
2894
2895 static void init_excp_750cl (CPUPPCState *env)
2896 {
2897 #if !defined(CONFIG_USER_ONLY)
2898 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2899 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2900 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2901 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2902 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2903 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2904 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2905 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2906 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2907 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2908 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2909 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2910 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2911 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2912 /* Hardware reset vector */
2913 env->hreset_vector = 0x00000100UL;
2914 #endif
2915 }
2916
2917 static void init_excp_750cx (CPUPPCState *env)
2918 {
2919 #if !defined(CONFIG_USER_ONLY)
2920 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2921 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2922 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2923 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2924 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2925 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2926 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2927 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2928 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2929 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2930 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2931 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2932 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2933 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2934 /* Hardware reset vector */
2935 env->hreset_vector = 0x00000100UL;
2936 #endif
2937 }
2938
2939 /* XXX: Check if this is correct */
2940 static void init_excp_7x5 (CPUPPCState *env)
2941 {
2942 #if !defined(CONFIG_USER_ONLY)
2943 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2944 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2945 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2946 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2947 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2948 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2949 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2950 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2951 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2952 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2953 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2954 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2955 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2956 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2957 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2958 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2959 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2960 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2961 /* Hardware reset vector */
2962 env->hreset_vector = 0x00000100UL;
2963 #endif
2964 }
2965
2966 static void init_excp_7400 (CPUPPCState *env)
2967 {
2968 #if !defined(CONFIG_USER_ONLY)
2969 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2970 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2971 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2972 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2973 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2974 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2975 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2976 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2977 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2978 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2979 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2980 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2981 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2982 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2983 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2984 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2985 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2986 /* Hardware reset vector */
2987 env->hreset_vector = 0x00000100UL;
2988 #endif
2989 }
2990
2991 static void init_excp_7450 (CPUPPCState *env)
2992 {
2993 #if !defined(CONFIG_USER_ONLY)
2994 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2995 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2996 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2997 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2998 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2999 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3000 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3001 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3002 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3003 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3004 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3005 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3006 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3007 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3008 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3009 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3010 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3011 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3012 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3013 /* Hardware reset vector */
3014 env->hreset_vector = 0x00000100UL;
3015 #endif
3016 }
3017
3018 #if defined (TARGET_PPC64)
3019 static void init_excp_970 (CPUPPCState *env)
3020 {
3021 #if !defined(CONFIG_USER_ONLY)
3022 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3023 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3024 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3025 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3026 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3027 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3028 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3029 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3030 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3031 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3032 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3033 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3034 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3035 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3036 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3037 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3038 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3039 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3040 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3041 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3042 /* Hardware reset vector */
3043 env->hreset_vector = 0x0000000000000100ULL;
3044 #endif
3045 }
3046
3047 static void init_excp_POWER7 (CPUPPCState *env)
3048 {
3049 #if !defined(CONFIG_USER_ONLY)
3050 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3051 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3052 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3053 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3054 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3055 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3056 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3057 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3058 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3059 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3060 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3061 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3062 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3063 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3064 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3065 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3066 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
3067 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3068 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3069 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3070 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3071 /* Hardware reset vector */
3072 env->hreset_vector = 0x0000000000000100ULL;
3073 #endif
3074 }
3075 #endif
3076
3077 /*****************************************************************************/
3078 /* Power management enable checks */
3079 static int check_pow_none (CPUPPCState *env)
3080 {
3081 return 0;
3082 }
3083
3084 static int check_pow_nocheck (CPUPPCState *env)
3085 {
3086 return 1;
3087 }
3088
3089 static int check_pow_hid0 (CPUPPCState *env)
3090 {
3091 if (env->spr[SPR_HID0] & 0x00E00000)
3092 return 1;
3093
3094 return 0;
3095 }
3096
3097 static int check_pow_hid0_74xx (CPUPPCState *env)
3098 {
3099 if (env->spr[SPR_HID0] & 0x00600000)
3100 return 1;
3101
3102 return 0;
3103 }
3104
3105 /*****************************************************************************/
3106 /* PowerPC implementations definitions */
3107
3108 #define POWERPC_FAMILY(_name) \
3109 static void \
3110 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3111 \
3112 static const TypeInfo \
3113 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
3114 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
3115 .parent = TYPE_POWERPC_CPU, \
3116 .abstract = true, \
3117 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
3118 }; \
3119 \
3120 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
3121 { \
3122 type_register_static( \
3123 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
3124 } \
3125 \
3126 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
3127 \
3128 static void glue(glue(ppc_, _name), _cpu_family_class_init)
3129
3130 static void init_proc_401 (CPUPPCState *env)
3131 {
3132 gen_spr_40x(env);
3133 gen_spr_401_403(env);
3134 gen_spr_401(env);
3135 init_excp_4xx_real(env);
3136 env->dcache_line_size = 32;
3137 env->icache_line_size = 32;
3138 /* Allocate hardware IRQ controller */
3139 ppc40x_irq_init(env);
3140
3141 SET_FIT_PERIOD(12, 16, 20, 24);
3142 SET_WDT_PERIOD(16, 20, 24, 28);
3143 }
3144
3145 POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
3146 {
3147 DeviceClass *dc = DEVICE_CLASS(oc);
3148 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3149
3150 dc->desc = "PowerPC 401";
3151 pcc->init_proc = init_proc_401;
3152 pcc->check_pow = check_pow_nocheck;
3153 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3154 PPC_WRTEE | PPC_DCR |
3155 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3156 PPC_CACHE_DCBZ |
3157 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3158 PPC_4xx_COMMON | PPC_40x_EXCP;
3159 pcc->msr_mask = 0x00000000000FD201ULL;
3160 pcc->mmu_model = POWERPC_MMU_REAL;
3161 pcc->excp_model = POWERPC_EXCP_40x;
3162 pcc->bus_model = PPC_FLAGS_INPUT_401;
3163 pcc->bfd_mach = bfd_mach_ppc_403;
3164 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3165 POWERPC_FLAG_BUS_CLK;
3166 }
3167
3168 static void init_proc_401x2 (CPUPPCState *env)
3169 {
3170 gen_spr_40x(env);
3171 gen_spr_401_403(env);
3172 gen_spr_401x2(env);
3173 gen_spr_compress(env);
3174 /* Memory management */
3175 #if !defined(CONFIG_USER_ONLY)
3176 env->nb_tlb = 64;
3177 env->nb_ways = 1;
3178 env->id_tlbs = 0;
3179 env->tlb_type = TLB_EMB;
3180 #endif
3181 init_excp_4xx_softmmu(env);
3182 env->dcache_line_size = 32;
3183 env->icache_line_size = 32;
3184 /* Allocate hardware IRQ controller */
3185 ppc40x_irq_init(env);
3186
3187 SET_FIT_PERIOD(12, 16, 20, 24);
3188 SET_WDT_PERIOD(16, 20, 24, 28);
3189 }
3190
3191 POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
3192 {
3193 DeviceClass *dc = DEVICE_CLASS(oc);
3194 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3195
3196 dc->desc = "PowerPC 401x2";
3197 pcc->init_proc = init_proc_401x2;
3198 pcc->check_pow = check_pow_nocheck;
3199 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3200 PPC_DCR | PPC_WRTEE |
3201 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3202 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3203 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3204 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3205 PPC_4xx_COMMON | PPC_40x_EXCP;
3206 pcc->msr_mask = 0x00000000001FD231ULL;
3207 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3208 pcc->excp_model = POWERPC_EXCP_40x;
3209 pcc->bus_model = PPC_FLAGS_INPUT_401;
3210 pcc->bfd_mach = bfd_mach_ppc_403;
3211 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3212 POWERPC_FLAG_BUS_CLK;
3213 }
3214
3215 static void init_proc_401x3 (CPUPPCState *env)
3216 {
3217 gen_spr_40x(env);
3218 gen_spr_401_403(env);
3219 gen_spr_401(env);
3220 gen_spr_401x2(env);
3221 gen_spr_compress(env);
3222 init_excp_4xx_softmmu(env);
3223 env->dcache_line_size = 32;
3224 env->icache_line_size = 32;
3225 /* Allocate hardware IRQ controller */
3226 ppc40x_irq_init(env);
3227
3228 SET_FIT_PERIOD(12, 16, 20, 24);
3229 SET_WDT_PERIOD(16, 20, 24, 28);
3230 }
3231
3232 POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
3233 {
3234 DeviceClass *dc = DEVICE_CLASS(oc);
3235 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3236
3237 dc->desc = "PowerPC 401x3";
3238 pcc->init_proc = init_proc_401x3;
3239 pcc->check_pow = check_pow_nocheck;
3240 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3241 PPC_DCR | PPC_WRTEE |
3242 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3243 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3244 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3245 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3246 PPC_4xx_COMMON | PPC_40x_EXCP;
3247 pcc->msr_mask = 0x00000000001FD631ULL;
3248 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3249 pcc->excp_model = POWERPC_EXCP_40x;
3250 pcc->bus_model = PPC_FLAGS_INPUT_401;
3251 pcc->bfd_mach = bfd_mach_ppc_403;
3252 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3253 POWERPC_FLAG_BUS_CLK;
3254 }
3255
3256 static void init_proc_IOP480 (CPUPPCState *env)
3257 {
3258 gen_spr_40x(env);
3259 gen_spr_401_403(env);
3260 gen_spr_401x2(env);
3261 gen_spr_compress(env);
3262 /* Memory management */
3263 #if !defined(CONFIG_USER_ONLY)
3264 env->nb_tlb = 64;
3265 env->nb_ways = 1;
3266 env->id_tlbs = 0;
3267 env->tlb_type = TLB_EMB;
3268 #endif
3269 init_excp_4xx_softmmu(env);
3270 env->dcache_line_size = 32;
3271 env->icache_line_size = 32;
3272 /* Allocate hardware IRQ controller */
3273 ppc40x_irq_init(env);
3274
3275 SET_FIT_PERIOD(8, 12, 16, 20);
3276 SET_WDT_PERIOD(16, 20, 24, 28);
3277 }
3278
3279 POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
3280 {
3281 DeviceClass *dc = DEVICE_CLASS(oc);
3282 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3283
3284 dc->desc = "IOP480";
3285 pcc->init_proc = init_proc_IOP480;
3286 pcc->check_pow = check_pow_nocheck;
3287 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3288 PPC_DCR | PPC_WRTEE |
3289 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3290 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3291 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3292 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3293 PPC_4xx_COMMON | PPC_40x_EXCP;
3294 pcc->msr_mask = 0x00000000001FD231ULL;
3295 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3296 pcc->excp_model = POWERPC_EXCP_40x;
3297 pcc->bus_model = PPC_FLAGS_INPUT_401;
3298 pcc->bfd_mach = bfd_mach_ppc_403;
3299 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3300 POWERPC_FLAG_BUS_CLK;
3301 }
3302
3303 static void init_proc_403 (CPUPPCState *env)
3304 {
3305 gen_spr_40x(env);
3306 gen_spr_401_403(env);
3307 gen_spr_403(env);
3308 gen_spr_403_real(env);
3309 init_excp_4xx_real(env);
3310 env->dcache_line_size = 32;
3311 env->icache_line_size = 32;
3312 /* Allocate hardware IRQ controller */
3313 ppc40x_irq_init(env);
3314
3315 SET_FIT_PERIOD(8, 12, 16, 20);
3316 SET_WDT_PERIOD(16, 20, 24, 28);
3317 }
3318
3319 POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
3320 {
3321 DeviceClass *dc = DEVICE_CLASS(oc);
3322 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3323
3324 dc->desc = "PowerPC 403";
3325 pcc->init_proc = init_proc_403;
3326 pcc->check_pow = check_pow_nocheck;
3327 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3328 PPC_DCR | PPC_WRTEE |
3329 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3330 PPC_CACHE_DCBZ |
3331 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3332 PPC_4xx_COMMON | PPC_40x_EXCP;
3333 pcc->msr_mask = 0x000000000007D00DULL;
3334 pcc->mmu_model = POWERPC_MMU_REAL;
3335 pcc->excp_model = POWERPC_EXCP_40x;
3336 pcc->bus_model = PPC_FLAGS_INPUT_401;
3337 pcc->bfd_mach = bfd_mach_ppc_403;
3338 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3339 POWERPC_FLAG_BUS_CLK;
3340 }
3341
3342 static void init_proc_403GCX (CPUPPCState *env)
3343 {
3344 gen_spr_40x(env);
3345 gen_spr_401_403(env);
3346 gen_spr_403(env);
3347 gen_spr_403_real(env);
3348 gen_spr_403_mmu(env);
3349 /* Bus access control */
3350 /* not emulated, as QEMU never does speculative access */
3351 spr_register(env, SPR_40x_SGR, "SGR",
3352 SPR_NOACCESS, SPR_NOACCESS,
3353 &spr_read_generic, &spr_write_generic,
3354 0xFFFFFFFF);
3355 /* not emulated, as QEMU do not emulate caches */
3356 spr_register(env, SPR_40x_DCWR, "DCWR",
3357 SPR_NOACCESS, SPR_NOACCESS,
3358 &spr_read_generic, &spr_write_generic,
3359 0x00000000);
3360 /* Memory management */
3361 #if !defined(CONFIG_USER_ONLY)
3362 env->nb_tlb = 64;
3363 env->nb_ways = 1;
3364 env->id_tlbs = 0;
3365 env->tlb_type = TLB_EMB;
3366 #endif
3367 init_excp_4xx_softmmu(env);
3368 env->dcache_line_size = 32;
3369 env->icache_line_size = 32;
3370 /* Allocate hardware IRQ controller */
3371 ppc40x_irq_init(env);
3372
3373 SET_FIT_PERIOD(8, 12, 16, 20);
3374 SET_WDT_PERIOD(16, 20, 24, 28);
3375 }
3376
3377 POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3378 {
3379 DeviceClass *dc = DEVICE_CLASS(oc);
3380 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3381
3382 dc->desc = "PowerPC 403 GCX";
3383 pcc->init_proc = init_proc_403GCX;
3384 pcc->check_pow = check_pow_nocheck;
3385 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3386 PPC_DCR | PPC_WRTEE |
3387 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3388 PPC_CACHE_DCBZ |
3389 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3390 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3391 PPC_4xx_COMMON | PPC_40x_EXCP;
3392 pcc->msr_mask = 0x000000000007D00DULL;
3393 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3394 pcc->excp_model = POWERPC_EXCP_40x;
3395 pcc->bus_model = PPC_FLAGS_INPUT_401;
3396 pcc->bfd_mach = bfd_mach_ppc_403;
3397 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3398 POWERPC_FLAG_BUS_CLK;
3399 }
3400
3401 static void init_proc_405 (CPUPPCState *env)
3402 {
3403 /* Time base */
3404 gen_tbl(env);
3405 gen_spr_40x(env);
3406 gen_spr_405(env);
3407 /* Bus access control */
3408 /* not emulated, as QEMU never does speculative access */
3409 spr_register(env, SPR_40x_SGR, "SGR",
3410 SPR_NOACCESS, SPR_NOACCESS,
3411 &spr_read_generic, &spr_write_generic,
3412 0xFFFFFFFF);
3413 /* not emulated, as QEMU do not emulate caches */
3414 spr_register(env, SPR_40x_DCWR, "DCWR",
3415 SPR_NOACCESS, SPR_NOACCESS,
3416 &spr_read_generic, &spr_write_generic,
3417 0x00000000);
3418 /* Memory management */
3419 #if !defined(CONFIG_USER_ONLY)
3420 env->nb_tlb = 64;
3421 env->nb_ways = 1;
3422 env->id_tlbs = 0;
3423 env->tlb_type = TLB_EMB;
3424 #endif
3425 init_excp_4xx_softmmu(env);
3426 env->dcache_line_size = 32;
3427 env->icache_line_size = 32;
3428 /* Allocate hardware IRQ controller */
3429 ppc40x_irq_init(env);
3430
3431 SET_FIT_PERIOD(8, 12, 16, 20);
3432 SET_WDT_PERIOD(16, 20, 24, 28);
3433 }
3434
3435 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3436 {
3437 DeviceClass *dc = DEVICE_CLASS(oc);
3438 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3439
3440 dc->desc = "PowerPC 405";
3441 pcc->init_proc = init_proc_405;
3442 pcc->check_pow = check_pow_nocheck;
3443 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3444 PPC_DCR | PPC_WRTEE |
3445 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3446 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3447 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3448 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3449 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3450 pcc->msr_mask = 0x000000000006E630ULL;
3451 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3452 pcc->excp_model = POWERPC_EXCP_40x;
3453 pcc->bus_model = PPC_FLAGS_INPUT_405;
3454 pcc->bfd_mach = bfd_mach_ppc_403;
3455 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3456 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3457 }
3458
3459 static void init_proc_440EP (CPUPPCState *env)
3460 {
3461 /* Time base */
3462 gen_tbl(env);
3463 gen_spr_BookE(env, 0x000000000000FFFFULL);
3464 gen_spr_440(env);
3465 gen_spr_usprgh(env);
3466 /* Processor identification */
3467 spr_register(env, SPR_BOOKE_PIR, "PIR",
3468 SPR_NOACCESS, SPR_NOACCESS,
3469 &spr_read_generic, &spr_write_pir,
3470 0x00000000);
3471 /* XXX : not implemented */
3472 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3473 SPR_NOACCESS, SPR_NOACCESS,
3474 &spr_read_generic, &spr_write_generic,
3475 0x00000000);
3476 /* XXX : not implemented */
3477 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3478 SPR_NOACCESS, SPR_NOACCESS,
3479 &spr_read_generic, &spr_write_generic,
3480 0x00000000);
3481 /* XXX : not implemented */
3482 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3483 SPR_NOACCESS, SPR_NOACCESS,
3484 &spr_read_generic, &spr_write_generic,
3485 0x00000000);
3486 /* XXX : not implemented */
3487 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3488 SPR_NOACCESS, SPR_NOACCESS,
3489 &spr_read_generic, &spr_write_generic,
3490 0x00000000);
3491 /* XXX : not implemented */
3492 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3493 SPR_NOACCESS, SPR_NOACCESS,
3494 &spr_read_generic, &spr_write_generic,
3495 0x00000000);
3496 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3497 SPR_NOACCESS, SPR_NOACCESS,
3498 &spr_read_generic, &spr_write_generic,
3499 0x00000000);
3500 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3501 SPR_NOACCESS, SPR_NOACCESS,
3502 &spr_read_generic, &spr_write_generic,
3503 0x00000000);
3504 /* XXX : not implemented */
3505 spr_register(env, SPR_440_CCR1, "CCR1",
3506 SPR_NOACCESS, SPR_NOACCESS,
3507 &spr_read_generic, &spr_write_generic,
3508 0x00000000);
3509 /* Memory management */
3510 #if !defined(CONFIG_USER_ONLY)
3511 env->nb_tlb = 64;
3512 env->nb_ways = 1;
3513 env->id_tlbs = 0;
3514 env->tlb_type = TLB_EMB;
3515 #endif
3516 init_excp_BookE(env);
3517 env->dcache_line_size = 32;
3518 env->icache_line_size = 32;
3519 ppc40x_irq_init(env);
3520
3521 SET_FIT_PERIOD(12, 16, 20, 24);
3522 SET_WDT_PERIOD(20, 24, 28, 32);
3523 }
3524
3525 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3526 {
3527 DeviceClass *dc = DEVICE_CLASS(oc);
3528 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3529
3530 dc->desc = "PowerPC 440 EP";
3531 pcc->init_proc = init_proc_440EP;
3532 pcc->check_pow = check_pow_nocheck;
3533 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3534 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3535 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3536 PPC_FLOAT_STFIWX |
3537 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3538 PPC_CACHE | PPC_CACHE_ICBI |
3539 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3540 PPC_MEM_TLBSYNC | PPC_MFTB |
3541 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3542 PPC_440_SPEC;
3543 pcc->msr_mask = 0x000000000006FF30ULL;
3544 pcc->mmu_model = POWERPC_MMU_BOOKE;
3545 pcc->excp_model = POWERPC_EXCP_BOOKE;
3546 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3547 pcc->bfd_mach = bfd_mach_ppc_403;
3548 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3549 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3550 }
3551
3552 static void init_proc_440GP (CPUPPCState *env)
3553 {
3554 /* Time base */
3555 gen_tbl(env);
3556 gen_spr_BookE(env, 0x000000000000FFFFULL);
3557 gen_spr_440(env);
3558 gen_spr_usprgh(env);
3559 /* Processor identification */
3560 spr_register(env, SPR_BOOKE_PIR, "PIR",
3561 SPR_NOACCESS, SPR_NOACCESS,
3562 &spr_read_generic, &spr_write_pir,
3563 0x00000000);
3564 /* XXX : not implemented */
3565 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3566 SPR_NOACCESS, SPR_NOACCESS,
3567 &spr_read_generic, &spr_write_generic,
3568 0x00000000);
3569 /* XXX : not implemented */
3570 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3571 SPR_NOACCESS, SPR_NOACCESS,
3572 &spr_read_generic, &spr_write_generic,
3573 0x00000000);
3574 /* XXX : not implemented */
3575 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3576 SPR_NOACCESS, SPR_NOACCESS,
3577 &spr_read_generic, &spr_write_generic,
3578 0x00000000);
3579 /* XXX : not implemented */
3580 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3581 SPR_NOACCESS, SPR_NOACCESS,
3582 &spr_read_generic, &spr_write_generic,
3583 0x00000000);
3584 /* Memory management */
3585 #if !defined(CONFIG_USER_ONLY)
3586 env->nb_tlb = 64;
3587 env->nb_ways = 1;
3588 env->id_tlbs = 0;
3589 env->tlb_type = TLB_EMB;
3590 #endif
3591 init_excp_BookE(env);
3592 env->dcache_line_size = 32;
3593 env->icache_line_size = 32;
3594 /* XXX: TODO: allocate internal IRQ controller */
3595
3596 SET_FIT_PERIOD(12, 16, 20, 24);
3597 SET_WDT_PERIOD(20, 24, 28, 32);
3598 }
3599
3600 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
3601 {
3602 DeviceClass *dc = DEVICE_CLASS(oc);
3603 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3604
3605 dc->desc = "PowerPC 440 GP";
3606 pcc->init_proc = init_proc_440GP;
3607 pcc->check_pow = check_pow_nocheck;
3608 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3609 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
3610 PPC_CACHE | PPC_CACHE_ICBI |
3611 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3612 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
3613 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3614 PPC_440_SPEC;
3615 pcc->msr_mask = 0x000000000006FF30ULL;
3616 pcc->mmu_model = POWERPC_MMU_BOOKE;
3617 pcc->excp_model = POWERPC_EXCP_BOOKE;
3618 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3619 pcc->bfd_mach = bfd_mach_ppc_403;
3620 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3621 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3622 }
3623
3624 static void init_proc_440x4 (CPUPPCState *env)
3625 {
3626 /* Time base */
3627 gen_tbl(env);
3628 gen_spr_BookE(env, 0x000000000000FFFFULL);
3629 gen_spr_440(env);
3630 gen_spr_usprgh(env);
3631 /* Processor identification */
3632 spr_register(env, SPR_BOOKE_PIR, "PIR",
3633 SPR_NOACCESS, SPR_NOACCESS,
3634 &spr_read_generic, &spr_write_pir,
3635 0x00000000);
3636 /* XXX : not implemented */
3637 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3638 SPR_NOACCESS, SPR_NOACCESS,
3639 &spr_read_generic, &spr_write_generic,
3640 0x00000000);
3641 /* XXX : not implemented */
3642 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3643 SPR_NOACCESS, SPR_NOACCESS,
3644 &spr_read_generic, &spr_write_generic,
3645 0x00000000);
3646 /* XXX : not implemented */
3647 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3648 SPR_NOACCESS, SPR_NOACCESS,
3649 &spr_read_generic, &spr_write_generic,
3650 0x00000000);
3651 /* XXX : not implemented */
3652 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3653 SPR_NOACCESS, SPR_NOACCESS,
3654 &spr_read_generic, &spr_write_generic,
3655 0x00000000);
3656 /* Memory management */
3657 #if !defined(CONFIG_USER_ONLY)
3658 env->nb_tlb = 64;
3659 env->nb_ways = 1;
3660 env->id_tlbs = 0;
3661 env->tlb_type = TLB_EMB;
3662 #endif
3663 init_excp_BookE(env);
3664 env->dcache_line_size = 32;
3665 env->icache_line_size = 32;
3666 /* XXX: TODO: allocate internal IRQ controller */
3667
3668 SET_FIT_PERIOD(12, 16, 20, 24);
3669 SET_WDT_PERIOD(20, 24, 28, 32);
3670 }
3671
3672 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
3673 {
3674 DeviceClass *dc = DEVICE_CLASS(oc);
3675 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3676
3677 dc->desc = "PowerPC 440x4";
3678 pcc->init_proc = init_proc_440x4;
3679 pcc->check_pow = check_pow_nocheck;
3680 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3681 PPC_DCR | PPC_WRTEE |
3682 PPC_CACHE | PPC_CACHE_ICBI |
3683 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3684 PPC_MEM_TLBSYNC | PPC_MFTB |
3685 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3686 PPC_440_SPEC;
3687 pcc->msr_mask = 0x000000000006FF30ULL;
3688 pcc->mmu_model = POWERPC_MMU_BOOKE;
3689 pcc->excp_model = POWERPC_EXCP_BOOKE;
3690 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3691 pcc->bfd_mach = bfd_mach_ppc_403;
3692 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3693 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3694 }
3695
3696 static void init_proc_440x5 (CPUPPCState *env)
3697 {
3698 /* Time base */
3699 gen_tbl(env);
3700 gen_spr_BookE(env, 0x000000000000FFFFULL);
3701 gen_spr_440(env);
3702 gen_spr_usprgh(env);
3703 /* Processor identification */
3704 spr_register(env, SPR_BOOKE_PIR, "PIR",
3705 SPR_NOACCESS, SPR_NOACCESS,
3706 &spr_read_generic, &spr_write_pir,
3707 0x00000000);
3708 /* XXX : not implemented */
3709 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3710 SPR_NOACCESS, SPR_NOACCESS,
3711 &spr_read_generic, &spr_write_generic,
3712 0x00000000);
3713 /* XXX : not implemented */
3714 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3715 SPR_NOACCESS, SPR_NOACCESS,
3716 &spr_read_generic, &spr_write_generic,
3717 0x00000000);
3718 /* XXX : not implemented */
3719 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3720 SPR_NOACCESS, SPR_NOACCESS,
3721 &spr_read_generic, &spr_write_generic,
3722 0x00000000);
3723 /* XXX : not implemented */
3724 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3725 SPR_NOACCESS, SPR_NOACCESS,
3726 &spr_read_generic, &spr_write_generic,
3727 0x00000000);
3728 /* XXX : not implemented */
3729 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3730 SPR_NOACCESS, SPR_NOACCESS,
3731 &spr_read_generic, &spr_write_generic,
3732 0x00000000);
3733 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3734 SPR_NOACCESS, SPR_NOACCESS,
3735 &spr_read_generic, &spr_write_generic,
3736 0x00000000);
3737 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3738 SPR_NOACCESS, SPR_NOACCESS,
3739 &spr_read_generic, &spr_write_generic,
3740 0x00000000);
3741 /* XXX : not implemented */
3742 spr_register(env, SPR_440_CCR1, "CCR1",
3743 SPR_NOACCESS, SPR_NOACCESS,
3744 &spr_read_generic, &spr_write_generic,
3745 0x00000000);
3746 /* Memory management */
3747 #if !defined(CONFIG_USER_ONLY)
3748 env->nb_tlb = 64;
3749 env->nb_ways = 1;
3750 env->id_tlbs = 0;
3751 env->tlb_type = TLB_EMB;
3752 #endif
3753 init_excp_BookE(env);
3754 env->dcache_line_size = 32;
3755 env->icache_line_size = 32;
3756 ppc40x_irq_init(env);
3757
3758 SET_FIT_PERIOD(12, 16, 20, 24);
3759 SET_WDT_PERIOD(20, 24, 28, 32);
3760 }
3761
3762 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
3763 {
3764 DeviceClass *dc = DEVICE_CLASS(oc);
3765 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3766
3767 dc->desc = "PowerPC 440x5";
3768 pcc->init_proc = init_proc_440x5;
3769 pcc->check_pow = check_pow_nocheck;
3770 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3771 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3772 PPC_CACHE | PPC_CACHE_ICBI |
3773 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3774 PPC_MEM_TLBSYNC | PPC_MFTB |
3775 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3776 PPC_440_SPEC;
3777 pcc->msr_mask = 0x000000000006FF30ULL;
3778 pcc->mmu_model = POWERPC_MMU_BOOKE;
3779 pcc->excp_model = POWERPC_EXCP_BOOKE;
3780 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3781 pcc->bfd_mach = bfd_mach_ppc_403;
3782 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3783 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3784 }
3785
3786 static void init_proc_460 (CPUPPCState *env)
3787 {
3788 /* Time base */
3789 gen_tbl(env);
3790 gen_spr_BookE(env, 0x000000000000FFFFULL);
3791 gen_spr_440(env);
3792 gen_spr_usprgh(env);
3793 /* Processor identification */
3794 spr_register(env, SPR_BOOKE_PIR, "PIR",
3795 SPR_NOACCESS, SPR_NOACCESS,
3796 &spr_read_generic, &spr_write_pir,
3797 0x00000000);
3798 /* XXX : not implemented */
3799 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3800 SPR_NOACCESS, SPR_NOACCESS,
3801 &spr_read_generic, &spr_write_generic,
3802 0x00000000);
3803 /* XXX : not implemented */
3804 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3805 SPR_NOACCESS, SPR_NOACCESS,
3806 &spr_read_generic, &spr_write_generic,
3807 0x00000000);
3808 /* XXX : not implemented */
3809 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3810 SPR_NOACCESS, SPR_NOACCESS,
3811 &spr_read_generic, &spr_write_generic,
3812 0x00000000);
3813 /* XXX : not implemented */
3814 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3815 SPR_NOACCESS, SPR_NOACCESS,
3816 &spr_read_generic, &spr_write_generic,
3817 0x00000000);
3818 /* XXX : not implemented */
3819 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3820 SPR_NOACCESS, SPR_NOACCESS,
3821 &spr_read_generic, &spr_write_generic,
3822 0x00000000);
3823 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3824 SPR_NOACCESS, SPR_NOACCESS,
3825 &spr_read_generic, &spr_write_generic,
3826 0x00000000);
3827 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3828 SPR_NOACCESS, SPR_NOACCESS,
3829 &spr_read_generic, &spr_write_generic,
3830 0x00000000);
3831 /* XXX : not implemented */
3832 spr_register(env, SPR_440_CCR1, "CCR1",
3833 SPR_NOACCESS, SPR_NOACCESS,
3834 &spr_read_generic, &spr_write_generic,
3835 0x00000000);
3836 /* XXX : not implemented */
3837 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3838 &spr_read_generic, &spr_write_generic,
3839 &spr_read_generic, &spr_write_generic,
3840 0x00000000);
3841 /* Memory management */
3842 #if !defined(CONFIG_USER_ONLY)
3843 env->nb_tlb = 64;
3844 env->nb_ways = 1;
3845 env->id_tlbs = 0;
3846 env->tlb_type = TLB_EMB;
3847 #endif
3848 init_excp_BookE(env);
3849 env->dcache_line_size = 32;
3850 env->icache_line_size = 32;
3851 /* XXX: TODO: allocate internal IRQ controller */
3852
3853 SET_FIT_PERIOD(12, 16, 20, 24);
3854 SET_WDT_PERIOD(20, 24, 28, 32);
3855 }
3856
3857 POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
3858 {
3859 DeviceClass *dc = DEVICE_CLASS(oc);
3860 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3861
3862 dc->desc = "PowerPC 460 (guessed)";
3863 pcc->init_proc = init_proc_460;
3864 pcc->check_pow = check_pow_nocheck;
3865 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3866 PPC_DCR | PPC_DCRX | PPC_DCRUX |
3867 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |
3868 PPC_CACHE | PPC_CACHE_ICBI |
3869 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3870 PPC_MEM_TLBSYNC | PPC_TLBIVA |
3871 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3872 PPC_440_SPEC;
3873 pcc->msr_mask = 0x000000000006FF30ULL;
3874 pcc->mmu_model = POWERPC_MMU_BOOKE;
3875 pcc->excp_model = POWERPC_EXCP_BOOKE;
3876 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3877 pcc->bfd_mach = bfd_mach_ppc_403;
3878 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3879 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3880 }
3881
3882 static void init_proc_460F (CPUPPCState *env)
3883 {
3884 /* Time base */
3885 gen_tbl(env);
3886 gen_spr_BookE(env, 0x000000000000FFFFULL);
3887 gen_spr_440(env);
3888 gen_spr_usprgh(env);
3889 /* Processor identification */
3890 spr_register(env, SPR_BOOKE_PIR, "PIR",
3891 SPR_NOACCESS, SPR_NOACCESS,
3892 &spr_read_generic, &spr_write_pir,
3893 0x00000000);
3894 /* XXX : not implemented */
3895 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3896 SPR_NOACCESS, SPR_NOACCESS,
3897 &spr_read_generic, &spr_write_generic,
3898 0x00000000);
3899 /* XXX : not implemented */
3900 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3901 SPR_NOACCESS, SPR_NOACCESS,
3902 &spr_read_generic, &spr_write_generic,
3903 0x00000000);
3904 /* XXX : not implemented */
3905 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3906 SPR_NOACCESS, SPR_NOACCESS,
3907 &spr_read_generic, &spr_write_generic,
3908 0x00000000);
3909 /* XXX : not implemented */
3910 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3911 SPR_NOACCESS, SPR_NOACCESS,
3912 &spr_read_generic, &spr_write_generic,
3913 0x00000000);
3914 /* XXX : not implemented */
3915 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3916 SPR_NOACCESS, SPR_NOACCESS,
3917 &spr_read_generic, &spr_write_generic,
3918 0x00000000);
3919 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3920 SPR_NOACCESS, SPR_NOACCESS,
3921 &spr_read_generic, &spr_write_generic,
3922 0x00000000);
3923 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3924 SPR_NOACCESS, SPR_NOACCESS,
3925 &spr_read_generic, &spr_write_generic,
3926 0x00000000);
3927 /* XXX : not implemented */
3928 spr_register(env, SPR_440_CCR1, "CCR1",
3929 SPR_NOACCESS, SPR_NOACCESS,
3930 &spr_read_generic, &spr_write_generic,
3931 0x00000000);
3932 /* XXX : not implemented */
3933 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3934 &spr_read_generic, &spr_write_generic,
3935 &spr_read_generic, &spr_write_generic,
3936 0x00000000);
3937 /* Memory management */
3938 #if !defined(CONFIG_USER_ONLY)
3939 env->nb_tlb = 64;
3940 env->nb_ways = 1;
3941 env->id_tlbs = 0;
3942 env->tlb_type = TLB_EMB;
3943 #endif
3944 init_excp_BookE(env);
3945 env->dcache_line_size = 32;
3946 env->icache_line_size = 32;
3947 /* XXX: TODO: allocate internal IRQ controller */
3948
3949 SET_FIT_PERIOD(12, 16, 20, 24);
3950 SET_WDT_PERIOD(20, 24, 28, 32);
3951 }
3952
3953 POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
3954 {
3955 DeviceClass *dc = DEVICE_CLASS(oc);
3956 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3957
3958 dc->desc = "PowerPC 460F (guessed)";
3959 pcc->init_proc = init_proc_460F;
3960 pcc->check_pow = check_pow_nocheck;
3961 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3962 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3963 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3964 PPC_FLOAT_STFIWX | PPC_MFTB |
3965 PPC_DCR | PPC_DCRX | PPC_DCRUX |
3966 PPC_WRTEE | PPC_MFAPIDI |
3967 PPC_CACHE | PPC_CACHE_ICBI |
3968 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3969 PPC_MEM_TLBSYNC | PPC_TLBIVA |
3970 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3971 PPC_440_SPEC;
3972 pcc->msr_mask = 0x000000000006FF30ULL;
3973 pcc->mmu_model = POWERPC_MMU_BOOKE;
3974 pcc->excp_model = POWERPC_EXCP_BOOKE;
3975 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3976 pcc->bfd_mach = bfd_mach_ppc_403;
3977 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3978 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3979 }
3980
3981 static void init_proc_MPC5xx (CPUPPCState *env)
3982 {
3983 /* Time base */
3984 gen_tbl(env);
3985 gen_spr_5xx_8xx(env);
3986 gen_spr_5xx(env);
3987 init_excp_MPC5xx(env);
3988 env->dcache_line_size = 32;
3989 env->icache_line_size = 32;
3990 /* XXX: TODO: allocate internal IRQ controller */
3991 }
3992
3993 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
3994 {
3995 DeviceClass *dc = DEVICE_CLASS(oc);
3996 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3997
3998 dc->desc = "Freescale 5xx cores (aka RCPU)";
3999 pcc->init_proc = init_proc_MPC5xx;
4000 pcc->check_pow = check_pow_none;
4001 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4002 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4003 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
4004 PPC_MFTB;
4005 pcc->msr_mask = 0x000000000001FF43ULL;
4006 pcc->mmu_model = POWERPC_MMU_REAL;
4007 pcc->excp_model = POWERPC_EXCP_603;
4008 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4009 pcc->bfd_mach = bfd_mach_ppc_505;
4010 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4011 POWERPC_FLAG_BUS_CLK;
4012 }
4013
4014 static void init_proc_MPC8xx (CPUPPCState *env)
4015 {
4016 /* Time base */
4017 gen_tbl(env);
4018 gen_spr_5xx_8xx(env);
4019 gen_spr_8xx(env);
4020 init_excp_MPC8xx(env);
4021 env->dcache_line_size = 32;
4022 env->icache_line_size = 32;
4023 /* XXX: TODO: allocate internal IRQ controller */
4024 }
4025
4026 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
4027 {
4028 DeviceClass *dc = DEVICE_CLASS(oc);
4029 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4030
4031 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
4032 pcc->init_proc = init_proc_MPC8xx;
4033 pcc->check_pow = check_pow_none;
4034 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4035 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4036 PPC_CACHE_ICBI | PPC_MFTB;
4037 pcc->msr_mask = 0x000000000001F673ULL;
4038 pcc->mmu_model = POWERPC_MMU_MPC8xx;
4039 pcc->excp_model = POWERPC_EXCP_603;
4040 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4041 pcc->bfd_mach = bfd_mach_ppc_860;
4042 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4043 POWERPC_FLAG_BUS_CLK;
4044 }
4045
4046 /* Freescale 82xx cores (aka PowerQUICC-II) */
4047
4048 static void init_proc_G2 (CPUPPCState *env)
4049 {
4050 gen_spr_ne_601(env);
4051 gen_spr_G2_755(env);
4052 gen_spr_G2(env);
4053 /* Time base */
4054 gen_tbl(env);
4055 /* External access control */
4056 /* XXX : not implemented */
4057 spr_register(env, SPR_EAR, "EAR",
4058 SPR_NOACCESS, SPR_NOACCESS,
4059 &spr_read_generic, &spr_write_generic,
4060 0x00000000);
4061 /* Hardware implementation register */
4062 /* XXX : not implemented */
4063 spr_register(env, SPR_HID0, "HID0",
4064 SPR_NOACCESS, SPR_NOACCESS,
4065 &spr_read_generic, &spr_write_generic,
4066 0x00000000);
4067 /* XXX : not implemented */
4068 spr_register(env, SPR_HID1, "HID1",
4069 SPR_NOACCESS, SPR_NOACCESS,
4070 &spr_read_generic, &spr_write_generic,
4071 0x00000000);
4072 /* XXX : not implemented */
4073 spr_register(env, SPR_HID2, "HID2",
4074 SPR_NOACCESS, SPR_NOACCESS,
4075 &spr_read_generic, &spr_write_generic,
4076 0x00000000);
4077 /* Memory management */
4078 gen_low_BATs(env);
4079 gen_high_BATs(env);
4080 gen_6xx_7xx_soft_tlb(env, 64, 2);
4081 init_excp_G2(env);
4082 env->dcache_line_size = 32;
4083 env->icache_line_size = 32;
4084 /* Allocate hardware IRQ controller */
4085 ppc6xx_irq_init(env);
4086 }
4087
4088 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
4089 {
4090 DeviceClass *dc = DEVICE_CLASS(oc);
4091 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4092
4093 dc->desc = "PowerPC G2";
4094 pcc->init_proc = init_proc_G2;
4095 pcc->check_pow = check_pow_hid0;
4096 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4097 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4098 PPC_FLOAT_STFIWX |
4099 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4100 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4101 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4102 PPC_SEGMENT | PPC_EXTERN;
4103 pcc->msr_mask = 0x000000000006FFF2ULL;
4104 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4105 pcc->excp_model = POWERPC_EXCP_G2;
4106 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4107 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4108 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4109 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4110 }
4111
4112 static void init_proc_G2LE (CPUPPCState *env)
4113 {
4114 gen_spr_ne_601(env);
4115 gen_spr_G2_755(env);
4116 gen_spr_G2(env);
4117 /* Time base */
4118 gen_tbl(env);
4119 /* External access control */
4120 /* XXX : not implemented */
4121 spr_register(env, SPR_EAR, "EAR",
4122 SPR_NOACCESS, SPR_NOACCESS,
4123 &spr_read_generic, &spr_write_generic,
4124 0x00000000);
4125 /* Hardware implementation register */
4126 /* XXX : not implemented */
4127 spr_register(env, SPR_HID0, "HID0",
4128 SPR_NOACCESS, SPR_NOACCESS,
4129 &spr_read_generic, &spr_write_generic,
4130 0x00000000);
4131 /* XXX : not implemented */
4132 spr_register(env, SPR_HID1, "HID1",
4133 SPR_NOACCESS, SPR_NOACCESS,
4134 &spr_read_generic, &spr_write_generic,
4135 0x00000000);
4136 /* XXX : not implemented */
4137 spr_register(env, SPR_HID2, "HID2",
4138 SPR_NOACCESS, SPR_NOACCESS,
4139 &spr_read_generic, &spr_write_generic,
4140 0x00000000);
4141 /* Breakpoints */
4142 /* XXX : not implemented */
4143 spr_register(env, SPR_DABR, "DABR",
4144 SPR_NOACCESS, SPR_NOACCESS,
4145 &spr_read_generic, &spr_write_generic,
4146 0x00000000);
4147 /* XXX : not implemented */
4148 spr_register(env, SPR_DABR2, "DABR2",
4149 SPR_NOACCESS, SPR_NOACCESS,
4150 &spr_read_generic, &spr_write_generic,
4151 0x00000000);
4152 /* XXX : not implemented */
4153 spr_register(env, SPR_IABR2, "IABR2",
4154 SPR_NOACCESS, SPR_NOACCESS,
4155 &spr_read_generic, &spr_write_generic,
4156 0x00000000);
4157 /* XXX : not implemented */
4158 spr_register(env, SPR_IBCR, "IBCR",
4159 SPR_NOACCESS, SPR_NOACCESS,
4160 &spr_read_generic, &spr_write_generic,
4161 0x00000000);
4162 /* XXX : not implemented */
4163 spr_register(env, SPR_DBCR, "DBCR",
4164 SPR_NOACCESS, SPR_NOACCESS,
4165 &spr_read_generic, &spr_write_generic,
4166 0x00000000);
4167
4168 /* Memory management */
4169 gen_low_BATs(env);
4170 gen_high_BATs(env);
4171 gen_6xx_7xx_soft_tlb(env, 64, 2);
4172 init_excp_G2(env);
4173 env->dcache_line_size = 32;
4174 env->icache_line_size = 32;
4175 /* Allocate hardware IRQ controller */
4176 ppc6xx_irq_init(env);
4177 }
4178
4179 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
4180 {
4181 DeviceClass *dc = DEVICE_CLASS(oc);
4182 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4183
4184 dc->desc = "PowerPC G2LE";
4185 pcc->init_proc = init_proc_G2LE;
4186 pcc->check_pow = check_pow_hid0;
4187 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4188 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4189 PPC_FLOAT_STFIWX |
4190 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4191 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4192 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4193 PPC_SEGMENT | PPC_EXTERN;
4194 pcc->msr_mask = 0x000000000007FFF3ULL;
4195 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4196 pcc->excp_model = POWERPC_EXCP_G2;
4197 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4198 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4199 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4200 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4201 }
4202
4203 static void init_proc_e200 (CPUPPCState *env)
4204 {
4205 /* Time base */
4206 gen_tbl(env);
4207 gen_spr_BookE(env, 0x000000070000FFFFULL);
4208 /* XXX : not implemented */
4209 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4210 &spr_read_spefscr, &spr_write_spefscr,
4211 &spr_read_spefscr, &spr_write_spefscr,
4212 0x00000000);
4213 /* Memory management */
4214 gen_spr_BookE206(env, 0x0000005D, NULL);
4215 /* XXX : not implemented */
4216 spr_register(env, SPR_HID0, "HID0",
4217 SPR_NOACCESS, SPR_NOACCESS,
4218 &spr_read_generic, &spr_write_generic,
4219 0x00000000);
4220 /* XXX : not implemented */
4221 spr_register(env, SPR_HID1, "HID1",
4222 SPR_NOACCESS, SPR_NOACCESS,
4223 &spr_read_generic, &spr_write_generic,
4224 0x00000000);
4225 /* XXX : not implemented */
4226 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4227 SPR_NOACCESS, SPR_NOACCESS,
4228 &spr_read_generic, &spr_write_generic,
4229 0x00000000);
4230 /* XXX : not implemented */
4231 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4232 SPR_NOACCESS, SPR_NOACCESS,
4233 &spr_read_generic, &spr_write_generic,
4234 0x00000000);
4235 /* XXX : not implemented */
4236 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4237 SPR_NOACCESS, SPR_NOACCESS,
4238 &spr_read_generic, &spr_write_generic,
4239 0x00000000);
4240 /* XXX : not implemented */
4241 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4242 SPR_NOACCESS, SPR_NOACCESS,
4243 &spr_read_generic, &spr_write_generic,
4244 0x00000000);
4245 /* XXX : not implemented */
4246 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4247 SPR_NOACCESS, SPR_NOACCESS,
4248 &spr_read_generic, &spr_write_generic,
4249 0x00000000);
4250 /* XXX : not implemented */
4251 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4252 SPR_NOACCESS, SPR_NOACCESS,
4253 &spr_read_generic, &spr_write_generic,
4254 0x00000000);
4255 /* XXX : not implemented */
4256 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4257 SPR_NOACCESS, SPR_NOACCESS,
4258 &spr_read_generic, &spr_write_generic,
4259 0x00000000);
4260 /* XXX : not implemented */
4261 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4262 SPR_NOACCESS, SPR_NOACCESS,
4263 &spr_read_generic, &spr_write_generic,
4264 0x00000000);
4265 /* XXX : not implemented */
4266 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4267 SPR_NOACCESS, SPR_NOACCESS,
4268 &spr_read_generic, &spr_write_generic,
4269 0x00000000);
4270 /* XXX : not implemented */
4271 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4272 SPR_NOACCESS, SPR_NOACCESS,
4273 &spr_read_generic, &spr_write_generic,
4274 0x00000000);
4275 /* XXX : not implemented */
4276 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4277 SPR_NOACCESS, SPR_NOACCESS,
4278 &spr_read_generic, &spr_write_generic,
4279 0x00000000);
4280 /* XXX : not implemented */
4281 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4282 SPR_NOACCESS, SPR_NOACCESS,
4283 &spr_read_generic, &spr_write_generic,
4284 0x00000000);
4285 /* XXX : not implemented */
4286 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4287 SPR_NOACCESS, SPR_NOACCESS,
4288 &spr_read_generic, &spr_write_generic,
4289 0x00000000); /* TOFIX */
4290 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4291 SPR_NOACCESS, SPR_NOACCESS,
4292 &spr_read_generic, &spr_write_generic,
4293 0x00000000);
4294 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4295 SPR_NOACCESS, SPR_NOACCESS,
4296 &spr_read_generic, &spr_write_generic,
4297 0x00000000);
4298 #if !defined(CONFIG_USER_ONLY)
4299 env->nb_tlb = 64;
4300 env->nb_ways = 1;
4301 env->id_tlbs = 0;
4302 env->tlb_type = TLB_EMB;
4303 #endif
4304 init_excp_e200(env, 0xFFFF0000UL);
4305 env->dcache_line_size = 32;
4306 env->icache_line_size = 32;
4307 /* XXX: TODO: allocate internal IRQ controller */
4308 }
4309
4310 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
4311 {
4312 DeviceClass *dc = DEVICE_CLASS(oc);
4313 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4314
4315 dc->desc = "e200 core";
4316 pcc->init_proc = init_proc_e200;
4317 pcc->check_pow = check_pow_hid0;
4318 /* XXX: unimplemented instructions:
4319 * dcblc
4320 * dcbtlst
4321 * dcbtstls
4322 * icblc
4323 * icbtls
4324 * tlbivax
4325 * all SPE multiply-accumulate instructions
4326 */
4327 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4328 PPC_SPE | PPC_SPE_SINGLE |
4329 PPC_WRTEE | PPC_RFDI |
4330 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4331 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4332 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
4333 PPC_BOOKE;
4334 pcc->msr_mask = 0x000000000606FF30ULL;
4335 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4336 pcc->excp_model = POWERPC_EXCP_BOOKE;
4337 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4338 pcc->bfd_mach = bfd_mach_ppc_860;
4339 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4340 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4341 POWERPC_FLAG_BUS_CLK;
4342 }
4343
4344 static void init_proc_e300 (CPUPPCState *env)
4345 {
4346 gen_spr_ne_601(env);
4347 gen_spr_603(env);
4348 /* Time base */
4349 gen_tbl(env);
4350 /* hardware implementation registers */
4351 /* XXX : not implemented */
4352 spr_register(env, SPR_HID0, "HID0",
4353 SPR_NOACCESS, SPR_NOACCESS,
4354 &spr_read_generic, &spr_write_generic,
4355 0x00000000);
4356 /* XXX : not implemented */
4357 spr_register(env, SPR_HID1, "HID1",
4358 SPR_NOACCESS, SPR_NOACCESS,
4359 &spr_read_generic, &spr_write_generic,
4360 0x00000000);
4361 /* XXX : not implemented */
4362 spr_register(env, SPR_HID2, "HID2",
4363 SPR_NOACCESS, SPR_NOACCESS,
4364 &spr_read_generic, &spr_write_generic,
4365 0x00000000);
4366 /* Memory management */
4367 gen_low_BATs(env);
4368 gen_high_BATs(env);
4369 gen_6xx_7xx_soft_tlb(env, 64, 2);
4370 init_excp_603(env);
4371 env->dcache_line_size = 32;
4372 env->icache_line_size = 32;
4373 /* Allocate hardware IRQ controller */
4374 ppc6xx_irq_init(env);
4375 }
4376
4377 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4378 {
4379 DeviceClass *dc = DEVICE_CLASS(oc);
4380 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4381
4382 dc->desc = "e300 core";
4383 pcc->init_proc = init_proc_e300;
4384 pcc->check_pow = check_pow_hid0;
4385 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4386 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4387 PPC_FLOAT_STFIWX |
4388 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4389 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4390 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4391 PPC_SEGMENT | PPC_EXTERN;
4392 pcc->msr_mask = 0x000000000007FFF3ULL;
4393 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4394 pcc->excp_model = POWERPC_EXCP_603;
4395 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4396 pcc->bfd_mach = bfd_mach_ppc_603;
4397 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4398 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4399 }
4400
4401 #if !defined(CONFIG_USER_ONLY)
4402 static void spr_write_mas73(void *opaque, int sprn, int gprn)
4403 {
4404 TCGv val = tcg_temp_new();
4405 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4406 gen_store_spr(SPR_BOOKE_MAS3, val);
4407 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
4408 gen_store_spr(SPR_BOOKE_MAS7, val);
4409 tcg_temp_free(val);
4410 }
4411
4412 static void spr_read_mas73(void *opaque, int gprn, int sprn)
4413 {
4414 TCGv mas7 = tcg_temp_new();
4415 TCGv mas3 = tcg_temp_new();
4416 gen_load_spr(mas7, SPR_BOOKE_MAS7);
4417 tcg_gen_shli_tl(mas7, mas7, 32);
4418 gen_load_spr(mas3, SPR_BOOKE_MAS3);
4419 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4420 tcg_temp_free(mas3);
4421 tcg_temp_free(mas7);
4422 }
4423
4424 #endif
4425
4426 enum fsl_e500_version {
4427 fsl_e500v1,
4428 fsl_e500v2,
4429 fsl_e500mc,
4430 fsl_e5500,
4431 };
4432
4433 static void init_proc_e500 (CPUPPCState *env, int version)
4434 {
4435 PowerPCCPU *cpu = ppc_env_get_cpu(env);
4436 uint32_t tlbncfg[2];
4437 uint64_t ivor_mask;
4438 uint64_t ivpr_mask = 0xFFFF0000ULL;
4439 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4440 | 0x0020; /* 32 kb */
4441 #if !defined(CONFIG_USER_ONLY)
4442 int i;
4443 #endif
4444
4445 /* Time base */
4446 gen_tbl(env);
4447 /*
4448 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4449 * complain when accessing them.
4450 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4451 */
4452 switch (version) {
4453 case fsl_e500v1:
4454 case fsl_e500v2:
4455 default:
4456 ivor_mask = 0x0000000F0000FFFFULL;
4457 break;
4458 case fsl_e500mc:
4459 case fsl_e5500:
4460 ivor_mask = 0x000003FE0000FFFFULL;
4461 break;
4462 }
4463 gen_spr_BookE(env, ivor_mask);
4464 /* Processor identification */
4465 spr_register(env, SPR_BOOKE_PIR, "PIR",
4466 SPR_NOACCESS, SPR_NOACCESS,
4467 &spr_read_generic, &spr_write_pir,
4468 0x00000000);
4469 /* XXX : not implemented */
4470 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4471 &spr_read_spefscr, &spr_write_spefscr,
4472 &spr_read_spefscr, &spr_write_spefscr,
4473 0x00000000);
4474 #if !defined(CONFIG_USER_ONLY)
4475 /* Memory management */
4476 env->nb_pids = 3;
4477 env->nb_ways = 2;
4478 env->id_tlbs = 0;
4479 switch (version) {
4480 case fsl_e500v1:
4481 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4482 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4483 break;
4484 case fsl_e500v2:
4485 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4486 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4487 break;
4488 case fsl_e500mc:
4489 case fsl_e5500:
4490 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4491 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4492 break;
4493 default:
4494 cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4495 }
4496 #endif
4497 /* Cache sizes */
4498 switch (version) {
4499 case fsl_e500v1:
4500 case fsl_e500v2:
4501 env->dcache_line_size = 32;
4502 env->icache_line_size = 32;
4503 break;
4504 case fsl_e500mc:
4505 case fsl_e5500:
4506 env->dcache_line_size = 64;
4507 env->icache_line_size = 64;
4508 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4509 break;
4510 default:
4511 cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4512 }
4513 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
4514 /* XXX : not implemented */
4515 spr_register(env, SPR_HID0, "HID0",
4516 SPR_NOACCESS, SPR_NOACCESS,
4517 &spr_read_generic, &spr_write_generic,
4518 0x00000000);
4519 /* XXX : not implemented */
4520 spr_register(env, SPR_HID1, "HID1",
4521 SPR_NOACCESS, SPR_NOACCESS,
4522 &spr_read_generic, &spr_write_generic,
4523 0x00000000);
4524 /* XXX : not implemented */
4525 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4526 SPR_NOACCESS, SPR_NOACCESS,
4527 &spr_read_generic, &spr_write_generic,
4528 0x00000000);
4529 /* XXX : not implemented */
4530 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4531 SPR_NOACCESS, SPR_NOACCESS,
4532 &spr_read_generic, &spr_write_generic,
4533 0x00000000);
4534 /* XXX : not implemented */
4535 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4536 SPR_NOACCESS, SPR_NOACCESS,
4537 &spr_read_generic, &spr_write_generic,
4538 0x00000000);
4539 /* XXX : not implemented */
4540 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4541 SPR_NOACCESS, SPR_NOACCESS,
4542 &spr_read_generic, &spr_write_generic,
4543 0x00000000);
4544 /* XXX : not implemented */
4545 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4546 SPR_NOACCESS, SPR_NOACCESS,
4547 &spr_read_generic, &spr_write_generic,
4548 0x00000000);
4549 /* XXX : not implemented */
4550 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4551 SPR_NOACCESS, SPR_NOACCESS,
4552 &spr_read_generic, &spr_write_generic,
4553 0x00000000);
4554 /* XXX : not implemented */
4555 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4556 SPR_NOACCESS, SPR_NOACCESS,
4557 &spr_read_generic, &spr_write_generic,
4558 l1cfg0);
4559 /* XXX : not implemented */
4560 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4561 SPR_NOACCESS, SPR_NOACCESS,
4562 &spr_read_generic, &spr_write_e500_l1csr0,
4563 0x00000000);
4564 /* XXX : not implemented */
4565 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4566 SPR_NOACCESS, SPR_NOACCESS,
4567 &spr_read_generic, &spr_write_generic,
4568 0x00000000);
4569 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4570 SPR_NOACCESS, SPR_NOACCESS,
4571 &spr_read_generic, &spr_write_generic,
4572 0x00000000);
4573 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4574 SPR_NOACCESS, SPR_NOACCESS,
4575 &spr_read_generic, &spr_write_generic,
4576 0x00000000);
4577 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4578 SPR_NOACCESS, SPR_NOACCESS,
4579 &spr_read_generic, &spr_write_booke206_mmucsr0,
4580 0x00000000);
4581 spr_register(env, SPR_BOOKE_EPR, "EPR",
4582 SPR_NOACCESS, SPR_NOACCESS,
4583 &spr_read_generic, SPR_NOACCESS,
4584 0x00000000);
4585 /* XXX better abstract into Emb.xxx features */
4586 if (version == fsl_e5500) {
4587 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4588 SPR_NOACCESS, SPR_NOACCESS,
4589 &spr_read_generic, &spr_write_generic,
4590 0x00000000);
4591 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4592 SPR_NOACCESS, SPR_NOACCESS,
4593 &spr_read_mas73, &spr_write_mas73,
4594 0x00000000);
4595 ivpr_mask = (target_ulong)~0xFFFFULL;
4596 }
4597
4598 #if !defined(CONFIG_USER_ONLY)
4599 env->nb_tlb = 0;
4600 env->tlb_type = TLB_MAS;
4601 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4602 env->nb_tlb += booke206_tlb_size(env, i);
4603 }
4604 #endif
4605
4606 init_excp_e200(env, ivpr_mask);
4607 /* Allocate hardware IRQ controller */
4608 ppce500_irq_init(env);
4609 }
4610
4611 static void init_proc_e500v1(CPUPPCState *env)
4612 {
4613 init_proc_e500(env, fsl_e500v1);
4614 }
4615
4616 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
4617 {
4618 DeviceClass *dc = DEVICE_CLASS(oc);
4619 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4620
4621 dc->desc = "e500v1 core";
4622 pcc->init_proc = init_proc_e500v1;
4623 pcc->check_pow = check_pow_hid0;
4624 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4625 PPC_SPE | PPC_SPE_SINGLE |
4626 PPC_WRTEE | PPC_RFDI |
4627 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4628 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4629 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4630 pcc->insns_flags2 = PPC2_BOOKE206;
4631 pcc->msr_mask = 0x000000000606FF30ULL;
4632 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4633 pcc->excp_model = POWERPC_EXCP_BOOKE;
4634 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4635 pcc->bfd_mach = bfd_mach_ppc_860;
4636 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4637 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4638 POWERPC_FLAG_BUS_CLK;
4639 }
4640
4641 static void init_proc_e500v2(CPUPPCState *env)
4642 {
4643 init_proc_e500(env, fsl_e500v2);
4644 }
4645
4646 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
4647 {
4648 DeviceClass *dc = DEVICE_CLASS(oc);
4649 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4650
4651 dc->desc = "e500v2 core";
4652 pcc->init_proc = init_proc_e500v2;
4653 pcc->check_pow = check_pow_hid0;
4654 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4655 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
4656 PPC_WRTEE | PPC_RFDI |
4657 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4658 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4659 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4660 pcc->insns_flags2 = PPC2_BOOKE206;
4661 pcc->msr_mask = 0x000000000606FF30ULL;
4662 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4663 pcc->excp_model = POWERPC_EXCP_BOOKE;
4664 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4665 pcc->bfd_mach = bfd_mach_ppc_860;
4666 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4667 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4668 POWERPC_FLAG_BUS_CLK;
4669 }
4670
4671 static void init_proc_e500mc(CPUPPCState *env)
4672 {
4673 init_proc_e500(env, fsl_e500mc);
4674 }
4675
4676 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
4677 {
4678 DeviceClass *dc = DEVICE_CLASS(oc);
4679 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4680
4681 dc->desc = "e500mc core";
4682 pcc->init_proc = init_proc_e500mc;
4683 pcc->check_pow = check_pow_none;
4684 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4685 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4686 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4687 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4688 PPC_FLOAT | PPC_FLOAT_FRES |
4689 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4690 PPC_FLOAT_STFIWX | PPC_WAIT |
4691 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4692 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
4693 pcc->msr_mask = 0x000000001402FB36ULL;
4694 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4695 pcc->excp_model = POWERPC_EXCP_BOOKE;
4696 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4697 /* FIXME: figure out the correct flag for e500mc */
4698 pcc->bfd_mach = bfd_mach_ppc_e500;
4699 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4700 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4701 }
4702
4703 #ifdef TARGET_PPC64
4704 static void init_proc_e5500(CPUPPCState *env)
4705 {
4706 init_proc_e500(env, fsl_e5500);
4707 }
4708
4709 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
4710 {
4711 DeviceClass *dc = DEVICE_CLASS(oc);
4712 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4713
4714 dc->desc = "e5500 core";
4715 pcc->init_proc = init_proc_e5500;
4716 pcc->check_pow = check_pow_none;
4717 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4718 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4719 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4720 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4721 PPC_FLOAT | PPC_FLOAT_FRES |
4722 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4723 PPC_FLOAT_STFIWX | PPC_WAIT |
4724 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
4725 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
4726 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206;
4727 pcc->msr_mask = 0x000000009402FB36ULL;
4728 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4729 pcc->excp_model = POWERPC_EXCP_BOOKE;
4730 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4731 /* FIXME: figure out the correct flag for e5500 */
4732 pcc->bfd_mach = bfd_mach_ppc_e500;
4733 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4734 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4735 }
4736 #endif
4737
4738 /* Non-embedded PowerPC */
4739
4740 /* POWER : same as 601, without mfmsr, mfsr */
4741 POWERPC_FAMILY(POWER)(ObjectClass *oc, void *data)
4742 {
4743 DeviceClass *dc = DEVICE_CLASS(oc);
4744 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4745
4746 dc->desc = "POWER";
4747 /* pcc->insns_flags = XXX_TODO; */
4748 /* POWER RSC (from RAD6000) */
4749 pcc->msr_mask = 0x00000000FEF0ULL;
4750 }
4751
4752 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
4753
4754 static void init_proc_601 (CPUPPCState *env)
4755 {
4756 gen_spr_ne_601(env);
4757 gen_spr_601(env);
4758 /* Hardware implementation registers */
4759 /* XXX : not implemented */
4760 spr_register(env, SPR_HID0, "HID0",
4761 SPR_NOACCESS, SPR_NOACCESS,
4762 &spr_read_generic, &spr_write_hid0_601,
4763 0x80010080);
4764 /* XXX : not implemented */
4765 spr_register(env, SPR_HID1, "HID1",
4766 SPR_NOACCESS, SPR_NOACCESS,
4767 &spr_read_generic, &spr_write_generic,
4768 0x00000000);
4769 /* XXX : not implemented */
4770 spr_register(env, SPR_601_HID2, "HID2",
4771 SPR_NOACCESS, SPR_NOACCESS,
4772 &spr_read_generic, &spr_write_generic,
4773 0x00000000);
4774 /* XXX : not implemented */
4775 spr_register(env, SPR_601_HID5, "HID5",
4776 SPR_NOACCESS, SPR_NOACCESS,
4777 &spr_read_generic, &spr_write_generic,
4778 0x00000000);
4779 /* Memory management */
4780 init_excp_601(env);
4781 /* XXX: beware that dcache line size is 64
4782 * but dcbz uses 32 bytes "sectors"
4783 * XXX: this breaks clcs instruction !
4784 */
4785 env->dcache_line_size = 32;
4786 env->icache_line_size = 64;
4787 /* Allocate hardware IRQ controller */
4788 ppc6xx_irq_init(env);
4789 }
4790
4791 POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
4792 {
4793 DeviceClass *dc = DEVICE_CLASS(oc);
4794 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4795
4796 dc->desc = "PowerPC 601";
4797 pcc->init_proc = init_proc_601;
4798 pcc->check_pow = check_pow_none;
4799 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4800 PPC_FLOAT |
4801 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4802 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4803 PPC_SEGMENT | PPC_EXTERN;
4804 pcc->msr_mask = 0x000000000000FD70ULL;
4805 pcc->mmu_model = POWERPC_MMU_601;
4806 #if defined(CONFIG_SOFTMMU)
4807 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
4808 #endif
4809 pcc->excp_model = POWERPC_EXCP_601;
4810 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4811 pcc->bfd_mach = bfd_mach_ppc_601;
4812 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
4813 }
4814
4815 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
4816
4817 static void init_proc_601v (CPUPPCState *env)
4818 {
4819 init_proc_601(env);
4820 /* XXX : not implemented */
4821 spr_register(env, SPR_601_HID15, "HID15",
4822 SPR_NOACCESS, SPR_NOACCESS,
4823 &spr_read_generic, &spr_write_generic,
4824 0x00000000);
4825 }
4826
4827 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
4828 {
4829 DeviceClass *dc = DEVICE_CLASS(oc);
4830 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4831
4832 dc->desc = "PowerPC 601v";
4833 pcc->init_proc = init_proc_601v;
4834 pcc->check_pow = check_pow_none;
4835 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
4836 PPC_FLOAT |
4837 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4838 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
4839 PPC_SEGMENT | PPC_EXTERN;
4840 pcc->msr_mask = 0x000000000000FD70ULL;
4841 pcc->mmu_model = POWERPC_MMU_601;
4842 #if defined(CONFIG_SOFTMMU)
4843 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
4844 #endif
4845 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4846 pcc->bfd_mach = bfd_mach_ppc_601;
4847 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
4848 }
4849
4850 static void init_proc_602 (CPUPPCState *env)
4851 {
4852 gen_spr_ne_601(env);
4853 gen_spr_602(env);
4854 /* Time base */
4855 gen_tbl(env);
4856 /* hardware implementation registers */
4857 /* XXX : not implemented */
4858 spr_register(env, SPR_HID0, "HID0",
4859 SPR_NOACCESS, SPR_NOACCESS,
4860 &spr_read_generic, &spr_write_generic,
4861 0x00000000);
4862 /* XXX : not implemented */
4863 spr_register(env, SPR_HID1, "HID1",
4864 SPR_NOACCESS, SPR_NOACCESS,
4865 &spr_read_generic, &spr_write_generic,
4866 0x00000000);
4867 /* Memory management */
4868 gen_low_BATs(env);
4869 gen_6xx_7xx_soft_tlb(env, 64, 2);
4870 init_excp_602(env);
4871 env->dcache_line_size = 32;
4872 env->icache_line_size = 32;
4873 /* Allocate hardware IRQ controller */
4874 ppc6xx_irq_init(env);
4875 }
4876
4877 POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
4878 {
4879 DeviceClass *dc = DEVICE_CLASS(oc);
4880 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4881
4882 dc->desc = "PowerPC 602";
4883 pcc->init_proc = init_proc_602;
4884 pcc->check_pow = check_pow_hid0;
4885 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4886 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4887 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4888 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4889 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4890 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
4891 PPC_SEGMENT | PPC_602_SPEC;
4892 pcc->msr_mask = 0x0000000000C7FF73ULL;
4893 /* XXX: 602 MMU is quite specific. Should add a special case */
4894 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4895 pcc->excp_model = POWERPC_EXCP_602;
4896 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4897 pcc->bfd_mach = bfd_mach_ppc_602;
4898 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4899 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4900 }
4901
4902 static void init_proc_603 (CPUPPCState *env)
4903 {
4904 gen_spr_ne_601(env);
4905 gen_spr_603(env);
4906 /* Time base */
4907 gen_tbl(env);
4908 /* hardware implementation registers */
4909 /* XXX : not implemented */
4910 spr_register(env, SPR_HID0, "HID0",
4911 SPR_NOACCESS, SPR_NOACCESS,
4912 &spr_read_generic, &spr_write_generic,
4913 0x00000000);
4914 /* XXX : not implemented */
4915 spr_register(env, SPR_HID1, "HID1",
4916 SPR_NOACCESS, SPR_NOACCESS,
4917 &spr_read_generic, &spr_write_generic,
4918 0x00000000);
4919 /* Memory management */
4920 gen_low_BATs(env);
4921 gen_6xx_7xx_soft_tlb(env, 64, 2);
4922 init_excp_603(env);
4923 env->dcache_line_size = 32;
4924 env->icache_line_size = 32;
4925 /* Allocate hardware IRQ controller */
4926 ppc6xx_irq_init(env);
4927 }
4928
4929 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
4930 {
4931 DeviceClass *dc = DEVICE_CLASS(oc);
4932 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4933
4934 dc->desc = "PowerPC 603";
4935 pcc->init_proc = init_proc_603;
4936 pcc->check_pow = check_pow_hid0;
4937 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4938 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4939 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4940 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4941 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4942 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4943 PPC_SEGMENT | PPC_EXTERN;
4944 pcc->msr_mask = 0x000000000007FF73ULL;
4945 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4946 pcc->excp_model = POWERPC_EXCP_603;
4947 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4948 pcc->bfd_mach = bfd_mach_ppc_603;
4949 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4950 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4951 }
4952
4953 static void init_proc_603E (CPUPPCState *env)
4954 {
4955 gen_spr_ne_601(env);
4956 gen_spr_603(env);
4957 /* Time base */
4958 gen_tbl(env);
4959 /* hardware implementation registers */
4960 /* XXX : not implemented */
4961 spr_register(env, SPR_HID0, "HID0",
4962 SPR_NOACCESS, SPR_NOACCESS,
4963 &spr_read_generic, &spr_write_generic,
4964 0x00000000);
4965 /* XXX : not implemented */
4966 spr_register(env, SPR_HID1, "HID1",
4967 SPR_NOACCESS, SPR_NOACCESS,
4968 &spr_read_generic, &spr_write_generic,
4969 0x00000000);
4970 /* Memory management */
4971 gen_low_BATs(env);
4972 gen_6xx_7xx_soft_tlb(env, 64, 2);
4973 init_excp_603(env);
4974 env->dcache_line_size = 32;
4975 env->icache_line_size = 32;
4976 /* Allocate hardware IRQ controller */
4977 ppc6xx_irq_init(env);
4978 }
4979
4980 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
4981 {
4982 DeviceClass *dc = DEVICE_CLASS(oc);
4983 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4984
4985 dc->desc = "PowerPC 603e";
4986 pcc->init_proc = init_proc_603E;
4987 pcc->check_pow = check_pow_hid0;
4988 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4989 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4990 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
4991 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4992 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4993 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4994 PPC_SEGMENT | PPC_EXTERN;
4995 pcc->msr_mask = 0x000000000007FF73ULL;
4996 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4997 pcc->excp_model = POWERPC_EXCP_603E;
4998 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4999 pcc->bfd_mach = bfd_mach_ppc_ec603e;
5000 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5001 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5002 }
5003
5004 static void init_proc_604 (CPUPPCState *env)
5005 {
5006 gen_spr_ne_601(env);
5007 gen_spr_604(env);
5008 /* Time base */
5009 gen_tbl(env);
5010 /* Hardware implementation registers */
5011 /* XXX : not implemented */
5012 spr_register(env, SPR_HID0, "HID0",
5013 SPR_NOACCESS, SPR_NOACCESS,
5014 &spr_read_generic, &spr_write_generic,
5015 0x00000000);
5016 /* Memory management */
5017 gen_low_BATs(env);
5018 init_excp_604(env);
5019 env->dcache_line_size = 32;
5020 env->icache_line_size = 32;
5021 /* Allocate hardware IRQ controller */
5022 ppc6xx_irq_init(env);
5023 }
5024
5025 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
5026 {
5027 DeviceClass *dc = DEVICE_CLASS(oc);
5028 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5029
5030 dc->desc = "PowerPC 604";
5031 pcc->init_proc = init_proc_604;
5032 pcc->check_pow = check_pow_nocheck;
5033 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5034 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5035 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5036 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5037 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5038 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5039 PPC_SEGMENT | PPC_EXTERN;
5040 pcc->msr_mask = 0x000000000005FF77ULL;
5041 pcc->mmu_model = POWERPC_MMU_32B;
5042 #if defined(CONFIG_SOFTMMU)
5043 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5044 #endif
5045 pcc->excp_model = POWERPC_EXCP_604;
5046 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5047 pcc->bfd_mach = bfd_mach_ppc_604;
5048 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5049 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5050 }
5051
5052 static void init_proc_604E (CPUPPCState *env)
5053 {
5054 gen_spr_ne_601(env);
5055 gen_spr_604(env);
5056 /* XXX : not implemented */
5057 spr_register(env, SPR_MMCR1, "MMCR1",
5058 SPR_NOACCESS, SPR_NOACCESS,
5059 &spr_read_generic, &spr_write_generic,
5060 0x00000000);
5061 /* XXX : not implemented */
5062 spr_register(env, SPR_PMC3, "PMC3",
5063 SPR_NOACCESS, SPR_NOACCESS,
5064 &spr_read_generic, &spr_write_generic,
5065 0x00000000);
5066 /* XXX : not implemented */
5067 spr_register(env, SPR_PMC4, "PMC4",
5068 SPR_NOACCESS, SPR_NOACCESS,
5069 &spr_read_generic, &spr_write_generic,
5070 0x00000000);
5071 /* Time base */
5072 gen_tbl(env);
5073 /* Hardware implementation registers */
5074 /* XXX : not implemented */
5075 spr_register(env, SPR_HID0, "HID0",
5076 SPR_NOACCESS, SPR_NOACCESS,
5077 &spr_read_generic, &spr_write_generic,
5078 0x00000000);
5079 /* XXX : not implemented */
5080 spr_register(env, SPR_HID1, "HID1",
5081 SPR_NOACCESS, SPR_NOACCESS,
5082 &spr_read_generic, &spr_write_generic,
5083 0x00000000);
5084 /* Memory management */
5085 gen_low_BATs(env);
5086 init_excp_604(env);
5087 env->dcache_line_size = 32;
5088 env->icache_line_size = 32;
5089 /* Allocate hardware IRQ controller */
5090 ppc6xx_irq_init(env);
5091 }
5092
5093 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
5094 {
5095 DeviceClass *dc = DEVICE_CLASS(oc);
5096 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5097
5098 dc->desc = "PowerPC 604E";
5099 pcc->init_proc = init_proc_604E;
5100 pcc->check_pow = check_pow_nocheck;
5101 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5102 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5103 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5104 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5105 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5106 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5107 PPC_SEGMENT | PPC_EXTERN;
5108 pcc->msr_mask = 0x000000000005FF77ULL;
5109 pcc->mmu_model = POWERPC_MMU_32B;
5110 #if defined(CONFIG_SOFTMMU)
5111 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5112 #endif
5113 pcc->excp_model = POWERPC_EXCP_604;
5114 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5115 pcc->bfd_mach = bfd_mach_ppc_604;
5116 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5117 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5118 }
5119
5120 static void init_proc_740 (CPUPPCState *env)
5121 {
5122 gen_spr_ne_601(env);
5123 gen_spr_7xx(env);
5124 /* Time base */
5125 gen_tbl(env);
5126 /* Thermal management */
5127 gen_spr_thrm(env);
5128 /* Hardware implementation registers */
5129 /* XXX : not implemented */
5130 spr_register(env, SPR_HID0, "HID0",
5131 SPR_NOACCESS, SPR_NOACCESS,
5132 &spr_read_generic, &spr_write_generic,
5133 0x00000000);
5134 /* XXX : not implemented */
5135 spr_register(env, SPR_HID1, "HID1",
5136 SPR_NOACCESS, SPR_NOACCESS,
5137 &spr_read_generic, &spr_write_generic,
5138 0x00000000);
5139 /* Memory management */
5140 gen_low_BATs(env);
5141 init_excp_7x0(env);
5142 env->dcache_line_size = 32;
5143 env->icache_line_size = 32;
5144 /* Allocate hardware IRQ controller */
5145 ppc6xx_irq_init(env);
5146 }
5147
5148 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
5149 {
5150 DeviceClass *dc = DEVICE_CLASS(oc);
5151 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5152
5153 dc->desc = "PowerPC 740";
5154 pcc->init_proc = init_proc_740;
5155 pcc->check_pow = check_pow_hid0;
5156 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5157 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5158 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5159 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5160 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5161 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5162 PPC_SEGMENT | PPC_EXTERN;
5163 pcc->msr_mask = 0x000000000005FF77ULL;
5164 pcc->mmu_model = POWERPC_MMU_32B;
5165 #if defined(CONFIG_SOFTMMU)
5166 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5167 #endif
5168 pcc->excp_model = POWERPC_EXCP_7x0;
5169 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5170 pcc->bfd_mach = bfd_mach_ppc_750;
5171 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5172 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5173 }
5174
5175 static void init_proc_750 (CPUPPCState *env)
5176 {
5177 gen_spr_ne_601(env);
5178 gen_spr_7xx(env);
5179 /* XXX : not implemented */
5180 spr_register(env, SPR_L2CR, "L2CR",
5181 SPR_NOACCESS, SPR_NOACCESS,
5182 &spr_read_generic, spr_access_nop,
5183 0x00000000);
5184 /* Time base */
5185 gen_tbl(env);
5186 /* Thermal management */
5187 gen_spr_thrm(env);
5188 /* Hardware implementation registers */
5189 /* XXX : not implemented */
5190 spr_register(env, SPR_HID0, "HID0",
5191 SPR_NOACCESS, SPR_NOACCESS,
5192 &spr_read_generic, &spr_write_generic,
5193 0x00000000);
5194 /* XXX : not implemented */
5195 spr_register(env, SPR_HID1, "HID1",
5196 SPR_NOACCESS, SPR_NOACCESS,
5197 &spr_read_generic, &spr_write_generic,
5198 0x00000000);
5199 /* Memory management */
5200 gen_low_BATs(env);
5201 /* XXX: high BATs are also present but are known to be bugged on
5202 * die version 1.x
5203 */
5204 init_excp_7x0(env);
5205 env->dcache_line_size = 32;
5206 env->icache_line_size = 32;
5207 /* Allocate hardware IRQ controller */
5208 ppc6xx_irq_init(env);
5209 }
5210
5211 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
5212 {
5213 DeviceClass *dc = DEVICE_CLASS(oc);
5214 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5215
5216 dc->desc = "PowerPC 750";
5217 pcc->init_proc = init_proc_750;
5218 pcc->check_pow = check_pow_hid0;
5219 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5220 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5221 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5222 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5223 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5224 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5225 PPC_SEGMENT | PPC_EXTERN;
5226 pcc->msr_mask = 0x000000000005FF77ULL;
5227 pcc->mmu_model = POWERPC_MMU_32B;
5228 #if defined(CONFIG_SOFTMMU)
5229 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5230 #endif
5231 pcc->excp_model = POWERPC_EXCP_7x0;
5232 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5233 pcc->bfd_mach = bfd_mach_ppc_750;
5234 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5235 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5236 }
5237
5238 static void init_proc_750cl (CPUPPCState *env)
5239 {
5240 gen_spr_ne_601(env);
5241 gen_spr_7xx(env);
5242 /* XXX : not implemented */
5243 spr_register(env, SPR_L2CR, "L2CR",
5244 SPR_NOACCESS, SPR_NOACCESS,
5245 &spr_read_generic, spr_access_nop,
5246 0x00000000);
5247 /* Time base */
5248 gen_tbl(env);
5249 /* Thermal management */
5250 /* Those registers are fake on 750CL */
5251 spr_register(env, SPR_THRM1, "THRM1",
5252 SPR_NOACCESS, SPR_NOACCESS,
5253 &spr_read_generic, &spr_write_generic,
5254 0x00000000);
5255 spr_register(env, SPR_THRM2, "THRM2",
5256 SPR_NOACCESS, SPR_NOACCESS,
5257 &spr_read_generic, &spr_write_generic,
5258 0x00000000);
5259 spr_register(env, SPR_THRM3, "THRM3",
5260 SPR_NOACCESS, SPR_NOACCESS,
5261 &spr_read_generic, &spr_write_generic,
5262 0x00000000);
5263 /* XXX: not implemented */
5264 spr_register(env, SPR_750_TDCL, "TDCL",
5265 SPR_NOACCESS, SPR_NOACCESS,
5266 &spr_read_generic, &spr_write_generic,
5267 0x00000000);
5268 spr_register(env, SPR_750_TDCH, "TDCH",
5269 SPR_NOACCESS, SPR_NOACCESS,
5270 &spr_read_generic, &spr_write_generic,
5271 0x00000000);
5272 /* DMA */
5273 /* XXX : not implemented */
5274 spr_register(env, SPR_750_WPAR, "WPAR",
5275 SPR_NOACCESS, SPR_NOACCESS,
5276 &spr_read_generic, &spr_write_generic,
5277 0x00000000);
5278 spr_register(env, SPR_750_DMAL, "DMAL",
5279 SPR_NOACCESS, SPR_NOACCESS,
5280 &spr_read_generic, &spr_write_generic,
5281 0x00000000);
5282 spr_register(env, SPR_750_DMAU, "DMAU",
5283 SPR_NOACCESS, SPR_NOACCESS,
5284 &spr_read_generic, &spr_write_generic,
5285 0x00000000);
5286 /* Hardware implementation registers */
5287 /* XXX : not implemented */
5288 spr_register(env, SPR_HID0, "HID0",
5289 SPR_NOACCESS, SPR_NOACCESS,
5290 &spr_read_generic, &spr_write_generic,
5291 0x00000000);
5292 /* XXX : not implemented */
5293 spr_register(env, SPR_HID1, "HID1",
5294 SPR_NOACCESS, SPR_NOACCESS,
5295 &spr_read_generic, &spr_write_generic,
5296 0x00000000);
5297 /* XXX : not implemented */
5298 spr_register(env, SPR_750CL_HID2, "HID2",
5299 SPR_NOACCESS, SPR_NOACCESS,
5300 &spr_read_generic, &spr_write_generic,
5301 0x00000000);
5302 /* XXX : not implemented */
5303 spr_register(env, SPR_750CL_HID4, "HID4",
5304 SPR_NOACCESS, SPR_NOACCESS,
5305 &spr_read_generic, &spr_write_generic,
5306 0x00000000);
5307 /* Quantization registers */
5308 /* XXX : not implemented */
5309 spr_register(env, SPR_750_GQR0, "GQR0",
5310 SPR_NOACCESS, SPR_NOACCESS,
5311 &spr_read_generic, &spr_write_generic,
5312 0x00000000);
5313 /* XXX : not implemented */
5314 spr_register(env, SPR_750_GQR1, "GQR1",
5315 SPR_NOACCESS, SPR_NOACCESS,
5316 &spr_read_generic, &spr_write_generic,
5317 0x00000000);
5318 /* XXX : not implemented */
5319 spr_register(env, SPR_750_GQR2, "GQR2",
5320 SPR_NOACCESS, SPR_NOACCESS,
5321 &spr_read_generic, &spr_write_generic,
5322 0x00000000);
5323 /* XXX : not implemented */
5324 spr_register(env, SPR_750_GQR3, "GQR3",
5325 SPR_NOACCESS, SPR_NOACCESS,
5326 &spr_read_generic, &spr_write_generic,
5327 0x00000000);
5328 /* XXX : not implemented */
5329 spr_register(env, SPR_750_GQR4, "GQR4",
5330 SPR_NOACCESS, SPR_NOACCESS,
5331 &spr_read_generic, &spr_write_generic,
5332 0x00000000);
5333 /* XXX : not implemented */
5334 spr_register(env, SPR_750_GQR5, "GQR5",
5335 SPR_NOACCESS, SPR_NOACCESS,
5336 &spr_read_generic, &spr_write_generic,
5337 0x00000000);
5338 /* XXX : not implemented */
5339 spr_register(env, SPR_750_GQR6, "GQR6",
5340 SPR_NOACCESS, SPR_NOACCESS,
5341 &spr_read_generic, &spr_write_generic,
5342 0x00000000);
5343 /* XXX : not implemented */
5344 spr_register(env, SPR_750_GQR7, "GQR7",
5345 SPR_NOACCESS, SPR_NOACCESS,
5346 &spr_read_generic, &spr_write_generic,
5347 0x00000000);
5348 /* Memory management */
5349 gen_low_BATs(env);
5350 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5351 gen_high_BATs(env);
5352 init_excp_750cl(env);
5353 env->dcache_line_size = 32;
5354 env->icache_line_size = 32;
5355 /* Allocate hardware IRQ controller */
5356 ppc6xx_irq_init(env);
5357 }
5358
5359 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
5360 {
5361 DeviceClass *dc = DEVICE_CLASS(oc);
5362 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5363
5364 dc->desc = "PowerPC 750 CL";
5365 pcc->init_proc = init_proc_750cl;
5366 pcc->check_pow = check_pow_hid0;
5367 /* XXX: not implemented:
5368 * cache lock instructions:
5369 * dcbz_l
5370 * floating point paired instructions
5371 * psq_lux
5372 * psq_lx
5373 * psq_stux
5374 * psq_stx
5375 * ps_abs
5376 * ps_add
5377 * ps_cmpo0
5378 * ps_cmpo1
5379 * ps_cmpu0
5380 * ps_cmpu1
5381 * ps_div
5382 * ps_madd
5383 * ps_madds0
5384 * ps_madds1
5385 * ps_merge00
5386 * ps_merge01
5387 * ps_merge10
5388 * ps_merge11
5389 * ps_mr
5390 * ps_msub
5391 * ps_mul
5392 * ps_muls0
5393 * ps_muls1
5394 * ps_nabs
5395 * ps_neg
5396 * ps_nmadd
5397 * ps_nmsub
5398 * ps_res
5399 * ps_rsqrte
5400 * ps_sel
5401 * ps_sub
5402 * ps_sum0
5403 * ps_sum1
5404 */
5405 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5406 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5407 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5408 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5409 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5410 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5411 PPC_SEGMENT | PPC_EXTERN;
5412 pcc->msr_mask = 0x000000000005FF77ULL;
5413 pcc->mmu_model = POWERPC_MMU_32B;
5414 #if defined(CONFIG_SOFTMMU)
5415 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5416 #endif
5417 pcc->excp_model = POWERPC_EXCP_7x0;
5418 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5419 pcc->bfd_mach = bfd_mach_ppc_750;
5420 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5421 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5422 }
5423
5424 static void init_proc_750cx (CPUPPCState *env)
5425 {
5426 gen_spr_ne_601(env);
5427 gen_spr_7xx(env);
5428 /* XXX : not implemented */
5429 spr_register(env, SPR_L2CR, "L2CR",
5430 SPR_NOACCESS, SPR_NOACCESS,
5431 &spr_read_generic, spr_access_nop,
5432 0x00000000);
5433 /* Time base */
5434 gen_tbl(env);
5435 /* Thermal management */
5436 gen_spr_thrm(env);
5437 /* This register is not implemented but is present for compatibility */
5438 spr_register(env, SPR_SDA, "SDA",
5439 SPR_NOACCESS, SPR_NOACCESS,
5440 &spr_read_generic, &spr_write_generic,
5441 0x00000000);
5442 /* Hardware implementation registers */
5443 /* XXX : not implemented */
5444 spr_register(env, SPR_HID0, "HID0",
5445 SPR_NOACCESS, SPR_NOACCESS,
5446 &spr_read_generic, &spr_write_generic,
5447 0x00000000);
5448 /* XXX : not implemented */
5449 spr_register(env, SPR_HID1, "HID1",
5450 SPR_NOACCESS, SPR_NOACCESS,
5451 &spr_read_generic, &spr_write_generic,
5452 0x00000000);
5453 /* Memory management */
5454 gen_low_BATs(env);
5455 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5456 gen_high_BATs(env);
5457 init_excp_750cx(env);
5458 env->dcache_line_size = 32;
5459 env->icache_line_size = 32;
5460 /* Allocate hardware IRQ controller */
5461 ppc6xx_irq_init(env);
5462 }
5463
5464 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
5465 {
5466 DeviceClass *dc = DEVICE_CLASS(oc);
5467 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5468
5469 dc->desc = "PowerPC 750CX";
5470 pcc->init_proc = init_proc_750cx;
5471 pcc->check_pow = check_pow_hid0;
5472 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5473 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5474 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5475 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5476 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5477 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5478 PPC_SEGMENT | PPC_EXTERN;
5479 pcc->msr_mask = 0x000000000005FF77ULL;
5480 pcc->mmu_model = POWERPC_MMU_32B;
5481 #if defined(CONFIG_SOFTMMU)
5482 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5483 #endif
5484 pcc->excp_model = POWERPC_EXCP_7x0;
5485 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5486 pcc->bfd_mach = bfd_mach_ppc_750;
5487 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5488 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5489 }
5490
5491 static void init_proc_750fx (CPUPPCState *env)
5492 {
5493 gen_spr_ne_601(env);
5494 gen_spr_7xx(env);
5495 /* XXX : not implemented */
5496 spr_register(env, SPR_L2CR, "L2CR",
5497 SPR_NOACCESS, SPR_NOACCESS,
5498 &spr_read_generic, spr_access_nop,
5499 0x00000000);
5500 /* Time base */
5501 gen_tbl(env);
5502 /* Thermal management */
5503 gen_spr_thrm(env);
5504 /* XXX : not implemented */
5505 spr_register(env, SPR_750_THRM4, "THRM4",
5506 SPR_NOACCESS, SPR_NOACCESS,
5507 &spr_read_generic, &spr_write_generic,
5508 0x00000000);
5509 /* Hardware implementation registers */
5510 /* XXX : not implemented */
5511 spr_register(env, SPR_HID0, "HID0",
5512 SPR_NOACCESS, SPR_NOACCESS,
5513 &spr_read_generic, &spr_write_generic,
5514 0x00000000);
5515 /* XXX : not implemented */
5516 spr_register(env, SPR_HID1, "HID1",
5517 SPR_NOACCESS, SPR_NOACCESS,
5518 &spr_read_generic, &spr_write_generic,
5519 0x00000000);
5520 /* XXX : not implemented */
5521 spr_register(env, SPR_750FX_HID2, "HID2",
5522 SPR_NOACCESS, SPR_NOACCESS,
5523 &spr_read_generic, &spr_write_generic,
5524 0x00000000);
5525 /* Memory management */
5526 gen_low_BATs(env);
5527 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5528 gen_high_BATs(env);
5529 init_excp_7x0(env);
5530 env->dcache_line_size = 32;
5531 env->icache_line_size = 32;
5532 /* Allocate hardware IRQ controller */
5533 ppc6xx_irq_init(env);
5534 }
5535
5536 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
5537 {
5538 DeviceClass *dc = DEVICE_CLASS(oc);
5539 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5540
5541 dc->desc = "PowerPC 750FX";
5542 pcc->init_proc = init_proc_750fx;
5543 pcc->check_pow = check_pow_hid0;
5544 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5545 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5546 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5547 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5548 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5549 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5550 PPC_SEGMENT | PPC_EXTERN;
5551 pcc->msr_mask = 0x000000000005FF77ULL;
5552 pcc->mmu_model = POWERPC_MMU_32B;
5553 #if defined(CONFIG_SOFTMMU)
5554 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5555 #endif
5556 pcc->excp_model = POWERPC_EXCP_7x0;
5557 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5558 pcc->bfd_mach = bfd_mach_ppc_750;
5559 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5560 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5561 }
5562
5563 static void init_proc_750gx (CPUPPCState *env)
5564 {
5565 gen_spr_ne_601(env);
5566 gen_spr_7xx(env);
5567 /* XXX : not implemented (XXX: different from 750fx) */
5568 spr_register(env, SPR_L2CR, "L2CR",
5569 SPR_NOACCESS, SPR_NOACCESS,
5570 &spr_read_generic, spr_access_nop,
5571 0x00000000);
5572 /* Time base */
5573 gen_tbl(env);
5574 /* Thermal management */
5575 gen_spr_thrm(env);
5576 /* XXX : not implemented */
5577 spr_register(env, SPR_750_THRM4, "THRM4",
5578 SPR_NOACCESS, SPR_NOACCESS,
5579 &spr_read_generic, &spr_write_generic,
5580 0x00000000);
5581 /* Hardware implementation registers */
5582 /* XXX : not implemented (XXX: different from 750fx) */
5583 spr_register(env, SPR_HID0, "HID0",
5584 SPR_NOACCESS, SPR_NOACCESS,
5585 &spr_read_generic, &spr_write_generic,
5586 0x00000000);
5587 /* XXX : not implemented */
5588 spr_register(env, SPR_HID1, "HID1",
5589 SPR_NOACCESS, SPR_NOACCESS,
5590 &spr_read_generic, &spr_write_generic,
5591 0x00000000);
5592 /* XXX : not implemented (XXX: different from 750fx) */
5593 spr_register(env, SPR_750FX_HID2, "HID2",
5594 SPR_NOACCESS, SPR_NOACCESS,
5595 &spr_read_generic, &spr_write_generic,
5596 0x00000000);
5597 /* Memory management */
5598 gen_low_BATs(env);
5599 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5600 gen_high_BATs(env);
5601 init_excp_7x0(env);
5602 env->dcache_line_size = 32;
5603 env->icache_line_size = 32;
5604 /* Allocate hardware IRQ controller */
5605 ppc6xx_irq_init(env);
5606 }
5607
5608 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
5609 {
5610 DeviceClass *dc = DEVICE_CLASS(oc);
5611 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5612
5613 dc->desc = "PowerPC 750GX";
5614 pcc->init_proc = init_proc_750gx;
5615 pcc->check_pow = check_pow_hid0;
5616 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5617 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5618 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5619 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5620 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5621 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5622 PPC_SEGMENT | PPC_EXTERN;
5623 pcc->msr_mask = 0x000000000005FF77ULL;
5624 pcc->mmu_model = POWERPC_MMU_32B;
5625 #if defined(CONFIG_SOFTMMU)
5626 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5627 #endif
5628 pcc->excp_model = POWERPC_EXCP_7x0;
5629 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5630 pcc->bfd_mach = bfd_mach_ppc_750;
5631 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5632 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5633 }
5634
5635 static void init_proc_745 (CPUPPCState *env)
5636 {
5637 gen_spr_ne_601(env);
5638 gen_spr_7xx(env);
5639 gen_spr_G2_755(env);
5640 /* Time base */
5641 gen_tbl(env);
5642 /* Thermal management */
5643 gen_spr_thrm(env);
5644 /* Hardware implementation registers */
5645 /* XXX : not implemented */
5646 spr_register(env, SPR_HID0, "HID0",
5647 SPR_NOACCESS, SPR_NOACCESS,
5648 &spr_read_generic, &spr_write_generic,
5649 0x00000000);
5650 /* XXX : not implemented */
5651 spr_register(env, SPR_HID1, "HID1",
5652 SPR_NOACCESS, SPR_NOACCESS,
5653 &spr_read_generic, &spr_write_generic,
5654 0x00000000);
5655 /* XXX : not implemented */
5656 spr_register(env, SPR_HID2, "HID2",
5657 SPR_NOACCESS, SPR_NOACCESS,
5658 &spr_read_generic, &spr_write_generic,
5659 0x00000000);
5660 /* Memory management */
5661 gen_low_BATs(env);
5662 gen_high_BATs(env);
5663 gen_6xx_7xx_soft_tlb(env, 64, 2);
5664 init_excp_7x5(env);
5665 env->dcache_line_size = 32;
5666 env->icache_line_size = 32;
5667 /* Allocate hardware IRQ controller */
5668 ppc6xx_irq_init(env);
5669 }
5670
5671 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
5672 {
5673 DeviceClass *dc = DEVICE_CLASS(oc);
5674 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5675
5676 dc->desc = "PowerPC 745";
5677 pcc->init_proc = init_proc_745;
5678 pcc->check_pow = check_pow_hid0;
5679 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5680 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5681 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5682 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5683 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5684 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5685 PPC_SEGMENT | PPC_EXTERN;
5686 pcc->msr_mask = 0x000000000005FF77ULL;
5687 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5688 pcc->excp_model = POWERPC_EXCP_7x5;
5689 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5690 pcc->bfd_mach = bfd_mach_ppc_750;
5691 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5692 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5693 }
5694
5695 static void init_proc_755 (CPUPPCState *env)
5696 {
5697 gen_spr_ne_601(env);
5698 gen_spr_7xx(env);
5699 gen_spr_G2_755(env);
5700 /* Time base */
5701 gen_tbl(env);
5702 /* L2 cache control */
5703 /* XXX : not implemented */
5704 spr_register(env, SPR_L2CR, "L2CR",
5705 SPR_NOACCESS, SPR_NOACCESS,
5706 &spr_read_generic, spr_access_nop,
5707 0x00000000);
5708 /* XXX : not implemented */
5709 spr_register(env, SPR_L2PMCR, "L2PMCR",
5710 SPR_NOACCESS, SPR_NOACCESS,
5711 &spr_read_generic, &spr_write_generic,
5712 0x00000000);
5713 /* Thermal management */
5714 gen_spr_thrm(env);
5715 /* Hardware implementation registers */
5716 /* XXX : not implemented */
5717 spr_register(env, SPR_HID0, "HID0",
5718 SPR_NOACCESS, SPR_NOACCESS,
5719 &spr_read_generic, &spr_write_generic,
5720 0x00000000);
5721 /* XXX : not implemented */
5722 spr_register(env, SPR_HID1, "HID1",
5723 SPR_NOACCESS, SPR_NOACCESS,
5724 &spr_read_generic, &spr_write_generic,
5725 0x00000000);
5726 /* XXX : not implemented */
5727 spr_register(env, SPR_HID2, "HID2",
5728 SPR_NOACCESS, SPR_NOACCESS,
5729 &spr_read_generic, &spr_write_generic,
5730 0x00000000);
5731 /* Memory management */
5732 gen_low_BATs(env);
5733 gen_high_BATs(env);
5734 gen_6xx_7xx_soft_tlb(env, 64, 2);
5735 init_excp_7x5(env);
5736 env->dcache_line_size = 32;
5737 env->icache_line_size = 32;
5738 /* Allocate hardware IRQ controller */
5739 ppc6xx_irq_init(env);
5740 }
5741
5742 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
5743 {
5744 DeviceClass *dc = DEVICE_CLASS(oc);
5745 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5746
5747 dc->desc = "PowerPC 755";
5748 pcc->init_proc = init_proc_755;
5749 pcc->check_pow = check_pow_hid0;
5750 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5751 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5752 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5753 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5754 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5755 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5756 PPC_SEGMENT | PPC_EXTERN;
5757 pcc->msr_mask = 0x000000000005FF77ULL;
5758 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5759 pcc->excp_model = POWERPC_EXCP_7x5;
5760 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5761 pcc->bfd_mach = bfd_mach_ppc_750;
5762 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5763 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5764 }
5765
5766 static void init_proc_7400 (CPUPPCState *env)
5767 {
5768 gen_spr_ne_601(env);
5769 gen_spr_7xx(env);
5770 /* Time base */
5771 gen_tbl(env);
5772 /* 74xx specific SPR */
5773 gen_spr_74xx(env);
5774 /* XXX : not implemented */
5775 spr_register(env, SPR_UBAMR, "UBAMR",
5776 &spr_read_ureg, SPR_NOACCESS,
5777 &spr_read_ureg, SPR_NOACCESS,
5778 0x00000000);
5779 /* XXX: this seems not implemented on all revisions. */
5780 /* XXX : not implemented */
5781 spr_register(env, SPR_MSSCR1, "MSSCR1",
5782 SPR_NOACCESS, SPR_NOACCESS,
5783 &spr_read_generic, &spr_write_generic,
5784 0x00000000);
5785 /* Thermal management */
5786 gen_spr_thrm(env);
5787 /* Memory management */
5788 gen_low_BATs(env);
5789 init_excp_7400(env);
5790 env->dcache_line_size = 32;
5791 env->icache_line_size = 32;
5792 /* Allocate hardware IRQ controller */
5793 ppc6xx_irq_init(env);
5794 }
5795
5796 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
5797 {
5798 DeviceClass *dc = DEVICE_CLASS(oc);
5799 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5800
5801 dc->desc = "PowerPC 7400 (aka G4)";
5802 pcc->init_proc = init_proc_7400;
5803 pcc->check_pow = check_pow_hid0;
5804 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5805 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5806 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5807 PPC_FLOAT_STFIWX |
5808 PPC_CACHE | PPC_CACHE_ICBI |
5809 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5810 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5811 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5812 PPC_MEM_TLBIA |
5813 PPC_SEGMENT | PPC_EXTERN |
5814 PPC_ALTIVEC;
5815 pcc->msr_mask = 0x000000000205FF77ULL;
5816 pcc->mmu_model = POWERPC_MMU_32B;
5817 #if defined(CONFIG_SOFTMMU)
5818 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5819 #endif
5820 pcc->excp_model = POWERPC_EXCP_74xx;
5821 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5822 pcc->bfd_mach = bfd_mach_ppc_7400;
5823 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5824 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5825 POWERPC_FLAG_BUS_CLK;
5826 }
5827
5828 static void init_proc_7410 (CPUPPCState *env)
5829 {
5830 gen_spr_ne_601(env);
5831 gen_spr_7xx(env);
5832 /* Time base */
5833 gen_tbl(env);
5834 /* 74xx specific SPR */
5835 gen_spr_74xx(env);
5836 /* XXX : not implemented */
5837 spr_register(env, SPR_UBAMR, "UBAMR",
5838 &spr_read_ureg, SPR_NOACCESS,
5839 &spr_read_ureg, SPR_NOACCESS,
5840 0x00000000);
5841 /* Thermal management */
5842 gen_spr_thrm(env);
5843 /* L2PMCR */
5844 /* XXX : not implemented */
5845 spr_register(env, SPR_L2PMCR, "L2PMCR",
5846 SPR_NOACCESS, SPR_NOACCESS,
5847 &spr_read_generic, &spr_write_generic,
5848 0x00000000);
5849 /* LDSTDB */
5850 /* XXX : not implemented */
5851 spr_register(env, SPR_LDSTDB, "LDSTDB",
5852 SPR_NOACCESS, SPR_NOACCESS,
5853 &spr_read_generic, &spr_write_generic,
5854 0x00000000);
5855 /* Memory management */
5856 gen_low_BATs(env);
5857 init_excp_7400(env);
5858 env->dcache_line_size = 32;
5859 env->icache_line_size = 32;
5860 /* Allocate hardware IRQ controller */
5861 ppc6xx_irq_init(env);
5862 }
5863
5864 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
5865 {
5866 DeviceClass *dc = DEVICE_CLASS(oc);
5867 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5868
5869 dc->desc = "PowerPC 7410 (aka G4)";
5870 pcc->init_proc = init_proc_7410;
5871 pcc->check_pow = check_pow_hid0;
5872 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5873 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5874 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5875 PPC_FLOAT_STFIWX |
5876 PPC_CACHE | PPC_CACHE_ICBI |
5877 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5878 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5879 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5880 PPC_MEM_TLBIA |
5881 PPC_SEGMENT | PPC_EXTERN |
5882 PPC_ALTIVEC;
5883 pcc->msr_mask = 0x000000000205FF77ULL;
5884 pcc->mmu_model = POWERPC_MMU_32B;
5885 #if defined(CONFIG_SOFTMMU)
5886 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5887 #endif
5888 pcc->excp_model = POWERPC_EXCP_74xx;
5889 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5890 pcc->bfd_mach = bfd_mach_ppc_7400;
5891 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5892 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5893 POWERPC_FLAG_BUS_CLK;
5894 }
5895
5896 static void init_proc_7440 (CPUPPCState *env)
5897 {
5898 gen_spr_ne_601(env);
5899 gen_spr_7xx(env);
5900 /* Time base */
5901 gen_tbl(env);
5902 /* 74xx specific SPR */
5903 gen_spr_74xx(env);
5904 /* XXX : not implemented */
5905 spr_register(env, SPR_UBAMR, "UBAMR",
5906 &spr_read_ureg, SPR_NOACCESS,
5907 &spr_read_ureg, SPR_NOACCESS,
5908 0x00000000);
5909 /* LDSTCR */
5910 /* XXX : not implemented */
5911 spr_register(env, SPR_LDSTCR, "LDSTCR",
5912 SPR_NOACCESS, SPR_NOACCESS,
5913 &spr_read_generic, &spr_write_generic,
5914 0x00000000);
5915 /* ICTRL */
5916 /* XXX : not implemented */
5917 spr_register(env, SPR_ICTRL, "ICTRL",
5918 SPR_NOACCESS, SPR_NOACCESS,
5919 &spr_read_generic, &spr_write_generic,
5920 0x00000000);
5921 /* MSSSR0 */
5922 /* XXX : not implemented */
5923 spr_register(env, SPR_MSSSR0, "MSSSR0",
5924 SPR_NOACCESS, SPR_NOACCESS,
5925 &spr_read_generic, &spr_write_generic,
5926 0x00000000);
5927 /* PMC */
5928 /* XXX : not implemented */
5929 spr_register(env, SPR_PMC5, "PMC5",
5930 SPR_NOACCESS, SPR_NOACCESS,
5931 &spr_read_generic, &spr_write_generic,
5932 0x00000000);
5933 /* XXX : not implemented */
5934 spr_register(env, SPR_UPMC5, "UPMC5",
5935 &spr_read_ureg, SPR_NOACCESS,
5936 &spr_read_ureg, SPR_NOACCESS,
5937 0x00000000);
5938 /* XXX : not implemented */
5939 spr_register(env, SPR_PMC6, "PMC6",
5940 SPR_NOACCESS, SPR_NOACCESS,
5941 &spr_read_generic, &spr_write_generic,
5942 0x00000000);
5943 /* XXX : not implemented */
5944 spr_register(env, SPR_UPMC6, "UPMC6",
5945 &spr_read_ureg, SPR_NOACCESS,
5946 &spr_read_ureg, SPR_NOACCESS,
5947 0x00000000);
5948 /* Memory management */
5949 gen_low_BATs(env);
5950 gen_74xx_soft_tlb(env, 128, 2);
5951 init_excp_7450(env);
5952 env->dcache_line_size = 32;
5953 env->icache_line_size = 32;
5954 /* Allocate hardware IRQ controller */
5955 ppc6xx_irq_init(env);
5956 }
5957
5958 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
5959 {
5960 DeviceClass *dc = DEVICE_CLASS(oc);
5961 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5962
5963 dc->desc = "PowerPC 7440 (aka G4)";
5964 pcc->init_proc = init_proc_7440;
5965 pcc->check_pow = check_pow_hid0_74xx;
5966 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5967 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5968 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
5969 PPC_FLOAT_STFIWX |
5970 PPC_CACHE | PPC_CACHE_ICBI |
5971 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
5972 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5973 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5974 PPC_MEM_TLBIA | PPC_74xx_TLB |
5975 PPC_SEGMENT | PPC_EXTERN |
5976 PPC_ALTIVEC;
5977 pcc->msr_mask = 0x000000000205FF77ULL;
5978 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
5979 pcc->excp_model = POWERPC_EXCP_74xx;
5980 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5981 pcc->bfd_mach = bfd_mach_ppc_7400;
5982 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
5983 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
5984 POWERPC_FLAG_BUS_CLK;
5985 }
5986
5987 static void init_proc_7450 (CPUPPCState *env)
5988 {
5989 gen_spr_ne_601(env);
5990 gen_spr_7xx(env);
5991 /* Time base */
5992 gen_tbl(env);
5993 /* 74xx specific SPR */
5994 gen_spr_74xx(env);
5995 /* Level 3 cache control */
5996 gen_l3_ctrl(env);
5997 /* L3ITCR1 */
5998 /* XXX : not implemented */
5999 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6000 SPR_NOACCESS, SPR_NOACCESS,
6001 &spr_read_generic, &spr_write_generic,
6002 0x00000000);
6003 /* L3ITCR2 */
6004 /* XXX : not implemented */
6005 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6006 SPR_NOACCESS, SPR_NOACCESS,
6007 &spr_read_generic, &spr_write_generic,
6008 0x00000000);
6009 /* L3ITCR3 */
6010 /* XXX : not implemented */
6011 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6012 SPR_NOACCESS, SPR_NOACCESS,
6013 &spr_read_generic, &spr_write_generic,
6014 0x00000000);
6015 /* L3OHCR */
6016 /* XXX : not implemented */
6017 spr_register(env, SPR_L3OHCR, "L3OHCR",
6018 SPR_NOACCESS, SPR_NOACCESS,
6019 &spr_read_generic, &spr_write_generic,
6020 0x00000000);
6021 /* XXX : not implemented */
6022 spr_register(env, SPR_UBAMR, "UBAMR",
6023 &spr_read_ureg, SPR_NOACCESS,
6024 &spr_read_ureg, SPR_NOACCESS,
6025 0x00000000);
6026 /* LDSTCR */
6027 /* XXX : not implemented */
6028 spr_register(env, SPR_LDSTCR, "LDSTCR",
6029 SPR_NOACCESS, SPR_NOACCESS,
6030 &spr_read_generic, &spr_write_generic,
6031 0x00000000);
6032 /* ICTRL */
6033 /* XXX : not implemented */
6034 spr_register(env, SPR_ICTRL, "ICTRL",
6035 SPR_NOACCESS, SPR_NOACCESS,
6036 &spr_read_generic, &spr_write_generic,
6037 0x00000000);
6038 /* MSSSR0 */
6039 /* XXX : not implemented */
6040 spr_register(env, SPR_MSSSR0, "MSSSR0",
6041 SPR_NOACCESS, SPR_NOACCESS,
6042 &spr_read_generic, &spr_write_generic,
6043 0x00000000);
6044 /* PMC */
6045 /* XXX : not implemented */
6046 spr_register(env, SPR_PMC5, "PMC5",
6047 SPR_NOACCESS, SPR_NOACCESS,
6048 &spr_read_generic, &spr_write_generic,
6049 0x00000000);
6050 /* XXX : not implemented */
6051 spr_register(env, SPR_UPMC5, "UPMC5",
6052 &spr_read_ureg, SPR_NOACCESS,
6053 &spr_read_ureg, SPR_NOACCESS,
6054 0x00000000);
6055 /* XXX : not implemented */
6056 spr_register(env, SPR_PMC6, "PMC6",
6057 SPR_NOACCESS, SPR_NOACCESS,
6058 &spr_read_generic, &spr_write_generic,
6059 0x00000000);
6060 /* XXX : not implemented */
6061 spr_register(env, SPR_UPMC6, "UPMC6",
6062 &spr_read_ureg, SPR_NOACCESS,
6063 &spr_read_ureg, SPR_NOACCESS,
6064 0x00000000);
6065 /* Memory management */
6066 gen_low_BATs(env);
6067 gen_74xx_soft_tlb(env, 128, 2);
6068 init_excp_7450(env);
6069 env->dcache_line_size = 32;
6070 env->icache_line_size = 32;
6071 /* Allocate hardware IRQ controller */
6072 ppc6xx_irq_init(env);
6073 }
6074
6075 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
6076 {
6077 DeviceClass *dc = DEVICE_CLASS(oc);
6078 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6079
6080 dc->desc = "PowerPC 7450 (aka G4)";
6081 pcc->init_proc = init_proc_7450;
6082 pcc->check_pow = check_pow_hid0_74xx;
6083 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6084 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6085 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6086 PPC_FLOAT_STFIWX |
6087 PPC_CACHE | PPC_CACHE_ICBI |
6088 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6089 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6090 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6091 PPC_MEM_TLBIA | PPC_74xx_TLB |
6092 PPC_SEGMENT | PPC_EXTERN |
6093 PPC_ALTIVEC;
6094 pcc->msr_mask = 0x000000000205FF77ULL;
6095 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6096 pcc->excp_model = POWERPC_EXCP_74xx;
6097 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6098 pcc->bfd_mach = bfd_mach_ppc_7400;
6099 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6100 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6101 POWERPC_FLAG_BUS_CLK;
6102 }
6103
6104 static void init_proc_7445 (CPUPPCState *env)
6105 {
6106 gen_spr_ne_601(env);
6107 gen_spr_7xx(env);
6108 /* Time base */
6109 gen_tbl(env);
6110 /* 74xx specific SPR */
6111 gen_spr_74xx(env);
6112 /* LDSTCR */
6113 /* XXX : not implemented */
6114 spr_register(env, SPR_LDSTCR, "LDSTCR",
6115 SPR_NOACCESS, SPR_NOACCESS,
6116 &spr_read_generic, &spr_write_generic,
6117 0x00000000);
6118 /* ICTRL */
6119 /* XXX : not implemented */
6120 spr_register(env, SPR_ICTRL, "ICTRL",
6121 SPR_NOACCESS, SPR_NOACCESS,
6122 &spr_read_generic, &spr_write_generic,
6123 0x00000000);
6124 /* MSSSR0 */
6125 /* XXX : not implemented */
6126 spr_register(env, SPR_MSSSR0, "MSSSR0",
6127 SPR_NOACCESS, SPR_NOACCESS,
6128 &spr_read_generic, &spr_write_generic,
6129 0x00000000);
6130 /* PMC */
6131 /* XXX : not implemented */
6132 spr_register(env, SPR_PMC5, "PMC5",
6133 SPR_NOACCESS, SPR_NOACCESS,
6134 &spr_read_generic, &spr_write_generic,
6135 0x00000000);
6136 /* XXX : not implemented */
6137 spr_register(env, SPR_UPMC5, "UPMC5",
6138 &spr_read_ureg, SPR_NOACCESS,
6139 &spr_read_ureg, SPR_NOACCESS,
6140 0x00000000);
6141 /* XXX : not implemented */
6142 spr_register(env, SPR_PMC6, "PMC6",
6143 SPR_NOACCESS, SPR_NOACCESS,
6144 &spr_read_generic, &spr_write_generic,
6145 0x00000000);
6146 /* XXX : not implemented */
6147 spr_register(env, SPR_UPMC6, "UPMC6",
6148 &spr_read_ureg, SPR_NOACCESS,
6149 &spr_read_ureg, SPR_NOACCESS,
6150 0x00000000);
6151 /* SPRGs */
6152 spr_register(env, SPR_SPRG4, "SPRG4",
6153 SPR_NOACCESS, SPR_NOACCESS,
6154 &spr_read_generic, &spr_write_generic,
6155 0x00000000);
6156 spr_register(env, SPR_USPRG4, "USPRG4",
6157 &spr_read_ureg, SPR_NOACCESS,
6158 &spr_read_ureg, SPR_NOACCESS,
6159 0x00000000);
6160 spr_register(env, SPR_SPRG5, "SPRG5",
6161 SPR_NOACCESS, SPR_NOACCESS,
6162 &spr_read_generic, &spr_write_generic,
6163 0x00000000);
6164 spr_register(env, SPR_USPRG5, "USPRG5",
6165 &spr_read_ureg, SPR_NOACCESS,
6166 &spr_read_ureg, SPR_NOACCESS,
6167 0x00000000);
6168 spr_register(env, SPR_SPRG6, "SPRG6",
6169 SPR_NOACCESS, SPR_NOACCESS,
6170 &spr_read_generic, &spr_write_generic,
6171 0x00000000);
6172 spr_register(env, SPR_USPRG6, "USPRG6",
6173 &spr_read_ureg, SPR_NOACCESS,
6174 &spr_read_ureg, SPR_NOACCESS,
6175 0x00000000);
6176 spr_register(env, SPR_SPRG7, "SPRG7",
6177 SPR_NOACCESS, SPR_NOACCESS,
6178 &spr_read_generic, &spr_write_generic,
6179 0x00000000);
6180 spr_register(env, SPR_USPRG7, "USPRG7",
6181 &spr_read_ureg, SPR_NOACCESS,
6182 &spr_read_ureg, SPR_NOACCESS,
6183 0x00000000);
6184 /* Memory management */
6185 gen_low_BATs(env);
6186 gen_high_BATs(env);
6187 gen_74xx_soft_tlb(env, 128, 2);
6188 init_excp_7450(env);
6189 env->dcache_line_size = 32;
6190 env->icache_line_size = 32;
6191 /* Allocate hardware IRQ controller */
6192 ppc6xx_irq_init(env);
6193 }
6194
6195 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
6196 {
6197 DeviceClass *dc = DEVICE_CLASS(oc);
6198 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6199
6200 dc->desc = "PowerPC 7445 (aka G4)";
6201 pcc->init_proc = init_proc_7445;
6202 pcc->check_pow = check_pow_hid0_74xx;
6203 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6204 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6205 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6206 PPC_FLOAT_STFIWX |
6207 PPC_CACHE | PPC_CACHE_ICBI |
6208 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6209 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6210 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6211 PPC_MEM_TLBIA | PPC_74xx_TLB |
6212 PPC_SEGMENT | PPC_EXTERN |
6213 PPC_ALTIVEC;
6214 pcc->msr_mask = 0x000000000205FF77ULL;
6215 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6216 pcc->excp_model = POWERPC_EXCP_74xx;
6217 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6218 pcc->bfd_mach = bfd_mach_ppc_7400;
6219 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6220 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6221 POWERPC_FLAG_BUS_CLK;
6222 }
6223
6224 static void init_proc_7455 (CPUPPCState *env)
6225 {
6226 gen_spr_ne_601(env);
6227 gen_spr_7xx(env);
6228 /* Time base */
6229 gen_tbl(env);
6230 /* 74xx specific SPR */
6231 gen_spr_74xx(env);
6232 /* Level 3 cache control */
6233 gen_l3_ctrl(env);
6234 /* LDSTCR */
6235 /* XXX : not implemented */
6236 spr_register(env, SPR_LDSTCR, "LDSTCR",
6237 SPR_NOACCESS, SPR_NOACCESS,
6238 &spr_read_generic, &spr_write_generic,
6239 0x00000000);
6240 /* ICTRL */
6241 /* XXX : not implemented */
6242 spr_register(env, SPR_ICTRL, "ICTRL",
6243 SPR_NOACCESS, SPR_NOACCESS,
6244 &spr_read_generic, &spr_write_generic,
6245 0x00000000);
6246 /* MSSSR0 */
6247 /* XXX : not implemented */
6248 spr_register(env, SPR_MSSSR0, "MSSSR0",
6249 SPR_NOACCESS, SPR_NOACCESS,
6250 &spr_read_generic, &spr_write_generic,
6251 0x00000000);
6252 /* PMC */
6253 /* XXX : not implemented */
6254 spr_register(env, SPR_PMC5, "PMC5",
6255 SPR_NOACCESS, SPR_NOACCESS,
6256 &spr_read_generic, &spr_write_generic,
6257 0x00000000);
6258 /* XXX : not implemented */
6259 spr_register(env, SPR_UPMC5, "UPMC5",
6260 &spr_read_ureg, SPR_NOACCESS,
6261 &spr_read_ureg, SPR_NOACCESS,
6262 0x00000000);
6263 /* XXX : not implemented */
6264 spr_register(env, SPR_PMC6, "PMC6",
6265 SPR_NOACCESS, SPR_NOACCESS,
6266 &spr_read_generic, &spr_write_generic,
6267 0x00000000);
6268 /* XXX : not implemented */
6269 spr_register(env, SPR_UPMC6, "UPMC6",
6270 &spr_read_ureg, SPR_NOACCESS,
6271 &spr_read_ureg, SPR_NOACCESS,
6272 0x00000000);
6273 /* SPRGs */
6274 spr_register(env, SPR_SPRG4, "SPRG4",
6275 SPR_NOACCESS, SPR_NOACCESS,
6276 &spr_read_generic, &spr_write_generic,
6277 0x00000000);
6278 spr_register(env, SPR_USPRG4, "USPRG4",
6279 &spr_read_ureg, SPR_NOACCESS,
6280 &spr_read_ureg, SPR_NOACCESS,
6281 0x00000000);
6282 spr_register(env, SPR_SPRG5, "SPRG5",
6283 SPR_NOACCESS, SPR_NOACCESS,
6284 &spr_read_generic, &spr_write_generic,
6285 0x00000000);
6286 spr_register(env, SPR_USPRG5, "USPRG5",
6287 &spr_read_ureg, SPR_NOACCESS,
6288 &spr_read_ureg, SPR_NOACCESS,
6289 0x00000000);
6290 spr_register(env, SPR_SPRG6, "SPRG6",
6291 SPR_NOACCESS, SPR_NOACCESS,
6292 &spr_read_generic, &spr_write_generic,
6293 0x00000000);
6294 spr_register(env, SPR_USPRG6, "USPRG6",
6295 &spr_read_ureg, SPR_NOACCESS,
6296 &spr_read_ureg, SPR_NOACCESS,
6297 0x00000000);
6298 spr_register(env, SPR_SPRG7, "SPRG7",
6299 SPR_NOACCESS, SPR_NOACCESS,
6300 &spr_read_generic, &spr_write_generic,
6301 0x00000000);
6302 spr_register(env, SPR_USPRG7, "USPRG7",
6303 &spr_read_ureg, SPR_NOACCESS,
6304 &spr_read_ureg, SPR_NOACCESS,
6305 0x00000000);
6306 /* Memory management */
6307 gen_low_BATs(env);
6308 gen_high_BATs(env);
6309 gen_74xx_soft_tlb(env, 128, 2);
6310 init_excp_7450(env);
6311 env->dcache_line_size = 32;
6312 env->icache_line_size = 32;
6313 /* Allocate hardware IRQ controller */
6314 ppc6xx_irq_init(env);
6315 }
6316
6317 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
6318 {
6319 DeviceClass *dc = DEVICE_CLASS(oc);
6320 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6321
6322 dc->desc = "PowerPC 7455 (aka G4)";
6323 pcc->init_proc = init_proc_7455;
6324 pcc->check_pow = check_pow_hid0_74xx;
6325 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6326 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6327 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6328 PPC_FLOAT_STFIWX |
6329 PPC_CACHE | PPC_CACHE_ICBI |
6330 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6331 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6332 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6333 PPC_MEM_TLBIA | PPC_74xx_TLB |
6334 PPC_SEGMENT | PPC_EXTERN |
6335 PPC_ALTIVEC;
6336 pcc->msr_mask = 0x000000000205FF77ULL;
6337 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6338 pcc->excp_model = POWERPC_EXCP_74xx;
6339 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6340 pcc->bfd_mach = bfd_mach_ppc_7400;
6341 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6342 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6343 POWERPC_FLAG_BUS_CLK;
6344 }
6345
6346 static void init_proc_7457 (CPUPPCState *env)
6347 {
6348 gen_spr_ne_601(env);
6349 gen_spr_7xx(env);
6350 /* Time base */
6351 gen_tbl(env);
6352 /* 74xx specific SPR */
6353 gen_spr_74xx(env);
6354 /* Level 3 cache control */
6355 gen_l3_ctrl(env);
6356 /* L3ITCR1 */
6357 /* XXX : not implemented */
6358 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6359 SPR_NOACCESS, SPR_NOACCESS,
6360 &spr_read_generic, &spr_write_generic,
6361 0x00000000);
6362 /* L3ITCR2 */
6363 /* XXX : not implemented */
6364 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6365 SPR_NOACCESS, SPR_NOACCESS,
6366 &spr_read_generic, &spr_write_generic,
6367 0x00000000);
6368 /* L3ITCR3 */
6369 /* XXX : not implemented */
6370 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6371 SPR_NOACCESS, SPR_NOACCESS,
6372 &spr_read_generic, &spr_write_generic,
6373 0x00000000);
6374 /* L3OHCR */
6375 /* XXX : not implemented */
6376 spr_register(env, SPR_L3OHCR, "L3OHCR",
6377 SPR_NOACCESS, SPR_NOACCESS,
6378 &spr_read_generic, &spr_write_generic,
6379 0x00000000);
6380 /* LDSTCR */
6381 /* XXX : not implemented */
6382 spr_register(env, SPR_LDSTCR, "LDSTCR",
6383 SPR_NOACCESS, SPR_NOACCESS,
6384 &spr_read_generic, &spr_write_generic,
6385 0x00000000);
6386 /* ICTRL */
6387 /* XXX : not implemented */
6388 spr_register(env, SPR_ICTRL, "ICTRL",
6389 SPR_NOACCESS, SPR_NOACCESS,
6390 &spr_read_generic, &spr_write_generic,
6391 0x00000000);
6392 /* MSSSR0 */
6393 /* XXX : not implemented */
6394 spr_register(env, SPR_MSSSR0, "MSSSR0",
6395 SPR_NOACCESS, SPR_NOACCESS,
6396 &spr_read_generic, &spr_write_generic,
6397 0x00000000);
6398 /* PMC */
6399 /* XXX : not implemented */
6400 spr_register(env, SPR_PMC5, "PMC5",
6401 SPR_NOACCESS, SPR_NOACCESS,
6402 &spr_read_generic, &spr_write_generic,
6403 0x00000000);
6404 /* XXX : not implemented */
6405 spr_register(env, SPR_UPMC5, "UPMC5",
6406 &spr_read_ureg, SPR_NOACCESS,
6407 &spr_read_ureg, SPR_NOACCESS,
6408 0x00000000);
6409 /* XXX : not implemented */
6410 spr_register(env, SPR_PMC6, "PMC6",
6411 SPR_NOACCESS, SPR_NOACCESS,
6412 &spr_read_generic, &spr_write_generic,
6413 0x00000000);
6414 /* XXX : not implemented */
6415 spr_register(env, SPR_UPMC6, "UPMC6",
6416 &spr_read_ureg, SPR_NOACCESS,
6417 &spr_read_ureg, SPR_NOACCESS,
6418 0x00000000);
6419 /* SPRGs */
6420 spr_register(env, SPR_SPRG4, "SPRG4",
6421 SPR_NOACCESS, SPR_NOACCESS,
6422 &spr_read_generic, &spr_write_generic,
6423 0x00000000);
6424 spr_register(env, SPR_USPRG4, "USPRG4",
6425 &spr_read_ureg, SPR_NOACCESS,
6426 &spr_read_ureg, SPR_NOACCESS,
6427 0x00000000);
6428 spr_register(env, SPR_SPRG5, "SPRG5",
6429 SPR_NOACCESS, SPR_NOACCESS,
6430 &spr_read_generic, &spr_write_generic,
6431 0x00000000);
6432 spr_register(env, SPR_USPRG5, "USPRG5",
6433 &spr_read_ureg, SPR_NOACCESS,
6434 &spr_read_ureg, SPR_NOACCESS,
6435 0x00000000);
6436 spr_register(env, SPR_SPRG6, "SPRG6",
6437 SPR_NOACCESS, SPR_NOACCESS,
6438 &spr_read_generic, &spr_write_generic,
6439 0x00000000);
6440 spr_register(env, SPR_USPRG6, "USPRG6",
6441 &spr_read_ureg, SPR_NOACCESS,
6442 &spr_read_ureg, SPR_NOACCESS,
6443 0x00000000);
6444 spr_register(env, SPR_SPRG7, "SPRG7",
6445 SPR_NOACCESS, SPR_NOACCESS,
6446 &spr_read_generic, &spr_write_generic,
6447 0x00000000);
6448 spr_register(env, SPR_USPRG7, "USPRG7",
6449 &spr_read_ureg, SPR_NOACCESS,
6450 &spr_read_ureg, SPR_NOACCESS,
6451 0x00000000);
6452 /* Memory management */
6453 gen_low_BATs(env);
6454 gen_high_BATs(env);
6455 gen_74xx_soft_tlb(env, 128, 2);
6456 init_excp_7450(env);
6457 env->dcache_line_size = 32;
6458 env->icache_line_size = 32;
6459 /* Allocate hardware IRQ controller */
6460 ppc6xx_irq_init(env);
6461 }
6462
6463 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
6464 {
6465 DeviceClass *dc = DEVICE_CLASS(oc);
6466 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6467
6468 dc->desc = "PowerPC 7457 (aka G4)";
6469 pcc->init_proc = init_proc_7457;
6470 pcc->check_pow = check_pow_hid0_74xx;
6471 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6472 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6473 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6474 PPC_FLOAT_STFIWX |
6475 PPC_CACHE | PPC_CACHE_ICBI |
6476 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6477 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6478 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6479 PPC_MEM_TLBIA | PPC_74xx_TLB |
6480 PPC_SEGMENT | PPC_EXTERN |
6481 PPC_ALTIVEC;
6482 pcc->msr_mask = 0x000000000205FF77ULL;
6483 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6484 pcc->excp_model = POWERPC_EXCP_74xx;
6485 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6486 pcc->bfd_mach = bfd_mach_ppc_7400;
6487 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6488 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6489 POWERPC_FLAG_BUS_CLK;
6490 }
6491
6492 static void init_proc_e600 (CPUPPCState *env)
6493 {
6494 gen_spr_ne_601(env);
6495 gen_spr_7xx(env);
6496 /* Time base */
6497 gen_tbl(env);
6498 /* 74xx specific SPR */
6499 gen_spr_74xx(env);
6500 /* XXX : not implemented */
6501 spr_register(env, SPR_UBAMR, "UBAMR",
6502 &spr_read_ureg, SPR_NOACCESS,
6503 &spr_read_ureg, SPR_NOACCESS,
6504 0x00000000);
6505 /* XXX : not implemented */
6506 spr_register(env, SPR_LDSTCR, "LDSTCR",
6507 SPR_NOACCESS, SPR_NOACCESS,
6508 &spr_read_generic, &spr_write_generic,
6509 0x00000000);
6510 /* XXX : not implemented */
6511 spr_register(env, SPR_ICTRL, "ICTRL",
6512 SPR_NOACCESS, SPR_NOACCESS,
6513 &spr_read_generic, &spr_write_generic,
6514 0x00000000);
6515 /* XXX : not implemented */
6516 spr_register(env, SPR_MSSSR0, "MSSSR0",
6517 SPR_NOACCESS, SPR_NOACCESS,
6518 &spr_read_generic, &spr_write_generic,
6519 0x00000000);
6520 /* XXX : not implemented */
6521 spr_register(env, SPR_PMC5, "PMC5",
6522 SPR_NOACCESS, SPR_NOACCESS,
6523 &spr_read_generic, &spr_write_generic,
6524 0x00000000);
6525 /* XXX : not implemented */
6526 spr_register(env, SPR_UPMC5, "UPMC5",
6527 &spr_read_ureg, SPR_NOACCESS,
6528 &spr_read_ureg, SPR_NOACCESS,
6529 0x00000000);
6530 /* XXX : not implemented */
6531 spr_register(env, SPR_PMC6, "PMC6",
6532 SPR_NOACCESS, SPR_NOACCESS,
6533 &spr_read_generic, &spr_write_generic,
6534 0x00000000);
6535 /* XXX : not implemented */
6536 spr_register(env, SPR_UPMC6, "UPMC6",
6537 &spr_read_ureg, SPR_NOACCESS,
6538 &spr_read_ureg, SPR_NOACCESS,
6539 0x00000000);
6540 /* SPRGs */
6541 spr_register(env, SPR_SPRG4, "SPRG4",
6542 SPR_NOACCESS, SPR_NOACCESS,
6543 &spr_read_generic, &spr_write_generic,
6544 0x00000000);
6545 spr_register(env, SPR_USPRG4, "USPRG4",
6546 &spr_read_ureg, SPR_NOACCESS,
6547 &spr_read_ureg, SPR_NOACCESS,
6548 0x00000000);
6549 spr_register(env, SPR_SPRG5, "SPRG5",
6550 SPR_NOACCESS, SPR_NOACCESS,
6551 &spr_read_generic, &spr_write_generic,
6552 0x00000000);
6553 spr_register(env, SPR_USPRG5, "USPRG5",
6554 &spr_read_ureg, SPR_NOACCESS,
6555 &spr_read_ureg, SPR_NOACCESS,
6556 0x00000000);
6557 spr_register(env, SPR_SPRG6, "SPRG6",
6558 SPR_NOACCESS, SPR_NOACCESS,
6559 &spr_read_generic, &spr_write_generic,
6560 0x00000000);
6561 spr_register(env, SPR_USPRG6, "USPRG6",
6562 &spr_read_ureg, SPR_NOACCESS,
6563 &spr_read_ureg, SPR_NOACCESS,
6564 0x00000000);
6565 spr_register(env, SPR_SPRG7, "SPRG7",
6566 SPR_NOACCESS, SPR_NOACCESS,
6567 &spr_read_generic, &spr_write_generic,
6568 0x00000000);
6569 spr_register(env, SPR_USPRG7, "USPRG7",
6570 &spr_read_ureg, SPR_NOACCESS,
6571 &spr_read_ureg, SPR_NOACCESS,
6572 0x00000000);
6573 /* Memory management */
6574 gen_low_BATs(env);
6575 gen_high_BATs(env);
6576 gen_74xx_soft_tlb(env, 128, 2);
6577 init_excp_7450(env);
6578 env->dcache_line_size = 32;
6579 env->icache_line_size = 32;
6580 /* Allocate hardware IRQ controller */
6581 ppc6xx_irq_init(env);
6582 }
6583
6584 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
6585 {
6586 DeviceClass *dc = DEVICE_CLASS(oc);
6587 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6588
6589 dc->desc = "PowerPC e600";
6590 pcc->init_proc = init_proc_e600;
6591 pcc->check_pow = check_pow_hid0_74xx;
6592 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6593 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6594 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6595 PPC_FLOAT_STFIWX |
6596 PPC_CACHE | PPC_CACHE_ICBI |
6597 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6598 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6599 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6600 PPC_MEM_TLBIA | PPC_74xx_TLB |
6601 PPC_SEGMENT | PPC_EXTERN |
6602 PPC_ALTIVEC;
6603 pcc->insns_flags2 = PPC_NONE;
6604 pcc->msr_mask = 0x000000000205FF77ULL;
6605 pcc->mmu_model = POWERPC_MMU_32B;
6606 #if defined(CONFIG_SOFTMMU)
6607 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6608 #endif
6609 pcc->excp_model = POWERPC_EXCP_74xx;
6610 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6611 pcc->bfd_mach = bfd_mach_ppc_7400;
6612 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6613 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6614 POWERPC_FLAG_BUS_CLK;
6615 }
6616
6617 #if defined (TARGET_PPC64)
6618 #if defined(CONFIG_USER_ONLY)
6619 #define POWERPC970_HID5_INIT 0x00000080
6620 #else
6621 #define POWERPC970_HID5_INIT 0x00000000
6622 #endif
6623
6624 static int check_pow_970 (CPUPPCState *env)
6625 {
6626 if (env->spr[SPR_HID0] & 0x00600000)
6627 return 1;
6628
6629 return 0;
6630 }
6631
6632 static void init_proc_970 (CPUPPCState *env)
6633 {
6634 gen_spr_ne_601(env);
6635 gen_spr_7xx(env);
6636 /* Time base */
6637 gen_tbl(env);
6638 /* Hardware implementation registers */
6639 /* XXX : not implemented */
6640 spr_register(env, SPR_HID0, "HID0",
6641 SPR_NOACCESS, SPR_NOACCESS,
6642 &spr_read_generic, &spr_write_clear,
6643 0x60000000);
6644 /* XXX : not implemented */
6645 spr_register(env, SPR_HID1, "HID1",
6646 SPR_NOACCESS, SPR_NOACCESS,
6647 &spr_read_generic, &spr_write_generic,
6648 0x00000000);
6649 /* XXX : not implemented */
6650 spr_register(env, SPR_970_HID5, "HID5",
6651 SPR_NOACCESS, SPR_NOACCESS,
6652 &spr_read_generic, &spr_write_generic,
6653 POWERPC970_HID5_INIT);
6654 /* Memory management */
6655 /* XXX: not correct */
6656 gen_low_BATs(env);
6657 spr_register(env, SPR_HIOR, "SPR_HIOR",
6658 SPR_NOACCESS, SPR_NOACCESS,
6659 &spr_read_hior, &spr_write_hior,
6660 0x00000000);
6661 #if !defined(CONFIG_USER_ONLY)
6662 env->slb_nr = 32;
6663 #endif
6664 init_excp_970(env);
6665 env->dcache_line_size = 128;
6666 env->icache_line_size = 128;
6667 /* Allocate hardware IRQ controller */
6668 ppc970_irq_init(env);
6669 /* Can't find information on what this should be on reset. This
6670 * value is the one used by 74xx processors. */
6671 vscr_init(env, 0x00010000);
6672 }
6673
6674 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
6675 {
6676 DeviceClass *dc = DEVICE_CLASS(oc);
6677 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6678
6679 dc->desc = "PowerPC 970";
6680 pcc->init_proc = init_proc_970;
6681 pcc->check_pow = check_pow_970;
6682 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6683 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6684 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6685 PPC_FLOAT_STFIWX |
6686 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6687 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6688 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6689 PPC_64B | PPC_ALTIVEC |
6690 PPC_SEGMENT_64B | PPC_SLBI;
6691 pcc->msr_mask = 0x900000000204FF36ULL;
6692 pcc->mmu_model = POWERPC_MMU_64B;
6693 #if defined(CONFIG_SOFTMMU)
6694 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
6695 #endif
6696 pcc->excp_model = POWERPC_EXCP_970;
6697 pcc->bus_model = PPC_FLAGS_INPUT_970;
6698 pcc->bfd_mach = bfd_mach_ppc64;
6699 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6700 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6701 POWERPC_FLAG_BUS_CLK;
6702 }
6703
6704 static int check_pow_970FX (CPUPPCState *env)
6705 {
6706 if (env->spr[SPR_HID0] & 0x00600000)
6707 return 1;
6708
6709 return 0;
6710 }
6711
6712 static void init_proc_970FX (CPUPPCState *env)
6713 {
6714 gen_spr_ne_601(env);
6715 gen_spr_7xx(env);
6716 /* Time base */
6717 gen_tbl(env);
6718 /* Hardware implementation registers */
6719 /* XXX : not implemented */
6720 spr_register(env, SPR_HID0, "HID0",
6721 SPR_NOACCESS, SPR_NOACCESS,
6722 &spr_read_generic, &spr_write_clear,
6723 0x60000000);
6724 /* XXX : not implemented */
6725 spr_register(env, SPR_HID1, "HID1",
6726 SPR_NOACCESS, SPR_NOACCESS,
6727 &spr_read_generic, &spr_write_generic,
6728 0x00000000);
6729 /* XXX : not implemented */
6730 spr_register(env, SPR_970_HID5, "HID5",
6731 SPR_NOACCESS, SPR_NOACCESS,
6732 &spr_read_generic, &spr_write_generic,
6733 POWERPC970_HID5_INIT);
6734 /* Memory management */
6735 /* XXX: not correct */
6736 gen_low_BATs(env);
6737 spr_register(env, SPR_HIOR, "SPR_HIOR",
6738 SPR_NOACCESS, SPR_NOACCESS,
6739 &spr_read_hior, &spr_write_hior,
6740 0x00000000);
6741 spr_register(env, SPR_CTRL, "SPR_CTRL",
6742 SPR_NOACCESS, SPR_NOACCESS,
6743 SPR_NOACCESS, &spr_write_generic,
6744 0x00000000);
6745 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6746 SPR_NOACCESS, SPR_NOACCESS,
6747 &spr_read_generic, SPR_NOACCESS,
6748 0x00000000);
6749 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6750 &spr_read_generic, &spr_write_generic,
6751 &spr_read_generic, &spr_write_generic,
6752 0x00000000);
6753 #if !defined(CONFIG_USER_ONLY)
6754 env->slb_nr = 64;
6755 #endif
6756 init_excp_970(env);
6757 env->dcache_line_size = 128;
6758 env->icache_line_size = 128;
6759 /* Allocate hardware IRQ controller */
6760 ppc970_irq_init(env);
6761 /* Can't find information on what this should be on reset. This
6762 * value is the one used by 74xx processors. */
6763 vscr_init(env, 0x00010000);
6764 }
6765
6766 POWERPC_FAMILY(970FX)(ObjectClass *oc, void *data)
6767 {
6768 DeviceClass *dc = DEVICE_CLASS(oc);
6769 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6770
6771 dc->desc = "PowerPC 970FX (aka G5)";
6772 pcc->init_proc = init_proc_970FX;
6773 pcc->check_pow = check_pow_970FX;
6774 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6775 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6776 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6777 PPC_FLOAT_STFIWX |
6778 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6779 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6780 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6781 PPC_64B | PPC_ALTIVEC |
6782 PPC_SEGMENT_64B | PPC_SLBI;
6783 pcc->msr_mask = 0x800000000204FF36ULL;
6784 pcc->mmu_model = POWERPC_MMU_64B;
6785 #if defined(CONFIG_SOFTMMU)
6786 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
6787 #endif
6788 pcc->excp_model = POWERPC_EXCP_970;
6789 pcc->bus_model = PPC_FLAGS_INPUT_970;
6790 pcc->bfd_mach = bfd_mach_ppc64;
6791 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6792 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6793 POWERPC_FLAG_BUS_CLK;
6794 }
6795
6796 static int check_pow_970MP (CPUPPCState *env)
6797 {
6798 if (env->spr[SPR_HID0] & 0x01C00000)
6799 return 1;
6800
6801 return 0;
6802 }
6803
6804 static void init_proc_970MP (CPUPPCState *env)
6805 {
6806 gen_spr_ne_601(env);
6807 gen_spr_7xx(env);
6808 /* Time base */
6809 gen_tbl(env);
6810 /* Hardware implementation registers */
6811 /* XXX : not implemented */
6812 spr_register(env, SPR_HID0, "HID0",
6813 SPR_NOACCESS, SPR_NOACCESS,
6814 &spr_read_generic, &spr_write_clear,
6815 0x60000000);
6816 /* XXX : not implemented */
6817 spr_register(env, SPR_HID1, "HID1",
6818 SPR_NOACCESS, SPR_NOACCESS,
6819 &spr_read_generic, &spr_write_generic,
6820 0x00000000);
6821 /* XXX : not implemented */
6822 spr_register(env, SPR_970_HID5, "HID5",
6823 SPR_NOACCESS, SPR_NOACCESS,
6824 &spr_read_generic, &spr_write_generic,
6825 POWERPC970_HID5_INIT);
6826 /* XXX : not implemented */
6827 /* Memory management */
6828 /* XXX: not correct */
6829 gen_low_BATs(env);
6830 spr_register(env, SPR_HIOR, "SPR_HIOR",
6831 SPR_NOACCESS, SPR_NOACCESS,
6832 &spr_read_hior, &spr_write_hior,
6833 0x00000000);
6834 /* Logical partitionning */
6835 spr_register_kvm(env, SPR_LPCR, "LPCR",
6836 SPR_NOACCESS, SPR_NOACCESS,
6837 &spr_read_generic, &spr_write_generic,
6838 KVM_REG_PPC_LPCR, 0x00000000);
6839 #if !defined(CONFIG_USER_ONLY)
6840 env->slb_nr = 32;
6841 #endif
6842 init_excp_970(env);
6843 env->dcache_line_size = 128;
6844 env->icache_line_size = 128;
6845 /* Allocate hardware IRQ controller */
6846 ppc970_irq_init(env);
6847 /* Can't find information on what this should be on reset. This
6848 * value is the one used by 74xx processors. */
6849 vscr_init(env, 0x00010000);
6850 }
6851
6852 POWERPC_FAMILY(970MP)(ObjectClass *oc, void *data)
6853 {
6854 DeviceClass *dc = DEVICE_CLASS(oc);
6855 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6856
6857 dc->desc = "PowerPC 970 MP";
6858 pcc->init_proc = init_proc_970MP;
6859 pcc->check_pow = check_pow_970MP;
6860 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6861 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6862 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6863 PPC_FLOAT_STFIWX |
6864 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6865 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6866 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6867 PPC_64B | PPC_ALTIVEC |
6868 PPC_SEGMENT_64B | PPC_SLBI;
6869 pcc->msr_mask = 0x900000000204FF36ULL;
6870 pcc->mmu_model = POWERPC_MMU_64B;
6871 #if defined(CONFIG_SOFTMMU)
6872 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
6873 #endif
6874 pcc->excp_model = POWERPC_EXCP_970;
6875 pcc->bus_model = PPC_FLAGS_INPUT_970;
6876 pcc->bfd_mach = bfd_mach_ppc64;
6877 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6878 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6879 POWERPC_FLAG_BUS_CLK;
6880 }
6881
6882 static void init_proc_power5plus(CPUPPCState *env)
6883 {
6884 gen_spr_ne_601(env);
6885 gen_spr_7xx(env);
6886 /* Time base */
6887 gen_tbl(env);
6888 /* Hardware implementation registers */
6889 /* XXX : not implemented */
6890 spr_register(env, SPR_HID0, "HID0",
6891 SPR_NOACCESS, SPR_NOACCESS,
6892 &spr_read_generic, &spr_write_clear,
6893 0x60000000);
6894 /* XXX : not implemented */
6895 spr_register(env, SPR_HID1, "HID1",
6896 SPR_NOACCESS, SPR_NOACCESS,
6897 &spr_read_generic, &spr_write_generic,
6898 0x00000000);
6899 /* XXX : not implemented */
6900 spr_register(env, SPR_970_HID5, "HID5",
6901 SPR_NOACCESS, SPR_NOACCESS,
6902 &spr_read_generic, &spr_write_generic,
6903 POWERPC970_HID5_INIT);
6904 /* Memory management */
6905 /* XXX: not correct */
6906 gen_low_BATs(env);
6907 spr_register(env, SPR_HIOR, "SPR_HIOR",
6908 SPR_NOACCESS, SPR_NOACCESS,
6909 &spr_read_hior, &spr_write_hior,
6910 0x00000000);
6911 spr_register(env, SPR_CTRL, "SPR_CTRL",
6912 SPR_NOACCESS, SPR_NOACCESS,
6913 SPR_NOACCESS, &spr_write_generic,
6914 0x00000000);
6915 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
6916 SPR_NOACCESS, SPR_NOACCESS,
6917 &spr_read_generic, SPR_NOACCESS,
6918 0x00000000);
6919 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
6920 &spr_read_generic, &spr_write_generic,
6921 &spr_read_generic, &spr_write_generic,
6922 0x00000000);
6923 /* Logical partitionning */
6924 spr_register_kvm(env, SPR_LPCR, "LPCR",
6925 SPR_NOACCESS, SPR_NOACCESS,
6926 &spr_read_generic, &spr_write_generic,
6927 KVM_REG_PPC_LPCR, 0x00000000);
6928 #if !defined(CONFIG_USER_ONLY)
6929 env->slb_nr = 64;
6930 #endif
6931 init_excp_970(env);
6932 env->dcache_line_size = 128;
6933 env->icache_line_size = 128;
6934 /* Allocate hardware IRQ controller */
6935 ppc970_irq_init(env);
6936 /* Can't find information on what this should be on reset. This
6937 * value is the one used by 74xx processors. */
6938 vscr_init(env, 0x00010000);
6939 }
6940
6941 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
6942 {
6943 DeviceClass *dc = DEVICE_CLASS(oc);
6944 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6945
6946 dc->fw_name = "PowerPC,POWER5";
6947 dc->desc = "POWER5+";
6948 pcc->init_proc = init_proc_power5plus;
6949 pcc->check_pow = check_pow_970FX;
6950 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6951 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6952 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6953 PPC_FLOAT_STFIWX |
6954 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6955 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6956 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6957 PPC_64B |
6958 PPC_SEGMENT_64B | PPC_SLBI;
6959 pcc->msr_mask = 0x800000000204FF36ULL;
6960 pcc->mmu_model = POWERPC_MMU_64B;
6961 #if defined(CONFIG_SOFTMMU)
6962 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
6963 #endif
6964 pcc->excp_model = POWERPC_EXCP_970;
6965 pcc->bus_model = PPC_FLAGS_INPUT_970;
6966 pcc->bfd_mach = bfd_mach_ppc64;
6967 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6968 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6969 POWERPC_FLAG_BUS_CLK;
6970 }
6971
6972 static void init_proc_POWER7 (CPUPPCState *env)
6973 {
6974 gen_spr_ne_601(env);
6975 gen_spr_7xx(env);
6976 /* Time base */
6977 gen_tbl(env);
6978 /* Processor identification */
6979 spr_register(env, SPR_PIR, "PIR",
6980 SPR_NOACCESS, SPR_NOACCESS,
6981 &spr_read_generic, &spr_write_pir,
6982 0x00000000);
6983 #if !defined(CONFIG_USER_ONLY)
6984 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
6985 spr_register_kvm(env, SPR_PURR, "PURR",
6986 &spr_read_purr, SPR_NOACCESS,
6987 &spr_read_purr, SPR_NOACCESS,
6988 KVM_REG_PPC_PURR, 0x00000000);
6989 spr_register_kvm(env, SPR_SPURR, "SPURR",
6990 &spr_read_purr, SPR_NOACCESS,
6991 &spr_read_purr, SPR_NOACCESS,
6992 KVM_REG_PPC_SPURR, 0x00000000);
6993 spr_register(env, SPR_CFAR, "SPR_CFAR",
6994 SPR_NOACCESS, SPR_NOACCESS,
6995 &spr_read_cfar, &spr_write_cfar,
6996 0x00000000);
6997 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
6998 SPR_NOACCESS, SPR_NOACCESS,
6999 &spr_read_generic, &spr_write_generic,
7000 KVM_REG_PPC_DSCR, 0x00000000);
7001 spr_register_kvm(env, SPR_MMCRA, "SPR_MMCRA",
7002 SPR_NOACCESS, SPR_NOACCESS,
7003 &spr_read_generic, &spr_write_generic,
7004 KVM_REG_PPC_MMCRA, 0x00000000);
7005 spr_register_kvm(env, SPR_PMC5, "SPR_PMC5",
7006 SPR_NOACCESS, SPR_NOACCESS,
7007 &spr_read_generic, &spr_write_generic,
7008 KVM_REG_PPC_PMC5, 0x00000000);
7009 spr_register_kvm(env, SPR_PMC6, "SPR_PMC6",
7010 SPR_NOACCESS, SPR_NOACCESS,
7011 &spr_read_generic, &spr_write_generic,
7012 KVM_REG_PPC_PMC6, 0x00000000);
7013 #endif /* !CONFIG_USER_ONLY */
7014 gen_spr_amr(env);
7015 /* XXX : not implemented */
7016 spr_register(env, SPR_CTRL, "SPR_CTRLT",
7017 SPR_NOACCESS, SPR_NOACCESS,
7018 SPR_NOACCESS, &spr_write_generic,
7019 0x80800000);
7020 spr_register(env, SPR_UCTRL, "SPR_CTRLF",
7021 SPR_NOACCESS, SPR_NOACCESS,
7022 &spr_read_generic, SPR_NOACCESS,
7023 0x80800000);
7024 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
7025 &spr_read_generic, &spr_write_generic,
7026 &spr_read_generic, &spr_write_generic,
7027 0x00000000);
7028 spr_register(env, SPR_PPR, "PPR",
7029 &spr_read_generic, &spr_write_generic,
7030 &spr_read_generic, &spr_write_generic,
7031 0x00000000);
7032 /* Logical partitionning */
7033 spr_register_kvm(env, SPR_LPCR, "LPCR",
7034 SPR_NOACCESS, SPR_NOACCESS,
7035 &spr_read_generic, &spr_write_generic,
7036 KVM_REG_PPC_LPCR, 0x00000000);
7037 #if !defined(CONFIG_USER_ONLY)
7038 env->slb_nr = 32;
7039 #endif
7040 init_excp_POWER7(env);
7041 env->dcache_line_size = 128;
7042 env->icache_line_size = 128;
7043
7044 /* Allocate hardware IRQ controller */
7045 ppcPOWER7_irq_init(env);
7046 /* Can't find information on what this should be on reset. This
7047 * value is the one used by 74xx processors. */
7048 vscr_init(env, 0x00010000);
7049 }
7050
7051 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
7052 {
7053 DeviceClass *dc = DEVICE_CLASS(oc);
7054 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7055
7056 dc->fw_name = "PowerPC,POWER7";
7057 dc->desc = "POWER7";
7058 pcc->pvr = CPU_POWERPC_POWER7_BASE;
7059 pcc->pvr_mask = CPU_POWERPC_POWER7_MASK;
7060 pcc->init_proc = init_proc_POWER7;
7061 pcc->check_pow = check_pow_nocheck;
7062 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7063 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7064 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7065 PPC_FLOAT_FRSQRTES |
7066 PPC_FLOAT_STFIWX |
7067 PPC_FLOAT_EXT |
7068 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7069 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7070 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7071 PPC_64B | PPC_ALTIVEC |
7072 PPC_SEGMENT_64B | PPC_SLBI |
7073 PPC_POPCNTB | PPC_POPCNTWD;
7074 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
7075 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
7076 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7077 PPC2_FP_TST_ISA206;
7078 pcc->msr_mask = 0x800000000280FF37ULL;
7079 pcc->mmu_model = POWERPC_MMU_2_06;
7080 #if defined(CONFIG_SOFTMMU)
7081 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7082 #endif
7083 pcc->excp_model = POWERPC_EXCP_POWER7;
7084 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7085 pcc->bfd_mach = bfd_mach_ppc64;
7086 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7087 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7088 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7089 POWERPC_FLAG_VSX;
7090 pcc->l1_dcache_size = 0x8000;
7091 pcc->l1_icache_size = 0x8000;
7092 }
7093
7094 POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
7095 {
7096 DeviceClass *dc = DEVICE_CLASS(oc);
7097 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7098
7099 dc->fw_name = "PowerPC,POWER7+";
7100 dc->desc = "POWER7+";
7101 pcc->pvr = CPU_POWERPC_POWER7P_BASE;
7102 pcc->pvr_mask = CPU_POWERPC_POWER7P_MASK;
7103 pcc->init_proc = init_proc_POWER7;
7104 pcc->check_pow = check_pow_nocheck;
7105 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7106 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7107 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7108 PPC_FLOAT_FRSQRTES |
7109 PPC_FLOAT_STFIWX |
7110 PPC_FLOAT_EXT |
7111 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7112 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7113 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7114 PPC_64B | PPC_ALTIVEC |
7115 PPC_SEGMENT_64B | PPC_SLBI |
7116 PPC_POPCNTB | PPC_POPCNTWD;
7117 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
7118 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
7119 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7120 PPC2_FP_TST_ISA206;
7121 pcc->msr_mask = 0x800000000280FF37ULL;
7122 pcc->mmu_model = POWERPC_MMU_2_06;
7123 #if defined(CONFIG_SOFTMMU)
7124 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7125 #endif
7126 pcc->excp_model = POWERPC_EXCP_POWER7;
7127 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7128 pcc->bfd_mach = bfd_mach_ppc64;
7129 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7130 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7131 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7132 POWERPC_FLAG_VSX;
7133 pcc->l1_dcache_size = 0x8000;
7134 pcc->l1_icache_size = 0x8000;
7135 }
7136
7137 static void init_proc_POWER8(CPUPPCState *env)
7138 {
7139 /* inherit P7 */
7140 init_proc_POWER7(env);
7141
7142 /* P8 supports the TAR */
7143 spr_register(env, SPR_TAR, "TAR",
7144 &spr_read_generic, &spr_write_generic,
7145 &spr_read_generic, &spr_write_generic,
7146 0x00000000);
7147 }
7148
7149 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
7150 {
7151 DeviceClass *dc = DEVICE_CLASS(oc);
7152 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7153
7154 dc->fw_name = "PowerPC,POWER8";
7155 dc->desc = "POWER8";
7156 pcc->pvr = CPU_POWERPC_POWER8_BASE;
7157 pcc->pvr_mask = CPU_POWERPC_POWER8_MASK;
7158 pcc->init_proc = init_proc_POWER8;
7159 pcc->check_pow = check_pow_nocheck;
7160 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7161 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7162 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7163 PPC_FLOAT_FRSQRTES |
7164 PPC_FLOAT_STFIWX |
7165 PPC_FLOAT_EXT |
7166 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7167 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7168 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7169 PPC_64B | PPC_64BX | PPC_ALTIVEC |
7170 PPC_SEGMENT_64B | PPC_SLBI |
7171 PPC_POPCNTB | PPC_POPCNTWD;
7172 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
7173 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
7174 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7175 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
7176 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
7177 PPC2_ISA205 | PPC2_ISA207S;
7178 pcc->msr_mask = 0x800000000280FF37ULL;
7179 pcc->mmu_model = POWERPC_MMU_2_06;
7180 #if defined(CONFIG_SOFTMMU)
7181 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7182 #endif
7183 pcc->excp_model = POWERPC_EXCP_POWER7;
7184 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7185 pcc->bfd_mach = bfd_mach_ppc64;
7186 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7187 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7188 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7189 POWERPC_FLAG_VSX;
7190 pcc->l1_dcache_size = 0x8000;
7191 pcc->l1_icache_size = 0x8000;
7192 }
7193 #endif /* defined (TARGET_PPC64) */
7194
7195
7196 /*****************************************************************************/
7197 /* Generic CPU instantiation routine */
7198 static void init_ppc_proc(PowerPCCPU *cpu)
7199 {
7200 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7201 CPUPPCState *env = &cpu->env;
7202 #if !defined(CONFIG_USER_ONLY)
7203 int i;
7204
7205 env->irq_inputs = NULL;
7206 /* Set all exception vectors to an invalid address */
7207 for (i = 0; i < POWERPC_EXCP_NB; i++)
7208 env->excp_vectors[i] = (target_ulong)(-1ULL);
7209 env->ivor_mask = 0x00000000;
7210 env->ivpr_mask = 0x00000000;
7211 /* Default MMU definitions */
7212 env->nb_BATs = 0;
7213 env->nb_tlb = 0;
7214 env->nb_ways = 0;
7215 env->tlb_type = TLB_NONE;
7216 #endif
7217 /* Register SPR common to all PowerPC implementations */
7218 gen_spr_generic(env);
7219 spr_register(env, SPR_PVR, "PVR",
7220 /* Linux permits userspace to read PVR */
7221 #if defined(CONFIG_LINUX_USER)
7222 &spr_read_generic,
7223 #else
7224 SPR_NOACCESS,
7225 #endif
7226 SPR_NOACCESS,
7227 &spr_read_generic, SPR_NOACCESS,
7228 pcc->pvr);
7229 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
7230 if (pcc->svr != POWERPC_SVR_NONE) {
7231 if (pcc->svr & POWERPC_SVR_E500) {
7232 spr_register(env, SPR_E500_SVR, "SVR",
7233 SPR_NOACCESS, SPR_NOACCESS,
7234 &spr_read_generic, SPR_NOACCESS,
7235 pcc->svr & ~POWERPC_SVR_E500);
7236 } else {
7237 spr_register(env, SPR_SVR, "SVR",
7238 SPR_NOACCESS, SPR_NOACCESS,
7239 &spr_read_generic, SPR_NOACCESS,
7240 pcc->svr);
7241 }
7242 }
7243 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
7244 (*pcc->init_proc)(env);
7245
7246 /* MSR bits & flags consistency checks */
7247 if (env->msr_mask & (1 << 25)) {
7248 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7249 case POWERPC_FLAG_SPE:
7250 case POWERPC_FLAG_VRE:
7251 break;
7252 default:
7253 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7254 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
7255 exit(1);
7256 }
7257 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
7258 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7259 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
7260 exit(1);
7261 }
7262 if (env->msr_mask & (1 << 17)) {
7263 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7264 case POWERPC_FLAG_TGPR:
7265 case POWERPC_FLAG_CE:
7266 break;
7267 default:
7268 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7269 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
7270 exit(1);
7271 }
7272 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
7273 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7274 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
7275 exit(1);
7276 }
7277 if (env->msr_mask & (1 << 10)) {
7278 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7279 POWERPC_FLAG_UBLE)) {
7280 case POWERPC_FLAG_SE:
7281 case POWERPC_FLAG_DWE:
7282 case POWERPC_FLAG_UBLE:
7283 break;
7284 default:
7285 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7286 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
7287 "POWERPC_FLAG_UBLE\n");
7288 exit(1);
7289 }
7290 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
7291 POWERPC_FLAG_UBLE)) {
7292 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7293 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
7294 "POWERPC_FLAG_UBLE\n");
7295 exit(1);
7296 }
7297 if (env->msr_mask & (1 << 9)) {
7298 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7299 case POWERPC_FLAG_BE:
7300 case POWERPC_FLAG_DE:
7301 break;
7302 default:
7303 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7304 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
7305 exit(1);
7306 }
7307 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
7308 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7309 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
7310 exit(1);
7311 }
7312 if (env->msr_mask & (1 << 2)) {
7313 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7314 case POWERPC_FLAG_PX:
7315 case POWERPC_FLAG_PMM:
7316 break;
7317 default:
7318 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7319 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
7320 exit(1);
7321 }
7322 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
7323 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
7324 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
7325 exit(1);
7326 }
7327 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
7328 fprintf(stderr, "PowerPC flags inconsistency\n"
7329 "Should define the time-base and decrementer clock source\n");
7330 exit(1);
7331 }
7332 /* Allocate TLBs buffer when needed */
7333 #if !defined(CONFIG_USER_ONLY)
7334 if (env->nb_tlb != 0) {
7335 int nb_tlb = env->nb_tlb;
7336 if (env->id_tlbs != 0)
7337 nb_tlb *= 2;
7338 switch (env->tlb_type) {
7339 case TLB_6XX:
7340 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
7341 break;
7342 case TLB_EMB:
7343 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
7344 break;
7345 case TLB_MAS:
7346 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
7347 break;
7348 }
7349 /* Pre-compute some useful values */
7350 env->tlb_per_way = env->nb_tlb / env->nb_ways;
7351 }
7352 if (env->irq_inputs == NULL) {
7353 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
7354 " Attempt QEMU to crash very soon !\n");
7355 }
7356 #endif
7357 if (env->check_pow == NULL) {
7358 fprintf(stderr, "WARNING: no power management check handler "
7359 "registered.\n"
7360 " Attempt QEMU to crash very soon !\n");
7361 }
7362 }
7363
7364 #if defined(PPC_DUMP_CPU)
7365 static void dump_ppc_sprs (CPUPPCState *env)
7366 {
7367 ppc_spr_t *spr;
7368 #if !defined(CONFIG_USER_ONLY)
7369 uint32_t sr, sw;
7370 #endif
7371 uint32_t ur, uw;
7372 int i, j, n;
7373
7374 printf("Special purpose registers:\n");
7375 for (i = 0; i < 32; i++) {
7376 for (j = 0; j < 32; j++) {
7377 n = (i << 5) | j;
7378 spr = &env->spr_cb[n];
7379 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
7380 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
7381 #if !defined(CONFIG_USER_ONLY)
7382 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
7383 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
7384 if (sw || sr || uw || ur) {
7385 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
7386 (i << 5) | j, (i << 5) | j, spr->name,
7387 sw ? 'w' : '-', sr ? 'r' : '-',
7388 uw ? 'w' : '-', ur ? 'r' : '-');
7389 }
7390 #else
7391 if (uw || ur) {
7392 printf("SPR: %4d (%03x) %-8s u%c%c\n",
7393 (i << 5) | j, (i << 5) | j, spr->name,
7394 uw ? 'w' : '-', ur ? 'r' : '-');
7395 }
7396 #endif
7397 }
7398 }
7399 fflush(stdout);
7400 fflush(stderr);
7401 }
7402 #endif
7403
7404 /*****************************************************************************/
7405 #include <stdlib.h>
7406 #include <string.h>
7407
7408 /* Opcode types */
7409 enum {
7410 PPC_DIRECT = 0, /* Opcode routine */
7411 PPC_INDIRECT = 1, /* Indirect opcode table */
7412 };
7413
7414 static inline int is_indirect_opcode (void *handler)
7415 {
7416 return ((uintptr_t)handler & 0x03) == PPC_INDIRECT;
7417 }
7418
7419 static inline opc_handler_t **ind_table(void *handler)
7420 {
7421 return (opc_handler_t **)((uintptr_t)handler & ~3);
7422 }
7423
7424 /* Instruction table creation */
7425 /* Opcodes tables creation */
7426 static void fill_new_table (opc_handler_t **table, int len)
7427 {
7428 int i;
7429
7430 for (i = 0; i < len; i++)
7431 table[i] = &invalid_handler;
7432 }
7433
7434 static int create_new_table (opc_handler_t **table, unsigned char idx)
7435 {
7436 opc_handler_t **tmp;
7437
7438 tmp = g_new(opc_handler_t *, 0x20);
7439 fill_new_table(tmp, 0x20);
7440 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
7441
7442 return 0;
7443 }
7444
7445 static int insert_in_table (opc_handler_t **table, unsigned char idx,
7446 opc_handler_t *handler)
7447 {
7448 if (table[idx] != &invalid_handler)
7449 return -1;
7450 table[idx] = handler;
7451
7452 return 0;
7453 }
7454
7455 static int register_direct_insn (opc_handler_t **ppc_opcodes,
7456 unsigned char idx, opc_handler_t *handler)
7457 {
7458 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
7459 printf("*** ERROR: opcode %02x already assigned in main "
7460 "opcode table\n", idx);
7461 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
7462 printf(" Registered handler '%s' - new handler '%s'\n",
7463 ppc_opcodes[idx]->oname, handler->oname);
7464 #endif
7465 return -1;
7466 }
7467
7468 return 0;
7469 }
7470
7471 static int register_ind_in_table (opc_handler_t **table,
7472 unsigned char idx1, unsigned char idx2,
7473 opc_handler_t *handler)
7474 {
7475 if (table[idx1] == &invalid_handler) {
7476 if (create_new_table(table, idx1) < 0) {
7477 printf("*** ERROR: unable to create indirect table "
7478 "idx=%02x\n", idx1);
7479 return -1;
7480 }
7481 } else {
7482 if (!is_indirect_opcode(table[idx1])) {
7483 printf("*** ERROR: idx %02x already assigned to a direct "
7484 "opcode\n", idx1);
7485 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
7486 printf(" Registered handler '%s' - new handler '%s'\n",
7487 ind_table(table[idx1])[idx2]->oname, handler->oname);
7488 #endif
7489 return -1;
7490 }
7491 }
7492 if (handler != NULL &&
7493 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
7494 printf("*** ERROR: opcode %02x already assigned in "
7495 "opcode table %02x\n", idx2, idx1);
7496 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
7497 printf(" Registered handler '%s' - new handler '%s'\n",
7498 ind_table(table[idx1])[idx2]->oname, handler->oname);
7499 #endif
7500 return -1;
7501 }
7502
7503 return 0;
7504 }
7505
7506 static int register_ind_insn (opc_handler_t **ppc_opcodes,
7507 unsigned char idx1, unsigned char idx2,
7508 opc_handler_t *handler)
7509 {
7510 int ret;
7511
7512 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
7513
7514 return ret;
7515 }
7516
7517 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
7518 unsigned char idx1, unsigned char idx2,
7519 unsigned char idx3, opc_handler_t *handler)
7520 {
7521 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
7522 printf("*** ERROR: unable to join indirect table idx "
7523 "[%02x-%02x]\n", idx1, idx2);
7524 return -1;
7525 }
7526 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
7527 handler) < 0) {
7528 printf("*** ERROR: unable to insert opcode "
7529 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
7530 return -1;
7531 }
7532
7533 return 0;
7534 }
7535
7536 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
7537 {
7538 if (insn->opc2 != 0xFF) {
7539 if (insn->opc3 != 0xFF) {
7540 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
7541 insn->opc3, &insn->handler) < 0)
7542 return -1;
7543 } else {
7544 if (register_ind_insn(ppc_opcodes, insn->opc1,
7545 insn->opc2, &insn->handler) < 0)
7546 return -1;
7547 }
7548 } else {
7549 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
7550 return -1;
7551 }
7552
7553 return 0;
7554 }
7555
7556 static int test_opcode_table (opc_handler_t **table, int len)
7557 {
7558 int i, count, tmp;
7559
7560 for (i = 0, count = 0; i < len; i++) {
7561 /* Consistency fixup */
7562 if (table[i] == NULL)
7563 table[i] = &invalid_handler;
7564 if (table[i] != &invalid_handler) {
7565 if (is_indirect_opcode(table[i])) {
7566 tmp = test_opcode_table(ind_table(table[i]), 0x20);
7567 if (tmp == 0) {
7568 free(table[i]);
7569 table[i] = &invalid_handler;
7570 } else {
7571 count++;
7572 }
7573 } else {
7574 count++;
7575 }
7576 }
7577 }
7578
7579 return count;
7580 }
7581
7582 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
7583 {
7584 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
7585 printf("*** WARNING: no opcode defined !\n");
7586 }
7587
7588 /*****************************************************************************/
7589 static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
7590 {
7591 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7592 CPUPPCState *env = &cpu->env;
7593 opcode_t *opc;
7594
7595 fill_new_table(env->opcodes, 0x40);
7596 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
7597 if (((opc->handler.type & pcc->insns_flags) != 0) ||
7598 ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
7599 if (register_insn(env->opcodes, opc) < 0) {
7600 error_setg(errp, "ERROR initializing PowerPC instruction "
7601 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
7602 opc->opc3);
7603 return;
7604 }
7605 }
7606 }
7607 fix_opcode_tables(env->opcodes);
7608 fflush(stdout);
7609 fflush(stderr);
7610 }
7611
7612 #if defined(PPC_DUMP_CPU)
7613 static void dump_ppc_insns (CPUPPCState *env)
7614 {
7615 opc_handler_t **table, *handler;
7616 const char *p, *q;
7617 uint8_t opc1, opc2, opc3;
7618
7619 printf("Instructions set:\n");
7620 /* opc1 is 6 bits long */
7621 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
7622 table = env->opcodes;
7623 handler = table[opc1];
7624 if (is_indirect_opcode(handler)) {
7625 /* opc2 is 5 bits long */
7626 for (opc2 = 0; opc2 < 0x20; opc2++) {
7627 table = env->opcodes;
7628 handler = env->opcodes[opc1];
7629 table = ind_table(handler);
7630 handler = table[opc2];
7631 if (is_indirect_opcode(handler)) {
7632 table = ind_table(handler);
7633 /* opc3 is 5 bits long */
7634 for (opc3 = 0; opc3 < 0x20; opc3++) {
7635 handler = table[opc3];
7636 if (handler->handler != &gen_invalid) {
7637 /* Special hack to properly dump SPE insns */
7638 p = strchr(handler->oname, '_');
7639 if (p == NULL) {
7640 printf("INSN: %02x %02x %02x (%02d %04d) : "
7641 "%s\n",
7642 opc1, opc2, opc3, opc1,
7643 (opc3 << 5) | opc2,
7644 handler->oname);
7645 } else {
7646 q = "speundef";
7647 if ((p - handler->oname) != strlen(q) ||
7648 memcmp(handler->oname, q, strlen(q)) != 0) {
7649 /* First instruction */
7650 printf("INSN: %02x %02x %02x (%02d %04d) : "
7651 "%.*s\n",
7652 opc1, opc2 << 1, opc3, opc1,
7653 (opc3 << 6) | (opc2 << 1),
7654 (int)(p - handler->oname),
7655 handler->oname);
7656 }
7657 if (strcmp(p + 1, q) != 0) {
7658 /* Second instruction */
7659 printf("INSN: %02x %02x %02x (%02d %04d) : "
7660 "%s\n",
7661 opc1, (opc2 << 1) | 1, opc3, opc1,
7662 (opc3 << 6) | (opc2 << 1) | 1,
7663 p + 1);
7664 }
7665 }
7666 }
7667 }
7668 } else {
7669 if (handler->handler != &gen_invalid) {
7670 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
7671 opc1, opc2, opc1, opc2, handler->oname);
7672 }
7673 }
7674 }
7675 } else {
7676 if (handler->handler != &gen_invalid) {
7677 printf("INSN: %02x -- -- (%02d ----) : %s\n",
7678 opc1, opc1, handler->oname);
7679 }
7680 }
7681 }
7682 }
7683 #endif
7684
7685 static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7686 {
7687 if (n < 32) {
7688 stfq_p(mem_buf, env->fpr[n]);
7689 return 8;
7690 }
7691 if (n == 32) {
7692 stl_p(mem_buf, env->fpscr);
7693 return 4;
7694 }
7695 return 0;
7696 }
7697
7698 static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7699 {
7700 if (n < 32) {
7701 env->fpr[n] = ldfq_p(mem_buf);
7702 return 8;
7703 }
7704 if (n == 32) {
7705 helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff);
7706 return 4;
7707 }
7708 return 0;
7709 }
7710
7711 static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7712 {
7713 if (n < 32) {
7714 #ifdef HOST_WORDS_BIGENDIAN
7715 stq_p(mem_buf, env->avr[n].u64[0]);
7716 stq_p(mem_buf+8, env->avr[n].u64[1]);
7717 #else
7718 stq_p(mem_buf, env->avr[n].u64[1]);
7719 stq_p(mem_buf+8, env->avr[n].u64[0]);
7720 #endif
7721 return 16;
7722 }
7723 if (n == 32) {
7724 stl_p(mem_buf, env->vscr);
7725 return 4;
7726 }
7727 if (n == 33) {
7728 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
7729 return 4;
7730 }
7731 return 0;
7732 }
7733
7734 static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7735 {
7736 if (n < 32) {
7737 #ifdef HOST_WORDS_BIGENDIAN
7738 env->avr[n].u64[0] = ldq_p(mem_buf);
7739 env->avr[n].u64[1] = ldq_p(mem_buf+8);
7740 #else
7741 env->avr[n].u64[1] = ldq_p(mem_buf);
7742 env->avr[n].u64[0] = ldq_p(mem_buf+8);
7743 #endif
7744 return 16;
7745 }
7746 if (n == 32) {
7747 env->vscr = ldl_p(mem_buf);
7748 return 4;
7749 }
7750 if (n == 33) {
7751 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
7752 return 4;
7753 }
7754 return 0;
7755 }
7756
7757 static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7758 {
7759 if (n < 32) {
7760 #if defined(TARGET_PPC64)
7761 stl_p(mem_buf, env->gpr[n] >> 32);
7762 #else
7763 stl_p(mem_buf, env->gprh[n]);
7764 #endif
7765 return 4;
7766 }
7767 if (n == 32) {
7768 stq_p(mem_buf, env->spe_acc);
7769 return 8;
7770 }
7771 if (n == 33) {
7772 stl_p(mem_buf, env->spe_fscr);
7773 return 4;
7774 }
7775 return 0;
7776 }
7777
7778 static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
7779 {
7780 if (n < 32) {
7781 #if defined(TARGET_PPC64)
7782 target_ulong lo = (uint32_t)env->gpr[n];
7783 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
7784 env->gpr[n] = lo | hi;
7785 #else
7786 env->gprh[n] = ldl_p(mem_buf);
7787 #endif
7788 return 4;
7789 }
7790 if (n == 32) {
7791 env->spe_acc = ldq_p(mem_buf);
7792 return 8;
7793 }
7794 if (n == 33) {
7795 env->spe_fscr = ldl_p(mem_buf);
7796 return 4;
7797 }
7798 return 0;
7799 }
7800
7801 static int ppc_fixup_cpu(PowerPCCPU *cpu)
7802 {
7803 CPUPPCState *env = &cpu->env;
7804
7805 /* TCG doesn't (yet) emulate some groups of instructions that
7806 * are implemented on some otherwise supported CPUs (e.g. VSX
7807 * and decimal floating point instructions on POWER7). We
7808 * remove unsupported instruction groups from the cpu state's
7809 * instruction masks and hope the guest can cope. For at
7810 * least the pseries machine, the unavailability of these
7811 * instructions can be advertised to the guest via the device
7812 * tree. */
7813 if ((env->insns_flags & ~PPC_TCG_INSNS)
7814 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
7815 fprintf(stderr, "Warning: Disabling some instructions which are not "
7816 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n",
7817 env->insns_flags & ~PPC_TCG_INSNS,
7818 env->insns_flags2 & ~PPC_TCG_INSNS2);
7819 }
7820 env->insns_flags &= PPC_TCG_INSNS;
7821 env->insns_flags2 &= PPC_TCG_INSNS2;
7822 return 0;
7823 }
7824
7825 static inline bool ppc_cpu_is_valid(PowerPCCPUClass *pcc)
7826 {
7827 #ifdef TARGET_PPCEMB
7828 return pcc->mmu_model == POWERPC_MMU_BOOKE ||
7829 pcc->mmu_model == POWERPC_MMU_SOFT_4xx ||
7830 pcc->mmu_model == POWERPC_MMU_SOFT_4xx_Z;
7831 #else
7832 return true;
7833 #endif
7834 }
7835
7836 static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
7837 {
7838 CPUState *cs = CPU(dev);
7839 PowerPCCPU *cpu = POWERPC_CPU(dev);
7840 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
7841 Error *local_err = NULL;
7842 #if !defined(CONFIG_USER_ONLY)
7843 int max_smt = kvm_enabled() ? kvmppc_smt_threads() : 1;
7844 #endif
7845
7846 #if !defined(CONFIG_USER_ONLY)
7847 if (smp_threads > max_smt) {
7848 error_setg(errp, "Cannot support more than %d threads on PPC with %s",
7849 max_smt, kvm_enabled() ? "KVM" : "TCG");
7850 return;
7851 }
7852 if (!is_power_of_2(smp_threads)) {
7853 error_setg(errp, "Cannot support %d threads on PPC with %s, "
7854 "threads count must be a power of 2.",
7855 smp_threads, kvm_enabled() ? "KVM" : "TCG");
7856 return;
7857 }
7858
7859 cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * max_smt
7860 + (cs->cpu_index % smp_threads);
7861 #endif
7862
7863 if (tcg_enabled()) {
7864 if (ppc_fixup_cpu(cpu) != 0) {
7865 error_setg(errp, "Unable to emulate selected CPU with TCG");
7866 return;
7867 }
7868 }
7869
7870 #if defined(TARGET_PPCEMB)
7871 if (!ppc_cpu_is_valid(pcc)) {
7872 error_setg(errp, "CPU does not possess a BookE or 4xx MMU. "
7873 "Please use qemu-system-ppc or qemu-system-ppc64 instead "
7874 "or choose another CPU model.");
7875 return;
7876 }
7877 #endif
7878
7879 create_ppc_opcodes(cpu, &local_err);
7880 if (local_err != NULL) {
7881 error_propagate(errp, local_err);
7882 return;
7883 }
7884 init_ppc_proc(cpu);
7885
7886 if (pcc->insns_flags & PPC_FLOAT) {
7887 gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg,
7888 33, "power-fpu.xml", 0);
7889 }
7890 if (pcc->insns_flags & PPC_ALTIVEC) {
7891 gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg,
7892 34, "power-altivec.xml", 0);
7893 }
7894 if (pcc->insns_flags & PPC_SPE) {
7895 gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg,
7896 34, "power-spe.xml", 0);
7897 }
7898
7899 qemu_init_vcpu(cs);
7900
7901 pcc->parent_realize(dev, errp);
7902
7903 #if defined(PPC_DUMP_CPU)
7904 {
7905 CPUPPCState *env = &cpu->env;
7906 const char *mmu_model, *excp_model, *bus_model;
7907 switch (env->mmu_model) {
7908 case POWERPC_MMU_32B:
7909 mmu_model = "PowerPC 32";
7910 break;
7911 case POWERPC_MMU_SOFT_6xx:
7912 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
7913 break;
7914 case POWERPC_MMU_SOFT_74xx:
7915 mmu_model = "PowerPC 74xx with software driven TLBs";
7916 break;
7917 case POWERPC_MMU_SOFT_4xx:
7918 mmu_model = "PowerPC 4xx with software driven TLBs";
7919 break;
7920 case POWERPC_MMU_SOFT_4xx_Z:
7921 mmu_model = "PowerPC 4xx with software driven TLBs "
7922 "and zones protections";
7923 break;
7924 case POWERPC_MMU_REAL:
7925 mmu_model = "PowerPC real mode only";
7926 break;
7927 case POWERPC_MMU_MPC8xx:
7928 mmu_model = "PowerPC MPC8xx";
7929 break;
7930 case POWERPC_MMU_BOOKE:
7931 mmu_model = "PowerPC BookE";
7932 break;
7933 case POWERPC_MMU_BOOKE206:
7934 mmu_model = "PowerPC BookE 2.06";
7935 break;
7936 case POWERPC_MMU_601:
7937 mmu_model = "PowerPC 601";
7938 break;
7939 #if defined (TARGET_PPC64)
7940 case POWERPC_MMU_64B:
7941 mmu_model = "PowerPC 64";
7942 break;
7943 #endif
7944 default:
7945 mmu_model = "Unknown or invalid";
7946 break;
7947 }
7948 switch (env->excp_model) {
7949 case POWERPC_EXCP_STD:
7950 excp_model = "PowerPC";
7951 break;
7952 case POWERPC_EXCP_40x:
7953 excp_model = "PowerPC 40x";
7954 break;
7955 case POWERPC_EXCP_601:
7956 excp_model = "PowerPC 601";
7957 break;
7958 case POWERPC_EXCP_602:
7959 excp_model = "PowerPC 602";
7960 break;
7961 case POWERPC_EXCP_603:
7962 excp_model = "PowerPC 603";
7963 break;
7964 case POWERPC_EXCP_603E:
7965 excp_model = "PowerPC 603e";
7966 break;
7967 case POWERPC_EXCP_604:
7968 excp_model = "PowerPC 604";
7969 break;
7970 case POWERPC_EXCP_7x0:
7971 excp_model = "PowerPC 740/750";
7972 break;
7973 case POWERPC_EXCP_7x5:
7974 excp_model = "PowerPC 745/755";
7975 break;
7976 case POWERPC_EXCP_74xx:
7977 excp_model = "PowerPC 74xx";
7978 break;
7979 case POWERPC_EXCP_BOOKE:
7980 excp_model = "PowerPC BookE";
7981 break;
7982 #if defined (TARGET_PPC64)
7983 case POWERPC_EXCP_970:
7984 excp_model = "PowerPC 970";
7985 break;
7986 #endif
7987 default:
7988 excp_model = "Unknown or invalid";
7989 break;
7990 }
7991 switch (env->bus_model) {
7992 case PPC_FLAGS_INPUT_6xx:
7993 bus_model = "PowerPC 6xx";
7994 break;
7995 case PPC_FLAGS_INPUT_BookE:
7996 bus_model = "PowerPC BookE";
7997 break;
7998 case PPC_FLAGS_INPUT_405:
7999 bus_model = "PowerPC 405";
8000 break;
8001 case PPC_FLAGS_INPUT_401:
8002 bus_model = "PowerPC 401/403";
8003 break;
8004 case PPC_FLAGS_INPUT_RCPU:
8005 bus_model = "RCPU / MPC8xx";
8006 break;
8007 #if defined (TARGET_PPC64)
8008 case PPC_FLAGS_INPUT_970:
8009 bus_model = "PowerPC 970";
8010 break;
8011 #endif
8012 default:
8013 bus_model = "Unknown or invalid";
8014 break;
8015 }
8016 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
8017 " MMU model : %s\n",
8018 object_class_get_name(OBJECT_CLASS(pcc)),
8019 pcc->pvr, pcc->msr_mask, mmu_model);
8020 #if !defined(CONFIG_USER_ONLY)
8021 if (env->tlb.tlb6) {
8022 printf(" %d %s TLB in %d ways\n",
8023 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
8024 env->nb_ways);
8025 }
8026 #endif
8027 printf(" Exceptions model : %s\n"
8028 " Bus model : %s\n",
8029 excp_model, bus_model);
8030 printf(" MSR features :\n");
8031 if (env->flags & POWERPC_FLAG_SPE)
8032 printf(" signal processing engine enable"
8033 "\n");
8034 else if (env->flags & POWERPC_FLAG_VRE)
8035 printf(" vector processor enable\n");
8036 if (env->flags & POWERPC_FLAG_TGPR)
8037 printf(" temporary GPRs\n");
8038 else if (env->flags & POWERPC_FLAG_CE)
8039 printf(" critical input enable\n");
8040 if (env->flags & POWERPC_FLAG_SE)
8041 printf(" single-step trace mode\n");
8042 else if (env->flags & POWERPC_FLAG_DWE)
8043 printf(" debug wait enable\n");
8044 else if (env->flags & POWERPC_FLAG_UBLE)
8045 printf(" user BTB lock enable\n");
8046 if (env->flags & POWERPC_FLAG_BE)
8047 printf(" branch-step trace mode\n");
8048 else if (env->flags & POWERPC_FLAG_DE)
8049 printf(" debug interrupt enable\n");
8050 if (env->flags & POWERPC_FLAG_PX)
8051 printf(" inclusive protection\n");
8052 else if (env->flags & POWERPC_FLAG_PMM)
8053 printf(" performance monitor mark\n");
8054 if (env->flags == POWERPC_FLAG_NONE)
8055 printf(" none\n");
8056 printf(" Time-base/decrementer clock source: %s\n",
8057 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
8058 dump_ppc_insns(env);
8059 dump_ppc_sprs(env);
8060 fflush(stdout);
8061 }
8062 #endif
8063 }
8064
8065 static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp)
8066 {
8067 PowerPCCPU *cpu = POWERPC_CPU(dev);
8068 CPUPPCState *env = &cpu->env;
8069 int i;
8070
8071 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
8072 if (env->opcodes[i] != &invalid_handler) {
8073 g_free(env->opcodes[i]);
8074 }
8075 }
8076 }
8077
8078 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
8079 {
8080 ObjectClass *oc = (ObjectClass *)a;
8081 uint32_t pvr = *(uint32_t *)b;
8082 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
8083
8084 /* -cpu host does a PVR lookup during construction */
8085 if (unlikely(strcmp(object_class_get_name(oc),
8086 TYPE_HOST_POWERPC_CPU) == 0)) {
8087 return -1;
8088 }
8089
8090 if (!ppc_cpu_is_valid(pcc)) {
8091 return -1;
8092 }
8093
8094 return pcc->pvr == pvr ? 0 : -1;
8095 }
8096
8097 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
8098 {
8099 GSList *list, *item;
8100 PowerPCCPUClass *pcc = NULL;
8101
8102 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8103 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
8104 if (item != NULL) {
8105 pcc = POWERPC_CPU_CLASS(item->data);
8106 }
8107 g_slist_free(list);
8108
8109 return pcc;
8110 }
8111
8112 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
8113 {
8114 ObjectClass *oc = (ObjectClass *)a;
8115 uint32_t pvr = *(uint32_t *)b;
8116 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
8117 gint ret;
8118
8119 /* -cpu host does a PVR lookup during construction */
8120 if (unlikely(strcmp(object_class_get_name(oc),
8121 TYPE_HOST_POWERPC_CPU) == 0)) {
8122 return -1;
8123 }
8124
8125 if (!ppc_cpu_is_valid(pcc)) {
8126 return -1;
8127 }
8128
8129 ret = (((pcc->pvr & pcc->pvr_mask) == (pvr & pcc->pvr_mask)) ? 0 : -1);
8130
8131 return ret;
8132 }
8133
8134 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
8135 {
8136 GSList *list, *item;
8137 PowerPCCPUClass *pcc = NULL;
8138
8139 list = object_class_get_list(TYPE_POWERPC_CPU, true);
8140 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
8141 if (item != NULL) {
8142 pcc = POWERPC_CPU_CLASS(item->data);
8143 }
8144 g_slist_free(list);
8145
8146 return pcc;
8147 }
8148
8149 static gint ppc_cpu_compare_class_name(gconstpointer a, gconstpointer b)
8150 {
8151 ObjectClass *oc = (ObjectClass *)a;
8152 const char *name = b;
8153 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8154
8155 if (strncasecmp(name, object_class_get_name(oc), strlen(name)) == 0 &&
8156 ppc_cpu_is_valid(pcc) &&
8157 strcmp(object_class_get_name(oc) + strlen(name),
8158 "-" TYPE_POWERPC_CPU) == 0) {
8159 return 0;
8160 }
8161 return -1;
8162 }
8163
8164 #include <ctype.h>
8165
8166 static ObjectClass *ppc_cpu_class_by_name(const char *name);
8167
8168 static ObjectClass *ppc_cpu_class_by_alias(PowerPCCPUAlias *alias)
8169 {
8170 ObjectClass *invalid_class = (void*)ppc_cpu_class_by_alias;
8171
8172 /* Cache target class lookups in the alias table */
8173 if (!alias->oc) {
8174 alias->oc = ppc_cpu_class_by_name(alias->model);
8175 if (!alias->oc) {
8176 /* Fast check for non-existing aliases */
8177 alias->oc = invalid_class;
8178 }
8179 }
8180
8181 if (alias->oc == invalid_class) {
8182 return NULL;
8183 } else {
8184 return alias->oc;
8185 }
8186 }
8187
8188 static ObjectClass *ppc_cpu_class_by_name(const char *name)
8189 {
8190 GSList *list, *item;
8191 ObjectClass *ret = NULL;
8192 const char *p;
8193 int i, len;
8194
8195 /* Check if the given name is a PVR */
8196 len = strlen(name);
8197 if (len == 10 && name[0] == '0' && name[1] == 'x') {
8198 p = name + 2;
8199 goto check_pvr;
8200 } else if (len == 8) {
8201 p = name;
8202 check_pvr:
8203 for (i = 0; i < 8; i++) {
8204 if (!qemu_isxdigit(*p++))
8205 break;
8206 }
8207 if (i == 8) {
8208 ret = OBJECT_CLASS(ppc_cpu_class_by_pvr(strtoul(name, NULL, 16)));
8209 return ret;
8210 }
8211 }
8212
8213 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
8214 if (strcmp(ppc_cpu_aliases[i].alias, name) == 0) {
8215 return ppc_cpu_class_by_alias(&ppc_cpu_aliases[i]);
8216 }
8217 }
8218
8219 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8220 item = g_slist_find_custom(list, name, ppc_cpu_compare_class_name);
8221 if (item != NULL) {
8222 ret = OBJECT_CLASS(item->data);
8223 }
8224 g_slist_free(list);
8225
8226 return ret;
8227 }
8228
8229 PowerPCCPU *cpu_ppc_init(const char *cpu_model)
8230 {
8231 return POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, cpu_model));
8232 }
8233
8234 /* Sort by PVR, ordering special case "host" last. */
8235 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
8236 {
8237 ObjectClass *oc_a = (ObjectClass *)a;
8238 ObjectClass *oc_b = (ObjectClass *)b;
8239 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
8240 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
8241 const char *name_a = object_class_get_name(oc_a);
8242 const char *name_b = object_class_get_name(oc_b);
8243
8244 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
8245 return 1;
8246 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
8247 return -1;
8248 } else {
8249 /* Avoid an integer overflow during subtraction */
8250 if (pcc_a->pvr < pcc_b->pvr) {
8251 return -1;
8252 } else if (pcc_a->pvr > pcc_b->pvr) {
8253 return 1;
8254 } else {
8255 return 0;
8256 }
8257 }
8258 }
8259
8260 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
8261 {
8262 ObjectClass *oc = data;
8263 CPUListState *s = user_data;
8264 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8265 const char *typename = object_class_get_name(oc);
8266 char *name;
8267 int i;
8268
8269 if (!ppc_cpu_is_valid(pcc)) {
8270 return;
8271 }
8272 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
8273 return;
8274 }
8275
8276 name = g_strndup(typename,
8277 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
8278 (*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
8279 name, pcc->pvr);
8280 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
8281 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
8282 ObjectClass *alias_oc = ppc_cpu_class_by_alias(alias);
8283
8284 if (alias_oc != oc) {
8285 continue;
8286 }
8287 (*s->cpu_fprintf)(s->file, "PowerPC %-16s (alias for %s)\n",
8288 alias->alias, name);
8289 }
8290 g_free(name);
8291 }
8292
8293 void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
8294 {
8295 CPUListState s = {
8296 .file = f,
8297 .cpu_fprintf = cpu_fprintf,
8298 };
8299 GSList *list;
8300
8301 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8302 list = g_slist_sort(list, ppc_cpu_list_compare);
8303 g_slist_foreach(list, ppc_cpu_list_entry, &s);
8304 g_slist_free(list);
8305
8306 #ifdef CONFIG_KVM
8307 cpu_fprintf(f, "\n");
8308 cpu_fprintf(f, "PowerPC %-16s\n", "host");
8309 #endif
8310 }
8311
8312 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
8313 {
8314 ObjectClass *oc = data;
8315 CpuDefinitionInfoList **first = user_data;
8316 const char *typename;
8317 CpuDefinitionInfoList *entry;
8318 CpuDefinitionInfo *info;
8319 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8320
8321 if (!ppc_cpu_is_valid(pcc)) {
8322 return;
8323 }
8324
8325 typename = object_class_get_name(oc);
8326 info = g_malloc0(sizeof(*info));
8327 info->name = g_strndup(typename,
8328 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
8329
8330 entry = g_malloc0(sizeof(*entry));
8331 entry->value = info;
8332 entry->next = *first;
8333 *first = entry;
8334 }
8335
8336 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
8337 {
8338 CpuDefinitionInfoList *cpu_list = NULL;
8339 GSList *list;
8340 int i;
8341
8342 list = object_class_get_list(TYPE_POWERPC_CPU, false);
8343 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
8344 g_slist_free(list);
8345
8346 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
8347 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
8348 ObjectClass *oc;
8349 CpuDefinitionInfoList *entry;
8350 CpuDefinitionInfo *info;
8351
8352 oc = ppc_cpu_class_by_alias(alias);
8353 if (oc == NULL) {
8354 continue;
8355 }
8356
8357 info = g_malloc0(sizeof(*info));
8358 info->name = g_strdup(alias->alias);
8359
8360 entry = g_malloc0(sizeof(*entry));
8361 entry->value = info;
8362 entry->next = cpu_list;
8363 cpu_list = entry;
8364 }
8365
8366 return cpu_list;
8367 }
8368
8369 static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
8370 {
8371 PowerPCCPU *cpu = POWERPC_CPU(cs);
8372
8373 cpu->env.nip = value;
8374 }
8375
8376 static bool ppc_cpu_has_work(CPUState *cs)
8377 {
8378 PowerPCCPU *cpu = POWERPC_CPU(cs);
8379 CPUPPCState *env = &cpu->env;
8380
8381 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
8382 }
8383
8384 /* CPUClass::reset() */
8385 static void ppc_cpu_reset(CPUState *s)
8386 {
8387 PowerPCCPU *cpu = POWERPC_CPU(s);
8388 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8389 CPUPPCState *env = &cpu->env;
8390 target_ulong msr;
8391 int i;
8392
8393 pcc->parent_reset(s);
8394
8395 msr = (target_ulong)0;
8396 if (0) {
8397 /* XXX: find a suitable condition to enable the hypervisor mode */
8398 msr |= (target_ulong)MSR_HVB;
8399 }
8400 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
8401 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
8402 msr |= (target_ulong)1 << MSR_EP;
8403 #if defined(DO_SINGLE_STEP) && 0
8404 /* Single step trace mode */
8405 msr |= (target_ulong)1 << MSR_SE;
8406 msr |= (target_ulong)1 << MSR_BE;
8407 #endif
8408 #if defined(CONFIG_USER_ONLY)
8409 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
8410 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
8411 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
8412 msr |= (target_ulong)1 << MSR_PR;
8413 #endif
8414
8415 #if defined(TARGET_PPC64)
8416 if (env->mmu_model & POWERPC_MMU_64) {
8417 env->msr |= (1ULL << MSR_SF);
8418 }
8419 #endif
8420
8421 hreg_store_msr(env, msr, 1);
8422
8423 #if !defined(CONFIG_USER_ONLY)
8424 env->nip = env->hreset_vector | env->excp_prefix;
8425 if (env->mmu_model != POWERPC_MMU_REAL) {
8426 ppc_tlb_invalidate_all(env);
8427 }
8428 #endif
8429
8430 hreg_compute_hflags(env);
8431 env->reserve_addr = (target_ulong)-1ULL;
8432 /* Be sure no exception or interrupt is pending */
8433 env->pending_interrupts = 0;
8434 s->exception_index = POWERPC_EXCP_NONE;
8435 env->error_code = 0;
8436
8437 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
8438 env->vpa_addr = 0;
8439 env->slb_shadow_addr = 0;
8440 env->slb_shadow_size = 0;
8441 env->dtl_addr = 0;
8442 env->dtl_size = 0;
8443 #endif /* TARGET_PPC64 */
8444
8445 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
8446 ppc_spr_t *spr = &env->spr_cb[i];
8447
8448 if (!spr->name) {
8449 continue;
8450 }
8451 env->spr[i] = spr->default_value;
8452 }
8453
8454 /* Flush all TLBs */
8455 tlb_flush(s, 1);
8456 }
8457
8458 static void ppc_cpu_initfn(Object *obj)
8459 {
8460 CPUState *cs = CPU(obj);
8461 PowerPCCPU *cpu = POWERPC_CPU(obj);
8462 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8463 CPUPPCState *env = &cpu->env;
8464
8465 cs->env_ptr = env;
8466 cpu_exec_init(env);
8467 cpu->cpu_dt_id = cs->cpu_index;
8468
8469 env->msr_mask = pcc->msr_mask;
8470 env->mmu_model = pcc->mmu_model;
8471 env->excp_model = pcc->excp_model;
8472 env->bus_model = pcc->bus_model;
8473 env->insns_flags = pcc->insns_flags;
8474 env->insns_flags2 = pcc->insns_flags2;
8475 env->flags = pcc->flags;
8476 env->bfd_mach = pcc->bfd_mach;
8477 env->check_pow = pcc->check_pow;
8478
8479 #if defined(TARGET_PPC64)
8480 if (pcc->sps) {
8481 env->sps = *pcc->sps;
8482 } else if (env->mmu_model & POWERPC_MMU_64) {
8483 /* Use default sets of page sizes */
8484 static const struct ppc_segment_page_sizes defsps = {
8485 .sps = {
8486 { .page_shift = 12, /* 4K */
8487 .slb_enc = 0,
8488 .enc = { { .page_shift = 12, .pte_enc = 0 } }
8489 },
8490 { .page_shift = 24, /* 16M */
8491 .slb_enc = 0x100,
8492 .enc = { { .page_shift = 24, .pte_enc = 0 } }
8493 },
8494 },
8495 };
8496 env->sps = defsps;
8497 }
8498 #endif /* defined(TARGET_PPC64) */
8499
8500 if (tcg_enabled()) {
8501 ppc_translate_init();
8502 }
8503 }
8504
8505 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
8506 {
8507 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
8508 CPUClass *cc = CPU_CLASS(oc);
8509 DeviceClass *dc = DEVICE_CLASS(oc);
8510
8511 pcc->parent_realize = dc->realize;
8512 pcc->pvr = CPU_POWERPC_DEFAULT_MASK;
8513 pcc->pvr_mask = CPU_POWERPC_DEFAULT_MASK;
8514 dc->realize = ppc_cpu_realizefn;
8515 dc->unrealize = ppc_cpu_unrealizefn;
8516
8517 pcc->parent_reset = cc->reset;
8518 cc->reset = ppc_cpu_reset;
8519
8520 cc->class_by_name = ppc_cpu_class_by_name;
8521 cc->has_work = ppc_cpu_has_work;
8522 cc->do_interrupt = ppc_cpu_do_interrupt;
8523 cc->dump_state = ppc_cpu_dump_state;
8524 cc->dump_statistics = ppc_cpu_dump_statistics;
8525 cc->set_pc = ppc_cpu_set_pc;
8526 cc->gdb_read_register = ppc_cpu_gdb_read_register;
8527 cc->gdb_write_register = ppc_cpu_gdb_write_register;
8528 #ifdef CONFIG_USER_ONLY
8529 cc->handle_mmu_fault = ppc_cpu_handle_mmu_fault;
8530 #else
8531 cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
8532 cc->vmsd = &vmstate_ppc_cpu;
8533 #if defined(TARGET_PPC64)
8534 cc->write_elf64_note = ppc64_cpu_write_elf64_note;
8535 cc->write_elf64_qemunote = ppc64_cpu_write_elf64_qemunote;
8536 #endif
8537 #endif
8538
8539 cc->gdb_num_core_regs = 71;
8540 #if defined(TARGET_PPC64)
8541 cc->gdb_core_xml_file = "power64-core.xml";
8542 #else
8543 cc->gdb_core_xml_file = "power-core.xml";
8544 #endif
8545
8546 dc->fw_name = "PowerPC,UNKNOWN";
8547 }
8548
8549 static const TypeInfo ppc_cpu_type_info = {
8550 .name = TYPE_POWERPC_CPU,
8551 .parent = TYPE_CPU,
8552 .instance_size = sizeof(PowerPCCPU),
8553 .instance_init = ppc_cpu_initfn,
8554 .abstract = true,
8555 .class_size = sizeof(PowerPCCPUClass),
8556 .class_init = ppc_cpu_class_init,
8557 };
8558
8559 static void ppc_cpu_register_types(void)
8560 {
8561 type_register_static(&ppc_cpu_type_info);
8562 }
8563
8564 type_init(ppc_cpu_register_types)
AR7 emulation for QEMU