hw/block/pflash_cfi02.c

   1 /*
   2  *  CFI parallel flash with AMD command set emulation
   3  *
   4  *  Copyright (c) 2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 /*
  21  * For now, this code can emulate flashes of 1, 2 or 4 bytes width.
  22  * Supported commands/modes are:
  23  * - flash read
  24  * - flash write
  25  * - flash ID read
  26  * - sector erase
  27  * - chip erase
  28  * - unlock bypass command
  29  * - CFI queries
  30  *
  31  * It does not support flash interleaving.
  32  * It does not implement boot blocs with reduced size
  33  * It does not implement software data protection as found in many real chips
  34  * It does not implement erase suspend/resume commands
  35  * It does not implement multiple sectors erase
  36  */
  37
  38 #include "hw/hw.h"
  39 #include "hw/block/flash.h"
  40 #include "qemu/timer.h"
  41 #include "sysemu/block-backend.h"
  42 #include "exec/address-spaces.h"
  43 #include "qemu/host-utils.h"
  44 #include "hw/sysbus.h"
  45
  46 //#define PFLASH_DEBUG
  47 #ifdef PFLASH_DEBUG
  48 #define DPRINTF(fmt, ...)                                  \
  49 do {                                                       \
  50     fprintf(stderr, "PFLASH: " fmt , ## __VA_ARGS__);       \
  51 } while (0)
  52 #else
  53 #define DPRINTF(fmt, ...) do { } while (0)
  54 #endif
  55
  56 #define PFLASH_LAZY_ROMD_THRESHOLD 42
  57
  58 #define TYPE_CFI_PFLASH02 "cfi.pflash02"
  59 #define CFI_PFLASH02(obj) OBJECT_CHECK(pflash_t, (obj), TYPE_CFI_PFLASH02)
  60
  61 struct pflash_t {
  62     /*< private >*/
  63     SysBusDevice parent_obj;
  64     /*< public >*/
  65
  66     BlockBackend *blk;
  67     uint32_t sector_len;
  68     uint32_t nb_blocs;
  69     uint32_t chip_len;
  70     uint8_t mappings;
  71     uint8_t width;
  72     uint8_t be;
  73     int wcycle; /* if 0, the flash is read normally */
  74     int bypass;
  75     int ro;
  76     uint8_t cmd;
  77     uint8_t status;
  78     /* FIXME: implement array device properties */
  79     uint16_t ident0;
  80     uint16_t ident1;
  81     uint16_t ident2;
  82     uint16_t ident3;
  83     uint16_t unlock_addr0;
  84     uint16_t unlock_addr1;
  85     uint8_t cfi_len;
  86     uint8_t cfi_table[0x52];
  87     QEMUTimer *timer;
  88     /* The device replicates the flash memory across its memory space.  Emulate
  89      * that by having a container (.mem) filled with an array of aliases
  90      * (.mem_mappings) pointing to the flash memory (.orig_mem).
  91      */
  92     MemoryRegion mem;
  93     MemoryRegion *mem_mappings;    /* array; one per mapping */
  94     MemoryRegion orig_mem;
  95     int rom_mode;
  96     int read_counter; /* used for lazy switch-back to rom mode */
  97     char *name;
  98     void *storage;
  99 };
 100
 101 /*
 102  * Set up replicated mappings of the same region.
 103  */
 104 static void pflash_setup_mappings(pflash_t *pfl)
 105 {
 106     unsigned i;
 107     hwaddr size = memory_region_size(&pfl->orig_mem);
 108
 109     memory_region_init(&pfl->mem, OBJECT(pfl), "pflash", pfl->mappings * size);
 110     pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings);
 111     for (i = 0; i < pfl->mappings; ++i) {
 112         memory_region_init_alias(&pfl->mem_mappings[i], OBJECT(pfl),
 113                                  "pflash-alias", &pfl->orig_mem, 0, size);
 114         memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]);
 115     }
 116 }
 117
 118 static void pflash_register_memory(pflash_t *pfl, int rom_mode)
 119 {
 120     memory_region_rom_device_set_romd(&pfl->orig_mem, rom_mode);
 121     pfl->rom_mode = rom_mode;
 122 }
 123
 124 static void pflash_timer (void *opaque)
 125 {
 126     pflash_t *pfl = opaque;
 127
 128     DPRINTF("%s: command %02x done\n", __func__, pfl->cmd);
 129     /* Reset flash */
 130     pfl->status ^= 0x80;
 131     if (pfl->bypass) {
 132         pfl->wcycle = 2;
 133     } else {
 134         pflash_register_memory(pfl, 1);
 135         pfl->wcycle = 0;
 136     }
 137     pfl->cmd = 0;
 138 }
 139
 140 static uint32_t pflash_read (pflash_t *pfl, hwaddr offset,
 141                              int width, int be)
 142 {
 143     hwaddr boff;
 144     uint32_t ret;
 145     uint8_t *p;
 146
 147     DPRINTF("%s: offset " TARGET_FMT_plx "\n", __func__, offset);
 148     ret = -1;
 149     /* Lazy reset to ROMD mode after a certain amount of read accesses */
 150     if (!pfl->rom_mode && pfl->wcycle == 0 &&
 151         ++pfl->read_counter > PFLASH_LAZY_ROMD_THRESHOLD) {
 152         pflash_register_memory(pfl, 1);
 153     }
 154     offset &= pfl->chip_len - 1;
 155     boff = offset & 0xFF;
 156     if (pfl->width == 2)
 157         boff = boff >> 1;
 158     else if (pfl->width == 4)
 159         boff = boff >> 2;
 160     switch (pfl->cmd) {
 161     default:
 162         /* This should never happen : reset state & treat it as a read*/
 163         DPRINTF("%s: unknown command state: %x\n", __func__, pfl->cmd);
 164         pfl->wcycle = 0;
 165         pfl->cmd = 0;
 166         /* fall through to the read code */
 167     case 0x80:
 168         /* We accept reads during second unlock sequence... */
 169     case 0x00:
 170     flash_read:
 171         /* Flash area read */
 172         p = pfl->storage;
 173         switch (width) {
 174         case 1:
 175             ret = p[offset];
 176 //            DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret);
 177             break;
 178         case 2:
 179             if (be) {
 180                 ret = p[offset] << 8;
 181                 ret |= p[offset + 1];
 182             } else {
 183                 ret = p[offset];
 184                 ret |= p[offset + 1] << 8;
 185             }
 186 //            DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret);
 187             break;
 188         case 4:
 189             if (be) {
 190                 ret = p[offset] << 24;
 191                 ret |= p[offset + 1] << 16;
 192                 ret |= p[offset + 2] << 8;
 193                 ret |= p[offset + 3];
 194             } else {
 195                 ret = p[offset];
 196                 ret |= p[offset + 1] << 8;
 197                 ret |= p[offset + 2] << 16;
 198                 ret |= p[offset + 3] << 24;
 199             }
 200 //            DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
 201             break;
 202         }
 203         break;
 204     case 0x90:
 205         /* flash ID read */
 206         switch (boff) {
 207         case 0x00:
 208         case 0x01:
 209             ret = boff & 0x01 ? pfl->ident1 : pfl->ident0;
 210             break;
 211         case 0x02:
 212             ret = 0x00; /* Pretend all sectors are unprotected */
 213             break;
 214         case 0x0E:
 215         case 0x0F:
 216             ret = boff & 0x01 ? pfl->ident3 : pfl->ident2;
 217             if (ret == (uint8_t)-1) {
 218                 goto flash_read;
 219             }
 220             break;
 221         default:
 222             goto flash_read;
 223         }
 224         DPRINTF("%s: ID " TARGET_FMT_plx " %x\n", __func__, boff, ret);
 225         break;
 226     case 0xA0:
 227     case 0x10:
 228     case 0x30:
 229         /* Status register read */
 230         ret = pfl->status;
 231         DPRINTF("%s: status %x\n", __func__, ret);
 232         /* Toggle bit 6 */
 233         pfl->status ^= 0x40;
 234         break;
 235     case 0x98:
 236         /* CFI query mode */
 237         if (boff > pfl->cfi_len)
 238             ret = 0;
 239         else
 240             ret = pfl->cfi_table[boff];
 241         break;
 242     }
 243
 244     return ret;
 245 }
 246
 247 /* update flash content on disk */
 248 static void pflash_update(pflash_t *pfl, int offset,
 249                           int size)
 250 {
 251     int offset_end;
 252     if (pfl->blk) {
 253         offset_end = offset + size;
 254         /* round to sectors */
 255         offset = offset >> 9;
 256         offset_end = (offset_end + 511) >> 9;
 257         blk_write(pfl->blk, offset, pfl->storage + (offset << 9),
 258                   offset_end - offset);
 259     }
 260 }
 261
 262 static void pflash_write (pflash_t *pfl, hwaddr offset,
 263                           uint32_t value, int width, int be)
 264 {
 265     hwaddr boff;
 266     uint8_t *p;
 267     uint8_t cmd;
 268
 269     cmd = value;
 270     if (pfl->cmd != 0xA0 && cmd == 0xF0) {
 271 #if 0
 272         DPRINTF("%s: flash reset asked (%02x %02x)\n",
 273                 __func__, pfl->cmd, cmd);
 274 #endif
 275         goto reset_flash;
 276     }
 277     DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d %d\n", __func__,
 278             offset, value, width, pfl->wcycle);
 279     offset &= pfl->chip_len - 1;
 280
 281     DPRINTF("%s: offset " TARGET_FMT_plx " %08x %d\n", __func__,
 282             offset, value, width);
 283     boff = offset & (pfl->sector_len - 1);
 284     if (pfl->width == 2)
 285         boff = boff >> 1;
 286     else if (pfl->width == 4)
 287         boff = boff >> 2;
 288     switch (pfl->wcycle) {
 289     case 0:
 290         /* Set the device in I/O access mode if required */
 291         if (pfl->rom_mode)
 292             pflash_register_memory(pfl, 0);
 293         pfl->read_counter = 0;
 294         /* We're in read mode */
 295     check_unlock0:
 296         if (boff == 0x55 && cmd == 0x98) {
 297         enter_CFI_mode:
 298             /* Enter CFI query mode */
 299             pfl->wcycle = 7;
 300             pfl->cmd = 0x98;
 301             return;
 302         }
 303         if (boff != pfl->unlock_addr0 || cmd != 0xAA) {
 304             DPRINTF("%s: unlock0 failed " TARGET_FMT_plx " %02x %04x\n",
 305                     __func__, boff, cmd, pfl->unlock_addr0);
 306             goto reset_flash;
 307         }
 308         DPRINTF("%s: unlock sequence started\n", __func__);
 309         break;
 310     case 1:
 311         /* We started an unlock sequence */
 312     check_unlock1:
 313         if (boff != pfl->unlock_addr1 || cmd != 0x55) {
 314             DPRINTF("%s: unlock1 failed " TARGET_FMT_plx " %02x\n", __func__,
 315                     boff, cmd);
 316             goto reset_flash;
 317         }
 318         DPRINTF("%s: unlock sequence done\n", __func__);
 319         break;
 320     case 2:
 321         /* We finished an unlock sequence */
 322         if (!pfl->bypass && boff != pfl->unlock_addr0) {
 323             DPRINTF("%s: command failed " TARGET_FMT_plx " %02x\n", __func__,
 324                     boff, cmd);
 325             goto reset_flash;
 326         }
 327         switch (cmd) {
 328         case 0x20:
 329             pfl->bypass = 1;
 330             goto do_bypass;
 331         case 0x80:
 332         case 0x90:
 333         case 0xA0:
 334             pfl->cmd = cmd;
 335             DPRINTF("%s: starting command %02x\n", __func__, cmd);
 336             break;
 337         default:
 338             DPRINTF("%s: unknown command %02x\n", __func__, cmd);
 339             goto reset_flash;
 340         }
 341         break;
 342     case 3:
 343         switch (pfl->cmd) {
 344         case 0x80:
 345             /* We need another unlock sequence */
 346             goto check_unlock0;
 347         case 0xA0:
 348             DPRINTF("%s: write data offset " TARGET_FMT_plx " %08x %d\n",
 349                     __func__, offset, value, width);
 350             p = pfl->storage;
 351             if (!pfl->ro) {
 352                 switch (width) {
 353                 case 1:
 354                     p[offset] &= value;
 355                     pflash_update(pfl, offset, 1);
 356                     break;
 357                 case 2:
 358                     if (be) {
 359                         p[offset] &= value >> 8;
 360                         p[offset + 1] &= value;
 361                     } else {
 362                         p[offset] &= value;
 363                         p[offset + 1] &= value >> 8;
 364                     }
 365                     pflash_update(pfl, offset, 2);
 366                     break;
 367                 case 4:
 368                     if (be) {
 369                         p[offset] &= value >> 24;
 370                         p[offset + 1] &= value >> 16;
 371                         p[offset + 2] &= value >> 8;
 372                         p[offset + 3] &= value;
 373                     } else {
 374                         p[offset] &= value;
 375                         p[offset + 1] &= value >> 8;
 376                         p[offset + 2] &= value >> 16;
 377                         p[offset + 3] &= value >> 24;
 378                     }
 379                     pflash_update(pfl, offset, 4);
 380                     break;
 381                 }
 382             }
 383             pfl->status = 0x00 | ~(value & 0x80);
 384             /* Let's pretend write is immediate */
 385             if (pfl->bypass)
 386                 goto do_bypass;
 387             goto reset_flash;
 388         case 0x90:
 389             if (pfl->bypass && cmd == 0x00) {
 390                 /* Unlock bypass reset */
 391                 goto reset_flash;
 392             }
 393             /* We can enter CFI query mode from autoselect mode */
 394             if (boff == 0x55 && cmd == 0x98)
 395                 goto enter_CFI_mode;
 396             /* No break here */
 397         default:
 398             DPRINTF("%s: invalid write for command %02x\n",
 399                     __func__, pfl->cmd);
 400             goto reset_flash;
 401         }
 402     case 4:
 403         switch (pfl->cmd) {
 404         case 0xA0:
 405             /* Ignore writes while flash data write is occurring */
 406             /* As we suppose write is immediate, this should never happen */
 407             return;
 408         case 0x80:
 409             goto check_unlock1;
 410         default:
 411             /* Should never happen */
 412             DPRINTF("%s: invalid command state %02x (wc 4)\n",
 413                     __func__, pfl->cmd);
 414             goto reset_flash;
 415         }
 416         break;
 417     case 5:
 418         switch (cmd) {
 419         case 0x10:
 420             if (boff != pfl->unlock_addr0) {
 421                 DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx "\n",
 422                         __func__, offset);
 423                 goto reset_flash;
 424             }
 425             /* Chip erase */
 426             DPRINTF("%s: start chip erase\n", __func__);
 427             if (!pfl->ro) {
 428                 memset(pfl->storage, 0xFF, pfl->chip_len);
 429                 pflash_update(pfl, 0, pfl->chip_len);
 430             }
 431             pfl->status = 0x00;
 432             /* Let's wait 5 seconds before chip erase is done */
 433             timer_mod(pfl->timer,
 434                            qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() * 5));
 435             break;
 436         case 0x30:
 437             /* Sector erase */
 438             p = pfl->storage;
 439             offset &= ~(pfl->sector_len - 1);
 440             DPRINTF("%s: start sector erase at " TARGET_FMT_plx "\n", __func__,
 441                     offset);
 442             if (!pfl->ro) {
 443                 memset(p + offset, 0xFF, pfl->sector_len);
 444                 pflash_update(pfl, offset, pfl->sector_len);
 445             }
 446             pfl->status = 0x00;
 447             /* Let's wait 1/2 second before sector erase is done */
 448             timer_mod(pfl->timer,
 449                            qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() / 2));
 450             break;
 451         default:
 452             DPRINTF("%s: invalid command %02x (wc 5)\n", __func__, cmd);
 453             goto reset_flash;
 454         }
 455         pfl->cmd = cmd;
 456         break;
 457     case 6:
 458         switch (pfl->cmd) {
 459         case 0x10:
 460             /* Ignore writes during chip erase */
 461             return;
 462         case 0x30:
 463             /* Ignore writes during sector erase */
 464             return;
 465         default:
 466             /* Should never happen */
 467             DPRINTF("%s: invalid command state %02x (wc 6)\n",
 468                     __func__, pfl->cmd);
 469             goto reset_flash;
 470         }
 471         break;
 472     case 7: /* Special value for CFI queries */
 473         DPRINTF("%s: invalid write in CFI query mode\n", __func__);
 474         goto reset_flash;
 475     default:
 476         /* Should never happen */
 477         DPRINTF("%s: invalid write state (wc 7)\n",  __func__);
 478         goto reset_flash;
 479     }
 480     pfl->wcycle++;
 481
 482     return;
 483
 484     /* Reset flash */
 485  reset_flash:
 486     pfl->bypass = 0;
 487     pfl->wcycle = 0;
 488     pfl->cmd = 0;
 489     return;
 490
 491  do_bypass:
 492     pfl->wcycle = 2;
 493     pfl->cmd = 0;
 494 }
 495
 496
 497 static uint32_t pflash_readb_be(void *opaque, hwaddr addr)
 498 {
 499     return pflash_read(opaque, addr, 1, 1);
 500 }
 501
 502 static uint32_t pflash_readb_le(void *opaque, hwaddr addr)
 503 {
 504     return pflash_read(opaque, addr, 1, 0);
 505 }
 506
 507 static uint32_t pflash_readw_be(void *opaque, hwaddr addr)
 508 {
 509     pflash_t *pfl = opaque;
 510
 511     return pflash_read(pfl, addr, 2, 1);
 512 }
 513
 514 static uint32_t pflash_readw_le(void *opaque, hwaddr addr)
 515 {
 516     pflash_t *pfl = opaque;
 517
 518     return pflash_read(pfl, addr, 2, 0);
 519 }
 520
 521 static uint32_t pflash_readl_be(void *opaque, hwaddr addr)
 522 {
 523     pflash_t *pfl = opaque;
 524
 525     return pflash_read(pfl, addr, 4, 1);
 526 }
 527
 528 static uint32_t pflash_readl_le(void *opaque, hwaddr addr)
 529 {
 530     pflash_t *pfl = opaque;
 531
 532     return pflash_read(pfl, addr, 4, 0);
 533 }
 534
 535 static void pflash_writeb_be(void *opaque, hwaddr addr,
 536                              uint32_t value)
 537 {
 538     pflash_write(opaque, addr, value, 1, 1);
 539 }
 540
 541 static void pflash_writeb_le(void *opaque, hwaddr addr,
 542                              uint32_t value)
 543 {
 544     pflash_write(opaque, addr, value, 1, 0);
 545 }
 546
 547 static void pflash_writew_be(void *opaque, hwaddr addr,
 548                              uint32_t value)
 549 {
 550     pflash_t *pfl = opaque;
 551
 552     pflash_write(pfl, addr, value, 2, 1);
 553 }
 554
 555 static void pflash_writew_le(void *opaque, hwaddr addr,
 556                              uint32_t value)
 557 {
 558     pflash_t *pfl = opaque;
 559
 560     pflash_write(pfl, addr, value, 2, 0);
 561 }
 562
 563 static void pflash_writel_be(void *opaque, hwaddr addr,
 564                              uint32_t value)
 565 {
 566     pflash_t *pfl = opaque;
 567
 568     pflash_write(pfl, addr, value, 4, 1);
 569 }
 570
 571 static void pflash_writel_le(void *opaque, hwaddr addr,
 572                              uint32_t value)
 573 {
 574     pflash_t *pfl = opaque;
 575
 576     pflash_write(pfl, addr, value, 4, 0);
 577 }
 578
 579 static const MemoryRegionOps pflash_cfi02_ops_be = {
 580     .old_mmio = {
 581         .read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, },
 582         .write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, },
 583     },
 584     .endianness = DEVICE_NATIVE_ENDIAN,
 585 };
 586
 587 static const MemoryRegionOps pflash_cfi02_ops_le = {
 588     .old_mmio = {
 589         .read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, },
 590         .write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, },
 591     },
 592     .endianness = DEVICE_NATIVE_ENDIAN,
 593 };
 594
 595 static void pflash_cfi02_realize(DeviceState *dev, Error **errp)
 596 {
 597     pflash_t *pfl = CFI_PFLASH02(dev);
 598     uint32_t chip_len;
 599     int ret;
 600     Error *local_err = NULL;
 601
 602     chip_len = pfl->sector_len * pfl->nb_blocs;
 603     /* XXX: to be fixed */
 604 #if 0
 605     if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
 606         total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
 607         return NULL;
 608 #endif
 609
 610     memory_region_init_rom_device(&pfl->orig_mem, OBJECT(pfl), pfl->be ?
 611                                   &pflash_cfi02_ops_be : &pflash_cfi02_ops_le,
 612                                   pfl, pfl->name, chip_len, &local_err);
 613     if (local_err) {
 614         error_propagate(errp, local_err);
 615         return;
 616     }
 617
 618     vmstate_register_ram(&pfl->orig_mem, DEVICE(pfl));
 619     pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem);
 620     pfl->chip_len = chip_len;
 621     if (pfl->blk) {
 622         /* read the initial flash content */
 623         ret = blk_read(pfl->blk, 0, pfl->storage, chip_len >> 9);
 624         if (ret < 0) {
 625             vmstate_unregister_ram(&pfl->orig_mem, DEVICE(pfl));
 626             error_setg(errp, "failed to read the initial flash content");
 627             return;
 628         }
 629     }
 630
 631     pflash_setup_mappings(pfl);
 632     pfl->rom_mode = 1;
 633     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &pfl->mem);
 634
 635     if (pfl->blk) {
 636         pfl->ro = blk_is_read_only(pfl->blk);
 637     } else {
 638         pfl->ro = 0;
 639     }
 640
 641     pfl->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pflash_timer, pfl);
 642     pfl->wcycle = 0;
 643     pfl->cmd = 0;
 644     pfl->status = 0;
 645     /* Hardcoded CFI table (mostly from SG29 Spansion flash) */
 646     pfl->cfi_len = 0x52;
 647     /* Standard "QRY" string */
 648     pfl->cfi_table[0x10] = 'Q';
 649     pfl->cfi_table[0x11] = 'R';
 650     pfl->cfi_table[0x12] = 'Y';
 651     /* Command set (AMD/Fujitsu) */
 652     pfl->cfi_table[0x13] = 0x02;
 653     pfl->cfi_table[0x14] = 0x00;
 654     /* Primary extended table address */
 655     pfl->cfi_table[0x15] = 0x31;
 656     pfl->cfi_table[0x16] = 0x00;
 657     /* Alternate command set (none) */
 658     pfl->cfi_table[0x17] = 0x00;
 659     pfl->cfi_table[0x18] = 0x00;
 660     /* Alternate extended table (none) */
 661     pfl->cfi_table[0x19] = 0x00;
 662     pfl->cfi_table[0x1A] = 0x00;
 663     /* Vcc min */
 664     pfl->cfi_table[0x1B] = 0x27;
 665     /* Vcc max */
 666     pfl->cfi_table[0x1C] = 0x36;
 667     /* Vpp min (no Vpp pin) */
 668     pfl->cfi_table[0x1D] = 0x00;
 669     /* Vpp max (no Vpp pin) */
 670     pfl->cfi_table[0x1E] = 0x00;
 671     /* Reserved */
 672     pfl->cfi_table[0x1F] = 0x07;
 673     /* Timeout for min size buffer write (NA) */
 674     pfl->cfi_table[0x20] = 0x00;
 675     /* Typical timeout for block erase (512 ms) */
 676     pfl->cfi_table[0x21] = 0x09;
 677     /* Typical timeout for full chip erase (4096 ms) */
 678     pfl->cfi_table[0x22] = 0x0C;
 679     /* Reserved */
 680     pfl->cfi_table[0x23] = 0x01;
 681     /* Max timeout for buffer write (NA) */
 682     pfl->cfi_table[0x24] = 0x00;
 683     /* Max timeout for block erase */
 684     pfl->cfi_table[0x25] = 0x0A;
 685     /* Max timeout for chip erase */
 686     pfl->cfi_table[0x26] = 0x0D;
 687     /* Device size */
 688     pfl->cfi_table[0x27] = ctz32(chip_len);
 689     /* Flash device interface (8 & 16 bits) */
 690     pfl->cfi_table[0x28] = 0x02;
 691     pfl->cfi_table[0x29] = 0x00;
 692     /* Max number of bytes in multi-bytes write */
 693     /* XXX: disable buffered write as it's not supported */
 694     //    pfl->cfi_table[0x2A] = 0x05;
 695     pfl->cfi_table[0x2A] = 0x00;
 696     pfl->cfi_table[0x2B] = 0x00;
 697     /* Number of erase block regions (uniform) */
 698     pfl->cfi_table[0x2C] = 0x01;
 699     /* Erase block region 1 */
 700     pfl->cfi_table[0x2D] = pfl->nb_blocs - 1;
 701     pfl->cfi_table[0x2E] = (pfl->nb_blocs - 1) >> 8;
 702     pfl->cfi_table[0x2F] = pfl->sector_len >> 8;
 703     pfl->cfi_table[0x30] = pfl->sector_len >> 16;
 704
 705     /* Extended */
 706     pfl->cfi_table[0x31] = 'P';
 707     pfl->cfi_table[0x32] = 'R';
 708     pfl->cfi_table[0x33] = 'I';
 709
 710     pfl->cfi_table[0x34] = '1';
 711     pfl->cfi_table[0x35] = '0';
 712
 713     pfl->cfi_table[0x36] = 0x00;
 714     pfl->cfi_table[0x37] = 0x00;
 715     pfl->cfi_table[0x38] = 0x00;
 716     pfl->cfi_table[0x39] = 0x00;
 717
 718     pfl->cfi_table[0x3a] = 0x00;
 719
 720     pfl->cfi_table[0x3b] = 0x00;
 721     pfl->cfi_table[0x3c] = 0x00;
 722 }
 723
 724 static Property pflash_cfi02_properties[] = {
 725     DEFINE_PROP_DRIVE("drive", struct pflash_t, blk),
 726     DEFINE_PROP_UINT32("num-blocks", struct pflash_t, nb_blocs, 0),
 727     DEFINE_PROP_UINT32("sector-length", struct pflash_t, sector_len, 0),
 728     DEFINE_PROP_UINT8("width", struct pflash_t, width, 0),
 729     DEFINE_PROP_UINT8("mappings", struct pflash_t, mappings, 0),
 730     DEFINE_PROP_UINT8("big-endian", struct pflash_t, be, 0),
 731     DEFINE_PROP_UINT16("id0", struct pflash_t, ident0, 0),
 732     DEFINE_PROP_UINT16("id1", struct pflash_t, ident1, 0),
 733     DEFINE_PROP_UINT16("id2", struct pflash_t, ident2, 0),
 734     DEFINE_PROP_UINT16("id3", struct pflash_t, ident3, 0),
 735     DEFINE_PROP_UINT16("unlock-addr0", struct pflash_t, unlock_addr0, 0),
 736     DEFINE_PROP_UINT16("unlock-addr1", struct pflash_t, unlock_addr1, 0),
 737     DEFINE_PROP_STRING("name", struct pflash_t, name),
 738     DEFINE_PROP_END_OF_LIST(),
 739 };
 740
 741 static void pflash_cfi02_class_init(ObjectClass *klass, void *data)
 742 {
 743     DeviceClass *dc = DEVICE_CLASS(klass);
 744
 745     dc->realize = pflash_cfi02_realize;
 746     dc->props = pflash_cfi02_properties;
 747     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 748 }
 749
 750 static const TypeInfo pflash_cfi02_info = {
 751     .name           = TYPE_CFI_PFLASH02,
 752     .parent         = TYPE_SYS_BUS_DEVICE,
 753     .instance_size  = sizeof(struct pflash_t),
 754     .class_init     = pflash_cfi02_class_init,
 755 };
 756
 757 static void pflash_cfi02_register_types(void)
 758 {
 759     type_register_static(&pflash_cfi02_info);
 760 }
 761
 762 type_init(pflash_cfi02_register_types)
 763
 764 pflash_t *pflash_cfi02_register(hwaddr base,
 765                                 DeviceState *qdev, const char *name,
 766                                 hwaddr size,
 767                                 BlockBackend *blk, uint32_t sector_len,
 768                                 int nb_blocs, int nb_mappings, int width,
 769                                 uint16_t id0, uint16_t id1,
 770                                 uint16_t id2, uint16_t id3,
 771                                 uint16_t unlock_addr0, uint16_t unlock_addr1,
 772                                 int be)
 773 {
 774     DeviceState *dev = qdev_create(NULL, TYPE_CFI_PFLASH02);
 775
 776     if (blk) {
 777         qdev_prop_set_drive(dev, "drive", blk, &error_abort);
 778     }
 779     qdev_prop_set_uint32(dev, "num-blocks", nb_blocs);
 780     qdev_prop_set_uint32(dev, "sector-length", sector_len);
 781     qdev_prop_set_uint8(dev, "width", width);
 782     qdev_prop_set_uint8(dev, "mappings", nb_mappings);
 783     qdev_prop_set_uint8(dev, "big-endian", !!be);
 784     qdev_prop_set_uint16(dev, "id0", id0);
 785     qdev_prop_set_uint16(dev, "id1", id1);
 786     qdev_prop_set_uint16(dev, "id2", id2);
 787     qdev_prop_set_uint16(dev, "id3", id3);
 788     qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0);
 789     qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1);
 790     qdev_prop_set_string(dev, "name", name);
 791     qdev_init_nofail(dev);
 792
 793     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 794     return CFI_PFLASH02(dev);
 795 }