2 * ioapic.c IOAPIC emulation logic
4 * Copyright (c) 2004-2005 Fabrice Bellard
6 * Split the ioapic logic from apic.c
7 * Xiantao Zhang <xiantao.zhang@intel.com>
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "monitor/monitor.h"
26 #include "hw/i386/pc.h"
27 #include "hw/i386/apic.h"
28 #include "hw/i386/ioapic.h"
29 #include "hw/i386/ioapic_internal.h"
30 #include "hw/pci/msi.h"
31 #include "hw/qdev-properties.h"
32 #include "sysemu/kvm.h"
33 #include "sysemu/sysemu.h"
34 #include "hw/i386/apic-msidef.h"
35 #include "hw/i386/x86-iommu.h"
38 #define APIC_DELIVERY_MODE_SHIFT 8
39 #define APIC_POLARITY_SHIFT 14
40 #define APIC_TRIG_MODE_SHIFT 15
42 static IOAPICCommonState
*ioapics
[MAX_IOAPICS
];
44 /* global variable from ioapic_common.c */
47 struct ioapic_entry_info
{
48 /* fields parsed from IOAPIC entries */
53 uint8_t delivery_mode
;
56 /* MSI message generated from above parsed fields */
61 static void ioapic_entry_parse(uint64_t entry
, struct ioapic_entry_info
*info
)
63 memset(info
, 0, sizeof(*info
));
64 info
->masked
= (entry
>> IOAPIC_LVT_MASKED_SHIFT
) & 1;
65 info
->trig_mode
= (entry
>> IOAPIC_LVT_TRIGGER_MODE_SHIFT
) & 1;
67 * By default, this would be dest_id[8] + reserved[8]. When IR
68 * is enabled, this would be interrupt_index[15] +
69 * interrupt_format[1]. This field never means anything, but
70 * only used to generate corresponding MSI.
72 info
->dest_idx
= (entry
>> IOAPIC_LVT_DEST_IDX_SHIFT
) & 0xffff;
73 info
->dest_mode
= (entry
>> IOAPIC_LVT_DEST_MODE_SHIFT
) & 1;
74 info
->delivery_mode
= (entry
>> IOAPIC_LVT_DELIV_MODE_SHIFT
) \
76 if (info
->delivery_mode
== IOAPIC_DM_EXTINT
) {
77 info
->vector
= pic_read_irq(isa_pic
);
79 info
->vector
= entry
& IOAPIC_VECTOR_MASK
;
82 info
->addr
= APIC_DEFAULT_ADDRESS
| \
83 (info
->dest_idx
<< MSI_ADDR_DEST_IDX_SHIFT
) | \
84 (info
->dest_mode
<< MSI_ADDR_DEST_MODE_SHIFT
);
85 info
->data
= (info
->vector
<< MSI_DATA_VECTOR_SHIFT
) | \
86 (info
->trig_mode
<< MSI_DATA_TRIGGER_SHIFT
) | \
87 (info
->delivery_mode
<< MSI_DATA_DELIVERY_MODE_SHIFT
);
90 static void ioapic_service(IOAPICCommonState
*s
)
92 AddressSpace
*ioapic_as
= PC_MACHINE(qdev_get_machine())->ioapic_as
;
93 struct ioapic_entry_info info
;
98 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
103 entry
= s
->ioredtbl
[i
];
104 ioapic_entry_parse(entry
, &info
);
106 if (info
.trig_mode
== IOAPIC_TRIGGER_EDGE
) {
109 coalesce
= s
->ioredtbl
[i
] & IOAPIC_LVT_REMOTE_IRR
;
110 trace_ioapic_set_remote_irr(i
);
111 s
->ioredtbl
[i
] |= IOAPIC_LVT_REMOTE_IRR
;
115 /* We are level triggered interrupts, and the
116 * guest should be still working on previous one,
122 if (kvm_irqchip_is_split()) {
123 if (info
.trig_mode
== IOAPIC_TRIGGER_EDGE
) {
124 kvm_set_irq(kvm_state
, i
, 1);
125 kvm_set_irq(kvm_state
, i
, 0);
127 kvm_set_irq(kvm_state
, i
, 1);
133 /* No matter whether IR is enabled, we translate
134 * the IOAPIC message into a MSI one, and its
135 * address space will decide whether we need a
137 stl_le_phys(ioapic_as
, info
.addr
, info
.data
);
143 #define SUCCESSIVE_IRQ_MAX_COUNT 10000
145 static void delayed_ioapic_service_cb(void *opaque
)
147 IOAPICCommonState
*s
= opaque
;
152 static void ioapic_set_irq(void *opaque
, int vector
, int level
)
154 IOAPICCommonState
*s
= opaque
;
156 /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
157 * to GSI 2. GSI maps to ioapic 1-1. This is not
158 * the cleanest way of doing it but it should work. */
160 trace_ioapic_set_irq(vector
, level
);
161 ioapic_stat_update_irq(s
, vector
, level
);
165 if (vector
< IOAPIC_NUM_PINS
) {
166 uint32_t mask
= 1 << vector
;
167 uint64_t entry
= s
->ioredtbl
[vector
];
169 if (((entry
>> IOAPIC_LVT_TRIGGER_MODE_SHIFT
) & 1) ==
170 IOAPIC_TRIGGER_LEVEL
) {
171 /* level triggered */
174 if (!(entry
& IOAPIC_LVT_REMOTE_IRR
)) {
181 /* According to the 82093AA manual, we must ignore edge requests
182 * if the input pin is masked. */
183 if (level
&& !(entry
& IOAPIC_LVT_MASKED
)) {
191 static void ioapic_update_kvm_routes(IOAPICCommonState
*s
)
196 if (kvm_irqchip_is_split()) {
197 for (i
= 0; i
< IOAPIC_NUM_PINS
; i
++) {
199 struct ioapic_entry_info info
;
200 ioapic_entry_parse(s
->ioredtbl
[i
], &info
);
202 msg
.address
= info
.addr
;
203 msg
.data
= info
.data
;
204 kvm_irqchip_update_msi_route(kvm_state
, i
, msg
, NULL
);
207 kvm_irqchip_commit_routes(kvm_state
);
213 static void ioapic_iec_notifier(void *private, bool global
,
214 uint32_t index
, uint32_t mask
)
216 IOAPICCommonState
*s
= (IOAPICCommonState
*)private;
217 /* For simplicity, we just update all the routes */
218 ioapic_update_kvm_routes(s
);
222 void ioapic_eoi_broadcast(int vector
)
224 IOAPICCommonState
*s
;
228 trace_ioapic_eoi_broadcast(vector
);
230 for (i
= 0; i
< MAX_IOAPICS
; i
++) {
235 for (n
= 0; n
< IOAPIC_NUM_PINS
; n
++) {
236 entry
= s
->ioredtbl
[n
];
238 if ((entry
& IOAPIC_VECTOR_MASK
) != vector
||
239 ((entry
>> IOAPIC_LVT_TRIGGER_MODE_SHIFT
) & 1) != IOAPIC_TRIGGER_LEVEL
) {
243 if (!(entry
& IOAPIC_LVT_REMOTE_IRR
)) {
247 trace_ioapic_clear_remote_irr(n
, vector
);
248 s
->ioredtbl
[n
] = entry
& ~IOAPIC_LVT_REMOTE_IRR
;
250 if (!(entry
& IOAPIC_LVT_MASKED
) && (s
->irr
& (1 << n
))) {
252 if (s
->irq_eoi
[n
] >= SUCCESSIVE_IRQ_MAX_COUNT
) {
254 * Real hardware does not deliver the interrupt immediately
255 * during eoi broadcast, and this lets a buggy guest make
256 * slow progress even if it does not correctly handle a
257 * level-triggered interrupt. Emulate this behavior if we
258 * detect an interrupt storm.
261 timer_mod_anticipate(s
->delayed_ioapic_service_timer
,
262 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
263 NANOSECONDS_PER_SECOND
/ 100);
264 trace_ioapic_eoi_delayed_reassert(n
);
276 ioapic_mem_read(void *opaque
, hwaddr addr
, unsigned int size
)
278 IOAPICCommonState
*s
= opaque
;
285 case IOAPIC_IOREGSEL
:
292 switch (s
->ioregsel
) {
295 val
= s
->id
<< IOAPIC_ID_SHIFT
;
299 ((IOAPIC_NUM_PINS
- 1) << IOAPIC_VER_ENTRIES_SHIFT
);
302 index
= (s
->ioregsel
- IOAPIC_REG_REDTBL_BASE
) >> 1;
303 if (index
>= 0 && index
< IOAPIC_NUM_PINS
) {
304 if (s
->ioregsel
& 1) {
305 val
= s
->ioredtbl
[index
] >> 32;
307 val
= s
->ioredtbl
[index
] & 0xffffffff;
314 trace_ioapic_mem_read(addr
, s
->ioregsel
, size
, val
);
320 * This is to satisfy the hack in Linux kernel. One hack of it is to
321 * simulate clearing the Remote IRR bit of IOAPIC entry using the
324 * "For IO-APIC's with EOI register, we use that to do an explicit EOI.
325 * Otherwise, we simulate the EOI message manually by changing the trigger
326 * mode to edge and then back to level, with RTE being masked during
329 * (See linux kernel __eoi_ioapic_pin() comment in commit c0205701)
331 * This is based on the assumption that, Remote IRR bit will be
332 * cleared by IOAPIC hardware when configured as edge-triggered
335 * Without this, level-triggered interrupts in IR mode might fail to
339 ioapic_fix_edge_remote_irr(uint64_t *entry
)
341 if (!(*entry
& IOAPIC_LVT_TRIGGER_MODE
)) {
342 /* Edge-triggered interrupts, make sure remote IRR is zero */
343 *entry
&= ~((uint64_t)IOAPIC_LVT_REMOTE_IRR
);
348 ioapic_mem_write(void *opaque
, hwaddr addr
, uint64_t val
,
351 IOAPICCommonState
*s
= opaque
;
355 trace_ioapic_mem_write(addr
, s
->ioregsel
, size
, val
);
358 case IOAPIC_IOREGSEL
:
365 switch (s
->ioregsel
) {
367 s
->id
= (val
>> IOAPIC_ID_SHIFT
) & IOAPIC_ID_MASK
;
373 index
= (s
->ioregsel
- IOAPIC_REG_REDTBL_BASE
) >> 1;
374 if (index
>= 0 && index
< IOAPIC_NUM_PINS
) {
375 uint64_t ro_bits
= s
->ioredtbl
[index
] & IOAPIC_RO_BITS
;
376 if (s
->ioregsel
& 1) {
377 s
->ioredtbl
[index
] &= 0xffffffff;
378 s
->ioredtbl
[index
] |= (uint64_t)val
<< 32;
380 s
->ioredtbl
[index
] &= ~0xffffffffULL
;
381 s
->ioredtbl
[index
] |= val
;
383 /* restore RO bits */
384 s
->ioredtbl
[index
] &= IOAPIC_RW_BITS
;
385 s
->ioredtbl
[index
] |= ro_bits
;
386 s
->irq_eoi
[index
] = 0;
387 ioapic_fix_edge_remote_irr(&s
->ioredtbl
[index
]);
393 /* Explicit EOI is only supported for IOAPIC version 0x20 */
394 if (size
!= 4 || s
->version
!= 0x20) {
397 ioapic_eoi_broadcast(val
);
401 ioapic_update_kvm_routes(s
);
404 static const MemoryRegionOps ioapic_io_ops
= {
405 .read
= ioapic_mem_read
,
406 .write
= ioapic_mem_write
,
407 .endianness
= DEVICE_NATIVE_ENDIAN
,
410 static void ioapic_machine_done_notify(Notifier
*notifier
, void *data
)
413 IOAPICCommonState
*s
= container_of(notifier
, IOAPICCommonState
,
416 if (kvm_irqchip_is_split()) {
417 X86IOMMUState
*iommu
= x86_iommu_get_default();
419 /* Register this IOAPIC with IOMMU IEC notifier, so that
420 * when there are IR invalidates, we can be notified to
421 * update kernel IR cache. */
422 x86_iommu_iec_register_notifier(iommu
, ioapic_iec_notifier
, s
);
428 #define IOAPIC_VER_DEF 0x20
430 static void ioapic_realize(DeviceState
*dev
, Error
**errp
)
432 IOAPICCommonState
*s
= IOAPIC_COMMON(dev
);
434 if (s
->version
!= 0x11 && s
->version
!= 0x20) {
435 error_setg(errp
, "IOAPIC only supports version 0x11 or 0x20 "
436 "(default: 0x%x).", IOAPIC_VER_DEF
);
440 memory_region_init_io(&s
->io_memory
, OBJECT(s
), &ioapic_io_ops
, s
,
443 s
->delayed_ioapic_service_timer
=
444 timer_new_ns(QEMU_CLOCK_VIRTUAL
, delayed_ioapic_service_cb
, s
);
446 qdev_init_gpio_in(dev
, ioapic_set_irq
, IOAPIC_NUM_PINS
);
448 ioapics
[ioapic_no
] = s
;
449 s
->machine_done
.notify
= ioapic_machine_done_notify
;
450 qemu_add_machine_init_done_notifier(&s
->machine_done
);
453 static void ioapic_unrealize(DeviceState
*dev
, Error
**errp
)
455 IOAPICCommonState
*s
= IOAPIC_COMMON(dev
);
457 timer_del(s
->delayed_ioapic_service_timer
);
458 timer_free(s
->delayed_ioapic_service_timer
);
461 static Property ioapic_properties
[] = {
462 DEFINE_PROP_UINT8("version", IOAPICCommonState
, version
, IOAPIC_VER_DEF
),
463 DEFINE_PROP_END_OF_LIST(),
466 static void ioapic_class_init(ObjectClass
*klass
, void *data
)
468 IOAPICCommonClass
*k
= IOAPIC_COMMON_CLASS(klass
);
469 DeviceClass
*dc
= DEVICE_CLASS(klass
);
471 k
->realize
= ioapic_realize
;
472 k
->unrealize
= ioapic_unrealize
;
474 * If APIC is in kernel, we need to update the kernel cache after
475 * migration, otherwise first 24 gsi routes will be invalid.
477 k
->post_load
= ioapic_update_kvm_routes
;
478 dc
->reset
= ioapic_reset_common
;
479 dc
->props
= ioapic_properties
;
482 static const TypeInfo ioapic_info
= {
484 .parent
= TYPE_IOAPIC_COMMON
,
485 .instance_size
= sizeof(IOAPICCommonState
),
486 .class_init
= ioapic_class_init
,
489 static void ioapic_register_types(void)
491 type_register_static(&ioapic_info
);
494 type_init(ioapic_register_types
)