2 * x86 FPU, MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4/PNI helpers
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu/host-utils.h"
25 #if !defined(CONFIG_USER_ONLY)
26 #include "exec/softmmu_exec.h"
27 #endif /* !defined(CONFIG_USER_ONLY) */
29 #define FPU_RC_MASK 0xc00
30 #define FPU_RC_NEAR 0x000
31 #define FPU_RC_DOWN 0x400
32 #define FPU_RC_UP 0x800
33 #define FPU_RC_CHOP 0xc00
35 #define MAXTAN 9223372036854775808.0
37 /* the following deal with x86 long double-precision numbers */
38 #define MAXEXPD 0x7fff
40 #define EXPD(fp) (fp.l.upper & 0x7fff)
41 #define SIGND(fp) ((fp.l.upper) & 0x8000)
42 #define MANTD(fp) (fp.l.lower)
43 #define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7fff)) | EXPBIAS
45 #define FPUS_IE (1 << 0)
46 #define FPUS_DE (1 << 1)
47 #define FPUS_ZE (1 << 2)
48 #define FPUS_OE (1 << 3)
49 #define FPUS_UE (1 << 4)
50 #define FPUS_PE (1 << 5)
51 #define FPUS_SF (1 << 6)
52 #define FPUS_SE (1 << 7)
53 #define FPUS_B (1 << 15)
57 #define floatx80_lg2 make_floatx80(0x3ffd, 0x9a209a84fbcff799LL)
58 #define floatx80_l2e make_floatx80(0x3fff, 0xb8aa3b295c17f0bcLL)
59 #define floatx80_l2t make_floatx80(0x4000, 0xd49a784bcd1b8afeLL)
61 static inline void fpush(CPUX86State
*env
)
63 env
->fpstt
= (env
->fpstt
- 1) & 7;
64 env
->fptags
[env
->fpstt
] = 0; /* validate stack entry */
67 static inline void fpop(CPUX86State
*env
)
69 env
->fptags
[env
->fpstt
] = 1; /* invalidate stack entry */
70 env
->fpstt
= (env
->fpstt
+ 1) & 7;
73 static inline floatx80
helper_fldt(CPUX86State
*env
, target_ulong ptr
)
77 temp
.l
.lower
= cpu_ldq_data(env
, ptr
);
78 temp
.l
.upper
= cpu_lduw_data(env
, ptr
+ 8);
82 static inline void helper_fstt(CPUX86State
*env
, floatx80 f
, target_ulong ptr
)
87 cpu_stq_data(env
, ptr
, temp
.l
.lower
);
88 cpu_stw_data(env
, ptr
+ 8, temp
.l
.upper
);
93 static inline double floatx80_to_double(CPUX86State
*env
, floatx80 a
)
100 u
.f64
= floatx80_to_float64(a
, &env
->fp_status
);
104 static inline floatx80
double_to_floatx80(CPUX86State
*env
, double a
)
112 return float64_to_floatx80(u
.f64
, &env
->fp_status
);
115 static void fpu_set_exception(CPUX86State
*env
, int mask
)
118 if (env
->fpus
& (~env
->fpuc
& FPUC_EM
)) {
119 env
->fpus
|= FPUS_SE
| FPUS_B
;
123 static inline floatx80
helper_fdiv(CPUX86State
*env
, floatx80 a
, floatx80 b
)
125 if (floatx80_is_zero(b
)) {
126 fpu_set_exception(env
, FPUS_ZE
);
128 return floatx80_div(a
, b
, &env
->fp_status
);
131 static void fpu_raise_exception(CPUX86State
*env
)
133 if (env
->cr
[0] & CR0_NE_MASK
) {
134 raise_exception(env
, EXCP10_COPR
);
136 #if !defined(CONFIG_USER_ONLY)
143 void helper_flds_FT0(CPUX86State
*env
, uint32_t val
)
151 FT0
= float32_to_floatx80(u
.f
, &env
->fp_status
);
154 void helper_fldl_FT0(CPUX86State
*env
, uint64_t val
)
162 FT0
= float64_to_floatx80(u
.f
, &env
->fp_status
);
165 void helper_fildl_FT0(CPUX86State
*env
, int32_t val
)
167 FT0
= int32_to_floatx80(val
, &env
->fp_status
);
170 void helper_flds_ST0(CPUX86State
*env
, uint32_t val
)
178 new_fpstt
= (env
->fpstt
- 1) & 7;
180 env
->fpregs
[new_fpstt
].d
= float32_to_floatx80(u
.f
, &env
->fp_status
);
181 env
->fpstt
= new_fpstt
;
182 env
->fptags
[new_fpstt
] = 0; /* validate stack entry */
185 void helper_fldl_ST0(CPUX86State
*env
, uint64_t val
)
193 new_fpstt
= (env
->fpstt
- 1) & 7;
195 env
->fpregs
[new_fpstt
].d
= float64_to_floatx80(u
.f
, &env
->fp_status
);
196 env
->fpstt
= new_fpstt
;
197 env
->fptags
[new_fpstt
] = 0; /* validate stack entry */
200 void helper_fildl_ST0(CPUX86State
*env
, int32_t val
)
204 new_fpstt
= (env
->fpstt
- 1) & 7;
205 env
->fpregs
[new_fpstt
].d
= int32_to_floatx80(val
, &env
->fp_status
);
206 env
->fpstt
= new_fpstt
;
207 env
->fptags
[new_fpstt
] = 0; /* validate stack entry */
210 void helper_fildll_ST0(CPUX86State
*env
, int64_t val
)
214 new_fpstt
= (env
->fpstt
- 1) & 7;
215 env
->fpregs
[new_fpstt
].d
= int64_to_floatx80(val
, &env
->fp_status
);
216 env
->fpstt
= new_fpstt
;
217 env
->fptags
[new_fpstt
] = 0; /* validate stack entry */
220 uint32_t helper_fsts_ST0(CPUX86State
*env
)
227 u
.f
= floatx80_to_float32(ST0
, &env
->fp_status
);
231 uint64_t helper_fstl_ST0(CPUX86State
*env
)
238 u
.f
= floatx80_to_float64(ST0
, &env
->fp_status
);
242 int32_t helper_fist_ST0(CPUX86State
*env
)
246 val
= floatx80_to_int32(ST0
, &env
->fp_status
);
247 if (val
!= (int16_t)val
) {
253 int32_t helper_fistl_ST0(CPUX86State
*env
)
257 val
= floatx80_to_int32(ST0
, &env
->fp_status
);
261 int64_t helper_fistll_ST0(CPUX86State
*env
)
265 val
= floatx80_to_int64(ST0
, &env
->fp_status
);
269 int32_t helper_fistt_ST0(CPUX86State
*env
)
273 val
= floatx80_to_int32_round_to_zero(ST0
, &env
->fp_status
);
274 if (val
!= (int16_t)val
) {
280 int32_t helper_fisttl_ST0(CPUX86State
*env
)
284 val
= floatx80_to_int32_round_to_zero(ST0
, &env
->fp_status
);
288 int64_t helper_fisttll_ST0(CPUX86State
*env
)
292 val
= floatx80_to_int64_round_to_zero(ST0
, &env
->fp_status
);
296 void helper_fldt_ST0(CPUX86State
*env
, target_ulong ptr
)
300 new_fpstt
= (env
->fpstt
- 1) & 7;
301 env
->fpregs
[new_fpstt
].d
= helper_fldt(env
, ptr
);
302 env
->fpstt
= new_fpstt
;
303 env
->fptags
[new_fpstt
] = 0; /* validate stack entry */
306 void helper_fstt_ST0(CPUX86State
*env
, target_ulong ptr
)
308 helper_fstt(env
, ST0
, ptr
);
311 void helper_fpush(CPUX86State
*env
)
316 void helper_fpop(CPUX86State
*env
)
321 void helper_fdecstp(CPUX86State
*env
)
323 env
->fpstt
= (env
->fpstt
- 1) & 7;
324 env
->fpus
&= ~0x4700;
327 void helper_fincstp(CPUX86State
*env
)
329 env
->fpstt
= (env
->fpstt
+ 1) & 7;
330 env
->fpus
&= ~0x4700;
335 void helper_ffree_STN(CPUX86State
*env
, int st_index
)
337 env
->fptags
[(env
->fpstt
+ st_index
) & 7] = 1;
340 void helper_fmov_ST0_FT0(CPUX86State
*env
)
345 void helper_fmov_FT0_STN(CPUX86State
*env
, int st_index
)
350 void helper_fmov_ST0_STN(CPUX86State
*env
, int st_index
)
355 void helper_fmov_STN_ST0(CPUX86State
*env
, int st_index
)
360 void helper_fxchg_ST0_STN(CPUX86State
*env
, int st_index
)
371 static const int fcom_ccval
[4] = {0x0100, 0x4000, 0x0000, 0x4500};
373 void helper_fcom_ST0_FT0(CPUX86State
*env
)
377 ret
= floatx80_compare(ST0
, FT0
, &env
->fp_status
);
378 env
->fpus
= (env
->fpus
& ~0x4500) | fcom_ccval
[ret
+ 1];
381 void helper_fucom_ST0_FT0(CPUX86State
*env
)
385 ret
= floatx80_compare_quiet(ST0
, FT0
, &env
->fp_status
);
386 env
->fpus
= (env
->fpus
& ~0x4500) | fcom_ccval
[ret
+ 1];
389 static const int fcomi_ccval
[4] = {CC_C
, CC_Z
, 0, CC_Z
| CC_P
| CC_C
};
391 void helper_fcomi_ST0_FT0(CPUX86State
*env
)
396 ret
= floatx80_compare(ST0
, FT0
, &env
->fp_status
);
397 eflags
= cpu_cc_compute_all(env
, CC_OP
);
398 eflags
= (eflags
& ~(CC_Z
| CC_P
| CC_C
)) | fcomi_ccval
[ret
+ 1];
402 void helper_fucomi_ST0_FT0(CPUX86State
*env
)
407 ret
= floatx80_compare_quiet(ST0
, FT0
, &env
->fp_status
);
408 eflags
= cpu_cc_compute_all(env
, CC_OP
);
409 eflags
= (eflags
& ~(CC_Z
| CC_P
| CC_C
)) | fcomi_ccval
[ret
+ 1];
413 void helper_fadd_ST0_FT0(CPUX86State
*env
)
415 ST0
= floatx80_add(ST0
, FT0
, &env
->fp_status
);
418 void helper_fmul_ST0_FT0(CPUX86State
*env
)
420 ST0
= floatx80_mul(ST0
, FT0
, &env
->fp_status
);
423 void helper_fsub_ST0_FT0(CPUX86State
*env
)
425 ST0
= floatx80_sub(ST0
, FT0
, &env
->fp_status
);
428 void helper_fsubr_ST0_FT0(CPUX86State
*env
)
430 ST0
= floatx80_sub(FT0
, ST0
, &env
->fp_status
);
433 void helper_fdiv_ST0_FT0(CPUX86State
*env
)
435 ST0
= helper_fdiv(env
, ST0
, FT0
);
438 void helper_fdivr_ST0_FT0(CPUX86State
*env
)
440 ST0
= helper_fdiv(env
, FT0
, ST0
);
443 /* fp operations between STN and ST0 */
445 void helper_fadd_STN_ST0(CPUX86State
*env
, int st_index
)
447 ST(st_index
) = floatx80_add(ST(st_index
), ST0
, &env
->fp_status
);
450 void helper_fmul_STN_ST0(CPUX86State
*env
, int st_index
)
452 ST(st_index
) = floatx80_mul(ST(st_index
), ST0
, &env
->fp_status
);
455 void helper_fsub_STN_ST0(CPUX86State
*env
, int st_index
)
457 ST(st_index
) = floatx80_sub(ST(st_index
), ST0
, &env
->fp_status
);
460 void helper_fsubr_STN_ST0(CPUX86State
*env
, int st_index
)
462 ST(st_index
) = floatx80_sub(ST0
, ST(st_index
), &env
->fp_status
);
465 void helper_fdiv_STN_ST0(CPUX86State
*env
, int st_index
)
470 *p
= helper_fdiv(env
, *p
, ST0
);
473 void helper_fdivr_STN_ST0(CPUX86State
*env
, int st_index
)
478 *p
= helper_fdiv(env
, ST0
, *p
);
481 /* misc FPU operations */
482 void helper_fchs_ST0(CPUX86State
*env
)
484 ST0
= floatx80_chs(ST0
);
487 void helper_fabs_ST0(CPUX86State
*env
)
489 ST0
= floatx80_abs(ST0
);
492 void helper_fld1_ST0(CPUX86State
*env
)
497 void helper_fldl2t_ST0(CPUX86State
*env
)
502 void helper_fldl2e_ST0(CPUX86State
*env
)
507 void helper_fldpi_ST0(CPUX86State
*env
)
512 void helper_fldlg2_ST0(CPUX86State
*env
)
517 void helper_fldln2_ST0(CPUX86State
*env
)
522 void helper_fldz_ST0(CPUX86State
*env
)
527 void helper_fldz_FT0(CPUX86State
*env
)
532 uint32_t helper_fnstsw(CPUX86State
*env
)
534 return (env
->fpus
& ~0x3800) | (env
->fpstt
& 0x7) << 11;
537 uint32_t helper_fnstcw(CPUX86State
*env
)
542 static void update_fp_status(CPUX86State
*env
)
546 /* set rounding mode */
547 switch (env
->fpuc
& FPU_RC_MASK
) {
550 rnd_type
= float_round_nearest_even
;
553 rnd_type
= float_round_down
;
556 rnd_type
= float_round_up
;
559 rnd_type
= float_round_to_zero
;
562 set_float_rounding_mode(rnd_type
, &env
->fp_status
);
563 switch ((env
->fpuc
>> 8) & 3) {
575 set_floatx80_rounding_precision(rnd_type
, &env
->fp_status
);
578 void helper_fldcw(CPUX86State
*env
, uint32_t val
)
581 update_fp_status(env
);
584 void helper_fclex(CPUX86State
*env
)
589 void helper_fwait(CPUX86State
*env
)
591 if (env
->fpus
& FPUS_SE
) {
592 fpu_raise_exception(env
);
596 void helper_fninit(CPUX86State
*env
)
613 void helper_fbld_ST0(CPUX86State
*env
, target_ulong ptr
)
621 for (i
= 8; i
>= 0; i
--) {
622 v
= cpu_ldub_data(env
, ptr
+ i
);
623 val
= (val
* 100) + ((v
>> 4) * 10) + (v
& 0xf);
625 tmp
= int64_to_floatx80(val
, &env
->fp_status
);
626 if (cpu_ldub_data(env
, ptr
+ 9) & 0x80) {
633 void helper_fbst_ST0(CPUX86State
*env
, target_ulong ptr
)
636 target_ulong mem_ref
, mem_end
;
639 val
= floatx80_to_int64(ST0
, &env
->fp_status
);
641 mem_end
= mem_ref
+ 9;
643 cpu_stb_data(env
, mem_end
, 0x80);
646 cpu_stb_data(env
, mem_end
, 0x00);
648 while (mem_ref
< mem_end
) {
654 v
= ((v
/ 10) << 4) | (v
% 10);
655 cpu_stb_data(env
, mem_ref
++, v
);
657 while (mem_ref
< mem_end
) {
658 cpu_stb_data(env
, mem_ref
++, 0);
662 void helper_f2xm1(CPUX86State
*env
)
664 double val
= floatx80_to_double(env
, ST0
);
666 val
= pow(2.0, val
) - 1.0;
667 ST0
= double_to_floatx80(env
, val
);
670 void helper_fyl2x(CPUX86State
*env
)
672 double fptemp
= floatx80_to_double(env
, ST0
);
675 fptemp
= log(fptemp
) / log(2.0); /* log2(ST) */
676 fptemp
*= floatx80_to_double(env
, ST1
);
677 ST1
= double_to_floatx80(env
, fptemp
);
680 env
->fpus
&= ~0x4700;
685 void helper_fptan(CPUX86State
*env
)
687 double fptemp
= floatx80_to_double(env
, ST0
);
689 if ((fptemp
> MAXTAN
) || (fptemp
< -MAXTAN
)) {
692 fptemp
= tan(fptemp
);
693 ST0
= double_to_floatx80(env
, fptemp
);
696 env
->fpus
&= ~0x400; /* C2 <-- 0 */
697 /* the above code is for |arg| < 2**52 only */
701 void helper_fpatan(CPUX86State
*env
)
703 double fptemp
, fpsrcop
;
705 fpsrcop
= floatx80_to_double(env
, ST1
);
706 fptemp
= floatx80_to_double(env
, ST0
);
707 ST1
= double_to_floatx80(env
, atan2(fpsrcop
, fptemp
));
711 void helper_fxtract(CPUX86State
*env
)
717 if (floatx80_is_zero(ST0
)) {
718 /* Easy way to generate -inf and raising division by 0 exception */
719 ST0
= floatx80_div(floatx80_chs(floatx80_one
), floatx80_zero
,
726 expdif
= EXPD(temp
) - EXPBIAS
;
727 /* DP exponent bias */
728 ST0
= int32_to_floatx80(expdif
, &env
->fp_status
);
735 void helper_fprem1(CPUX86State
*env
)
737 double st0
, st1
, dblq
, fpsrcop
, fptemp
;
738 CPU_LDoubleU fpsrcop1
, fptemp1
;
740 signed long long int q
;
742 st0
= floatx80_to_double(env
, ST0
);
743 st1
= floatx80_to_double(env
, ST1
);
745 if (isinf(st0
) || isnan(st0
) || isnan(st1
) || (st1
== 0.0)) {
746 ST0
= double_to_floatx80(env
, 0.0 / 0.0); /* NaN */
747 env
->fpus
&= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
755 expdif
= EXPD(fpsrcop1
) - EXPD(fptemp1
);
758 /* optimisation? taken from the AMD docs */
759 env
->fpus
&= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
760 /* ST0 is unchanged */
765 dblq
= fpsrcop
/ fptemp
;
766 /* round dblq towards nearest integer */
768 st0
= fpsrcop
- fptemp
* dblq
;
770 /* convert dblq to q by truncating towards zero */
772 q
= (signed long long int)(-dblq
);
774 q
= (signed long long int)dblq
;
777 env
->fpus
&= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
778 /* (C0,C3,C1) <-- (q2,q1,q0) */
779 env
->fpus
|= (q
& 0x4) << (8 - 2); /* (C0) <-- q2 */
780 env
->fpus
|= (q
& 0x2) << (14 - 1); /* (C3) <-- q1 */
781 env
->fpus
|= (q
& 0x1) << (9 - 0); /* (C1) <-- q0 */
783 env
->fpus
|= 0x400; /* C2 <-- 1 */
784 fptemp
= pow(2.0, expdif
- 50);
785 fpsrcop
= (st0
/ st1
) / fptemp
;
786 /* fpsrcop = integer obtained by chopping */
787 fpsrcop
= (fpsrcop
< 0.0) ?
788 -(floor(fabs(fpsrcop
))) : floor(fpsrcop
);
789 st0
-= (st1
* fpsrcop
* fptemp
);
791 ST0
= double_to_floatx80(env
, st0
);
794 void helper_fprem(CPUX86State
*env
)
796 double st0
, st1
, dblq
, fpsrcop
, fptemp
;
797 CPU_LDoubleU fpsrcop1
, fptemp1
;
799 signed long long int q
;
801 st0
= floatx80_to_double(env
, ST0
);
802 st1
= floatx80_to_double(env
, ST1
);
804 if (isinf(st0
) || isnan(st0
) || isnan(st1
) || (st1
== 0.0)) {
805 ST0
= double_to_floatx80(env
, 0.0 / 0.0); /* NaN */
806 env
->fpus
&= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
814 expdif
= EXPD(fpsrcop1
) - EXPD(fptemp1
);
817 /* optimisation? taken from the AMD docs */
818 env
->fpus
&= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
819 /* ST0 is unchanged */
824 dblq
= fpsrcop
/ fptemp
; /* ST0 / ST1 */
825 /* round dblq towards zero */
826 dblq
= (dblq
< 0.0) ? ceil(dblq
) : floor(dblq
);
827 st0
= fpsrcop
- fptemp
* dblq
; /* fpsrcop is ST0 */
829 /* convert dblq to q by truncating towards zero */
831 q
= (signed long long int)(-dblq
);
833 q
= (signed long long int)dblq
;
836 env
->fpus
&= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
837 /* (C0,C3,C1) <-- (q2,q1,q0) */
838 env
->fpus
|= (q
& 0x4) << (8 - 2); /* (C0) <-- q2 */
839 env
->fpus
|= (q
& 0x2) << (14 - 1); /* (C3) <-- q1 */
840 env
->fpus
|= (q
& 0x1) << (9 - 0); /* (C1) <-- q0 */
842 int N
= 32 + (expdif
% 32); /* as per AMD docs */
844 env
->fpus
|= 0x400; /* C2 <-- 1 */
845 fptemp
= pow(2.0, (double)(expdif
- N
));
846 fpsrcop
= (st0
/ st1
) / fptemp
;
847 /* fpsrcop = integer obtained by chopping */
848 fpsrcop
= (fpsrcop
< 0.0) ?
849 -(floor(fabs(fpsrcop
))) : floor(fpsrcop
);
850 st0
-= (st1
* fpsrcop
* fptemp
);
852 ST0
= double_to_floatx80(env
, st0
);
855 void helper_fyl2xp1(CPUX86State
*env
)
857 double fptemp
= floatx80_to_double(env
, ST0
);
859 if ((fptemp
+ 1.0) > 0.0) {
860 fptemp
= log(fptemp
+ 1.0) / log(2.0); /* log2(ST + 1.0) */
861 fptemp
*= floatx80_to_double(env
, ST1
);
862 ST1
= double_to_floatx80(env
, fptemp
);
865 env
->fpus
&= ~0x4700;
870 void helper_fsqrt(CPUX86State
*env
)
872 if (floatx80_is_neg(ST0
)) {
873 env
->fpus
&= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
876 ST0
= floatx80_sqrt(ST0
, &env
->fp_status
);
879 void helper_fsincos(CPUX86State
*env
)
881 double fptemp
= floatx80_to_double(env
, ST0
);
883 if ((fptemp
> MAXTAN
) || (fptemp
< -MAXTAN
)) {
886 ST0
= double_to_floatx80(env
, sin(fptemp
));
888 ST0
= double_to_floatx80(env
, cos(fptemp
));
889 env
->fpus
&= ~0x400; /* C2 <-- 0 */
890 /* the above code is for |arg| < 2**63 only */
894 void helper_frndint(CPUX86State
*env
)
896 ST0
= floatx80_round_to_int(ST0
, &env
->fp_status
);
899 void helper_fscale(CPUX86State
*env
)
901 if (floatx80_is_any_nan(ST1
)) {
904 int n
= floatx80_to_int32_round_to_zero(ST1
, &env
->fp_status
);
905 ST0
= floatx80_scalbn(ST0
, n
, &env
->fp_status
);
909 void helper_fsin(CPUX86State
*env
)
911 double fptemp
= floatx80_to_double(env
, ST0
);
913 if ((fptemp
> MAXTAN
) || (fptemp
< -MAXTAN
)) {
916 ST0
= double_to_floatx80(env
, sin(fptemp
));
917 env
->fpus
&= ~0x400; /* C2 <-- 0 */
918 /* the above code is for |arg| < 2**53 only */
922 void helper_fcos(CPUX86State
*env
)
924 double fptemp
= floatx80_to_double(env
, ST0
);
926 if ((fptemp
> MAXTAN
) || (fptemp
< -MAXTAN
)) {
929 ST0
= double_to_floatx80(env
, cos(fptemp
));
930 env
->fpus
&= ~0x400; /* C2 <-- 0 */
931 /* the above code is for |arg| < 2**63 only */
935 void helper_fxam_ST0(CPUX86State
*env
)
942 env
->fpus
&= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
944 env
->fpus
|= 0x200; /* C1 <-- 1 */
947 /* XXX: test fptags too */
949 if (expdif
== MAXEXPD
) {
950 if (MANTD(temp
) == 0x8000000000000000ULL
) {
951 env
->fpus
|= 0x500; /* Infinity */
953 env
->fpus
|= 0x100; /* NaN */
955 } else if (expdif
== 0) {
956 if (MANTD(temp
) == 0) {
957 env
->fpus
|= 0x4000; /* Zero */
959 env
->fpus
|= 0x4400; /* Denormal */
966 void helper_fstenv(CPUX86State
*env
, target_ulong ptr
, int data32
)
968 int fpus
, fptag
, exp
, i
;
972 fpus
= (env
->fpus
& ~0x3800) | (env
->fpstt
& 0x7) << 11;
974 for (i
= 7; i
>= 0; i
--) {
976 if (env
->fptags
[i
]) {
979 tmp
.d
= env
->fpregs
[i
].d
;
982 if (exp
== 0 && mant
== 0) {
985 } else if (exp
== 0 || exp
== MAXEXPD
986 || (mant
& (1LL << 63)) == 0) {
987 /* NaNs, infinity, denormal */
994 cpu_stl_data(env
, ptr
, env
->fpuc
);
995 cpu_stl_data(env
, ptr
+ 4, fpus
);
996 cpu_stl_data(env
, ptr
+ 8, fptag
);
997 cpu_stl_data(env
, ptr
+ 12, 0); /* fpip */
998 cpu_stl_data(env
, ptr
+ 16, 0); /* fpcs */
999 cpu_stl_data(env
, ptr
+ 20, 0); /* fpoo */
1000 cpu_stl_data(env
, ptr
+ 24, 0); /* fpos */
1003 cpu_stw_data(env
, ptr
, env
->fpuc
);
1004 cpu_stw_data(env
, ptr
+ 2, fpus
);
1005 cpu_stw_data(env
, ptr
+ 4, fptag
);
1006 cpu_stw_data(env
, ptr
+ 6, 0);
1007 cpu_stw_data(env
, ptr
+ 8, 0);
1008 cpu_stw_data(env
, ptr
+ 10, 0);
1009 cpu_stw_data(env
, ptr
+ 12, 0);
1013 void helper_fldenv(CPUX86State
*env
, target_ulong ptr
, int data32
)
1018 env
->fpuc
= cpu_lduw_data(env
, ptr
);
1019 fpus
= cpu_lduw_data(env
, ptr
+ 4);
1020 fptag
= cpu_lduw_data(env
, ptr
+ 8);
1022 env
->fpuc
= cpu_lduw_data(env
, ptr
);
1023 fpus
= cpu_lduw_data(env
, ptr
+ 2);
1024 fptag
= cpu_lduw_data(env
, ptr
+ 4);
1026 env
->fpstt
= (fpus
>> 11) & 7;
1027 env
->fpus
= fpus
& ~0x3800;
1028 for (i
= 0; i
< 8; i
++) {
1029 env
->fptags
[i
] = ((fptag
& 3) == 3);
1034 void helper_fsave(CPUX86State
*env
, target_ulong ptr
, int data32
)
1039 helper_fstenv(env
, ptr
, data32
);
1041 ptr
+= (14 << data32
);
1042 for (i
= 0; i
< 8; i
++) {
1044 helper_fstt(env
, tmp
, ptr
);
1062 void helper_frstor(CPUX86State
*env
, target_ulong ptr
, int data32
)
1067 helper_fldenv(env
, ptr
, data32
);
1068 ptr
+= (14 << data32
);
1070 for (i
= 0; i
< 8; i
++) {
1071 tmp
= helper_fldt(env
, ptr
);
1077 #if defined(CONFIG_USER_ONLY)
1078 void cpu_x86_fsave(CPUX86State
*env
, target_ulong ptr
, int data32
)
1080 helper_fsave(env
, ptr
, data32
);
1083 void cpu_x86_frstor(CPUX86State
*env
, target_ulong ptr
, int data32
)
1085 helper_frstor(env
, ptr
, data32
);
1089 void helper_fxsave(CPUX86State
*env
, target_ulong ptr
, int data64
)
1091 int fpus
, fptag
, i
, nb_xmm_regs
;
1095 /* The operand must be 16 byte aligned */
1097 raise_exception(env
, EXCP0D_GPF
);
1100 fpus
= (env
->fpus
& ~0x3800) | (env
->fpstt
& 0x7) << 11;
1102 for (i
= 0; i
< 8; i
++) {
1103 fptag
|= (env
->fptags
[i
] << i
);
1105 cpu_stw_data(env
, ptr
, env
->fpuc
);
1106 cpu_stw_data(env
, ptr
+ 2, fpus
);
1107 cpu_stw_data(env
, ptr
+ 4, fptag
^ 0xff);
1108 #ifdef TARGET_X86_64
1110 cpu_stq_data(env
, ptr
+ 0x08, 0); /* rip */
1111 cpu_stq_data(env
, ptr
+ 0x10, 0); /* rdp */
1115 cpu_stl_data(env
, ptr
+ 0x08, 0); /* eip */
1116 cpu_stl_data(env
, ptr
+ 0x0c, 0); /* sel */
1117 cpu_stl_data(env
, ptr
+ 0x10, 0); /* dp */
1118 cpu_stl_data(env
, ptr
+ 0x14, 0); /* sel */
1122 for (i
= 0; i
< 8; i
++) {
1124 helper_fstt(env
, tmp
, addr
);
1128 if (env
->cr
[4] & CR4_OSFXSR_MASK
) {
1129 /* XXX: finish it */
1130 cpu_stl_data(env
, ptr
+ 0x18, env
->mxcsr
); /* mxcsr */
1131 cpu_stl_data(env
, ptr
+ 0x1c, 0x0000ffff); /* mxcsr_mask */
1132 if (env
->hflags
& HF_CS64_MASK
) {
1138 /* Fast FXSAVE leaves out the XMM registers */
1139 if (!(env
->efer
& MSR_EFER_FFXSR
)
1140 || (env
->hflags
& HF_CPL_MASK
)
1141 || !(env
->hflags
& HF_LMA_MASK
)) {
1142 for (i
= 0; i
< nb_xmm_regs
; i
++) {
1143 cpu_stq_data(env
, addr
, env
->xmm_regs
[i
].XMM_Q(0));
1144 cpu_stq_data(env
, addr
+ 8, env
->xmm_regs
[i
].XMM_Q(1));
1151 void helper_fxrstor(CPUX86State
*env
, target_ulong ptr
, int data64
)
1153 int i
, fpus
, fptag
, nb_xmm_regs
;
1157 /* The operand must be 16 byte aligned */
1159 raise_exception(env
, EXCP0D_GPF
);
1162 env
->fpuc
= cpu_lduw_data(env
, ptr
);
1163 fpus
= cpu_lduw_data(env
, ptr
+ 2);
1164 fptag
= cpu_lduw_data(env
, ptr
+ 4);
1165 env
->fpstt
= (fpus
>> 11) & 7;
1166 env
->fpus
= fpus
& ~0x3800;
1168 for (i
= 0; i
< 8; i
++) {
1169 env
->fptags
[i
] = ((fptag
>> i
) & 1);
1173 for (i
= 0; i
< 8; i
++) {
1174 tmp
= helper_fldt(env
, addr
);
1179 if (env
->cr
[4] & CR4_OSFXSR_MASK
) {
1180 /* XXX: finish it */
1181 env
->mxcsr
= cpu_ldl_data(env
, ptr
+ 0x18);
1182 /* cpu_ldl_data(env, ptr + 0x1c); */
1183 if (env
->hflags
& HF_CS64_MASK
) {
1189 /* Fast FXRESTORE leaves out the XMM registers */
1190 if (!(env
->efer
& MSR_EFER_FFXSR
)
1191 || (env
->hflags
& HF_CPL_MASK
)
1192 || !(env
->hflags
& HF_LMA_MASK
)) {
1193 for (i
= 0; i
< nb_xmm_regs
; i
++) {
1194 env
->xmm_regs
[i
].XMM_Q(0) = cpu_ldq_data(env
, addr
);
1195 env
->xmm_regs
[i
].XMM_Q(1) = cpu_ldq_data(env
, addr
+ 8);
1202 void cpu_get_fp80(uint64_t *pmant
, uint16_t *pexp
, floatx80 f
)
1207 *pmant
= temp
.l
.lower
;
1208 *pexp
= temp
.l
.upper
;
1211 floatx80
cpu_set_fp80(uint64_t mant
, uint16_t upper
)
1215 temp
.l
.upper
= upper
;
1216 temp
.l
.lower
= mant
;
1221 /* XXX: optimize by storing fptt and fptags in the static cpu state */
1223 #define SSE_DAZ 0x0040
1224 #define SSE_RC_MASK 0x6000
1225 #define SSE_RC_NEAR 0x0000
1226 #define SSE_RC_DOWN 0x2000
1227 #define SSE_RC_UP 0x4000
1228 #define SSE_RC_CHOP 0x6000
1229 #define SSE_FZ 0x8000
1231 static void update_sse_status(CPUX86State
*env
)
1235 /* set rounding mode */
1236 switch (env
->mxcsr
& SSE_RC_MASK
) {
1239 rnd_type
= float_round_nearest_even
;
1242 rnd_type
= float_round_down
;
1245 rnd_type
= float_round_up
;
1248 rnd_type
= float_round_to_zero
;
1251 set_float_rounding_mode(rnd_type
, &env
->sse_status
);
1253 /* set denormals are zero */
1254 set_flush_inputs_to_zero((env
->mxcsr
& SSE_DAZ
) ? 1 : 0, &env
->sse_status
);
1256 /* set flush to zero */
1257 set_flush_to_zero((env
->mxcsr
& SSE_FZ
) ? 1 : 0, &env
->fp_status
);
1260 void helper_ldmxcsr(CPUX86State
*env
, uint32_t val
)
1263 update_sse_status(env
);
1266 void helper_enter_mmx(CPUX86State
*env
)
1269 *(uint32_t *)(env
->fptags
) = 0;
1270 *(uint32_t *)(env
->fptags
+ 4) = 0;
1273 void helper_emms(CPUX86State
*env
)
1275 /* set to empty state */
1276 *(uint32_t *)(env
->fptags
) = 0x01010101;
1277 *(uint32_t *)(env
->fptags
+ 4) = 0x01010101;
1281 void helper_movq(CPUX86State
*env
, void *d
, void *s
)
1283 *(uint64_t *)d
= *(uint64_t *)s
;
1287 #include "ops_sse.h"
1290 #include "ops_sse.h"