hw/net/milkymist-minimac2.c

   1 /*
   2  *  QEMU model of the Milkymist minimac2 block.
   3  *
   4  *  Copyright (c) 2011 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   not available yet
  22  *
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qapi/error.h"
  27 #include "qom/object.h"
  28 #include "cpu.h" /* FIXME: why does this use TARGET_PAGE_ALIGN? */
  29 #include "hw/irq.h"
  30 #include "hw/qdev-properties.h"
  31 #include "hw/sysbus.h"
  32 #include "migration/vmstate.h"
  33 #include "trace.h"
  34 #include "net/net.h"
  35 #include "qemu/log.h"
  36 #include "qemu/module.h"
  37 #include "qemu/error-report.h"
  38
  39 #include <zlib.h>
  40
  41 enum {
  42     R_SETUP = 0,
  43     R_MDIO,
  44     R_STATE0,
  45     R_COUNT0,
  46     R_STATE1,
  47     R_COUNT1,
  48     R_TXCOUNT,
  49     R_MAX
  50 };
  51
  52 enum {
  53     SETUP_PHY_RST = (1<<0),
  54 };
  55
  56 enum {
  57     MDIO_DO  = (1<<0),
  58     MDIO_DI  = (1<<1),
  59     MDIO_OE  = (1<<2),
  60     MDIO_CLK = (1<<3),
  61 };
  62
  63 enum {
  64     STATE_EMPTY   = 0,
  65     STATE_LOADED  = 1,
  66     STATE_PENDING = 2,
  67 };
  68
  69 enum {
  70     MDIO_OP_WRITE = 1,
  71     MDIO_OP_READ  = 2,
  72 };
  73
  74 enum mdio_state {
  75     MDIO_STATE_IDLE,
  76     MDIO_STATE_READING,
  77     MDIO_STATE_WRITING,
  78 };
  79
  80 enum {
  81     R_PHY_ID1  = 2,
  82     R_PHY_ID2  = 3,
  83     R_PHY_MAX  = 32
  84 };
  85
  86 #define MINIMAC2_MTU 1530
  87 #define MINIMAC2_BUFFER_SIZE 2048
  88
  89 struct MilkymistMinimac2MdioState {
  90     int last_clk;
  91     int count;
  92     uint32_t data;
  93     uint16_t data_out;
  94     int state;
  95
  96     uint8_t phy_addr;
  97     uint8_t reg_addr;
  98 };
  99 typedef struct MilkymistMinimac2MdioState MilkymistMinimac2MdioState;
 100
 101 #define TYPE_MILKYMIST_MINIMAC2 "milkymist-minimac2"
 102 OBJECT_DECLARE_SIMPLE_TYPE(MilkymistMinimac2State, MILKYMIST_MINIMAC2)
 103
 104 struct MilkymistMinimac2State {
 105     SysBusDevice parent_obj;
 106
 107     NICState *nic;
 108     NICConf conf;
 109     char *phy_model;
 110     MemoryRegion buffers;
 111     MemoryRegion regs_region;
 112
 113     qemu_irq rx_irq;
 114     qemu_irq tx_irq;
 115
 116     uint32_t regs[R_MAX];
 117
 118     MilkymistMinimac2MdioState mdio;
 119
 120     uint16_t phy_regs[R_PHY_MAX];
 121
 122     uint8_t *rx0_buf;
 123     uint8_t *rx1_buf;
 124     uint8_t *tx_buf;
 125 };
 126
 127 static const uint8_t preamble_sfd[] = {
 128         0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xd5
 129 };
 130
 131 static void minimac2_mdio_write_reg(MilkymistMinimac2State *s,
 132         uint8_t phy_addr, uint8_t reg_addr, uint16_t value)
 133 {
 134     trace_milkymist_minimac2_mdio_write(phy_addr, reg_addr, value);
 135
 136     /* nop */
 137 }
 138
 139 static uint16_t minimac2_mdio_read_reg(MilkymistMinimac2State *s,
 140         uint8_t phy_addr, uint8_t reg_addr)
 141 {
 142     uint16_t r = s->phy_regs[reg_addr];
 143
 144     trace_milkymist_minimac2_mdio_read(phy_addr, reg_addr, r);
 145
 146     return r;
 147 }
 148
 149 static void minimac2_update_mdio(MilkymistMinimac2State *s)
 150 {
 151     MilkymistMinimac2MdioState *m = &s->mdio;
 152
 153     /* detect rising clk edge */
 154     if (m->last_clk == 0 && (s->regs[R_MDIO] & MDIO_CLK)) {
 155         /* shift data in */
 156         int bit = ((s->regs[R_MDIO] & MDIO_DO)
 157                    && (s->regs[R_MDIO] & MDIO_OE)) ? 1 : 0;
 158         m->data = (m->data << 1) | bit;
 159
 160         /* check for sync */
 161         if (m->data == 0xffffffff) {
 162             m->count = 32;
 163         }
 164
 165         if (m->count == 16) {
 166             uint8_t start = (m->data >> 14) & 0x3;
 167             uint8_t op = (m->data >> 12) & 0x3;
 168             uint8_t ta = (m->data) & 0x3;
 169
 170             if (start == 1 && op == MDIO_OP_WRITE && ta == 2) {
 171                 m->state = MDIO_STATE_WRITING;
 172             } else if (start == 1 && op == MDIO_OP_READ && (ta & 1) == 0) {
 173                 m->state = MDIO_STATE_READING;
 174             } else {
 175                 m->state = MDIO_STATE_IDLE;
 176             }
 177
 178             if (m->state != MDIO_STATE_IDLE) {
 179                 m->phy_addr = (m->data >> 7) & 0x1f;
 180                 m->reg_addr = (m->data >> 2) & 0x1f;
 181             }
 182
 183             if (m->state == MDIO_STATE_READING) {
 184                 m->data_out = minimac2_mdio_read_reg(s, m->phy_addr,
 185                         m->reg_addr);
 186             }
 187         }
 188
 189         if (m->count < 16 && m->state == MDIO_STATE_READING) {
 190             int bit = (m->data_out & 0x8000) ? 1 : 0;
 191             m->data_out <<= 1;
 192
 193             if (bit) {
 194                 s->regs[R_MDIO] |= MDIO_DI;
 195             } else {
 196                 s->regs[R_MDIO] &= ~MDIO_DI;
 197             }
 198         }
 199
 200         if (m->count == 0 && m->state) {
 201             if (m->state == MDIO_STATE_WRITING) {
 202                 uint16_t data = m->data & 0xffff;
 203                 minimac2_mdio_write_reg(s, m->phy_addr, m->reg_addr, data);
 204             }
 205             m->state = MDIO_STATE_IDLE;
 206         }
 207         m->count--;
 208     }
 209
 210     m->last_clk = (s->regs[R_MDIO] & MDIO_CLK) ? 1 : 0;
 211 }
 212
 213 static size_t assemble_frame(uint8_t *buf, size_t size,
 214         const uint8_t *payload, size_t payload_size)
 215 {
 216     uint32_t crc;
 217
 218     if (size < payload_size + 12) {
 219         qemu_log_mask(LOG_GUEST_ERROR, "milkymist_minimac2: frame too big "
 220                       "(%zd bytes)\n", payload_size);
 221         return 0;
 222     }
 223
 224     /* prepend preamble and sfd */
 225     memcpy(buf, preamble_sfd, 8);
 226
 227     /* now copy the payload */
 228     memcpy(buf + 8, payload, payload_size);
 229
 230     /* pad frame if needed */
 231     if (payload_size < 60) {
 232         memset(buf + payload_size + 8, 0, 60 - payload_size);
 233         payload_size = 60;
 234     }
 235
 236     /* append fcs */
 237     crc = cpu_to_le32(crc32(0, buf + 8, payload_size));
 238     memcpy(buf + payload_size + 8, &crc, 4);
 239
 240     return payload_size + 12;
 241 }
 242
 243 static void minimac2_tx(MilkymistMinimac2State *s)
 244 {
 245     uint32_t txcount = s->regs[R_TXCOUNT];
 246     uint8_t *buf = s->tx_buf;
 247
 248     if (txcount < 64) {
 249         error_report("milkymist_minimac2: ethernet frame too small (%u < %u)",
 250                 txcount, 64);
 251         goto err;
 252     }
 253
 254     if (txcount > MINIMAC2_MTU) {
 255         error_report("milkymist_minimac2: MTU exceeded (%u > %u)",
 256                 txcount, MINIMAC2_MTU);
 257         goto err;
 258     }
 259
 260     if (memcmp(buf, preamble_sfd, 8) != 0) {
 261         error_report("milkymist_minimac2: frame doesn't contain the preamble "
 262                 "and/or the SFD (%02x %02x %02x %02x %02x %02x %02x %02x)",
 263                 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]);
 264         goto err;
 265     }
 266
 267     trace_milkymist_minimac2_tx_frame(txcount - 12);
 268
 269     /* send packet, skipping preamble and sfd */
 270     qemu_send_packet_raw(qemu_get_queue(s->nic), buf + 8, txcount - 12);
 271
 272     s->regs[R_TXCOUNT] = 0;
 273
 274 err:
 275     trace_milkymist_minimac2_pulse_irq_tx();
 276     qemu_irq_pulse(s->tx_irq);
 277 }
 278
 279 static void update_rx_interrupt(MilkymistMinimac2State *s)
 280 {
 281     if (s->regs[R_STATE0] == STATE_PENDING
 282             || s->regs[R_STATE1] == STATE_PENDING) {
 283         trace_milkymist_minimac2_raise_irq_rx();
 284         qemu_irq_raise(s->rx_irq);
 285     } else {
 286         trace_milkymist_minimac2_lower_irq_rx();
 287         qemu_irq_lower(s->rx_irq);
 288     }
 289 }
 290
 291 static ssize_t minimac2_rx(NetClientState *nc, const uint8_t *buf, size_t size)
 292 {
 293     MilkymistMinimac2State *s = qemu_get_nic_opaque(nc);
 294
 295     uint32_t r_count;
 296     uint32_t r_state;
 297     uint8_t *rx_buf;
 298
 299     size_t frame_size;
 300
 301     trace_milkymist_minimac2_rx_frame(buf, size);
 302
 303     /* choose appropriate slot */
 304     if (s->regs[R_STATE0] == STATE_LOADED) {
 305         r_count = R_COUNT0;
 306         r_state = R_STATE0;
 307         rx_buf = s->rx0_buf;
 308     } else if (s->regs[R_STATE1] == STATE_LOADED) {
 309         r_count = R_COUNT1;
 310         r_state = R_STATE1;
 311         rx_buf = s->rx1_buf;
 312     } else {
 313         return 0;
 314     }
 315
 316     /* assemble frame */
 317     frame_size = assemble_frame(rx_buf, MINIMAC2_BUFFER_SIZE, buf, size);
 318
 319     if (frame_size == 0) {
 320         return size;
 321     }
 322
 323     trace_milkymist_minimac2_rx_transfer(rx_buf, frame_size);
 324
 325     /* update slot */
 326     s->regs[r_count] = frame_size;
 327     s->regs[r_state] = STATE_PENDING;
 328
 329     update_rx_interrupt(s);
 330
 331     return size;
 332 }
 333
 334 static uint64_t
 335 minimac2_read(void *opaque, hwaddr addr, unsigned size)
 336 {
 337     MilkymistMinimac2State *s = opaque;
 338     uint32_t r = 0;
 339
 340     addr >>= 2;
 341     switch (addr) {
 342     case R_SETUP:
 343     case R_MDIO:
 344     case R_STATE0:
 345     case R_COUNT0:
 346     case R_STATE1:
 347     case R_COUNT1:
 348     case R_TXCOUNT:
 349         r = s->regs[addr];
 350         break;
 351
 352     default:
 353         qemu_log_mask(LOG_GUEST_ERROR,
 354                       "milkymist_minimac2_rd%d: 0x%" HWADDR_PRIx "\n",
 355                       size, addr << 2);
 356         break;
 357     }
 358
 359     trace_milkymist_minimac2_memory_read(addr << 2, r);
 360
 361     return r;
 362 }
 363
 364 static int minimac2_can_rx(MilkymistMinimac2State *s)
 365 {
 366     if (s->regs[R_STATE0] == STATE_LOADED) {
 367         return 1;
 368     }
 369     if (s->regs[R_STATE1] == STATE_LOADED) {
 370         return 1;
 371     }
 372
 373     return 0;
 374 }
 375
 376 static void
 377 minimac2_write(void *opaque, hwaddr addr, uint64_t value,
 378                unsigned size)
 379 {
 380     MilkymistMinimac2State *s = opaque;
 381
 382     trace_milkymist_minimac2_memory_write(addr, value);
 383
 384     addr >>= 2;
 385     switch (addr) {
 386     case R_MDIO:
 387     {
 388         /* MDIO_DI is read only */
 389         int mdio_di = (s->regs[R_MDIO] & MDIO_DI);
 390         s->regs[R_MDIO] = value;
 391         if (mdio_di) {
 392             s->regs[R_MDIO] |= mdio_di;
 393         } else {
 394             s->regs[R_MDIO] &= ~mdio_di;
 395         }
 396
 397         minimac2_update_mdio(s);
 398     } break;
 399     case R_TXCOUNT:
 400         s->regs[addr] = value;
 401         if (value > 0) {
 402             minimac2_tx(s);
 403         }
 404         break;
 405     case R_STATE0:
 406     case R_STATE1:
 407         s->regs[addr] = value;
 408         update_rx_interrupt(s);
 409         if (minimac2_can_rx(s)) {
 410             qemu_flush_queued_packets(qemu_get_queue(s->nic));
 411         }
 412         break;
 413     case R_SETUP:
 414     case R_COUNT0:
 415     case R_COUNT1:
 416         s->regs[addr] = value;
 417         break;
 418
 419     default:
 420         qemu_log_mask(LOG_GUEST_ERROR,
 421                       "milkymist_minimac2_wr%d: 0x%" HWADDR_PRIx
 422                       " = 0x%" PRIx64 "\n",
 423                       size, addr << 2, value);
 424         break;
 425     }
 426 }
 427
 428 static const MemoryRegionOps minimac2_ops = {
 429     .read = minimac2_read,
 430     .write = minimac2_write,
 431     .valid = {
 432         .min_access_size = 4,
 433         .max_access_size = 4,
 434     },
 435     .endianness = DEVICE_NATIVE_ENDIAN,
 436 };
 437
 438 static void milkymist_minimac2_reset(DeviceState *d)
 439 {
 440     MilkymistMinimac2State *s = MILKYMIST_MINIMAC2(d);
 441     int i;
 442
 443     for (i = 0; i < R_MAX; i++) {
 444         s->regs[i] = 0;
 445     }
 446     for (i = 0; i < R_PHY_MAX; i++) {
 447         s->phy_regs[i] = 0;
 448     }
 449
 450     /* defaults */
 451     s->phy_regs[R_PHY_ID1] = 0x0022; /* Micrel KSZ8001L */
 452     s->phy_regs[R_PHY_ID2] = 0x161a;
 453 }
 454
 455 static NetClientInfo net_milkymist_minimac2_info = {
 456     .type = NET_CLIENT_DRIVER_NIC,
 457     .size = sizeof(NICState),
 458     .receive = minimac2_rx,
 459 };
 460
 461 static void milkymist_minimac2_realize(DeviceState *dev, Error **errp)
 462 {
 463     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 464     MilkymistMinimac2State *s = MILKYMIST_MINIMAC2(dev);
 465     size_t buffers_size = TARGET_PAGE_ALIGN(3 * MINIMAC2_BUFFER_SIZE);
 466
 467     sysbus_init_irq(sbd, &s->rx_irq);
 468     sysbus_init_irq(sbd, &s->tx_irq);
 469
 470     memory_region_init_io(&s->regs_region, OBJECT(dev), &minimac2_ops, s,
 471                           "milkymist-minimac2", R_MAX * 4);
 472     sysbus_init_mmio(sbd, &s->regs_region);
 473
 474     /* register buffers memory */
 475     memory_region_init_ram_nomigrate(&s->buffers, OBJECT(dev), "milkymist-minimac2.buffers",
 476                            buffers_size, &error_fatal);
 477     vmstate_register_ram_global(&s->buffers);
 478     s->rx0_buf = memory_region_get_ram_ptr(&s->buffers);
 479     s->rx1_buf = s->rx0_buf + MINIMAC2_BUFFER_SIZE;
 480     s->tx_buf = s->rx1_buf + MINIMAC2_BUFFER_SIZE;
 481
 482     sysbus_init_mmio(sbd, &s->buffers);
 483
 484     qemu_macaddr_default_if_unset(&s->conf.macaddr);
 485     s->nic = qemu_new_nic(&net_milkymist_minimac2_info, &s->conf,
 486                           object_get_typename(OBJECT(dev)), dev->id, s);
 487     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
 488 }
 489
 490 static const VMStateDescription vmstate_milkymist_minimac2_mdio = {
 491     .name = "milkymist-minimac2-mdio",
 492     .version_id = 1,
 493     .minimum_version_id = 1,
 494     .fields = (VMStateField[]) {
 495         VMSTATE_INT32(last_clk, MilkymistMinimac2MdioState),
 496         VMSTATE_INT32(count, MilkymistMinimac2MdioState),
 497         VMSTATE_UINT32(data, MilkymistMinimac2MdioState),
 498         VMSTATE_UINT16(data_out, MilkymistMinimac2MdioState),
 499         VMSTATE_INT32(state, MilkymistMinimac2MdioState),
 500         VMSTATE_UINT8(phy_addr, MilkymistMinimac2MdioState),
 501         VMSTATE_UINT8(reg_addr, MilkymistMinimac2MdioState),
 502         VMSTATE_END_OF_LIST()
 503     }
 504 };
 505
 506 static const VMStateDescription vmstate_milkymist_minimac2 = {
 507     .name = "milkymist-minimac2",
 508     .version_id = 1,
 509     .minimum_version_id = 1,
 510     .fields = (VMStateField[]) {
 511         VMSTATE_UINT32_ARRAY(regs, MilkymistMinimac2State, R_MAX),
 512         VMSTATE_UINT16_ARRAY(phy_regs, MilkymistMinimac2State, R_PHY_MAX),
 513         VMSTATE_STRUCT(mdio, MilkymistMinimac2State, 0,
 514                 vmstate_milkymist_minimac2_mdio, MilkymistMinimac2MdioState),
 515         VMSTATE_END_OF_LIST()
 516     }
 517 };
 518
 519 static Property milkymist_minimac2_properties[] = {
 520     DEFINE_NIC_PROPERTIES(MilkymistMinimac2State, conf),
 521     DEFINE_PROP_STRING("phy_model", MilkymistMinimac2State, phy_model),
 522     DEFINE_PROP_END_OF_LIST(),
 523 };
 524
 525 static void milkymist_minimac2_class_init(ObjectClass *klass, void *data)
 526 {
 527     DeviceClass *dc = DEVICE_CLASS(klass);
 528
 529     dc->realize = milkymist_minimac2_realize;
 530     dc->reset = milkymist_minimac2_reset;
 531     dc->vmsd = &vmstate_milkymist_minimac2;
 532     device_class_set_props(dc, milkymist_minimac2_properties);
 533 }
 534
 535 static const TypeInfo milkymist_minimac2_info = {
 536     .name          = TYPE_MILKYMIST_MINIMAC2,
 537     .parent        = TYPE_SYS_BUS_DEVICE,
 538     .instance_size = sizeof(MilkymistMinimac2State),
 539     .class_init    = milkymist_minimac2_class_init,
 540 };
 541
 542 static void milkymist_minimac2_register_types(void)
 543 {
 544     type_register_static(&milkymist_minimac2_info);
 545 }
 546
 547 type_init(milkymist_minimac2_register_types)