2 * QEMU lowRISC Ibex UART device
4 * Copyright (c) 2020 Western Digital
6 * For details check the documentation here:
7 * https://docs.opentitan.org/hw/ip/uart/doc/
9 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to deal
11 * in the Software without restriction, including without limitation the rights
12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 * copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 #include "qemu/osdep.h"
29 #include "hw/char/ibex_uart.h"
31 #include "hw/qdev-clock.h"
32 #include "hw/qdev-properties.h"
33 #include "hw/qdev-properties-system.h"
34 #include "migration/vmstate.h"
36 #include "qemu/module.h"
38 static void ibex_uart_update_irqs(IbexUartState
*s
)
40 if (s
->uart_intr_state
& s
->uart_intr_enable
& R_INTR_STATE_TX_WATERMARK_MASK
) {
41 qemu_set_irq(s
->tx_watermark
, 1);
43 qemu_set_irq(s
->tx_watermark
, 0);
46 if (s
->uart_intr_state
& s
->uart_intr_enable
& R_INTR_STATE_RX_WATERMARK_MASK
) {
47 qemu_set_irq(s
->rx_watermark
, 1);
49 qemu_set_irq(s
->rx_watermark
, 0);
52 if (s
->uart_intr_state
& s
->uart_intr_enable
& R_INTR_STATE_TX_EMPTY_MASK
) {
53 qemu_set_irq(s
->tx_empty
, 1);
55 qemu_set_irq(s
->tx_empty
, 0);
58 if (s
->uart_intr_state
& s
->uart_intr_enable
& R_INTR_STATE_RX_OVERFLOW_MASK
) {
59 qemu_set_irq(s
->rx_overflow
, 1);
61 qemu_set_irq(s
->rx_overflow
, 0);
65 static int ibex_uart_can_receive(void *opaque
)
67 IbexUartState
*s
= opaque
;
69 if (s
->uart_ctrl
& R_CTRL_RX_ENABLE_MASK
) {
76 static void ibex_uart_receive(void *opaque
, const uint8_t *buf
, int size
)
78 IbexUartState
*s
= opaque
;
79 uint8_t rx_fifo_level
= (s
->uart_fifo_ctrl
& R_FIFO_CTRL_RXILVL_MASK
)
80 >> R_FIFO_CTRL_RXILVL_SHIFT
;
84 s
->uart_status
&= ~R_STATUS_RXIDLE_MASK
;
85 s
->uart_status
&= ~R_STATUS_RXEMPTY_MASK
;
87 if (size
> rx_fifo_level
) {
88 s
->uart_intr_state
|= R_INTR_STATE_RX_WATERMARK_MASK
;
91 ibex_uart_update_irqs(s
);
94 static gboolean
ibex_uart_xmit(GIOChannel
*chan
, GIOCondition cond
,
97 IbexUartState
*s
= opaque
;
98 uint8_t tx_fifo_level
= (s
->uart_fifo_ctrl
& R_FIFO_CTRL_TXILVL_MASK
)
99 >> R_FIFO_CTRL_TXILVL_SHIFT
;
102 /* instant drain the fifo when there's no back-end */
103 if (!qemu_chr_fe_backend_connected(&s
->chr
)) {
109 s
->uart_status
&= ~R_STATUS_TXFULL_MASK
;
110 s
->uart_status
|= R_STATUS_TXEMPTY_MASK
;
111 s
->uart_intr_state
|= R_INTR_STATE_TX_EMPTY_MASK
;
112 s
->uart_intr_state
&= ~R_INTR_STATE_TX_WATERMARK_MASK
;
113 ibex_uart_update_irqs(s
);
117 ret
= qemu_chr_fe_write(&s
->chr
, s
->tx_fifo
, s
->tx_level
);
121 memmove(s
->tx_fifo
, s
->tx_fifo
+ ret
, s
->tx_level
);
125 guint r
= qemu_chr_fe_add_watch(&s
->chr
, G_IO_OUT
| G_IO_HUP
,
133 /* Clear the TX Full bit */
134 if (s
->tx_level
!= IBEX_UART_TX_FIFO_SIZE
) {
135 s
->uart_status
&= ~R_STATUS_TXFULL_MASK
;
138 /* Disable the TX_WATERMARK IRQ */
139 if (s
->tx_level
< tx_fifo_level
) {
140 s
->uart_intr_state
&= ~R_INTR_STATE_TX_WATERMARK_MASK
;
144 if (s
->tx_level
== 0) {
145 s
->uart_status
|= R_STATUS_TXEMPTY_MASK
;
146 s
->uart_intr_state
|= R_INTR_STATE_TX_EMPTY_MASK
;
149 ibex_uart_update_irqs(s
);
153 static void uart_write_tx_fifo(IbexUartState
*s
, const uint8_t *buf
,
156 uint64_t current_time
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
157 uint8_t tx_fifo_level
= (s
->uart_fifo_ctrl
& R_FIFO_CTRL_TXILVL_MASK
)
158 >> R_FIFO_CTRL_TXILVL_SHIFT
;
160 if (size
> IBEX_UART_TX_FIFO_SIZE
- s
->tx_level
) {
161 size
= IBEX_UART_TX_FIFO_SIZE
- s
->tx_level
;
162 qemu_log_mask(LOG_GUEST_ERROR
, "ibex_uart: TX FIFO overflow");
165 memcpy(s
->tx_fifo
+ s
->tx_level
, buf
, size
);
168 if (s
->tx_level
> 0) {
169 s
->uart_status
&= ~R_STATUS_TXEMPTY_MASK
;
172 if (s
->tx_level
>= tx_fifo_level
) {
173 s
->uart_intr_state
|= R_INTR_STATE_TX_WATERMARK_MASK
;
174 ibex_uart_update_irqs(s
);
177 if (s
->tx_level
== IBEX_UART_TX_FIFO_SIZE
) {
178 s
->uart_status
|= R_STATUS_TXFULL_MASK
;
181 timer_mod(s
->fifo_trigger_handle
, current_time
+
182 (s
->char_tx_time
* 4));
185 static void ibex_uart_reset(DeviceState
*dev
)
187 IbexUartState
*s
= IBEX_UART(dev
);
189 s
->uart_intr_state
= 0x00000000;
190 s
->uart_intr_state
= 0x00000000;
191 s
->uart_intr_enable
= 0x00000000;
192 s
->uart_ctrl
= 0x00000000;
193 s
->uart_status
= 0x0000003c;
194 s
->uart_rdata
= 0x00000000;
195 s
->uart_fifo_ctrl
= 0x00000000;
196 s
->uart_fifo_status
= 0x00000000;
197 s
->uart_ovrd
= 0x00000000;
198 s
->uart_val
= 0x00000000;
199 s
->uart_timeout_ctrl
= 0x00000000;
203 s
->char_tx_time
= (NANOSECONDS_PER_SECOND
/ 230400) * 10;
205 ibex_uart_update_irqs(s
);
208 static uint64_t ibex_uart_get_baud(IbexUartState
*s
)
212 baud
= ((s
->uart_ctrl
& R_CTRL_NCO_MASK
) >> 16);
213 baud
*= clock_get_hz(s
->f_clk
);
219 static uint64_t ibex_uart_read(void *opaque
, hwaddr addr
,
222 IbexUartState
*s
= opaque
;
223 uint64_t retvalue
= 0;
227 retvalue
= s
->uart_intr_state
;
230 retvalue
= s
->uart_intr_enable
;
233 qemu_log_mask(LOG_GUEST_ERROR
,
234 "%s: wdata is write only\n", __func__
);
238 retvalue
= s
->uart_ctrl
;
241 retvalue
= s
->uart_status
;
245 retvalue
= s
->uart_rdata
;
246 if (s
->uart_ctrl
& R_CTRL_RX_ENABLE_MASK
) {
247 qemu_chr_fe_accept_input(&s
->chr
);
249 s
->uart_status
|= R_STATUS_RXIDLE_MASK
;
250 s
->uart_status
|= R_STATUS_RXEMPTY_MASK
;
254 qemu_log_mask(LOG_GUEST_ERROR
,
255 "%s: wdata is write only\n", __func__
);
259 retvalue
= s
->uart_fifo_ctrl
;
262 retvalue
= s
->uart_fifo_status
;
264 retvalue
|= s
->tx_level
& 0x1F;
266 qemu_log_mask(LOG_UNIMP
,
267 "%s: RX fifos are not supported\n", __func__
);
271 retvalue
= s
->uart_ovrd
;
272 qemu_log_mask(LOG_UNIMP
,
273 "%s: ovrd is not supported\n", __func__
);
276 retvalue
= s
->uart_val
;
277 qemu_log_mask(LOG_UNIMP
,
278 "%s: val is not supported\n", __func__
);
281 retvalue
= s
->uart_timeout_ctrl
;
282 qemu_log_mask(LOG_UNIMP
,
283 "%s: timeout_ctrl is not supported\n", __func__
);
286 qemu_log_mask(LOG_GUEST_ERROR
,
287 "%s: Bad offset 0x%"HWADDR_PRIx
"\n", __func__
, addr
);
294 static void ibex_uart_write(void *opaque
, hwaddr addr
,
295 uint64_t val64
, unsigned int size
)
297 IbexUartState
*s
= opaque
;
298 uint32_t value
= val64
;
303 s
->uart_intr_state
&= ~value
;
304 ibex_uart_update_irqs(s
);
307 s
->uart_intr_enable
= value
;
308 ibex_uart_update_irqs(s
);
311 s
->uart_intr_state
|= value
;
312 ibex_uart_update_irqs(s
);
316 s
->uart_ctrl
= value
;
318 if (value
& R_CTRL_NF_MASK
) {
319 qemu_log_mask(LOG_UNIMP
,
320 "%s: UART_CTRL_NF is not supported\n", __func__
);
322 if (value
& R_CTRL_SLPBK_MASK
) {
323 qemu_log_mask(LOG_UNIMP
,
324 "%s: UART_CTRL_SLPBK is not supported\n", __func__
);
326 if (value
& R_CTRL_LLPBK_MASK
) {
327 qemu_log_mask(LOG_UNIMP
,
328 "%s: UART_CTRL_LLPBK is not supported\n", __func__
);
330 if (value
& R_CTRL_PARITY_EN_MASK
) {
331 qemu_log_mask(LOG_UNIMP
,
332 "%s: UART_CTRL_PARITY_EN is not supported\n",
335 if (value
& R_CTRL_PARITY_ODD_MASK
) {
336 qemu_log_mask(LOG_UNIMP
,
337 "%s: UART_CTRL_PARITY_ODD is not supported\n",
340 if (value
& R_CTRL_RXBLVL_MASK
) {
341 qemu_log_mask(LOG_UNIMP
,
342 "%s: UART_CTRL_RXBLVL is not supported\n", __func__
);
344 if (value
& R_CTRL_NCO_MASK
) {
345 uint64_t baud
= ibex_uart_get_baud(s
);
347 s
->char_tx_time
= (NANOSECONDS_PER_SECOND
/ baud
) * 10;
351 qemu_log_mask(LOG_GUEST_ERROR
,
352 "%s: status is read only\n", __func__
);
356 qemu_log_mask(LOG_GUEST_ERROR
,
357 "%s: rdata is read only\n", __func__
);
360 uart_write_tx_fifo(s
, (uint8_t *) &value
, 1);
364 s
->uart_fifo_ctrl
= value
;
366 if (value
& R_FIFO_CTRL_RXRST_MASK
) {
367 qemu_log_mask(LOG_UNIMP
,
368 "%s: RX fifos are not supported\n", __func__
);
370 if (value
& R_FIFO_CTRL_TXRST_MASK
) {
375 qemu_log_mask(LOG_GUEST_ERROR
,
376 "%s: fifo_status is read only\n", __func__
);
380 s
->uart_ovrd
= value
;
381 qemu_log_mask(LOG_UNIMP
,
382 "%s: ovrd is not supported\n", __func__
);
385 qemu_log_mask(LOG_GUEST_ERROR
,
386 "%s: val is read only\n", __func__
);
389 s
->uart_timeout_ctrl
= value
;
390 qemu_log_mask(LOG_UNIMP
,
391 "%s: timeout_ctrl is not supported\n", __func__
);
394 qemu_log_mask(LOG_GUEST_ERROR
,
395 "%s: Bad offset 0x%"HWADDR_PRIx
"\n", __func__
, addr
);
399 static void ibex_uart_clk_update(void *opaque
)
401 IbexUartState
*s
= opaque
;
403 /* recompute uart's speed on clock change */
404 uint64_t baud
= ibex_uart_get_baud(s
);
406 s
->char_tx_time
= (NANOSECONDS_PER_SECOND
/ baud
) * 10;
409 static void fifo_trigger_update(void *opaque
)
411 IbexUartState
*s
= opaque
;
413 if (s
->uart_ctrl
& R_CTRL_TX_ENABLE_MASK
) {
414 ibex_uart_xmit(NULL
, G_IO_OUT
, s
);
418 static const MemoryRegionOps ibex_uart_ops
= {
419 .read
= ibex_uart_read
,
420 .write
= ibex_uart_write
,
421 .endianness
= DEVICE_NATIVE_ENDIAN
,
422 .impl
.min_access_size
= 4,
423 .impl
.max_access_size
= 4,
426 static int ibex_uart_post_load(void *opaque
, int version_id
)
428 IbexUartState
*s
= opaque
;
430 ibex_uart_update_irqs(s
);
434 static const VMStateDescription vmstate_ibex_uart
= {
435 .name
= TYPE_IBEX_UART
,
437 .minimum_version_id
= 1,
438 .post_load
= ibex_uart_post_load
,
439 .fields
= (VMStateField
[]) {
440 VMSTATE_UINT8_ARRAY(tx_fifo
, IbexUartState
,
441 IBEX_UART_TX_FIFO_SIZE
),
442 VMSTATE_UINT32(tx_level
, IbexUartState
),
443 VMSTATE_UINT64(char_tx_time
, IbexUartState
),
444 VMSTATE_TIMER_PTR(fifo_trigger_handle
, IbexUartState
),
445 VMSTATE_UINT32(uart_intr_state
, IbexUartState
),
446 VMSTATE_UINT32(uart_intr_enable
, IbexUartState
),
447 VMSTATE_UINT32(uart_ctrl
, IbexUartState
),
448 VMSTATE_UINT32(uart_status
, IbexUartState
),
449 VMSTATE_UINT32(uart_rdata
, IbexUartState
),
450 VMSTATE_UINT32(uart_fifo_ctrl
, IbexUartState
),
451 VMSTATE_UINT32(uart_fifo_status
, IbexUartState
),
452 VMSTATE_UINT32(uart_ovrd
, IbexUartState
),
453 VMSTATE_UINT32(uart_val
, IbexUartState
),
454 VMSTATE_UINT32(uart_timeout_ctrl
, IbexUartState
),
455 VMSTATE_END_OF_LIST()
459 static Property ibex_uart_properties
[] = {
460 DEFINE_PROP_CHR("chardev", IbexUartState
, chr
),
461 DEFINE_PROP_END_OF_LIST(),
464 static void ibex_uart_init(Object
*obj
)
466 IbexUartState
*s
= IBEX_UART(obj
);
468 s
->f_clk
= qdev_init_clock_in(DEVICE(obj
), "f_clock",
469 ibex_uart_clk_update
, s
);
470 clock_set_hz(s
->f_clk
, IBEX_UART_CLOCK
);
472 sysbus_init_irq(SYS_BUS_DEVICE(obj
), &s
->tx_watermark
);
473 sysbus_init_irq(SYS_BUS_DEVICE(obj
), &s
->rx_watermark
);
474 sysbus_init_irq(SYS_BUS_DEVICE(obj
), &s
->tx_empty
);
475 sysbus_init_irq(SYS_BUS_DEVICE(obj
), &s
->rx_overflow
);
477 memory_region_init_io(&s
->mmio
, obj
, &ibex_uart_ops
, s
,
478 TYPE_IBEX_UART
, 0x400);
479 sysbus_init_mmio(SYS_BUS_DEVICE(obj
), &s
->mmio
);
482 static void ibex_uart_realize(DeviceState
*dev
, Error
**errp
)
484 IbexUartState
*s
= IBEX_UART(dev
);
486 s
->fifo_trigger_handle
= timer_new_ns(QEMU_CLOCK_VIRTUAL
,
487 fifo_trigger_update
, s
);
489 qemu_chr_fe_set_handlers(&s
->chr
, ibex_uart_can_receive
,
490 ibex_uart_receive
, NULL
, NULL
,
494 static void ibex_uart_class_init(ObjectClass
*klass
, void *data
)
496 DeviceClass
*dc
= DEVICE_CLASS(klass
);
498 dc
->reset
= ibex_uart_reset
;
499 dc
->realize
= ibex_uart_realize
;
500 dc
->vmsd
= &vmstate_ibex_uart
;
501 device_class_set_props(dc
, ibex_uart_properties
);
504 static const TypeInfo ibex_uart_info
= {
505 .name
= TYPE_IBEX_UART
,
506 .parent
= TYPE_SYS_BUS_DEVICE
,
507 .instance_size
= sizeof(IbexUartState
),
508 .instance_init
= ibex_uart_init
,
509 .class_init
= ibex_uart_class_init
,
512 static void ibex_uart_register_types(void)
514 type_register_static(&ibex_uart_info
);
517 type_init(ibex_uart_register_types
)