2 * Tiny Code Interpreter for QEMU
4 * Copyright (c) 2009, 2011 Stefan Weil
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 /* Defining NDEBUG disables assertions (which makes the code faster). */
23 #if !defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG)
27 #include "qemu-common.h"
28 #include "exec/exec-all.h" /* MAX_OPC_PARAM_IARGS */
31 /* Marker for missing code. */
34 fprintf(stderr, "TODO %s:%u: %s()\n", \
35 __FILE__, __LINE__, __func__); \
39 #if MAX_OPC_PARAM_IARGS != 5
40 # error Fix needed, number of supported input arguments changed!
42 #if TCG_TARGET_REG_BITS == 32
43 typedef uint64_t (*helper_function
)(tcg_target_ulong
, tcg_target_ulong
,
44 tcg_target_ulong
, tcg_target_ulong
,
45 tcg_target_ulong
, tcg_target_ulong
,
46 tcg_target_ulong
, tcg_target_ulong
,
47 tcg_target_ulong
, tcg_target_ulong
);
49 typedef uint64_t (*helper_function
)(tcg_target_ulong
, tcg_target_ulong
,
50 tcg_target_ulong
, tcg_target_ulong
,
54 /* Targets which don't use GETPC also don't need tci_tb_ptr
55 which makes them a little faster. */
60 static tcg_target_ulong tci_reg
[TCG_TARGET_NB_REGS
];
62 static tcg_target_ulong
tci_read_reg(TCGReg index
)
64 assert(index
< ARRAY_SIZE(tci_reg
));
65 return tci_reg
[index
];
68 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
69 static int8_t tci_read_reg8s(TCGReg index
)
71 return (int8_t)tci_read_reg(index
);
75 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
76 static int16_t tci_read_reg16s(TCGReg index
)
78 return (int16_t)tci_read_reg(index
);
82 #if TCG_TARGET_REG_BITS == 64
83 static int32_t tci_read_reg32s(TCGReg index
)
85 return (int32_t)tci_read_reg(index
);
89 static uint8_t tci_read_reg8(TCGReg index
)
91 return (uint8_t)tci_read_reg(index
);
94 static uint16_t tci_read_reg16(TCGReg index
)
96 return (uint16_t)tci_read_reg(index
);
99 static uint32_t tci_read_reg32(TCGReg index
)
101 return (uint32_t)tci_read_reg(index
);
104 #if TCG_TARGET_REG_BITS == 64
105 static uint64_t tci_read_reg64(TCGReg index
)
107 return tci_read_reg(index
);
111 static void tci_write_reg(TCGReg index
, tcg_target_ulong value
)
113 assert(index
< ARRAY_SIZE(tci_reg
));
114 assert(index
!= TCG_AREG0
);
115 tci_reg
[index
] = value
;
118 static void tci_write_reg8s(TCGReg index
, int8_t value
)
120 tci_write_reg(index
, value
);
123 static void tci_write_reg16s(TCGReg index
, int16_t value
)
125 tci_write_reg(index
, value
);
128 #if TCG_TARGET_REG_BITS == 64
129 static void tci_write_reg32s(TCGReg index
, int32_t value
)
131 tci_write_reg(index
, value
);
135 static void tci_write_reg8(TCGReg index
, uint8_t value
)
137 tci_write_reg(index
, value
);
140 static void tci_write_reg16(TCGReg index
, uint16_t value
)
142 tci_write_reg(index
, value
);
145 static void tci_write_reg32(TCGReg index
, uint32_t value
)
147 tci_write_reg(index
, value
);
150 #if TCG_TARGET_REG_BITS == 32
151 static void tci_write_reg64(uint32_t high_index
, uint32_t low_index
,
154 tci_write_reg(low_index
, value
);
155 tci_write_reg(high_index
, value
>> 32);
157 #elif TCG_TARGET_REG_BITS == 64
158 static void tci_write_reg64(TCGReg index
, uint64_t value
)
160 tci_write_reg(index
, value
);
164 #if TCG_TARGET_REG_BITS == 32
165 /* Create a 64 bit value from two 32 bit values. */
166 static uint64_t tci_uint64(uint32_t high
, uint32_t low
)
168 return ((uint64_t)high
<< 32) + low
;
172 /* Read constant (native size) from bytecode. */
173 static tcg_target_ulong
tci_read_i(uint8_t **tb_ptr
)
175 tcg_target_ulong value
= *(tcg_target_ulong
*)(*tb_ptr
);
176 *tb_ptr
+= sizeof(value
);
180 /* Read unsigned constant (32 bit) from bytecode. */
181 static uint32_t tci_read_i32(uint8_t **tb_ptr
)
183 uint32_t value
= *(uint32_t *)(*tb_ptr
);
184 *tb_ptr
+= sizeof(value
);
188 /* Read signed constant (32 bit) from bytecode. */
189 static int32_t tci_read_s32(uint8_t **tb_ptr
)
191 int32_t value
= *(int32_t *)(*tb_ptr
);
192 *tb_ptr
+= sizeof(value
);
196 #if TCG_TARGET_REG_BITS == 64
197 /* Read constant (64 bit) from bytecode. */
198 static uint64_t tci_read_i64(uint8_t **tb_ptr
)
200 uint64_t value
= *(uint64_t *)(*tb_ptr
);
201 *tb_ptr
+= sizeof(value
);
206 /* Read indexed register (native size) from bytecode. */
207 static tcg_target_ulong
tci_read_r(uint8_t **tb_ptr
)
209 tcg_target_ulong value
= tci_read_reg(**tb_ptr
);
214 /* Read indexed register (8 bit) from bytecode. */
215 static uint8_t tci_read_r8(uint8_t **tb_ptr
)
217 uint8_t value
= tci_read_reg8(**tb_ptr
);
222 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
223 /* Read indexed register (8 bit signed) from bytecode. */
224 static int8_t tci_read_r8s(uint8_t **tb_ptr
)
226 int8_t value
= tci_read_reg8s(**tb_ptr
);
232 /* Read indexed register (16 bit) from bytecode. */
233 static uint16_t tci_read_r16(uint8_t **tb_ptr
)
235 uint16_t value
= tci_read_reg16(**tb_ptr
);
240 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
241 /* Read indexed register (16 bit signed) from bytecode. */
242 static int16_t tci_read_r16s(uint8_t **tb_ptr
)
244 int16_t value
= tci_read_reg16s(**tb_ptr
);
250 /* Read indexed register (32 bit) from bytecode. */
251 static uint32_t tci_read_r32(uint8_t **tb_ptr
)
253 uint32_t value
= tci_read_reg32(**tb_ptr
);
258 #if TCG_TARGET_REG_BITS == 32
259 /* Read two indexed registers (2 * 32 bit) from bytecode. */
260 static uint64_t tci_read_r64(uint8_t **tb_ptr
)
262 uint32_t low
= tci_read_r32(tb_ptr
);
263 return tci_uint64(tci_read_r32(tb_ptr
), low
);
265 #elif TCG_TARGET_REG_BITS == 64
266 /* Read indexed register (32 bit signed) from bytecode. */
267 static int32_t tci_read_r32s(uint8_t **tb_ptr
)
269 int32_t value
= tci_read_reg32s(**tb_ptr
);
274 /* Read indexed register (64 bit) from bytecode. */
275 static uint64_t tci_read_r64(uint8_t **tb_ptr
)
277 uint64_t value
= tci_read_reg64(**tb_ptr
);
283 /* Read indexed register(s) with target address from bytecode. */
284 static target_ulong
tci_read_ulong(uint8_t **tb_ptr
)
286 target_ulong taddr
= tci_read_r(tb_ptr
);
287 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
288 taddr
+= (uint64_t)tci_read_r(tb_ptr
) << 32;
293 /* Read indexed register or constant (native size) from bytecode. */
294 static tcg_target_ulong
tci_read_ri(uint8_t **tb_ptr
)
296 tcg_target_ulong value
;
299 if (r
== TCG_CONST
) {
300 value
= tci_read_i(tb_ptr
);
302 value
= tci_read_reg(r
);
307 /* Read indexed register or constant (32 bit) from bytecode. */
308 static uint32_t tci_read_ri32(uint8_t **tb_ptr
)
313 if (r
== TCG_CONST
) {
314 value
= tci_read_i32(tb_ptr
);
316 value
= tci_read_reg32(r
);
321 #if TCG_TARGET_REG_BITS == 32
322 /* Read two indexed registers or constants (2 * 32 bit) from bytecode. */
323 static uint64_t tci_read_ri64(uint8_t **tb_ptr
)
325 uint32_t low
= tci_read_ri32(tb_ptr
);
326 return tci_uint64(tci_read_ri32(tb_ptr
), low
);
328 #elif TCG_TARGET_REG_BITS == 64
329 /* Read indexed register or constant (64 bit) from bytecode. */
330 static uint64_t tci_read_ri64(uint8_t **tb_ptr
)
335 if (r
== TCG_CONST
) {
336 value
= tci_read_i64(tb_ptr
);
338 value
= tci_read_reg64(r
);
344 static tcg_target_ulong
tci_read_label(uint8_t **tb_ptr
)
346 tcg_target_ulong label
= tci_read_i(tb_ptr
);
351 static bool tci_compare32(uint32_t u0
, uint32_t u1
, TCGCond condition
)
393 static bool tci_compare64(uint64_t u0
, uint64_t u1
, TCGCond condition
)
435 /* Interpret pseudo code in tb. */
436 tcg_target_ulong
tcg_qemu_tb_exec(CPUArchState
*env
, uint8_t *tb_ptr
)
438 tcg_target_ulong next_tb
= 0;
440 tci_reg
[TCG_AREG0
] = (tcg_target_ulong
)env
;
445 tci_tb_ptr
= (uintptr_t)tb_ptr
;
447 TCGOpcode opc
= tb_ptr
[0];
449 uint8_t op_size
= tb_ptr
[1];
450 uint8_t *old_code_ptr
= tb_ptr
;
455 tcg_target_ulong label
;
458 #ifndef CONFIG_SOFTMMU
459 tcg_target_ulong host_addr
;
465 #if TCG_TARGET_REG_BITS == 32
469 /* Skip opcode and size entry. */
480 case INDEX_op_discard
:
483 case INDEX_op_set_label
:
487 t0
= tci_read_ri(&tb_ptr
);
488 #if TCG_TARGET_REG_BITS == 32
489 tmp64
= ((helper_function
)t0
)(tci_read_reg(TCG_REG_R0
),
490 tci_read_reg(TCG_REG_R1
),
491 tci_read_reg(TCG_REG_R2
),
492 tci_read_reg(TCG_REG_R3
),
493 tci_read_reg(TCG_REG_R5
),
494 tci_read_reg(TCG_REG_R6
),
495 tci_read_reg(TCG_REG_R7
),
496 tci_read_reg(TCG_REG_R8
),
497 tci_read_reg(TCG_REG_R9
),
498 tci_read_reg(TCG_REG_R10
));
499 tci_write_reg(TCG_REG_R0
, tmp64
);
500 tci_write_reg(TCG_REG_R1
, tmp64
>> 32);
502 tmp64
= ((helper_function
)t0
)(tci_read_reg(TCG_REG_R0
),
503 tci_read_reg(TCG_REG_R1
),
504 tci_read_reg(TCG_REG_R2
),
505 tci_read_reg(TCG_REG_R3
),
506 tci_read_reg(TCG_REG_R5
));
507 tci_write_reg(TCG_REG_R0
, tmp64
);
511 label
= tci_read_label(&tb_ptr
);
512 assert(tb_ptr
== old_code_ptr
+ op_size
);
513 tb_ptr
= (uint8_t *)label
;
515 case INDEX_op_setcond_i32
:
517 t1
= tci_read_r32(&tb_ptr
);
518 t2
= tci_read_ri32(&tb_ptr
);
519 condition
= *tb_ptr
++;
520 tci_write_reg32(t0
, tci_compare32(t1
, t2
, condition
));
522 #if TCG_TARGET_REG_BITS == 32
523 case INDEX_op_setcond2_i32
:
525 tmp64
= tci_read_r64(&tb_ptr
);
526 v64
= tci_read_ri64(&tb_ptr
);
527 condition
= *tb_ptr
++;
528 tci_write_reg32(t0
, tci_compare64(tmp64
, v64
, condition
));
530 #elif TCG_TARGET_REG_BITS == 64
531 case INDEX_op_setcond_i64
:
533 t1
= tci_read_r64(&tb_ptr
);
534 t2
= tci_read_ri64(&tb_ptr
);
535 condition
= *tb_ptr
++;
536 tci_write_reg64(t0
, tci_compare64(t1
, t2
, condition
));
539 case INDEX_op_mov_i32
:
541 t1
= tci_read_r32(&tb_ptr
);
542 tci_write_reg32(t0
, t1
);
544 case INDEX_op_movi_i32
:
546 t1
= tci_read_i32(&tb_ptr
);
547 tci_write_reg32(t0
, t1
);
550 /* Load/store operations (32 bit). */
552 case INDEX_op_ld8u_i32
:
554 t1
= tci_read_r(&tb_ptr
);
555 t2
= tci_read_s32(&tb_ptr
);
556 tci_write_reg8(t0
, *(uint8_t *)(t1
+ t2
));
558 case INDEX_op_ld8s_i32
:
559 case INDEX_op_ld16u_i32
:
562 case INDEX_op_ld16s_i32
:
565 case INDEX_op_ld_i32
:
567 t1
= tci_read_r(&tb_ptr
);
568 t2
= tci_read_s32(&tb_ptr
);
569 tci_write_reg32(t0
, *(uint32_t *)(t1
+ t2
));
571 case INDEX_op_st8_i32
:
572 t0
= tci_read_r8(&tb_ptr
);
573 t1
= tci_read_r(&tb_ptr
);
574 t2
= tci_read_s32(&tb_ptr
);
575 *(uint8_t *)(t1
+ t2
) = t0
;
577 case INDEX_op_st16_i32
:
578 t0
= tci_read_r16(&tb_ptr
);
579 t1
= tci_read_r(&tb_ptr
);
580 t2
= tci_read_s32(&tb_ptr
);
581 *(uint16_t *)(t1
+ t2
) = t0
;
583 case INDEX_op_st_i32
:
584 t0
= tci_read_r32(&tb_ptr
);
585 t1
= tci_read_r(&tb_ptr
);
586 t2
= tci_read_s32(&tb_ptr
);
587 *(uint32_t *)(t1
+ t2
) = t0
;
590 /* Arithmetic operations (32 bit). */
592 case INDEX_op_add_i32
:
594 t1
= tci_read_ri32(&tb_ptr
);
595 t2
= tci_read_ri32(&tb_ptr
);
596 tci_write_reg32(t0
, t1
+ t2
);
598 case INDEX_op_sub_i32
:
600 t1
= tci_read_ri32(&tb_ptr
);
601 t2
= tci_read_ri32(&tb_ptr
);
602 tci_write_reg32(t0
, t1
- t2
);
604 case INDEX_op_mul_i32
:
606 t1
= tci_read_ri32(&tb_ptr
);
607 t2
= tci_read_ri32(&tb_ptr
);
608 tci_write_reg32(t0
, t1
* t2
);
610 #if TCG_TARGET_HAS_div_i32
611 case INDEX_op_div_i32
:
613 t1
= tci_read_ri32(&tb_ptr
);
614 t2
= tci_read_ri32(&tb_ptr
);
615 tci_write_reg32(t0
, (int32_t)t1
/ (int32_t)t2
);
617 case INDEX_op_divu_i32
:
619 t1
= tci_read_ri32(&tb_ptr
);
620 t2
= tci_read_ri32(&tb_ptr
);
621 tci_write_reg32(t0
, t1
/ t2
);
623 case INDEX_op_rem_i32
:
625 t1
= tci_read_ri32(&tb_ptr
);
626 t2
= tci_read_ri32(&tb_ptr
);
627 tci_write_reg32(t0
, (int32_t)t1
% (int32_t)t2
);
629 case INDEX_op_remu_i32
:
631 t1
= tci_read_ri32(&tb_ptr
);
632 t2
= tci_read_ri32(&tb_ptr
);
633 tci_write_reg32(t0
, t1
% t2
);
635 #elif TCG_TARGET_HAS_div2_i32
636 case INDEX_op_div2_i32
:
637 case INDEX_op_divu2_i32
:
641 case INDEX_op_and_i32
:
643 t1
= tci_read_ri32(&tb_ptr
);
644 t2
= tci_read_ri32(&tb_ptr
);
645 tci_write_reg32(t0
, t1
& t2
);
647 case INDEX_op_or_i32
:
649 t1
= tci_read_ri32(&tb_ptr
);
650 t2
= tci_read_ri32(&tb_ptr
);
651 tci_write_reg32(t0
, t1
| t2
);
653 case INDEX_op_xor_i32
:
655 t1
= tci_read_ri32(&tb_ptr
);
656 t2
= tci_read_ri32(&tb_ptr
);
657 tci_write_reg32(t0
, t1
^ t2
);
660 /* Shift/rotate operations (32 bit). */
662 case INDEX_op_shl_i32
:
664 t1
= tci_read_ri32(&tb_ptr
);
665 t2
= tci_read_ri32(&tb_ptr
);
666 tci_write_reg32(t0
, t1
<< t2
);
668 case INDEX_op_shr_i32
:
670 t1
= tci_read_ri32(&tb_ptr
);
671 t2
= tci_read_ri32(&tb_ptr
);
672 tci_write_reg32(t0
, t1
>> t2
);
674 case INDEX_op_sar_i32
:
676 t1
= tci_read_ri32(&tb_ptr
);
677 t2
= tci_read_ri32(&tb_ptr
);
678 tci_write_reg32(t0
, ((int32_t)t1
>> t2
));
680 #if TCG_TARGET_HAS_rot_i32
681 case INDEX_op_rotl_i32
:
683 t1
= tci_read_ri32(&tb_ptr
);
684 t2
= tci_read_ri32(&tb_ptr
);
685 tci_write_reg32(t0
, (t1
<< t2
) | (t1
>> (32 - t2
)));
687 case INDEX_op_rotr_i32
:
689 t1
= tci_read_ri32(&tb_ptr
);
690 t2
= tci_read_ri32(&tb_ptr
);
691 tci_write_reg32(t0
, (t1
>> t2
) | (t1
<< (32 - t2
)));
694 #if TCG_TARGET_HAS_deposit_i32
695 case INDEX_op_deposit_i32
:
697 t1
= tci_read_r32(&tb_ptr
);
698 t2
= tci_read_r32(&tb_ptr
);
701 tmp32
= (((1 << tmp8
) - 1) << tmp16
);
702 tci_write_reg32(t0
, (t1
& ~tmp32
) | ((t2
<< tmp16
) & tmp32
));
705 case INDEX_op_brcond_i32
:
706 t0
= tci_read_r32(&tb_ptr
);
707 t1
= tci_read_ri32(&tb_ptr
);
708 condition
= *tb_ptr
++;
709 label
= tci_read_label(&tb_ptr
);
710 if (tci_compare32(t0
, t1
, condition
)) {
711 assert(tb_ptr
== old_code_ptr
+ op_size
);
712 tb_ptr
= (uint8_t *)label
;
716 #if TCG_TARGET_REG_BITS == 32
717 case INDEX_op_add2_i32
:
720 tmp64
= tci_read_r64(&tb_ptr
);
721 tmp64
+= tci_read_r64(&tb_ptr
);
722 tci_write_reg64(t1
, t0
, tmp64
);
724 case INDEX_op_sub2_i32
:
727 tmp64
= tci_read_r64(&tb_ptr
);
728 tmp64
-= tci_read_r64(&tb_ptr
);
729 tci_write_reg64(t1
, t0
, tmp64
);
731 case INDEX_op_brcond2_i32
:
732 tmp64
= tci_read_r64(&tb_ptr
);
733 v64
= tci_read_ri64(&tb_ptr
);
734 condition
= *tb_ptr
++;
735 label
= tci_read_label(&tb_ptr
);
736 if (tci_compare64(tmp64
, v64
, condition
)) {
737 assert(tb_ptr
== old_code_ptr
+ op_size
);
738 tb_ptr
= (uint8_t *)label
;
742 case INDEX_op_mulu2_i32
:
745 t2
= tci_read_r32(&tb_ptr
);
746 tmp64
= tci_read_r32(&tb_ptr
);
747 tci_write_reg64(t1
, t0
, t2
* tmp64
);
749 #endif /* TCG_TARGET_REG_BITS == 32 */
750 #if TCG_TARGET_HAS_ext8s_i32
751 case INDEX_op_ext8s_i32
:
753 t1
= tci_read_r8s(&tb_ptr
);
754 tci_write_reg32(t0
, t1
);
757 #if TCG_TARGET_HAS_ext16s_i32
758 case INDEX_op_ext16s_i32
:
760 t1
= tci_read_r16s(&tb_ptr
);
761 tci_write_reg32(t0
, t1
);
764 #if TCG_TARGET_HAS_ext8u_i32
765 case INDEX_op_ext8u_i32
:
767 t1
= tci_read_r8(&tb_ptr
);
768 tci_write_reg32(t0
, t1
);
771 #if TCG_TARGET_HAS_ext16u_i32
772 case INDEX_op_ext16u_i32
:
774 t1
= tci_read_r16(&tb_ptr
);
775 tci_write_reg32(t0
, t1
);
778 #if TCG_TARGET_HAS_bswap16_i32
779 case INDEX_op_bswap16_i32
:
781 t1
= tci_read_r16(&tb_ptr
);
782 tci_write_reg32(t0
, bswap16(t1
));
785 #if TCG_TARGET_HAS_bswap32_i32
786 case INDEX_op_bswap32_i32
:
788 t1
= tci_read_r32(&tb_ptr
);
789 tci_write_reg32(t0
, bswap32(t1
));
792 #if TCG_TARGET_HAS_not_i32
793 case INDEX_op_not_i32
:
795 t1
= tci_read_r32(&tb_ptr
);
796 tci_write_reg32(t0
, ~t1
);
799 #if TCG_TARGET_HAS_neg_i32
800 case INDEX_op_neg_i32
:
802 t1
= tci_read_r32(&tb_ptr
);
803 tci_write_reg32(t0
, -t1
);
806 #if TCG_TARGET_REG_BITS == 64
807 case INDEX_op_mov_i64
:
809 t1
= tci_read_r64(&tb_ptr
);
810 tci_write_reg64(t0
, t1
);
812 case INDEX_op_movi_i64
:
814 t1
= tci_read_i64(&tb_ptr
);
815 tci_write_reg64(t0
, t1
);
818 /* Load/store operations (64 bit). */
820 case INDEX_op_ld8u_i64
:
822 t1
= tci_read_r(&tb_ptr
);
823 t2
= tci_read_s32(&tb_ptr
);
824 tci_write_reg8(t0
, *(uint8_t *)(t1
+ t2
));
826 case INDEX_op_ld8s_i64
:
827 case INDEX_op_ld16u_i64
:
828 case INDEX_op_ld16s_i64
:
831 case INDEX_op_ld32u_i64
:
833 t1
= tci_read_r(&tb_ptr
);
834 t2
= tci_read_s32(&tb_ptr
);
835 tci_write_reg32(t0
, *(uint32_t *)(t1
+ t2
));
837 case INDEX_op_ld32s_i64
:
839 t1
= tci_read_r(&tb_ptr
);
840 t2
= tci_read_s32(&tb_ptr
);
841 tci_write_reg32s(t0
, *(int32_t *)(t1
+ t2
));
843 case INDEX_op_ld_i64
:
845 t1
= tci_read_r(&tb_ptr
);
846 t2
= tci_read_s32(&tb_ptr
);
847 tci_write_reg64(t0
, *(uint64_t *)(t1
+ t2
));
849 case INDEX_op_st8_i64
:
850 t0
= tci_read_r8(&tb_ptr
);
851 t1
= tci_read_r(&tb_ptr
);
852 t2
= tci_read_s32(&tb_ptr
);
853 *(uint8_t *)(t1
+ t2
) = t0
;
855 case INDEX_op_st16_i64
:
856 t0
= tci_read_r16(&tb_ptr
);
857 t1
= tci_read_r(&tb_ptr
);
858 t2
= tci_read_s32(&tb_ptr
);
859 *(uint16_t *)(t1
+ t2
) = t0
;
861 case INDEX_op_st32_i64
:
862 t0
= tci_read_r32(&tb_ptr
);
863 t1
= tci_read_r(&tb_ptr
);
864 t2
= tci_read_s32(&tb_ptr
);
865 *(uint32_t *)(t1
+ t2
) = t0
;
867 case INDEX_op_st_i64
:
868 t0
= tci_read_r64(&tb_ptr
);
869 t1
= tci_read_r(&tb_ptr
);
870 t2
= tci_read_s32(&tb_ptr
);
871 *(uint64_t *)(t1
+ t2
) = t0
;
874 /* Arithmetic operations (64 bit). */
876 case INDEX_op_add_i64
:
878 t1
= tci_read_ri64(&tb_ptr
);
879 t2
= tci_read_ri64(&tb_ptr
);
880 tci_write_reg64(t0
, t1
+ t2
);
882 case INDEX_op_sub_i64
:
884 t1
= tci_read_ri64(&tb_ptr
);
885 t2
= tci_read_ri64(&tb_ptr
);
886 tci_write_reg64(t0
, t1
- t2
);
888 case INDEX_op_mul_i64
:
890 t1
= tci_read_ri64(&tb_ptr
);
891 t2
= tci_read_ri64(&tb_ptr
);
892 tci_write_reg64(t0
, t1
* t2
);
894 #if TCG_TARGET_HAS_div_i64
895 case INDEX_op_div_i64
:
896 case INDEX_op_divu_i64
:
897 case INDEX_op_rem_i64
:
898 case INDEX_op_remu_i64
:
901 #elif TCG_TARGET_HAS_div2_i64
902 case INDEX_op_div2_i64
:
903 case INDEX_op_divu2_i64
:
907 case INDEX_op_and_i64
:
909 t1
= tci_read_ri64(&tb_ptr
);
910 t2
= tci_read_ri64(&tb_ptr
);
911 tci_write_reg64(t0
, t1
& t2
);
913 case INDEX_op_or_i64
:
915 t1
= tci_read_ri64(&tb_ptr
);
916 t2
= tci_read_ri64(&tb_ptr
);
917 tci_write_reg64(t0
, t1
| t2
);
919 case INDEX_op_xor_i64
:
921 t1
= tci_read_ri64(&tb_ptr
);
922 t2
= tci_read_ri64(&tb_ptr
);
923 tci_write_reg64(t0
, t1
^ t2
);
926 /* Shift/rotate operations (64 bit). */
928 case INDEX_op_shl_i64
:
930 t1
= tci_read_ri64(&tb_ptr
);
931 t2
= tci_read_ri64(&tb_ptr
);
932 tci_write_reg64(t0
, t1
<< t2
);
934 case INDEX_op_shr_i64
:
936 t1
= tci_read_ri64(&tb_ptr
);
937 t2
= tci_read_ri64(&tb_ptr
);
938 tci_write_reg64(t0
, t1
>> t2
);
940 case INDEX_op_sar_i64
:
942 t1
= tci_read_ri64(&tb_ptr
);
943 t2
= tci_read_ri64(&tb_ptr
);
944 tci_write_reg64(t0
, ((int64_t)t1
>> t2
));
946 #if TCG_TARGET_HAS_rot_i64
947 case INDEX_op_rotl_i64
:
948 case INDEX_op_rotr_i64
:
952 #if TCG_TARGET_HAS_deposit_i64
953 case INDEX_op_deposit_i64
:
955 t1
= tci_read_r64(&tb_ptr
);
956 t2
= tci_read_r64(&tb_ptr
);
959 tmp64
= (((1ULL << tmp8
) - 1) << tmp16
);
960 tci_write_reg64(t0
, (t1
& ~tmp64
) | ((t2
<< tmp16
) & tmp64
));
963 case INDEX_op_brcond_i64
:
964 t0
= tci_read_r64(&tb_ptr
);
965 t1
= tci_read_ri64(&tb_ptr
);
966 condition
= *tb_ptr
++;
967 label
= tci_read_label(&tb_ptr
);
968 if (tci_compare64(t0
, t1
, condition
)) {
969 assert(tb_ptr
== old_code_ptr
+ op_size
);
970 tb_ptr
= (uint8_t *)label
;
974 #if TCG_TARGET_HAS_ext8u_i64
975 case INDEX_op_ext8u_i64
:
977 t1
= tci_read_r8(&tb_ptr
);
978 tci_write_reg64(t0
, t1
);
981 #if TCG_TARGET_HAS_ext8s_i64
982 case INDEX_op_ext8s_i64
:
984 t1
= tci_read_r8s(&tb_ptr
);
985 tci_write_reg64(t0
, t1
);
988 #if TCG_TARGET_HAS_ext16s_i64
989 case INDEX_op_ext16s_i64
:
991 t1
= tci_read_r16s(&tb_ptr
);
992 tci_write_reg64(t0
, t1
);
995 #if TCG_TARGET_HAS_ext16u_i64
996 case INDEX_op_ext16u_i64
:
998 t1
= tci_read_r16(&tb_ptr
);
999 tci_write_reg64(t0
, t1
);
1002 #if TCG_TARGET_HAS_ext32s_i64
1003 case INDEX_op_ext32s_i64
:
1005 t1
= tci_read_r32s(&tb_ptr
);
1006 tci_write_reg64(t0
, t1
);
1009 #if TCG_TARGET_HAS_ext32u_i64
1010 case INDEX_op_ext32u_i64
:
1012 t1
= tci_read_r32(&tb_ptr
);
1013 tci_write_reg64(t0
, t1
);
1016 #if TCG_TARGET_HAS_bswap16_i64
1017 case INDEX_op_bswap16_i64
:
1020 t1
= tci_read_r16(&tb_ptr
);
1021 tci_write_reg64(t0
, bswap16(t1
));
1024 #if TCG_TARGET_HAS_bswap32_i64
1025 case INDEX_op_bswap32_i64
:
1027 t1
= tci_read_r32(&tb_ptr
);
1028 tci_write_reg64(t0
, bswap32(t1
));
1031 #if TCG_TARGET_HAS_bswap64_i64
1032 case INDEX_op_bswap64_i64
:
1034 t1
= tci_read_r64(&tb_ptr
);
1035 tci_write_reg64(t0
, bswap64(t1
));
1038 #if TCG_TARGET_HAS_not_i64
1039 case INDEX_op_not_i64
:
1041 t1
= tci_read_r64(&tb_ptr
);
1042 tci_write_reg64(t0
, ~t1
);
1045 #if TCG_TARGET_HAS_neg_i64
1046 case INDEX_op_neg_i64
:
1048 t1
= tci_read_r64(&tb_ptr
);
1049 tci_write_reg64(t0
, -t1
);
1052 #endif /* TCG_TARGET_REG_BITS == 64 */
1054 /* QEMU specific operations. */
1056 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
1057 case INDEX_op_debug_insn_start
:
1061 case INDEX_op_debug_insn_start
:
1065 case INDEX_op_exit_tb
:
1066 next_tb
= *(uint64_t *)tb_ptr
;
1069 case INDEX_op_goto_tb
:
1070 t0
= tci_read_i32(&tb_ptr
);
1071 assert(tb_ptr
== old_code_ptr
+ op_size
);
1072 tb_ptr
+= (int32_t)t0
;
1074 case INDEX_op_qemu_ld8u
:
1076 taddr
= tci_read_ulong(&tb_ptr
);
1077 #ifdef CONFIG_SOFTMMU
1078 tmp8
= helper_ldb_mmu(env
, taddr
, tci_read_i(&tb_ptr
));
1080 host_addr
= (tcg_target_ulong
)taddr
;
1081 assert(taddr
== host_addr
);
1082 tmp8
= *(uint8_t *)(host_addr
+ GUEST_BASE
);
1084 tci_write_reg8(t0
, tmp8
);
1086 case INDEX_op_qemu_ld8s
:
1088 taddr
= tci_read_ulong(&tb_ptr
);
1089 #ifdef CONFIG_SOFTMMU
1090 tmp8
= helper_ldb_mmu(env
, taddr
, tci_read_i(&tb_ptr
));
1092 host_addr
= (tcg_target_ulong
)taddr
;
1093 assert(taddr
== host_addr
);
1094 tmp8
= *(uint8_t *)(host_addr
+ GUEST_BASE
);
1096 tci_write_reg8s(t0
, tmp8
);
1098 case INDEX_op_qemu_ld16u
:
1100 taddr
= tci_read_ulong(&tb_ptr
);
1101 #ifdef CONFIG_SOFTMMU
1102 tmp16
= helper_ldw_mmu(env
, taddr
, tci_read_i(&tb_ptr
));
1104 host_addr
= (tcg_target_ulong
)taddr
;
1105 assert(taddr
== host_addr
);
1106 tmp16
= tswap16(*(uint16_t *)(host_addr
+ GUEST_BASE
));
1108 tci_write_reg16(t0
, tmp16
);
1110 case INDEX_op_qemu_ld16s
:
1112 taddr
= tci_read_ulong(&tb_ptr
);
1113 #ifdef CONFIG_SOFTMMU
1114 tmp16
= helper_ldw_mmu(env
, taddr
, tci_read_i(&tb_ptr
));
1116 host_addr
= (tcg_target_ulong
)taddr
;
1117 assert(taddr
== host_addr
);
1118 tmp16
= tswap16(*(uint16_t *)(host_addr
+ GUEST_BASE
));
1120 tci_write_reg16s(t0
, tmp16
);
1122 #if TCG_TARGET_REG_BITS == 64
1123 case INDEX_op_qemu_ld32u
:
1125 taddr
= tci_read_ulong(&tb_ptr
);
1126 #ifdef CONFIG_SOFTMMU
1127 tmp32
= helper_ldl_mmu(env
, taddr
, tci_read_i(&tb_ptr
));
1129 host_addr
= (tcg_target_ulong
)taddr
;
1130 assert(taddr
== host_addr
);
1131 tmp32
= tswap32(*(uint32_t *)(host_addr
+ GUEST_BASE
));
1133 tci_write_reg32(t0
, tmp32
);
1135 case INDEX_op_qemu_ld32s
:
1137 taddr
= tci_read_ulong(&tb_ptr
);
1138 #ifdef CONFIG_SOFTMMU
1139 tmp32
= helper_ldl_mmu(env
, taddr
, tci_read_i(&tb_ptr
));
1141 host_addr
= (tcg_target_ulong
)taddr
;
1142 assert(taddr
== host_addr
);
1143 tmp32
= tswap32(*(uint32_t *)(host_addr
+ GUEST_BASE
));
1145 tci_write_reg32s(t0
, tmp32
);
1147 #endif /* TCG_TARGET_REG_BITS == 64 */
1148 case INDEX_op_qemu_ld32
:
1150 taddr
= tci_read_ulong(&tb_ptr
);
1151 #ifdef CONFIG_SOFTMMU
1152 tmp32
= helper_ldl_mmu(env
, taddr
, tci_read_i(&tb_ptr
));
1154 host_addr
= (tcg_target_ulong
)taddr
;
1155 assert(taddr
== host_addr
);
1156 tmp32
= tswap32(*(uint32_t *)(host_addr
+ GUEST_BASE
));
1158 tci_write_reg32(t0
, tmp32
);
1160 case INDEX_op_qemu_ld64
:
1162 #if TCG_TARGET_REG_BITS == 32
1165 taddr
= tci_read_ulong(&tb_ptr
);
1166 #ifdef CONFIG_SOFTMMU
1167 tmp64
= helper_ldq_mmu(env
, taddr
, tci_read_i(&tb_ptr
));
1169 host_addr
= (tcg_target_ulong
)taddr
;
1170 assert(taddr
== host_addr
);
1171 tmp64
= tswap64(*(uint64_t *)(host_addr
+ GUEST_BASE
));
1173 tci_write_reg(t0
, tmp64
);
1174 #if TCG_TARGET_REG_BITS == 32
1175 tci_write_reg(t1
, tmp64
>> 32);
1178 case INDEX_op_qemu_st8
:
1179 t0
= tci_read_r8(&tb_ptr
);
1180 taddr
= tci_read_ulong(&tb_ptr
);
1181 #ifdef CONFIG_SOFTMMU
1182 t2
= tci_read_i(&tb_ptr
);
1183 helper_stb_mmu(env
, taddr
, t0
, t2
);
1185 host_addr
= (tcg_target_ulong
)taddr
;
1186 assert(taddr
== host_addr
);
1187 *(uint8_t *)(host_addr
+ GUEST_BASE
) = t0
;
1190 case INDEX_op_qemu_st16
:
1191 t0
= tci_read_r16(&tb_ptr
);
1192 taddr
= tci_read_ulong(&tb_ptr
);
1193 #ifdef CONFIG_SOFTMMU
1194 t2
= tci_read_i(&tb_ptr
);
1195 helper_stw_mmu(env
, taddr
, t0
, t2
);
1197 host_addr
= (tcg_target_ulong
)taddr
;
1198 assert(taddr
== host_addr
);
1199 *(uint16_t *)(host_addr
+ GUEST_BASE
) = tswap16(t0
);
1202 case INDEX_op_qemu_st32
:
1203 t0
= tci_read_r32(&tb_ptr
);
1204 taddr
= tci_read_ulong(&tb_ptr
);
1205 #ifdef CONFIG_SOFTMMU
1206 t2
= tci_read_i(&tb_ptr
);
1207 helper_stl_mmu(env
, taddr
, t0
, t2
);
1209 host_addr
= (tcg_target_ulong
)taddr
;
1210 assert(taddr
== host_addr
);
1211 *(uint32_t *)(host_addr
+ GUEST_BASE
) = tswap32(t0
);
1214 case INDEX_op_qemu_st64
:
1215 tmp64
= tci_read_r64(&tb_ptr
);
1216 taddr
= tci_read_ulong(&tb_ptr
);
1217 #ifdef CONFIG_SOFTMMU
1218 t2
= tci_read_i(&tb_ptr
);
1219 helper_stq_mmu(env
, taddr
, tmp64
, t2
);
1221 host_addr
= (tcg_target_ulong
)taddr
;
1222 assert(taddr
== host_addr
);
1223 *(uint64_t *)(host_addr
+ GUEST_BASE
) = tswap64(tmp64
);
1230 assert(tb_ptr
== old_code_ptr
+ op_size
);