tcg/tcg.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #ifndef TCG_H
  26 #define TCG_H
  27
  28 #include "qemu-common.h"
  29 #include "cpu.h"
  30 #include "exec/tb-context.h"
  31 #include "qemu/bitops.h"
  32 #include "qemu/queue.h"
  33 #include "tcg-mo.h"
  34 #include "tcg-target.h"
  35 #include "qemu/int128.h"
  36
  37 /* XXX: make safe guess about sizes */
  38 #define MAX_OP_PER_INSTR 266
  39
  40 #if HOST_LONG_BITS == 32
  41 #define MAX_OPC_PARAM_PER_ARG 2
  42 #else
  43 #define MAX_OPC_PARAM_PER_ARG 1
  44 #endif
  45 #define MAX_OPC_PARAM_IARGS 6
  46 #define MAX_OPC_PARAM_OARGS 1
  47 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
  48
  49 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
  50  * and up to 4 + N parameters on 64-bit archs
  51  * (N = number of input arguments + output arguments).  */
  52 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
  53
  54 #define CPU_TEMP_BUF_NLONGS 128
  55
  56 /* Default target word size to pointer size.  */
  57 #ifndef TCG_TARGET_REG_BITS
  58 # if UINTPTR_MAX == UINT32_MAX
  59 #  define TCG_TARGET_REG_BITS 32
  60 # elif UINTPTR_MAX == UINT64_MAX
  61 #  define TCG_TARGET_REG_BITS 64
  62 # else
  63 #  error Unknown pointer size for tcg target
  64 # endif
  65 #endif
  66
  67 #if TCG_TARGET_REG_BITS == 32
  68 typedef int32_t tcg_target_long;
  69 typedef uint32_t tcg_target_ulong;
  70 #define TCG_PRIlx PRIx32
  71 #define TCG_PRIld PRId32
  72 #elif TCG_TARGET_REG_BITS == 64
  73 typedef int64_t tcg_target_long;
  74 typedef uint64_t tcg_target_ulong;
  75 #define TCG_PRIlx PRIx64
  76 #define TCG_PRIld PRId64
  77 #else
  78 #error unsupported
  79 #endif
  80
  81 /* Oversized TCG guests make things like MTTCG hard
  82  * as we can't use atomics for cputlb updates.
  83  */
  84 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
  85 #define TCG_OVERSIZED_GUEST 1
  86 #else
  87 #define TCG_OVERSIZED_GUEST 0
  88 #endif
  89
  90 #if TCG_TARGET_NB_REGS <= 32
  91 typedef uint32_t TCGRegSet;
  92 #elif TCG_TARGET_NB_REGS <= 64
  93 typedef uint64_t TCGRegSet;
  94 #else
  95 #error unsupported
  96 #endif
  97
  98 #if TCG_TARGET_REG_BITS == 32
  99 /* Turn some undef macros into false macros.  */
 100 #define TCG_TARGET_HAS_extrl_i64_i32    0
 101 #define TCG_TARGET_HAS_extrh_i64_i32    0
 102 #define TCG_TARGET_HAS_div_i64          0
 103 #define TCG_TARGET_HAS_rem_i64          0
 104 #define TCG_TARGET_HAS_div2_i64         0
 105 #define TCG_TARGET_HAS_rot_i64          0
 106 #define TCG_TARGET_HAS_ext8s_i64        0
 107 #define TCG_TARGET_HAS_ext16s_i64       0
 108 #define TCG_TARGET_HAS_ext32s_i64       0
 109 #define TCG_TARGET_HAS_ext8u_i64        0
 110 #define TCG_TARGET_HAS_ext16u_i64       0
 111 #define TCG_TARGET_HAS_ext32u_i64       0
 112 #define TCG_TARGET_HAS_bswap16_i64      0
 113 #define TCG_TARGET_HAS_bswap32_i64      0
 114 #define TCG_TARGET_HAS_bswap64_i64      0
 115 #define TCG_TARGET_HAS_neg_i64          0
 116 #define TCG_TARGET_HAS_not_i64          0
 117 #define TCG_TARGET_HAS_andc_i64         0
 118 #define TCG_TARGET_HAS_orc_i64          0
 119 #define TCG_TARGET_HAS_eqv_i64          0
 120 #define TCG_TARGET_HAS_nand_i64         0
 121 #define TCG_TARGET_HAS_nor_i64          0
 122 #define TCG_TARGET_HAS_clz_i64          0
 123 #define TCG_TARGET_HAS_ctz_i64          0
 124 #define TCG_TARGET_HAS_ctpop_i64        0
 125 #define TCG_TARGET_HAS_deposit_i64      0
 126 #define TCG_TARGET_HAS_extract_i64      0
 127 #define TCG_TARGET_HAS_sextract_i64     0
 128 #define TCG_TARGET_HAS_movcond_i64      0
 129 #define TCG_TARGET_HAS_add2_i64         0
 130 #define TCG_TARGET_HAS_sub2_i64         0
 131 #define TCG_TARGET_HAS_mulu2_i64        0
 132 #define TCG_TARGET_HAS_muls2_i64        0
 133 #define TCG_TARGET_HAS_muluh_i64        0
 134 #define TCG_TARGET_HAS_mulsh_i64        0
 135 /* Turn some undef macros into true macros.  */
 136 #define TCG_TARGET_HAS_add2_i32         1
 137 #define TCG_TARGET_HAS_sub2_i32         1
 138 #endif
 139
 140 #ifndef TCG_TARGET_deposit_i32_valid
 141 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1
 142 #endif
 143 #ifndef TCG_TARGET_deposit_i64_valid
 144 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1
 145 #endif
 146 #ifndef TCG_TARGET_extract_i32_valid
 147 #define TCG_TARGET_extract_i32_valid(ofs, len) 1
 148 #endif
 149 #ifndef TCG_TARGET_extract_i64_valid
 150 #define TCG_TARGET_extract_i64_valid(ofs, len) 1
 151 #endif
 152
 153 /* Only one of DIV or DIV2 should be defined.  */
 154 #if defined(TCG_TARGET_HAS_div_i32)
 155 #define TCG_TARGET_HAS_div2_i32         0
 156 #elif defined(TCG_TARGET_HAS_div2_i32)
 157 #define TCG_TARGET_HAS_div_i32          0
 158 #define TCG_TARGET_HAS_rem_i32          0
 159 #endif
 160 #if defined(TCG_TARGET_HAS_div_i64)
 161 #define TCG_TARGET_HAS_div2_i64         0
 162 #elif defined(TCG_TARGET_HAS_div2_i64)
 163 #define TCG_TARGET_HAS_div_i64          0
 164 #define TCG_TARGET_HAS_rem_i64          0
 165 #endif
 166
 167 /* For 32-bit targets, some sort of unsigned widening multiply is required.  */
 168 #if TCG_TARGET_REG_BITS == 32 \
 169     && !(defined(TCG_TARGET_HAS_mulu2_i32) \
 170          || defined(TCG_TARGET_HAS_muluh_i32))
 171 # error "Missing unsigned widening multiply"
 172 #endif
 173
 174 #if !defined(TCG_TARGET_HAS_v64) \
 175     && !defined(TCG_TARGET_HAS_v128) \
 176     && !defined(TCG_TARGET_HAS_v256)
 177 #define TCG_TARGET_MAYBE_vec            0
 178 #define TCG_TARGET_HAS_neg_vec          0
 179 #define TCG_TARGET_HAS_not_vec          0
 180 #define TCG_TARGET_HAS_andc_vec         0
 181 #define TCG_TARGET_HAS_orc_vec          0
 182 #define TCG_TARGET_HAS_shi_vec          0
 183 #define TCG_TARGET_HAS_shs_vec          0
 184 #define TCG_TARGET_HAS_shv_vec          0
 185 #define TCG_TARGET_HAS_mul_vec          0
 186 #else
 187 #define TCG_TARGET_MAYBE_vec            1
 188 #endif
 189 #ifndef TCG_TARGET_HAS_v64
 190 #define TCG_TARGET_HAS_v64              0
 191 #endif
 192 #ifndef TCG_TARGET_HAS_v128
 193 #define TCG_TARGET_HAS_v128             0
 194 #endif
 195 #ifndef TCG_TARGET_HAS_v256
 196 #define TCG_TARGET_HAS_v256             0
 197 #endif
 198
 199 #ifndef TARGET_INSN_START_EXTRA_WORDS
 200 # define TARGET_INSN_START_WORDS 1
 201 #else
 202 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
 203 #endif
 204
 205 typedef enum TCGOpcode {
 206 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name,
 207 #include "tcg-opc.h"
 208 #undef DEF
 209     NB_OPS,
 210 } TCGOpcode;
 211
 212 #define tcg_regset_set_reg(d, r)   ((d) |= (TCGRegSet)1 << (r))
 213 #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r)))
 214 #define tcg_regset_test_reg(d, r)  (((d) >> (r)) & 1)
 215
 216 #ifndef TCG_TARGET_INSN_UNIT_SIZE
 217 # error "Missing TCG_TARGET_INSN_UNIT_SIZE"
 218 #elif TCG_TARGET_INSN_UNIT_SIZE == 1
 219 typedef uint8_t tcg_insn_unit;
 220 #elif TCG_TARGET_INSN_UNIT_SIZE == 2
 221 typedef uint16_t tcg_insn_unit;
 222 #elif TCG_TARGET_INSN_UNIT_SIZE == 4
 223 typedef uint32_t tcg_insn_unit;
 224 #elif TCG_TARGET_INSN_UNIT_SIZE == 8
 225 typedef uint64_t tcg_insn_unit;
 226 #else
 227 /* The port better have done this.  */
 228 #endif
 229
 230
 231 #if defined CONFIG_DEBUG_TCG || defined QEMU_STATIC_ANALYSIS
 232 # define tcg_debug_assert(X) do { assert(X); } while (0)
 233 #elif QEMU_GNUC_PREREQ(4, 5)
 234 # define tcg_debug_assert(X) \
 235     do { if (!(X)) { __builtin_unreachable(); } } while (0)
 236 #else
 237 # define tcg_debug_assert(X) do { (void)(X); } while (0)
 238 #endif
 239
 240 typedef struct TCGRelocation {
 241     struct TCGRelocation *next;
 242     int type;
 243     tcg_insn_unit *ptr;
 244     intptr_t addend;
 245 } TCGRelocation;
 246
 247 typedef struct TCGLabel {
 248     unsigned has_value : 1;
 249     unsigned id : 31;
 250     union {
 251         uintptr_t value;
 252         tcg_insn_unit *value_ptr;
 253         TCGRelocation *first_reloc;
 254     } u;
 255 } TCGLabel;
 256
 257 typedef struct TCGPool {
 258     struct TCGPool *next;
 259     int size;
 260     uint8_t data[0] __attribute__ ((aligned));
 261 } TCGPool;
 262
 263 #define TCG_POOL_CHUNK_SIZE 32768
 264
 265 #define TCG_MAX_TEMPS 512
 266 #define TCG_MAX_INSNS 512
 267
 268 /* when the size of the arguments of a called function is smaller than
 269    this value, they are statically allocated in the TB stack frame */
 270 #define TCG_STATIC_CALL_ARGS_SIZE 128
 271
 272 typedef enum TCGType {
 273     TCG_TYPE_I32,
 274     TCG_TYPE_I64,
 275
 276     TCG_TYPE_V64,
 277     TCG_TYPE_V128,
 278     TCG_TYPE_V256,
 279
 280     TCG_TYPE_COUNT, /* number of different types */
 281
 282     /* An alias for the size of the host register.  */
 283 #if TCG_TARGET_REG_BITS == 32
 284     TCG_TYPE_REG = TCG_TYPE_I32,
 285 #else
 286     TCG_TYPE_REG = TCG_TYPE_I64,
 287 #endif
 288
 289     /* An alias for the size of the native pointer.  */
 290 #if UINTPTR_MAX == UINT32_MAX
 291     TCG_TYPE_PTR = TCG_TYPE_I32,
 292 #else
 293     TCG_TYPE_PTR = TCG_TYPE_I64,
 294 #endif
 295
 296     /* An alias for the size of the target "long", aka register.  */
 297 #if TARGET_LONG_BITS == 64
 298     TCG_TYPE_TL = TCG_TYPE_I64,
 299 #else
 300     TCG_TYPE_TL = TCG_TYPE_I32,
 301 #endif
 302 } TCGType;
 303
 304 /* Constants for qemu_ld and qemu_st for the Memory Operation field.  */
 305 typedef enum TCGMemOp {
 306     MO_8     = 0,
 307     MO_16    = 1,
 308     MO_32    = 2,
 309     MO_64    = 3,
 310     MO_SIZE  = 3,   /* Mask for the above.  */
 311
 312     MO_SIGN  = 4,   /* Sign-extended, otherwise zero-extended.  */
 313
 314     MO_BSWAP = 8,   /* Host reverse endian.  */
 315 #ifdef HOST_WORDS_BIGENDIAN
 316     MO_LE    = MO_BSWAP,
 317     MO_BE    = 0,
 318 #else
 319     MO_LE    = 0,
 320     MO_BE    = MO_BSWAP,
 321 #endif
 322 #ifdef TARGET_WORDS_BIGENDIAN
 323     MO_TE    = MO_BE,
 324 #else
 325     MO_TE    = MO_LE,
 326 #endif
 327
 328     /* MO_UNALN accesses are never checked for alignment.
 329      * MO_ALIGN accesses will result in a call to the CPU's
 330      * do_unaligned_access hook if the guest address is not aligned.
 331      * The default depends on whether the target CPU defines ALIGNED_ONLY.
 332      *
 333      * Some architectures (e.g. ARMv8) need the address which is aligned
 334      * to a size more than the size of the memory access.
 335      * Some architectures (e.g. SPARCv9) need an address which is aligned,
 336      * but less strictly than the natural alignment.
 337      *
 338      * MO_ALIGN supposes the alignment size is the size of a memory access.
 339      *
 340      * There are three options:
 341      * - unaligned access permitted (MO_UNALN).
 342      * - an alignment to the size of an access (MO_ALIGN);
 343      * - an alignment to a specified size, which may be more or less than
 344      *   the access size (MO_ALIGN_x where 'x' is a size in bytes);
 345      */
 346     MO_ASHIFT = 4,
 347     MO_AMASK = 7 << MO_ASHIFT,
 348 #ifdef ALIGNED_ONLY
 349     MO_ALIGN = 0,
 350     MO_UNALN = MO_AMASK,
 351 #else
 352     MO_ALIGN = MO_AMASK,
 353     MO_UNALN = 0,
 354 #endif
 355     MO_ALIGN_2  = 1 << MO_ASHIFT,
 356     MO_ALIGN_4  = 2 << MO_ASHIFT,
 357     MO_ALIGN_8  = 3 << MO_ASHIFT,
 358     MO_ALIGN_16 = 4 << MO_ASHIFT,
 359     MO_ALIGN_32 = 5 << MO_ASHIFT,
 360     MO_ALIGN_64 = 6 << MO_ASHIFT,
 361
 362     /* Combinations of the above, for ease of use.  */
 363     MO_UB    = MO_8,
 364     MO_UW    = MO_16,
 365     MO_UL    = MO_32,
 366     MO_SB    = MO_SIGN | MO_8,
 367     MO_SW    = MO_SIGN | MO_16,
 368     MO_SL    = MO_SIGN | MO_32,
 369     MO_Q     = MO_64,
 370
 371     MO_LEUW  = MO_LE | MO_UW,
 372     MO_LEUL  = MO_LE | MO_UL,
 373     MO_LESW  = MO_LE | MO_SW,
 374     MO_LESL  = MO_LE | MO_SL,
 375     MO_LEQ   = MO_LE | MO_Q,
 376
 377     MO_BEUW  = MO_BE | MO_UW,
 378     MO_BEUL  = MO_BE | MO_UL,
 379     MO_BESW  = MO_BE | MO_SW,
 380     MO_BESL  = MO_BE | MO_SL,
 381     MO_BEQ   = MO_BE | MO_Q,
 382
 383     MO_TEUW  = MO_TE | MO_UW,
 384     MO_TEUL  = MO_TE | MO_UL,
 385     MO_TESW  = MO_TE | MO_SW,
 386     MO_TESL  = MO_TE | MO_SL,
 387     MO_TEQ   = MO_TE | MO_Q,
 388
 389     MO_SSIZE = MO_SIZE | MO_SIGN,
 390 } TCGMemOp;
 391
 392 /**
 393  * get_alignment_bits
 394  * @memop: TCGMemOp value
 395  *
 396  * Extract the alignment size from the memop.
 397  */
 398 static inline unsigned get_alignment_bits(TCGMemOp memop)
 399 {
 400     unsigned a = memop & MO_AMASK;
 401
 402     if (a == MO_UNALN) {
 403         /* No alignment required.  */
 404         a = 0;
 405     } else if (a == MO_ALIGN) {
 406         /* A natural alignment requirement.  */
 407         a = memop & MO_SIZE;
 408     } else {
 409         /* A specific alignment requirement.  */
 410         a = a >> MO_ASHIFT;
 411     }
 412 #if defined(CONFIG_SOFTMMU)
 413     /* The requested alignment cannot overlap the TLB flags.  */
 414     tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0);
 415 #endif
 416     return a;
 417 }
 418
 419 typedef tcg_target_ulong TCGArg;
 420
 421 /* Define type and accessor macros for TCG variables.
 422
 423    TCG variables are the inputs and outputs of TCG ops, as described
 424    in tcg/README. Target CPU front-end code uses these types to deal
 425    with TCG variables as it emits TCG code via the tcg_gen_* functions.
 426    They come in several flavours:
 427     * TCGv_i32 : 32 bit integer type
 428     * TCGv_i64 : 64 bit integer type
 429     * TCGv_ptr : a host pointer type
 430     * TCGv_vec : a host vector type; the exact size is not exposed
 431                  to the CPU front-end code.
 432     * TCGv : an integer type the same size as target_ulong
 433              (an alias for either TCGv_i32 or TCGv_i64)
 434    The compiler's type checking will complain if you mix them
 435    up and pass the wrong sized TCGv to a function.
 436
 437    Users of tcg_gen_* don't need to know about any of the internal
 438    details of these, and should treat them as opaque types.
 439    You won't be able to look inside them in a debugger either.
 440
 441    Internal implementation details follow:
 442
 443    Note that there is no definition of the structs TCGv_i32_d etc anywhere.
 444    This is deliberate, because the values we store in variables of type
 445    TCGv_i32 are not really pointers-to-structures. They're just small
 446    integers, but keeping them in pointer types like this means that the
 447    compiler will complain if you accidentally pass a TCGv_i32 to a
 448    function which takes a TCGv_i64, and so on. Only the internals of
 449    TCG need to care about the actual contents of the types.  */
 450
 451 typedef struct TCGv_i32_d *TCGv_i32;
 452 typedef struct TCGv_i64_d *TCGv_i64;
 453 typedef struct TCGv_ptr_d *TCGv_ptr;
 454 typedef struct TCGv_vec_d *TCGv_vec;
 455 typedef TCGv_ptr TCGv_env;
 456 #if TARGET_LONG_BITS == 32
 457 #define TCGv TCGv_i32
 458 #elif TARGET_LONG_BITS == 64
 459 #define TCGv TCGv_i64
 460 #else
 461 #error Unhandled TARGET_LONG_BITS value
 462 #endif
 463
 464 /* call flags */
 465 /* Helper does not read globals (either directly or through an exception). It
 466    implies TCG_CALL_NO_WRITE_GLOBALS. */
 467 #define TCG_CALL_NO_READ_GLOBALS    0x0010
 468 /* Helper does not write globals */
 469 #define TCG_CALL_NO_WRITE_GLOBALS   0x0020
 470 /* Helper can be safely suppressed if the return value is not used. */
 471 #define TCG_CALL_NO_SIDE_EFFECTS    0x0040
 472
 473 /* convenience version of most used call flags */
 474 #define TCG_CALL_NO_RWG         TCG_CALL_NO_READ_GLOBALS
 475 #define TCG_CALL_NO_WG          TCG_CALL_NO_WRITE_GLOBALS
 476 #define TCG_CALL_NO_SE          TCG_CALL_NO_SIDE_EFFECTS
 477 #define TCG_CALL_NO_RWG_SE      (TCG_CALL_NO_RWG | TCG_CALL_NO_SE)
 478 #define TCG_CALL_NO_WG_SE       (TCG_CALL_NO_WG | TCG_CALL_NO_SE)
 479
 480 /* Used to align parameters.  See the comment before tcgv_i32_temp.  */
 481 #define TCG_CALL_DUMMY_ARG      ((TCGArg)0)
 482
 483 /* Conditions.  Note that these are laid out for easy manipulation by
 484    the functions below:
 485      bit 0 is used for inverting;
 486      bit 1 is signed,
 487      bit 2 is unsigned,
 488      bit 3 is used with bit 0 for swapping signed/unsigned.  */
 489 typedef enum {
 490     /* non-signed */
 491     TCG_COND_NEVER  = 0 | 0 | 0 | 0,
 492     TCG_COND_ALWAYS = 0 | 0 | 0 | 1,
 493     TCG_COND_EQ     = 8 | 0 | 0 | 0,
 494     TCG_COND_NE     = 8 | 0 | 0 | 1,
 495     /* signed */
 496     TCG_COND_LT     = 0 | 0 | 2 | 0,
 497     TCG_COND_GE     = 0 | 0 | 2 | 1,
 498     TCG_COND_LE     = 8 | 0 | 2 | 0,
 499     TCG_COND_GT     = 8 | 0 | 2 | 1,
 500     /* unsigned */
 501     TCG_COND_LTU    = 0 | 4 | 0 | 0,
 502     TCG_COND_GEU    = 0 | 4 | 0 | 1,
 503     TCG_COND_LEU    = 8 | 4 | 0 | 0,
 504     TCG_COND_GTU    = 8 | 4 | 0 | 1,
 505 } TCGCond;
 506
 507 /* Invert the sense of the comparison.  */
 508 static inline TCGCond tcg_invert_cond(TCGCond c)
 509 {
 510     return (TCGCond)(c ^ 1);
 511 }
 512
 513 /* Swap the operands in a comparison.  */
 514 static inline TCGCond tcg_swap_cond(TCGCond c)
 515 {
 516     return c & 6 ? (TCGCond)(c ^ 9) : c;
 517 }
 518
 519 /* Create an "unsigned" version of a "signed" comparison.  */
 520 static inline TCGCond tcg_unsigned_cond(TCGCond c)
 521 {
 522     return c & 2 ? (TCGCond)(c ^ 6) : c;
 523 }
 524
 525 /* Create a "signed" version of an "unsigned" comparison.  */
 526 static inline TCGCond tcg_signed_cond(TCGCond c)
 527 {
 528     return c & 4 ? (TCGCond)(c ^ 6) : c;
 529 }
 530
 531 /* Must a comparison be considered unsigned?  */
 532 static inline bool is_unsigned_cond(TCGCond c)
 533 {
 534     return (c & 4) != 0;
 535 }
 536
 537 /* Create a "high" version of a double-word comparison.
 538    This removes equality from a LTE or GTE comparison.  */
 539 static inline TCGCond tcg_high_cond(TCGCond c)
 540 {
 541     switch (c) {
 542     case TCG_COND_GE:
 543     case TCG_COND_LE:
 544     case TCG_COND_GEU:
 545     case TCG_COND_LEU:
 546         return (TCGCond)(c ^ 8);
 547     default:
 548         return c;
 549     }
 550 }
 551
 552 typedef enum TCGTempVal {
 553     TEMP_VAL_DEAD,
 554     TEMP_VAL_REG,
 555     TEMP_VAL_MEM,
 556     TEMP_VAL_CONST,
 557 } TCGTempVal;
 558
 559 typedef struct TCGTemp {
 560     TCGReg reg:8;
 561     TCGTempVal val_type:8;
 562     TCGType base_type:8;
 563     TCGType type:8;
 564     unsigned int fixed_reg:1;
 565     unsigned int indirect_reg:1;
 566     unsigned int indirect_base:1;
 567     unsigned int mem_coherent:1;
 568     unsigned int mem_allocated:1;
 569     /* If true, the temp is saved across both basic blocks and
 570        translation blocks.  */
 571     unsigned int temp_global:1;
 572     /* If true, the temp is saved across basic blocks but dead
 573        at the end of translation blocks.  If false, the temp is
 574        dead at the end of basic blocks.  */
 575     unsigned int temp_local:1;
 576     unsigned int temp_allocated:1;
 577
 578     tcg_target_long val;
 579     struct TCGTemp *mem_base;
 580     intptr_t mem_offset;
 581     const char *name;
 582
 583     /* Pass-specific information that can be stored for a temporary.
 584        One word worth of integer data, and one pointer to data
 585        allocated separately.  */
 586     uintptr_t state;
 587     void *state_ptr;
 588 } TCGTemp;
 589
 590 typedef struct TCGContext TCGContext;
 591
 592 typedef struct TCGTempSet {
 593     unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)];
 594 } TCGTempSet;
 595
 596 /* While we limit helpers to 6 arguments, for 32-bit hosts, with padding,
 597    this imples a max of 6*2 (64-bit in) + 2 (64-bit out) = 14 operands.
 598    There are never more than 2 outputs, which means that we can store all
 599    dead + sync data within 16 bits.  */
 600 #define DEAD_ARG  4
 601 #define SYNC_ARG  1
 602 typedef uint16_t TCGLifeData;
 603
 604 /* The layout here is designed to avoid a bitfield crossing of
 605    a 32-bit boundary, which would cause GCC to add extra padding.  */
 606 typedef struct TCGOp {
 607     TCGOpcode opc   : 8;        /*  8 */
 608
 609     /* Parameters for this opcode.  See below.  */
 610     unsigned param1 : 4;        /* 12 */
 611     unsigned param2 : 4;        /* 16 */
 612
 613     /* Lifetime data of the operands.  */
 614     unsigned life   : 16;       /* 32 */
 615
 616     /* Next and previous opcodes.  */
 617     QTAILQ_ENTRY(TCGOp) link;
 618
 619     /* Arguments for the opcode.  */
 620     TCGArg args[MAX_OPC_PARAM];
 621 } TCGOp;
 622
 623 #define TCGOP_CALLI(X)    (X)->param1
 624 #define TCGOP_CALLO(X)    (X)->param2
 625
 626 #define TCGOP_VECL(X)     (X)->param1
 627 #define TCGOP_VECE(X)     (X)->param2
 628
 629 /* Make sure operands fit in the bitfields above.  */
 630 QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8));
 631
 632 typedef struct TCGProfile {
 633     int64_t cpu_exec_time;
 634     int64_t tb_count1;
 635     int64_t tb_count;
 636     int64_t op_count; /* total insn count */
 637     int op_count_max; /* max insn per TB */
 638     int temp_count_max;
 639     int64_t temp_count;
 640     int64_t del_op_count;
 641     int64_t code_in_len;
 642     int64_t code_out_len;
 643     int64_t search_out_len;
 644     int64_t interm_time;
 645     int64_t code_time;
 646     int64_t la_time;
 647     int64_t opt_time;
 648     int64_t restore_count;
 649     int64_t restore_time;
 650     int64_t table_op_count[NB_OPS];
 651 } TCGProfile;
 652
 653 struct TCGContext {
 654     uint8_t *pool_cur, *pool_end;
 655     TCGPool *pool_first, *pool_current, *pool_first_large;
 656     int nb_labels;
 657     int nb_globals;
 658     int nb_temps;
 659     int nb_indirects;
 660     int nb_ops;
 661
 662     /* goto_tb support */
 663     tcg_insn_unit *code_buf;
 664     uint16_t *tb_jmp_reset_offset; /* tb->jmp_reset_offset */
 665     uintptr_t *tb_jmp_insn_offset; /* tb->jmp_target_arg if direct_jump */
 666     uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_arg if !direct_jump */
 667
 668     TCGRegSet reserved_regs;
 669     uint32_t tb_cflags; /* cflags of the current TB */
 670     intptr_t current_frame_offset;
 671     intptr_t frame_start;
 672     intptr_t frame_end;
 673     TCGTemp *frame_temp;
 674
 675     tcg_insn_unit *code_ptr;
 676
 677 #ifdef CONFIG_PROFILER
 678     TCGProfile prof;
 679 #endif
 680
 681 #ifdef CONFIG_DEBUG_TCG
 682     int temps_in_use;
 683     int goto_tb_issue_mask;
 684 #endif
 685
 686     /* Code generation.  Note that we specifically do not use tcg_insn_unit
 687        here, because there's too much arithmetic throughout that relies
 688        on addition and subtraction working on bytes.  Rely on the GCC
 689        extension that allows arithmetic on void*.  */
 690     void *code_gen_prologue;
 691     void *code_gen_epilogue;
 692     void *code_gen_buffer;
 693     size_t code_gen_buffer_size;
 694     void *code_gen_ptr;
 695     void *data_gen_ptr;
 696
 697     /* Threshold to flush the translated code buffer.  */
 698     void *code_gen_highwater;
 699
 700     size_t tb_phys_invalidate_count;
 701
 702     /* Track which vCPU triggers events */
 703     CPUState *cpu;                      /* *_trans */
 704
 705     /* These structures are private to tcg-target.inc.c.  */
 706 #ifdef TCG_TARGET_NEED_LDST_LABELS
 707     QSIMPLEQ_HEAD(ldst_labels, TCGLabelQemuLdst) ldst_labels;
 708 #endif
 709 #ifdef TCG_TARGET_NEED_POOL_LABELS
 710     struct TCGLabelPoolData *pool_labels;
 711 #endif
 712
 713     TCGLabel *exitreq_label;
 714
 715     TCGTempSet free_temps[TCG_TYPE_COUNT * 2];
 716     TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */
 717
 718     QTAILQ_HEAD(TCGOpHead, TCGOp) ops, free_ops;
 719
 720     /* Tells which temporary holds a given register.
 721        It does not take into account fixed registers */
 722     TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS];
 723
 724     uint16_t gen_insn_end_off[TCG_MAX_INSNS];
 725     target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS];
 726 };
 727
 728 extern TCGContext tcg_init_ctx;
 729 extern __thread TCGContext *tcg_ctx;
 730 extern TCGv_env cpu_env;
 731
 732 static inline size_t temp_idx(TCGTemp *ts)
 733 {
 734     ptrdiff_t n = ts - tcg_ctx->temps;
 735     tcg_debug_assert(n >= 0 && n < tcg_ctx->nb_temps);
 736     return n;
 737 }
 738
 739 static inline TCGArg temp_arg(TCGTemp *ts)
 740 {
 741     return (uintptr_t)ts;
 742 }
 743
 744 static inline TCGTemp *arg_temp(TCGArg a)
 745 {
 746     return (TCGTemp *)(uintptr_t)a;
 747 }
 748
 749 /* Using the offset of a temporary, relative to TCGContext, rather than
 750    its index means that we don't use 0.  That leaves offset 0 free for
 751    a NULL representation without having to leave index 0 unused.  */
 752 static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v)
 753 {
 754     uintptr_t o = (uintptr_t)v;
 755     TCGTemp *t = (void *)tcg_ctx + o;
 756     tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) == o);
 757     return t;
 758 }
 759
 760 static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v)
 761 {
 762     return tcgv_i32_temp((TCGv_i32)v);
 763 }
 764
 765 static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v)
 766 {
 767     return tcgv_i32_temp((TCGv_i32)v);
 768 }
 769
 770 static inline TCGTemp *tcgv_vec_temp(TCGv_vec v)
 771 {
 772     return tcgv_i32_temp((TCGv_i32)v);
 773 }
 774
 775 static inline TCGArg tcgv_i32_arg(TCGv_i32 v)
 776 {
 777     return temp_arg(tcgv_i32_temp(v));
 778 }
 779
 780 static inline TCGArg tcgv_i64_arg(TCGv_i64 v)
 781 {
 782     return temp_arg(tcgv_i64_temp(v));
 783 }
 784
 785 static inline TCGArg tcgv_ptr_arg(TCGv_ptr v)
 786 {
 787     return temp_arg(tcgv_ptr_temp(v));
 788 }
 789
 790 static inline TCGArg tcgv_vec_arg(TCGv_vec v)
 791 {
 792     return temp_arg(tcgv_vec_temp(v));
 793 }
 794
 795 static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t)
 796 {
 797     (void)temp_idx(t); /* trigger embedded assert */
 798     return (TCGv_i32)((void *)t - (void *)tcg_ctx);
 799 }
 800
 801 static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t)
 802 {
 803     return (TCGv_i64)temp_tcgv_i32(t);
 804 }
 805
 806 static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t)
 807 {
 808     return (TCGv_ptr)temp_tcgv_i32(t);
 809 }
 810
 811 static inline TCGv_vec temp_tcgv_vec(TCGTemp *t)
 812 {
 813     return (TCGv_vec)temp_tcgv_i32(t);
 814 }
 815
 816 #if TCG_TARGET_REG_BITS == 32
 817 static inline TCGv_i32 TCGV_LOW(TCGv_i64 t)
 818 {
 819     return temp_tcgv_i32(tcgv_i64_temp(t));
 820 }
 821
 822 static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t)
 823 {
 824     return temp_tcgv_i32(tcgv_i64_temp(t) + 1);
 825 }
 826 #endif
 827
 828 static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v)
 829 {
 830     op->args[arg] = v;
 831 }
 832
 833 static inline void tcg_set_insn_start_param(TCGOp *op, int arg, target_ulong v)
 834 {
 835 #if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
 836     tcg_set_insn_param(op, arg, v);
 837 #else
 838     tcg_set_insn_param(op, arg * 2, v);
 839     tcg_set_insn_param(op, arg * 2 + 1, v >> 32);
 840 #endif
 841 }
 842
 843 /* The last op that was emitted.  */
 844 static inline TCGOp *tcg_last_op(void)
 845 {
 846     return QTAILQ_LAST(&tcg_ctx->ops, TCGOpHead);
 847 }
 848
 849 /* Test for whether to terminate the TB for using too many opcodes.  */
 850 static inline bool tcg_op_buf_full(void)
 851 {
 852     /* This is not a hard limit, it merely stops translation when
 853      * we have produced "enough" opcodes.  We want to limit TB size
 854      * such that a RISC host can reasonably use a 16-bit signed
 855      * branch within the TB.  We also need to be mindful of the
 856      * 16-bit unsigned offsets, TranslationBlock.jmp_reset_offset[]
 857      * and TCGContext.gen_insn_end_off[].
 858      */
 859     return tcg_ctx->nb_ops >= 4000;
 860 }
 861
 862 /* pool based memory allocation */
 863
 864 /* user-mode: mmap_lock must be held for tcg_malloc_internal. */
 865 void *tcg_malloc_internal(TCGContext *s, int size);
 866 void tcg_pool_reset(TCGContext *s);
 867 TranslationBlock *tcg_tb_alloc(TCGContext *s);
 868
 869 void tcg_region_init(void);
 870 void tcg_region_reset_all(void);
 871
 872 size_t tcg_code_size(void);
 873 size_t tcg_code_capacity(void);
 874
 875 void tcg_tb_insert(TranslationBlock *tb);
 876 void tcg_tb_remove(TranslationBlock *tb);
 877 size_t tcg_tb_phys_invalidate_count(void);
 878 TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr);
 879 void tcg_tb_foreach(GTraverseFunc func, gpointer user_data);
 880 size_t tcg_nb_tbs(void);
 881
 882 /* user-mode: Called with mmap_lock held.  */
 883 static inline void *tcg_malloc(int size)
 884 {
 885     TCGContext *s = tcg_ctx;
 886     uint8_t *ptr, *ptr_end;
 887
 888     /* ??? This is a weak placeholder for minimum malloc alignment.  */
 889     size = QEMU_ALIGN_UP(size, 8);
 890
 891     ptr = s->pool_cur;
 892     ptr_end = ptr + size;
 893     if (unlikely(ptr_end > s->pool_end)) {
 894         return tcg_malloc_internal(tcg_ctx, size);
 895     } else {
 896         s->pool_cur = ptr_end;
 897         return ptr;
 898     }
 899 }
 900
 901 void tcg_context_init(TCGContext *s);
 902 void tcg_register_thread(void);
 903 void tcg_prologue_init(TCGContext *s);
 904 void tcg_func_start(TCGContext *s);
 905
 906 int tcg_gen_code(TCGContext *s, TranslationBlock *tb);
 907
 908 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);
 909
 910 TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr,
 911                                      intptr_t, const char *);
 912 TCGTemp *tcg_temp_new_internal(TCGType, bool);
 913 void tcg_temp_free_internal(TCGTemp *);
 914 TCGv_vec tcg_temp_new_vec(TCGType type);
 915 TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match);
 916
 917 static inline void tcg_temp_free_i32(TCGv_i32 arg)
 918 {
 919     tcg_temp_free_internal(tcgv_i32_temp(arg));
 920 }
 921
 922 static inline void tcg_temp_free_i64(TCGv_i64 arg)
 923 {
 924     tcg_temp_free_internal(tcgv_i64_temp(arg));
 925 }
 926
 927 static inline void tcg_temp_free_ptr(TCGv_ptr arg)
 928 {
 929     tcg_temp_free_internal(tcgv_ptr_temp(arg));
 930 }
 931
 932 static inline void tcg_temp_free_vec(TCGv_vec arg)
 933 {
 934     tcg_temp_free_internal(tcgv_vec_temp(arg));
 935 }
 936
 937 static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
 938                                               const char *name)
 939 {
 940     TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name);
 941     return temp_tcgv_i32(t);
 942 }
 943
 944 static inline TCGv_i32 tcg_temp_new_i32(void)
 945 {
 946     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, false);
 947     return temp_tcgv_i32(t);
 948 }
 949
 950 static inline TCGv_i32 tcg_temp_local_new_i32(void)
 951 {
 952     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, true);
 953     return temp_tcgv_i32(t);
 954 }
 955
 956 static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset,
 957                                               const char *name)
 958 {
 959     TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name);
 960     return temp_tcgv_i64(t);
 961 }
 962
 963 static inline TCGv_i64 tcg_temp_new_i64(void)
 964 {
 965     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, false);
 966     return temp_tcgv_i64(t);
 967 }
 968
 969 static inline TCGv_i64 tcg_temp_local_new_i64(void)
 970 {
 971     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, true);
 972     return temp_tcgv_i64(t);
 973 }
 974
 975 static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset,
 976                                               const char *name)
 977 {
 978     TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_PTR, reg, offset, name);
 979     return temp_tcgv_ptr(t);
 980 }
 981
 982 static inline TCGv_ptr tcg_temp_new_ptr(void)
 983 {
 984     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, false);
 985     return temp_tcgv_ptr(t);
 986 }
 987
 988 static inline TCGv_ptr tcg_temp_local_new_ptr(void)
 989 {
 990     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, true);
 991     return temp_tcgv_ptr(t);
 992 }
 993
 994 #if defined(CONFIG_DEBUG_TCG)
 995 /* If you call tcg_clear_temp_count() at the start of a section of
 996  * code which is not supposed to leak any TCG temporaries, then
 997  * calling tcg_check_temp_count() at the end of the section will
 998  * return 1 if the section did in fact leak a temporary.
 999  */
1000 void tcg_clear_temp_count(void);
1001 int tcg_check_temp_count(void);
1002 #else
1003 #define tcg_clear_temp_count() do { } while (0)
1004 #define tcg_check_temp_count() 0
1005 #endif
1006
1007 int64_t tcg_cpu_exec_time(void);
1008 void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf);
1009 void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf);
1010
1011 #define TCG_CT_ALIAS  0x80
1012 #define TCG_CT_IALIAS 0x40
1013 #define TCG_CT_NEWREG 0x20 /* output requires a new register */
1014 #define TCG_CT_REG    0x01
1015 #define TCG_CT_CONST  0x02 /* any constant of register size */
1016
1017 typedef struct TCGArgConstraint {
1018     uint16_t ct;
1019     uint8_t alias_index;
1020     union {
1021         TCGRegSet regs;
1022     } u;
1023 } TCGArgConstraint;
1024
1025 #define TCG_MAX_OP_ARGS 16
1026
1027 /* Bits for TCGOpDef->flags, 8 bits available.  */
1028 enum {
1029     /* Instruction defines the end of a basic block.  */
1030     TCG_OPF_BB_END       = 0x01,
1031     /* Instruction clobbers call registers and potentially update globals.  */
1032     TCG_OPF_CALL_CLOBBER = 0x02,
1033     /* Instruction has side effects: it cannot be removed if its outputs
1034        are not used, and might trigger exceptions.  */
1035     TCG_OPF_SIDE_EFFECTS = 0x04,
1036     /* Instruction operands are 64-bits (otherwise 32-bits).  */
1037     TCG_OPF_64BIT        = 0x08,
1038     /* Instruction is optional and not implemented by the host, or insn
1039        is generic and should not be implemened by the host.  */
1040     TCG_OPF_NOT_PRESENT  = 0x10,
1041     /* Instruction operands are vectors.  */
1042     TCG_OPF_VECTOR       = 0x20,
1043 };
1044
1045 typedef struct TCGOpDef {
1046     const char *name;
1047     uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args;
1048     uint8_t flags;
1049     TCGArgConstraint *args_ct;
1050     int *sorted_args;
1051 #if defined(CONFIG_DEBUG_TCG)
1052     int used;
1053 #endif
1054 } TCGOpDef;
1055
1056 extern TCGOpDef tcg_op_defs[];
1057 extern const size_t tcg_op_defs_max;
1058
1059 typedef struct TCGTargetOpDef {
1060     TCGOpcode op;
1061     const char *args_ct_str[TCG_MAX_OP_ARGS];
1062 } TCGTargetOpDef;
1063
1064 #define tcg_abort() \
1065 do {\
1066     fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\
1067     abort();\
1068 } while (0)
1069
1070 bool tcg_op_supported(TCGOpcode op);
1071
1072 void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args);
1073
1074 TCGOp *tcg_emit_op(TCGOpcode opc);
1075 void tcg_op_remove(TCGContext *s, TCGOp *op);
1076 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode opc, int narg);
1077 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, TCGOpcode opc, int narg);
1078
1079 void tcg_optimize(TCGContext *s);
1080
1081 /* only used for debugging purposes */
1082 void tcg_dump_ops(TCGContext *s);
1083
1084 TCGv_i32 tcg_const_i32(int32_t val);
1085 TCGv_i64 tcg_const_i64(int64_t val);
1086 TCGv_i32 tcg_const_local_i32(int32_t val);
1087 TCGv_i64 tcg_const_local_i64(int64_t val);
1088 TCGv_vec tcg_const_zeros_vec(TCGType);
1089 TCGv_vec tcg_const_ones_vec(TCGType);
1090 TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec);
1091 TCGv_vec tcg_const_ones_vec_matching(TCGv_vec);
1092
1093 #if UINTPTR_MAX == UINT32_MAX
1094 # define tcg_const_ptr(x)        ((TCGv_ptr)tcg_const_i32((intptr_t)(x)))
1095 # define tcg_const_local_ptr(x)  ((TCGv_ptr)tcg_const_local_i32((intptr_t)(x)))
1096 #else
1097 # define tcg_const_ptr(x)        ((TCGv_ptr)tcg_const_i64((intptr_t)(x)))
1098 # define tcg_const_local_ptr(x)  ((TCGv_ptr)tcg_const_local_i64((intptr_t)(x)))
1099 #endif
1100
1101 TCGLabel *gen_new_label(void);
1102
1103 /**
1104  * label_arg
1105  * @l: label
1106  *
1107  * Encode a label for storage in the TCG opcode stream.
1108  */
1109
1110 static inline TCGArg label_arg(TCGLabel *l)
1111 {
1112     return (uintptr_t)l;
1113 }
1114
1115 /**
1116  * arg_label
1117  * @i: value
1118  *
1119  * The opposite of label_arg.  Retrieve a label from the
1120  * encoding of the TCG opcode stream.
1121  */
1122
1123 static inline TCGLabel *arg_label(TCGArg i)
1124 {
1125     return (TCGLabel *)(uintptr_t)i;
1126 }
1127
1128 /**
1129  * tcg_ptr_byte_diff
1130  * @a, @b: addresses to be differenced
1131  *
1132  * There are many places within the TCG backends where we need a byte
1133  * difference between two pointers.  While this can be accomplished
1134  * with local casting, it's easy to get wrong -- especially if one is
1135  * concerned with the signedness of the result.
1136  *
1137  * This version relies on GCC's void pointer arithmetic to get the
1138  * correct result.
1139  */
1140
1141 static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b)
1142 {
1143     return a - b;
1144 }
1145
1146 /**
1147  * tcg_pcrel_diff
1148  * @s: the tcg context
1149  * @target: address of the target
1150  *
1151  * Produce a pc-relative difference, from the current code_ptr
1152  * to the destination address.
1153  */
1154
1155 static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, void *target)
1156 {
1157     return tcg_ptr_byte_diff(target, s->code_ptr);
1158 }
1159
1160 /**
1161  * tcg_current_code_size
1162  * @s: the tcg context
1163  *
1164  * Compute the current code size within the translation block.
1165  * This is used to fill in qemu's data structures for goto_tb.
1166  */
1167
1168 static inline size_t tcg_current_code_size(TCGContext *s)
1169 {
1170     return tcg_ptr_byte_diff(s->code_ptr, s->code_buf);
1171 }
1172
1173 /* Combine the TCGMemOp and mmu_idx parameters into a single value.  */
1174 typedef uint32_t TCGMemOpIdx;
1175
1176 /**
1177  * make_memop_idx
1178  * @op: memory operation
1179  * @idx: mmu index
1180  *
1181  * Encode these values into a single parameter.
1182  */
1183 static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx)
1184 {
1185     tcg_debug_assert(idx <= 15);
1186     return (op << 4) | idx;
1187 }
1188
1189 /**
1190  * get_memop
1191  * @oi: combined op/idx parameter
1192  *
1193  * Extract the memory operation from the combined value.
1194  */
1195 static inline TCGMemOp get_memop(TCGMemOpIdx oi)
1196 {
1197     return oi >> 4;
1198 }
1199
1200 /**
1201  * get_mmuidx
1202  * @oi: combined op/idx parameter
1203  *
1204  * Extract the mmu index from the combined value.
1205  */
1206 static inline unsigned get_mmuidx(TCGMemOpIdx oi)
1207 {
1208     return oi & 15;
1209 }
1210
1211 /**
1212  * tcg_qemu_tb_exec:
1213  * @env: pointer to CPUArchState for the CPU
1214  * @tb_ptr: address of generated code for the TB to execute
1215  *
1216  * Start executing code from a given translation block.
1217  * Where translation blocks have been linked, execution
1218  * may proceed from the given TB into successive ones.
1219  * Control eventually returns only when some action is needed
1220  * from the top-level loop: either control must pass to a TB
1221  * which has not yet been directly linked, or an asynchronous
1222  * event such as an interrupt needs handling.
1223  *
1224  * Return: The return value is the value passed to the corresponding
1225  * tcg_gen_exit_tb() at translation time of the last TB attempted to execute.
1226  * The value is either zero or a 4-byte aligned pointer to that TB combined
1227  * with additional information in its two least significant bits. The
1228  * additional information is encoded as follows:
1229  *  0, 1: the link between this TB and the next is via the specified
1230  *        TB index (0 or 1). That is, we left the TB via (the equivalent
1231  *        of) "goto_tb <index>". The main loop uses this to determine
1232  *        how to link the TB just executed to the next.
1233  *  2:    we are using instruction counting code generation, and we
1234  *        did not start executing this TB because the instruction counter
1235  *        would hit zero midway through it. In this case the pointer
1236  *        returned is the TB we were about to execute, and the caller must
1237  *        arrange to execute the remaining count of instructions.
1238  *  3:    we stopped because the CPU's exit_request flag was set
1239  *        (usually meaning that there is an interrupt that needs to be
1240  *        handled). The pointer returned is the TB we were about to execute
1241  *        when we noticed the pending exit request.
1242  *
1243  * If the bottom two bits indicate an exit-via-index then the CPU
1244  * state is correctly synchronised and ready for execution of the next
1245  * TB (and in particular the guest PC is the address to execute next).
1246  * Otherwise, we gave up on execution of this TB before it started, and
1247  * the caller must fix up the CPU state by calling the CPU's
1248  * synchronize_from_tb() method with the TB pointer we return (falling
1249  * back to calling the CPU's set_pc method with tb->pb if no
1250  * synchronize_from_tb() method exists).
1251  *
1252  * Note that TCG targets may use a different definition of tcg_qemu_tb_exec
1253  * to this default (which just calls the prologue.code emitted by
1254  * tcg_target_qemu_prologue()).
1255  */
1256 #define TB_EXIT_MASK      3
1257 #define TB_EXIT_IDX0      0
1258 #define TB_EXIT_IDX1      1
1259 #define TB_EXIT_IDXMAX    1
1260 #define TB_EXIT_REQUESTED 3
1261
1262 #ifdef HAVE_TCG_QEMU_TB_EXEC
1263 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr);
1264 #else
1265 # define tcg_qemu_tb_exec(env, tb_ptr) \
1266     ((uintptr_t (*)(void *, void *))tcg_ctx->code_gen_prologue)(env, tb_ptr)
1267 #endif
1268
1269 void tcg_register_jit(void *buf, size_t buf_size);
1270
1271 #if TCG_TARGET_MAYBE_vec
1272 /* Return zero if the tuple (opc, type, vece) is unsupportable;
1273    return > 0 if it is directly supportable;
1274    return < 0 if we must call tcg_expand_vec_op.  */
1275 int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned);
1276 #else
1277 static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve)
1278 {
1279     return 0;
1280 }
1281 #endif
1282
1283 /* Expand the tuple (opc, type, vece) on the given arguments.  */
1284 void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...);
1285
1286 /* Replicate a constant C accoring to the log2 of the element size.  */
1287 uint64_t dup_const(unsigned vece, uint64_t c);
1288
1289 #define dup_const(VECE, C)                                         \
1290     (__builtin_constant_p(VECE)                                    \
1291      ? (  (VECE) == MO_8  ? 0x0101010101010101ull * (uint8_t)(C)   \
1292         : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C)  \
1293         : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C)  \
1294         : dup_const(VECE, C))                                      \
1295      : dup_const(VECE, C))
1296
1297
1298 /*
1299  * Memory helpers that will be used by TCG generated code.
1300  */
1301 #ifdef CONFIG_SOFTMMU
1302 /* Value zero-extended to tcg register size.  */
1303 tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
1304                                      TCGMemOpIdx oi, uintptr_t retaddr);
1305 tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
1306                                     TCGMemOpIdx oi, uintptr_t retaddr);
1307 tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
1308                                     TCGMemOpIdx oi, uintptr_t retaddr);
1309 uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
1310                            TCGMemOpIdx oi, uintptr_t retaddr);
1311 tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
1312                                     TCGMemOpIdx oi, uintptr_t retaddr);
1313 tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
1314                                     TCGMemOpIdx oi, uintptr_t retaddr);
1315 uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
1316                            TCGMemOpIdx oi, uintptr_t retaddr);
1317
1318 /* Value sign-extended to tcg register size.  */
1319 tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
1320                                      TCGMemOpIdx oi, uintptr_t retaddr);
1321 tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
1322                                     TCGMemOpIdx oi, uintptr_t retaddr);
1323 tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
1324                                     TCGMemOpIdx oi, uintptr_t retaddr);
1325 tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
1326                                     TCGMemOpIdx oi, uintptr_t retaddr);
1327 tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
1328                                     TCGMemOpIdx oi, uintptr_t retaddr);
1329
1330 void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
1331                         TCGMemOpIdx oi, uintptr_t retaddr);
1332 void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
1333                        TCGMemOpIdx oi, uintptr_t retaddr);
1334 void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
1335                        TCGMemOpIdx oi, uintptr_t retaddr);
1336 void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
1337                        TCGMemOpIdx oi, uintptr_t retaddr);
1338 void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
1339                        TCGMemOpIdx oi, uintptr_t retaddr);
1340 void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
1341                        TCGMemOpIdx oi, uintptr_t retaddr);
1342 void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
1343                        TCGMemOpIdx oi, uintptr_t retaddr);
1344
1345 uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr,
1346                             TCGMemOpIdx oi, uintptr_t retaddr);
1347 uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr,
1348                             TCGMemOpIdx oi, uintptr_t retaddr);
1349 uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr,
1350                             TCGMemOpIdx oi, uintptr_t retaddr);
1351 uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr,
1352                             TCGMemOpIdx oi, uintptr_t retaddr);
1353 uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr,
1354                             TCGMemOpIdx oi, uintptr_t retaddr);
1355 uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr,
1356                             TCGMemOpIdx oi, uintptr_t retaddr);
1357 uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
1358                             TCGMemOpIdx oi, uintptr_t retaddr);
1359
1360 /* Temporary aliases until backends are converted.  */
1361 #ifdef TARGET_WORDS_BIGENDIAN
1362 # define helper_ret_ldsw_mmu  helper_be_ldsw_mmu
1363 # define helper_ret_lduw_mmu  helper_be_lduw_mmu
1364 # define helper_ret_ldsl_mmu  helper_be_ldsl_mmu
1365 # define helper_ret_ldul_mmu  helper_be_ldul_mmu
1366 # define helper_ret_ldl_mmu   helper_be_ldul_mmu
1367 # define helper_ret_ldq_mmu   helper_be_ldq_mmu
1368 # define helper_ret_stw_mmu   helper_be_stw_mmu
1369 # define helper_ret_stl_mmu   helper_be_stl_mmu
1370 # define helper_ret_stq_mmu   helper_be_stq_mmu
1371 # define helper_ret_ldw_cmmu  helper_be_ldw_cmmu
1372 # define helper_ret_ldl_cmmu  helper_be_ldl_cmmu
1373 # define helper_ret_ldq_cmmu  helper_be_ldq_cmmu
1374 #else
1375 # define helper_ret_ldsw_mmu  helper_le_ldsw_mmu
1376 # define helper_ret_lduw_mmu  helper_le_lduw_mmu
1377 # define helper_ret_ldsl_mmu  helper_le_ldsl_mmu
1378 # define helper_ret_ldul_mmu  helper_le_ldul_mmu
1379 # define helper_ret_ldl_mmu   helper_le_ldul_mmu
1380 # define helper_ret_ldq_mmu   helper_le_ldq_mmu
1381 # define helper_ret_stw_mmu   helper_le_stw_mmu
1382 # define helper_ret_stl_mmu   helper_le_stl_mmu
1383 # define helper_ret_stq_mmu   helper_le_stq_mmu
1384 # define helper_ret_ldw_cmmu  helper_le_ldw_cmmu
1385 # define helper_ret_ldl_cmmu  helper_le_ldl_cmmu
1386 # define helper_ret_ldq_cmmu  helper_le_ldq_cmmu
1387 #endif
1388
1389 uint32_t helper_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr,
1390                                     uint32_t cmpv, uint32_t newv,
1391                                     TCGMemOpIdx oi, uintptr_t retaddr);
1392 uint32_t helper_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr,
1393                                        uint32_t cmpv, uint32_t newv,
1394                                        TCGMemOpIdx oi, uintptr_t retaddr);
1395 uint32_t helper_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr,
1396                                        uint32_t cmpv, uint32_t newv,
1397                                        TCGMemOpIdx oi, uintptr_t retaddr);
1398 uint64_t helper_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr,
1399                                        uint64_t cmpv, uint64_t newv,
1400                                        TCGMemOpIdx oi, uintptr_t retaddr);
1401 uint32_t helper_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr,
1402                                        uint32_t cmpv, uint32_t newv,
1403                                        TCGMemOpIdx oi, uintptr_t retaddr);
1404 uint32_t helper_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr,
1405                                        uint32_t cmpv, uint32_t newv,
1406                                        TCGMemOpIdx oi, uintptr_t retaddr);
1407 uint64_t helper_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr,
1408                                        uint64_t cmpv, uint64_t newv,
1409                                        TCGMemOpIdx oi, uintptr_t retaddr);
1410
1411 #define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX)         \
1412 TYPE helper_atomic_ ## NAME ## SUFFIX ## _mmu         \
1413     (CPUArchState *env, target_ulong addr, TYPE val,  \
1414      TCGMemOpIdx oi, uintptr_t retaddr);
1415
1416 #ifdef CONFIG_ATOMIC64
1417 #define GEN_ATOMIC_HELPER_ALL(NAME)          \
1418     GEN_ATOMIC_HELPER(NAME, uint32_t, b)     \
1419     GEN_ATOMIC_HELPER(NAME, uint32_t, w_le)  \
1420     GEN_ATOMIC_HELPER(NAME, uint32_t, w_be)  \
1421     GEN_ATOMIC_HELPER(NAME, uint32_t, l_le)  \
1422     GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)  \
1423     GEN_ATOMIC_HELPER(NAME, uint64_t, q_le)  \
1424     GEN_ATOMIC_HELPER(NAME, uint64_t, q_be)
1425 #else
1426 #define GEN_ATOMIC_HELPER_ALL(NAME)          \
1427     GEN_ATOMIC_HELPER(NAME, uint32_t, b)     \
1428     GEN_ATOMIC_HELPER(NAME, uint32_t, w_le)  \
1429     GEN_ATOMIC_HELPER(NAME, uint32_t, w_be)  \
1430     GEN_ATOMIC_HELPER(NAME, uint32_t, l_le)  \
1431     GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)
1432 #endif
1433
1434 GEN_ATOMIC_HELPER_ALL(fetch_add)
1435 GEN_ATOMIC_HELPER_ALL(fetch_sub)
1436 GEN_ATOMIC_HELPER_ALL(fetch_and)
1437 GEN_ATOMIC_HELPER_ALL(fetch_or)
1438 GEN_ATOMIC_HELPER_ALL(fetch_xor)
1439 GEN_ATOMIC_HELPER_ALL(fetch_smin)
1440 GEN_ATOMIC_HELPER_ALL(fetch_umin)
1441 GEN_ATOMIC_HELPER_ALL(fetch_smax)
1442 GEN_ATOMIC_HELPER_ALL(fetch_umax)
1443
1444 GEN_ATOMIC_HELPER_ALL(add_fetch)
1445 GEN_ATOMIC_HELPER_ALL(sub_fetch)
1446 GEN_ATOMIC_HELPER_ALL(and_fetch)
1447 GEN_ATOMIC_HELPER_ALL(or_fetch)
1448 GEN_ATOMIC_HELPER_ALL(xor_fetch)
1449 GEN_ATOMIC_HELPER_ALL(smin_fetch)
1450 GEN_ATOMIC_HELPER_ALL(umin_fetch)
1451 GEN_ATOMIC_HELPER_ALL(smax_fetch)
1452 GEN_ATOMIC_HELPER_ALL(umax_fetch)
1453
1454 GEN_ATOMIC_HELPER_ALL(xchg)
1455
1456 #undef GEN_ATOMIC_HELPER_ALL
1457 #undef GEN_ATOMIC_HELPER
1458 #endif /* CONFIG_SOFTMMU */
1459
1460 /*
1461  * These aren't really a "proper" helpers because TCG cannot manage Int128.
1462  * However, use the same format as the others, for use by the backends.
1463  *
1464  * The cmpxchg functions are only defined if HAVE_CMPXCHG128;
1465  * the ld/st functions are only defined if HAVE_ATOMIC128,
1466  * as defined by <qemu/atomic128.h>.
1467  */
1468 Int128 helper_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr,
1469                                      Int128 cmpv, Int128 newv,
1470                                      TCGMemOpIdx oi, uintptr_t retaddr);
1471 Int128 helper_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr,
1472                                      Int128 cmpv, Int128 newv,
1473                                      TCGMemOpIdx oi, uintptr_t retaddr);
1474
1475 Int128 helper_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr,
1476                                 TCGMemOpIdx oi, uintptr_t retaddr);
1477 Int128 helper_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr,
1478                                 TCGMemOpIdx oi, uintptr_t retaddr);
1479 void helper_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val,
1480                               TCGMemOpIdx oi, uintptr_t retaddr);
1481 void helper_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val,
1482                               TCGMemOpIdx oi, uintptr_t retaddr);
1483
1484 #endif /* TCG_H */