hw/arm/xilinx_zynq.c

   1 /*
   2  * Xilinx Zynq Baseboard System emulation.
   3  *
   4  * Copyright (c) 2010 Xilinx.
   5  * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com)
   6  * Copyright (c) 2012 Petalogix Pty Ltd.
   7  * Written by Haibing Ma
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include "qemu/osdep.h"
  19 #include "qapi/error.h"
  20 #include "qemu-common.h"
  21 #include "cpu.h"
  22 #include "hw/sysbus.h"
  23 #include "hw/arm/arm.h"
  24 #include "net/net.h"
  25 #include "exec/address-spaces.h"
  26 #include "sysemu/sysemu.h"
  27 #include "hw/boards.h"
  28 #include "hw/block/flash.h"
  29 #include "hw/loader.h"
  30 #include "hw/misc/zynq-xadc.h"
  31 #include "hw/ssi/ssi.h"
  32 #include "qemu/error-report.h"
  33 #include "hw/sd/sdhci.h"
  34 #include "hw/char/cadence_uart.h"
  35 #include "hw/net/cadence_gem.h"
  36 #include "hw/cpu/a9mpcore.h"
  37
  38 #define NUM_SPI_FLASHES 4
  39 #define NUM_QSPI_FLASHES 2
  40 #define NUM_QSPI_BUSSES 2
  41
  42 #define FLASH_SIZE (64 * 1024 * 1024)
  43 #define FLASH_SECTOR_SIZE (128 * 1024)
  44
  45 #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
  46
  47 #define MPCORE_PERIPHBASE 0xF8F00000
  48 #define ZYNQ_BOARD_MIDR 0x413FC090
  49
  50 static const int dma_irqs[8] = {
  51     46, 47, 48, 49, 72, 73, 74, 75
  52 };
  53
  54 #define BOARD_SETUP_ADDR        0x100
  55
  56 #define SLCR_LOCK_OFFSET        0x004
  57 #define SLCR_UNLOCK_OFFSET      0x008
  58 #define SLCR_ARM_PLL_OFFSET     0x100
  59
  60 #define SLCR_XILINX_UNLOCK_KEY  0xdf0d
  61 #define SLCR_XILINX_LOCK_KEY    0x767b
  62
  63 #define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080  /* Datasheet: UG585 (v1.12.1) */
  64
  65 #define ARMV7_IMM16(x) (extract32((x),  0, 12) | \
  66                         extract32((x), 12,  4) << 16)
  67
  68 /* Write immediate val to address r0 + addr. r0 should contain base offset
  69  * of the SLCR block. Clobbers r1.
  70  */
  71
  72 #define SLCR_WRITE(addr, val) \
  73     0xe3001000 + ARMV7_IMM16(extract32((val),  0, 16)), /* movw r1 ... */ \
  74     0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \
  75     0xe5801000 + (addr)
  76
  77 static void zynq_write_board_setup(ARMCPU *cpu,
  78                                    const struct arm_boot_info *info)
  79 {
  80     int n;
  81     uint32_t board_setup_blob[] = {
  82         0xe3a004f8, /* mov r0, #0xf8000000 */
  83         SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY),
  84         SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008),
  85         SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY),
  86         0xe12fff1e, /* bx lr */
  87     };
  88     for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) {
  89         board_setup_blob[n] = tswap32(board_setup_blob[n]);
  90     }
  91     rom_add_blob_fixed("board-setup", board_setup_blob,
  92                        sizeof(board_setup_blob), BOARD_SETUP_ADDR);
  93 }
  94
  95 static struct arm_boot_info zynq_binfo = {};
  96
  97 static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
  98 {
  99     DeviceState *dev;
 100     SysBusDevice *s;
 101
 102     dev = qdev_create(NULL, TYPE_CADENCE_GEM);
 103     if (nd->used) {
 104         qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
 105         qdev_set_nic_properties(dev, nd);
 106     }
 107     qdev_init_nofail(dev);
 108     s = SYS_BUS_DEVICE(dev);
 109     sysbus_mmio_map(s, 0, base);
 110     sysbus_connect_irq(s, 0, irq);
 111 }
 112
 113 static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
 114                                          bool is_qspi)
 115 {
 116     DeviceState *dev;
 117     SysBusDevice *busdev;
 118     SSIBus *spi;
 119     DeviceState *flash_dev;
 120     int i, j;
 121     int num_busses =  is_qspi ? NUM_QSPI_BUSSES : 1;
 122     int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;
 123
 124     dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
 125     qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
 126     qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
 127     qdev_prop_set_uint8(dev, "num-busses", num_busses);
 128     qdev_init_nofail(dev);
 129     busdev = SYS_BUS_DEVICE(dev);
 130     sysbus_mmio_map(busdev, 0, base_addr);
 131     if (is_qspi) {
 132         sysbus_mmio_map(busdev, 1, 0xFC000000);
 133     }
 134     sysbus_connect_irq(busdev, 0, irq);
 135
 136     for (i = 0; i < num_busses; ++i) {
 137         char bus_name[16];
 138         qemu_irq cs_line;
 139
 140         snprintf(bus_name, 16, "spi%d", i);
 141         spi = (SSIBus *)qdev_get_child_bus(dev, bus_name);
 142
 143         for (j = 0; j < num_ss; ++j) {
 144             DriveInfo *dinfo = drive_get_next(IF_MTD);
 145             flash_dev = ssi_create_slave_no_init(spi, "n25q128");
 146             if (dinfo) {
 147                 qdev_prop_set_drive(flash_dev, "drive",
 148                                     blk_by_legacy_dinfo(dinfo), &error_fatal);
 149             }
 150             qdev_init_nofail(flash_dev);
 151
 152             cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
 153             sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);
 154         }
 155     }
 156
 157 }
 158
 159 static void zynq_init(MachineState *machine)
 160 {
 161     ram_addr_t ram_size = machine->ram_size;
 162     const char *kernel_filename = machine->kernel_filename;
 163     const char *kernel_cmdline = machine->kernel_cmdline;
 164     const char *initrd_filename = machine->initrd_filename;
 165     ARMCPU *cpu;
 166     MemoryRegion *address_space_mem = get_system_memory();
 167     MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
 168     MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
 169     DeviceState *dev;
 170     SysBusDevice *busdev;
 171     qemu_irq pic[64];
 172     int n;
 173
 174     cpu = ARM_CPU(object_new(machine->cpu_type));
 175
 176     /* By default A9 CPUs have EL3 enabled.  This board does not
 177      * currently support EL3 so the CPU EL3 property is disabled before
 178      * realization.
 179      */
 180     if (object_property_find(OBJECT(cpu), "has_el3", NULL)) {
 181         object_property_set_bool(OBJECT(cpu), false, "has_el3", &error_fatal);
 182     }
 183
 184     object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr",
 185                             &error_fatal);
 186     object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar",
 187                             &error_fatal);
 188     object_property_set_bool(OBJECT(cpu), true, "realized", &error_fatal);
 189
 190     /* max 2GB ram */
 191     if (ram_size > 0x80000000) {
 192         ram_size = 0x80000000;
 193     }
 194
 195     /* DDR remapped to address zero.  */
 196     memory_region_allocate_system_memory(ext_ram, NULL, "zynq.ext_ram",
 197                                          ram_size);
 198     memory_region_add_subregion(address_space_mem, 0, ext_ram);
 199
 200     /* 256K of on-chip memory */
 201     memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 << 10,
 202                            &error_fatal);
 203     memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);
 204
 205     DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
 206
 207     /* AMD */
 208     pflash_cfi02_register(0xe2000000, NULL, "zynq.pflash", FLASH_SIZE,
 209                           dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
 210                           FLASH_SECTOR_SIZE,
 211                           FLASH_SIZE/FLASH_SECTOR_SIZE, 1,
 212                           1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
 213                               0);
 214
 215     dev = qdev_create(NULL, "xilinx,zynq_slcr");
 216     qdev_init_nofail(dev);
 217     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000);
 218
 219     dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
 220     qdev_prop_set_uint32(dev, "num-cpu", 1);
 221     qdev_init_nofail(dev);
 222     busdev = SYS_BUS_DEVICE(dev);
 223     sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
 224     sysbus_connect_irq(busdev, 0,
 225                        qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
 226
 227     for (n = 0; n < 64; n++) {
 228         pic[n] = qdev_get_gpio_in(dev, n);
 229     }
 230
 231     zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false);
 232     zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false);
 233     zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true);
 234
 235     sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]);
 236     sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]);
 237
 238     cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0));
 239     cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1));
 240
 241     sysbus_create_varargs("cadence_ttc", 0xF8001000,
 242             pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
 243     sysbus_create_varargs("cadence_ttc", 0xF8002000,
 244             pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL);
 245
 246     gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]);
 247     gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]);
 248
 249     for (n = 0; n < 2; n++) {
 250         int hci_irq = n ? 79 : 56;
 251         hwaddr hci_addr = n ? 0xE0101000 : 0xE0100000;
 252         DriveInfo *di;
 253         BlockBackend *blk;
 254         DeviceState *carddev;
 255
 256         /* Compatible with:
 257          * - SD Host Controller Specification Version 2.0 Part A2
 258          * - SDIO Specification Version 2.0
 259          * - MMC Specification Version 3.31
 260          */
 261         dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI);
 262         qdev_prop_set_uint8(dev, "sd-spec-version", 2);
 263         qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES);
 264         qdev_init_nofail(dev);
 265         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr);
 266         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]);
 267
 268         di = drive_get_next(IF_SD);
 269         blk = di ? blk_by_legacy_dinfo(di) : NULL;
 270         carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
 271         qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
 272         object_property_set_bool(OBJECT(carddev), true, "realized",
 273                                  &error_fatal);
 274     }
 275
 276     dev = qdev_create(NULL, TYPE_ZYNQ_XADC);
 277     qdev_init_nofail(dev);
 278     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100);
 279     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]);
 280
 281     dev = qdev_create(NULL, "pl330");
 282     qdev_prop_set_uint8(dev, "num_chnls",  8);
 283     qdev_prop_set_uint8(dev, "num_periph_req",  4);
 284     qdev_prop_set_uint8(dev, "num_events",  16);
 285
 286     qdev_prop_set_uint8(dev, "data_width",  64);
 287     qdev_prop_set_uint8(dev, "wr_cap",  8);
 288     qdev_prop_set_uint8(dev, "wr_q_dep",  16);
 289     qdev_prop_set_uint8(dev, "rd_cap",  8);
 290     qdev_prop_set_uint8(dev, "rd_q_dep",  16);
 291     qdev_prop_set_uint16(dev, "data_buffer_dep",  256);
 292
 293     qdev_init_nofail(dev);
 294     busdev = SYS_BUS_DEVICE(dev);
 295     sysbus_mmio_map(busdev, 0, 0xF8003000);
 296     sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */
 297     for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) { /* event irqs */
 298         sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
 299     }
 300
 301     dev = qdev_create(NULL, "xlnx.ps7-dev-cfg");
 302     qdev_init_nofail(dev);
 303     busdev = SYS_BUS_DEVICE(dev);
 304     sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]);
 305     sysbus_mmio_map(busdev, 0, 0xF8007000);
 306
 307     zynq_binfo.ram_size = ram_size;
 308     zynq_binfo.kernel_filename = kernel_filename;
 309     zynq_binfo.kernel_cmdline = kernel_cmdline;
 310     zynq_binfo.initrd_filename = initrd_filename;
 311     zynq_binfo.nb_cpus = 1;
 312     zynq_binfo.board_id = 0xd32;
 313     zynq_binfo.loader_start = 0;
 314     zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR;
 315     zynq_binfo.write_board_setup = zynq_write_board_setup;
 316
 317     arm_load_kernel(ARM_CPU(first_cpu), &zynq_binfo);
 318 }
 319
 320 static void zynq_machine_init(MachineClass *mc)
 321 {
 322     mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
 323     mc->init = zynq_init;
 324     mc->max_cpus = 1;
 325     mc->no_sdcard = 1;
 326     mc->ignore_memory_transaction_failures = true;
 327     mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
 328 }
 329
 330 DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init)