tcg/tcg-opc.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 /*
  26  * DEF(name, oargs, iargs, cargs, flags)
  27  */
  28
  29 /* predefined ops */
  30 DEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT)
  31 DEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT)
  32
  33 /* variable number of parameters */
  34 DEF(call, 0, 0, 3, TCG_OPF_CALL_CLOBBER | TCG_OPF_NOT_PRESENT)
  35
  36 DEF(br, 0, 0, 1, TCG_OPF_BB_END)
  37
  38 #define IMPL(X) (__builtin_constant_p(X) && !(X) ? TCG_OPF_NOT_PRESENT : 0)
  39 #if TCG_TARGET_REG_BITS == 32
  40 # define IMPL64  TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT
  41 #else
  42 # define IMPL64  TCG_OPF_64BIT
  43 #endif
  44
  45 DEF(mb, 0, 0, 1, 0)
  46
  47 DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT)
  48 DEF(movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT)
  49 DEF(setcond_i32, 1, 2, 1, 0)
  50 DEF(movcond_i32, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32))
  51 /* load/store */
  52 DEF(ld8u_i32, 1, 1, 1, 0)
  53 DEF(ld8s_i32, 1, 1, 1, 0)
  54 DEF(ld16u_i32, 1, 1, 1, 0)
  55 DEF(ld16s_i32, 1, 1, 1, 0)
  56 DEF(ld_i32, 1, 1, 1, 0)
  57 DEF(st8_i32, 0, 2, 1, 0)
  58 DEF(st16_i32, 0, 2, 1, 0)
  59 DEF(st_i32, 0, 2, 1, 0)
  60 /* arith */
  61 DEF(add_i32, 1, 2, 0, 0)
  62 DEF(sub_i32, 1, 2, 0, 0)
  63 DEF(mul_i32, 1, 2, 0, 0)
  64 DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
  65 DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
  66 DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
  67 DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
  68 DEF(div2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
  69 DEF(divu2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
  70 DEF(and_i32, 1, 2, 0, 0)
  71 DEF(or_i32, 1, 2, 0, 0)
  72 DEF(xor_i32, 1, 2, 0, 0)
  73 /* shifts/rotates */
  74 DEF(shl_i32, 1, 2, 0, 0)
  75 DEF(shr_i32, 1, 2, 0, 0)
  76 DEF(sar_i32, 1, 2, 0, 0)
  77 DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
  78 DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
  79 DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32))
  80 DEF(extract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_extract_i32))
  81 DEF(sextract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_sextract_i32))
  82
  83 DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END)
  84
  85 DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2_i32))
  86 DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2_i32))
  87 DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_mulu2_i32))
  88 DEF(muls2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_muls2_i32))
  89 DEF(muluh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i32))
  90 DEF(mulsh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i32))
  91 DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | IMPL(TCG_TARGET_REG_BITS == 32))
  92 DEF(setcond2_i32, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS == 32))
  93
  94 DEF(ext8s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32))
  95 DEF(ext16s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16s_i32))
  96 DEF(ext8u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8u_i32))
  97 DEF(ext16u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16u_i32))
  98 DEF(bswap16_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap16_i32))
  99 DEF(bswap32_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap32_i32))
 100 DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32))
 101 DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32))
 102 DEF(andc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_i32))
 103 DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32))
 104 DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32))
 105 DEF(nand_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nand_i32))
 106 DEF(nor_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nor_i32))
 107 DEF(clz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_clz_i32))
 108 DEF(ctz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_ctz_i32))
 109 DEF(ctpop_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ctpop_i32))
 110
 111 DEF(mov_i64, 1, 1, 0, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT)
 112 DEF(movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT)
 113 DEF(setcond_i64, 1, 2, 1, IMPL64)
 114 DEF(movcond_i64, 1, 4, 1, IMPL64 | IMPL(TCG_TARGET_HAS_movcond_i64))
 115 /* load/store */
 116 DEF(ld8u_i64, 1, 1, 1, IMPL64)
 117 DEF(ld8s_i64, 1, 1, 1, IMPL64)
 118 DEF(ld16u_i64, 1, 1, 1, IMPL64)
 119 DEF(ld16s_i64, 1, 1, 1, IMPL64)
 120 DEF(ld32u_i64, 1, 1, 1, IMPL64)
 121 DEF(ld32s_i64, 1, 1, 1, IMPL64)
 122 DEF(ld_i64, 1, 1, 1, IMPL64)
 123 DEF(st8_i64, 0, 2, 1, IMPL64)
 124 DEF(st16_i64, 0, 2, 1, IMPL64)
 125 DEF(st32_i64, 0, 2, 1, IMPL64)
 126 DEF(st_i64, 0, 2, 1, IMPL64)
 127 /* arith */
 128 DEF(add_i64, 1, 2, 0, IMPL64)
 129 DEF(sub_i64, 1, 2, 0, IMPL64)
 130 DEF(mul_i64, 1, 2, 0, IMPL64)
 131 DEF(div_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
 132 DEF(divu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
 133 DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
 134 DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
 135 DEF(div2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
 136 DEF(divu2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
 137 DEF(and_i64, 1, 2, 0, IMPL64)
 138 DEF(or_i64, 1, 2, 0, IMPL64)
 139 DEF(xor_i64, 1, 2, 0, IMPL64)
 140 /* shifts/rotates */
 141 DEF(shl_i64, 1, 2, 0, IMPL64)
 142 DEF(shr_i64, 1, 2, 0, IMPL64)
 143 DEF(sar_i64, 1, 2, 0, IMPL64)
 144 DEF(rotl_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
 145 DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
 146 DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64))
 147 DEF(extract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_extract_i64))
 148 DEF(sextract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_sextract_i64))
 149
 150 /* size changing ops */
 151 DEF(ext_i32_i64, 1, 1, 0, IMPL64)
 152 DEF(extu_i32_i64, 1, 1, 0, IMPL64)
 153 DEF(extrl_i64_i32, 1, 1, 0,
 154     IMPL(TCG_TARGET_HAS_extrl_i64_i32)
 155     | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0))
 156 DEF(extrh_i64_i32, 1, 1, 0,
 157     IMPL(TCG_TARGET_HAS_extrh_i64_i32)
 158     | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0))
 159
 160 DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | IMPL64)
 161 DEF(ext8s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8s_i64))
 162 DEF(ext16s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16s_i64))
 163 DEF(ext32s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32s_i64))
 164 DEF(ext8u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8u_i64))
 165 DEF(ext16u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16u_i64))
 166 DEF(ext32u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32u_i64))
 167 DEF(bswap16_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap16_i64))
 168 DEF(bswap32_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap32_i64))
 169 DEF(bswap64_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap64_i64))
 170 DEF(not_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_not_i64))
 171 DEF(neg_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_neg_i64))
 172 DEF(andc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_andc_i64))
 173 DEF(orc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_orc_i64))
 174 DEF(eqv_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_eqv_i64))
 175 DEF(nand_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nand_i64))
 176 DEF(nor_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nor_i64))
 177 DEF(clz_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_clz_i64))
 178 DEF(ctz_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ctz_i64))
 179 DEF(ctpop_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ctpop_i64))
 180
 181 DEF(add2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_add2_i64))
 182 DEF(sub2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_sub2_i64))
 183 DEF(mulu2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulu2_i64))
 184 DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2_i64))
 185 DEF(muluh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i64))
 186 DEF(mulsh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i64))
 187
 188 #define TLADDR_ARGS  (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? 1 : 2)
 189 #define DATA64_ARGS  (TCG_TARGET_REG_BITS == 64 ? 1 : 2)
 190
 191 /* QEMU specific */
 192 DEF(insn_start, 0, 0, TLADDR_ARGS * TARGET_INSN_START_WORDS,
 193     TCG_OPF_NOT_PRESENT)
 194 DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END)
 195 DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END)
 196
 197 DEF(qemu_ld_i32, 1, TLADDR_ARGS, 1,
 198     TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 199 DEF(qemu_st_i32, 0, TLADDR_ARGS + 1, 1,
 200     TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 201 DEF(qemu_ld_i64, DATA64_ARGS, TLADDR_ARGS, 1,
 202     TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
 203 DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1,
 204     TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
 205
 206 #undef TLADDR_ARGS
 207 #undef DATA64_ARGS
 208 #undef IMPL
 209 #undef IMPL64
 210 #undef DEF