include/hw/arm/exynos4210.h

   1 /*
   2  *  Samsung exynos4210 SoC emulation
   3  *
   4  *  Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
   5  *    Maksim Kozlov <m.kozlov@samsung.com>
   6  *    Evgeny Voevodin <e.voevodin@samsung.com>
   7  *    Igor Mitsyanko <i.mitsyanko@samsung.com>
   8  *
   9  *
  10  *  This program is free software; you can redistribute it and/or modify it
  11  *  under the terms of the GNU General Public License as published by the
  12  *  Free Software Foundation; either version 2 of the License, or
  13  *  (at your option) any later version.
  14  *
  15  *  This program is distributed in the hope that it will be useful, but WITHOUT
  16  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  18  *  for more details.
  19  *
  20  *  You should have received a copy of the GNU General Public License along
  21  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  22  */
  23
  24 #ifndef EXYNOS4210_H
  25 #define EXYNOS4210_H
  26
  27 #include "hw/or-irq.h"
  28 #include "hw/sysbus.h"
  29 #include "hw/cpu/a9mpcore.h"
  30 #include "hw/intc/exynos4210_gic.h"
  31 #include "hw/core/split-irq.h"
  32 #include "target/arm/cpu-qom.h"
  33 #include "qom/object.h"
  34
  35 #define EXYNOS4210_NCPUS                    2
  36
  37 #define EXYNOS4210_DRAM0_BASE_ADDR          0x40000000
  38 #define EXYNOS4210_DRAM1_BASE_ADDR          0xa0000000
  39 #define EXYNOS4210_DRAM_MAX_SIZE            0x60000000  /* 1.5 GB */
  40
  41 #define EXYNOS4210_IROM_BASE_ADDR           0x00000000
  42 #define EXYNOS4210_IROM_SIZE                0x00010000  /* 64 KB */
  43 #define EXYNOS4210_IROM_MIRROR_BASE_ADDR    0x02000000
  44 #define EXYNOS4210_IROM_MIRROR_SIZE         0x00010000  /* 64 KB */
  45
  46 #define EXYNOS4210_IRAM_BASE_ADDR           0x02020000
  47 #define EXYNOS4210_IRAM_SIZE                0x00020000  /* 128 KB */
  48
  49 /* Secondary CPU startup code is in IROM memory */
  50 #define EXYNOS4210_SMP_BOOT_ADDR            EXYNOS4210_IROM_BASE_ADDR
  51 #define EXYNOS4210_SMP_BOOT_SIZE            0x1000
  52 #define EXYNOS4210_BASE_BOOT_ADDR           EXYNOS4210_DRAM0_BASE_ADDR
  53 /* Secondary CPU polling address to get loader start from */
  54 #define EXYNOS4210_SECOND_CPU_BOOTREG       0x10020814
  55
  56 #define EXYNOS4210_SMP_PRIVATE_BASE_ADDR    0x10500000
  57 #define EXYNOS4210_L2X0_BASE_ADDR           0x10502000
  58
  59 /*
  60  * exynos4210 IRQ subsystem stub definitions.
  61  */
  62 #define EXYNOS4210_IRQ_GATE_NINPUTS 2 /* Internal and External GIC */
  63
  64 #define EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ  64
  65 #define EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ  16
  66 #define EXYNOS4210_MAX_INT_COMBINER_IN_IRQ   \
  67     (EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ * 8)
  68 #define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ   \
  69     (EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8)
  70
  71 #define EXYNOS4210_I2C_NUMBER               9
  72
  73 #define EXYNOS4210_NUM_DMA      3
  74
  75 /*
  76  * We need one splitter for every external combiner input, plus
  77  * one for every non-zero entry in combiner_grp_to_gic_id[].
  78  * We'll assert in exynos4210_init_board_irqs() if this is wrong.
  79  */
  80 #define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 54)
  81
  82 typedef struct Exynos4210Irq {
  83     qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
  84     qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
  85 } Exynos4210Irq;
  86
  87 struct Exynos4210State {
  88     /*< private >*/
  89     SysBusDevice parent_obj;
  90     /*< public >*/
  91     ARMCPU *cpu[EXYNOS4210_NCPUS];
  92     Exynos4210Irq irqs;
  93     qemu_irq irq_table[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
  94
  95     MemoryRegion chipid_mem;
  96     MemoryRegion iram_mem;
  97     MemoryRegion irom_mem;
  98     MemoryRegion irom_alias_mem;
  99     MemoryRegion boot_secondary;
 100     MemoryRegion bootreg_mem;
 101     I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
 102     qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
 103     qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
 104     A9MPPrivState a9mpcore;
 105     Exynos4210GicState ext_gic;
 106     SplitIRQ splitter[EXYNOS4210_NUM_SPLITTERS];
 107 };
 108
 109 #define TYPE_EXYNOS4210_SOC "exynos4210"
 110 OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210_SOC)
 111
 112 void exynos4210_write_secondary(ARMCPU *cpu,
 113         const struct arm_boot_info *info);
 114
 115 /* Get IRQ number from exynos4210 IRQ subsystem stub.
 116  * To identify IRQ source use internal combiner group and bit number
 117  *  grp - group number
 118  *  bit - bit number inside group */
 119 uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit);
 120
 121 /*
 122  * exynos4210 UART
 123  */
 124 DeviceState *exynos4210_uart_create(hwaddr addr,
 125                                     int fifo_size,
 126                                     int channel,
 127                                     Chardev *chr,
 128                                     qemu_irq irq);
 129
 130 #endif /* EXYNOS4210_H */