target/xtensa/overlay_tool.h

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #define XTREG(idx, ofs, bi, sz, al, no, fl, cp, typ, grp, name, \
  29               a1, a2, a3, a4, a5, a6) { \
  30     .targno = (no), \
  31     .flags = (fl), \
  32     .type = (typ), \
  33     .group = (grp), \
  34     .size = (sz), \
  35 },
  36 #define XTREG_END { .targno = -1 },
  37
  38 #ifndef XCHAL_HAVE_DEPBITS
  39 #define XCHAL_HAVE_DEPBITS 0
  40 #endif
  41
  42 #ifndef XCHAL_HAVE_DIV32
  43 #define XCHAL_HAVE_DIV32 0
  44 #endif
  45
  46 #ifndef XCHAL_UNALIGNED_LOAD_HW
  47 #define XCHAL_UNALIGNED_LOAD_HW 0
  48 #endif
  49
  50 #ifndef XCHAL_HAVE_VECBASE
  51 #define XCHAL_HAVE_VECBASE 0
  52 #define XCHAL_VECBASE_RESET_VADDR 0
  53 #endif
  54
  55 #ifndef XCHAL_RESET_VECTOR0_VADDR
  56 #define XCHAL_RESET_VECTOR0_VADDR XCHAL_RESET_VECTOR_VADDR
  57 #endif
  58
  59 #ifndef XCHAL_RESET_VECTOR1_VADDR
  60 #define XCHAL_RESET_VECTOR1_VADDR XCHAL_RESET_VECTOR_VADDR
  61 #endif
  62
  63 #ifndef XCHAL_HW_MIN_VERSION
  64 #define XCHAL_HW_MIN_VERSION 0
  65 #endif
  66
  67 #ifndef XCHAL_LOOP_BUFFER_SIZE
  68 #define XCHAL_LOOP_BUFFER_SIZE 0
  69 #endif
  70
  71 #ifndef XCHAL_HAVE_EXTERN_REGS
  72 #define XCHAL_HAVE_EXTERN_REGS 0
  73 #endif
  74
  75 #ifndef XCHAL_HAVE_MPU
  76 #define XCHAL_HAVE_MPU 0
  77 #endif
  78
  79 #define XCHAL_OPTION(xchal, qemu) ((xchal) ? XTENSA_OPTION_BIT(qemu) : 0)
  80
  81 #define XTENSA_OPTIONS ( \
  82     XCHAL_OPTION(XCHAL_HAVE_DENSITY, XTENSA_OPTION_CODE_DENSITY) | \
  83     XCHAL_OPTION(XCHAL_HAVE_LOOPS, XTENSA_OPTION_LOOP) | \
  84     XCHAL_OPTION(XCHAL_HAVE_ABSOLUTE_LITERALS, XTENSA_OPTION_EXTENDED_L32R) | \
  85     XCHAL_OPTION(XCHAL_HAVE_MUL16, XTENSA_OPTION_16_BIT_IMUL) | \
  86     XCHAL_OPTION(XCHAL_HAVE_MUL32, XTENSA_OPTION_32_BIT_IMUL) | \
  87     XCHAL_OPTION(XCHAL_HAVE_MUL32_HIGH, XTENSA_OPTION_32_BIT_IMUL_HIGH) | \
  88     XCHAL_OPTION(XCHAL_HAVE_DIV32, XTENSA_OPTION_32_BIT_IDIV) | \
  89     XCHAL_OPTION(XCHAL_HAVE_MAC16, XTENSA_OPTION_MAC16) | \
  90     XCHAL_OPTION(XCHAL_HAVE_NSA, XTENSA_OPTION_MISC_OP_NSA) | \
  91     XCHAL_OPTION(XCHAL_HAVE_MINMAX, XTENSA_OPTION_MISC_OP_MINMAX) | \
  92     XCHAL_OPTION(XCHAL_HAVE_SEXT, XTENSA_OPTION_MISC_OP_SEXT) | \
  93     XCHAL_OPTION(XCHAL_HAVE_CLAMPS, XTENSA_OPTION_MISC_OP_CLAMPS) | \
  94     XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) | \
  95     XCHAL_OPTION(XCHAL_HAVE_BOOLEANS, XTENSA_OPTION_BOOLEAN) | \
  96     XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \
  97     XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \
  98     XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
  99     XCHAL_OPTION(XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >= 230000, \
 100         XTENSA_OPTION_ATOMCTL) | \
 101     XCHAL_OPTION(XCHAL_HAVE_DEPBITS, XTENSA_OPTION_DEPBITS) | \
 102     /* Interrupts and exceptions */ \
 103     XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) | \
 104     XCHAL_OPTION(XCHAL_HAVE_VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR) | \
 105     XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_EXCEPTION, \
 106         XTENSA_OPTION_UNALIGNED_EXCEPTION) | \
 107     XCHAL_OPTION(XCHAL_HAVE_INTERRUPTS, XTENSA_OPTION_INTERRUPT) | \
 108     XCHAL_OPTION(XCHAL_HAVE_HIGHPRI_INTERRUPTS, \
 109         XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT) | \
 110     XCHAL_OPTION(XCHAL_HAVE_CCOUNT, XTENSA_OPTION_TIMER_INTERRUPT) | \
 111     /* Local memory, TODO */ \
 112     XCHAL_OPTION(XCHAL_ICACHE_SIZE, XTENSA_OPTION_ICACHE) | \
 113     XCHAL_OPTION(XCHAL_ICACHE_LINE_LOCKABLE, \
 114             XTENSA_OPTION_ICACHE_INDEX_LOCK) | \
 115     XCHAL_OPTION(XCHAL_DCACHE_SIZE, XTENSA_OPTION_DCACHE) | \
 116     XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \
 117             XTENSA_OPTION_DCACHE_INDEX_LOCK) | \
 118     XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \
 119     XCHAL_OPTION(XCHAL_HAVE_MEM_ECC_PARITY, \
 120                  XTENSA_OPTION_MEMORY_ECC_PARITY) | \
 121     /* Memory protection and translation */ \
 122     XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \
 123             XTENSA_OPTION_REGION_PROTECTION) | \
 124     XCHAL_OPTION(XCHAL_HAVE_XLT_CACHEATTR, \
 125             XTENSA_OPTION_REGION_TRANSLATION) | \
 126     XCHAL_OPTION(XCHAL_HAVE_MPU, XTENSA_OPTION_MPU) | \
 127     XCHAL_OPTION(XCHAL_HAVE_PTP_MMU, XTENSA_OPTION_MMU) | \
 128     XCHAL_OPTION(XCHAL_HAVE_CACHEATTR, XTENSA_OPTION_CACHEATTR) | \
 129     /* Other, TODO */ \
 130     XCHAL_OPTION(XCHAL_HAVE_WINDOWED, XTENSA_OPTION_WINDOWED_REGISTER) | \
 131     XCHAL_OPTION(XCHAL_HAVE_DEBUG, XTENSA_OPTION_DEBUG) |\
 132     XCHAL_OPTION(XCHAL_NUM_MISC_REGS > 0, XTENSA_OPTION_MISC_SR) | \
 133     XCHAL_OPTION(XCHAL_HAVE_THREADPTR, XTENSA_OPTION_THREAD_POINTER) | \
 134     XCHAL_OPTION(XCHAL_HAVE_PRID, XTENSA_OPTION_PROCESSOR_ID) | \
 135     XCHAL_OPTION(XCHAL_HAVE_EXTERN_REGS, XTENSA_OPTION_EXTERN_REGS))
 136
 137 #ifndef XCHAL_WINDOW_OF4_VECOFS
 138 #define XCHAL_WINDOW_OF4_VECOFS         0x00000000
 139 #define XCHAL_WINDOW_UF4_VECOFS         0x00000040
 140 #define XCHAL_WINDOW_OF8_VECOFS         0x00000080
 141 #define XCHAL_WINDOW_UF8_VECOFS         0x000000C0
 142 #define XCHAL_WINDOW_OF12_VECOFS        0x00000100
 143 #define XCHAL_WINDOW_UF12_VECOFS        0x00000140
 144 #endif
 145
 146 #if XCHAL_HAVE_WINDOWED
 147 #define WINDOW_VECTORS \
 148    [EXC_WINDOW_OVERFLOW4] = XCHAL_WINDOW_OF4_VECOFS + \
 149        XCHAL_WINDOW_VECTORS_VADDR, \
 150    [EXC_WINDOW_UNDERFLOW4] = XCHAL_WINDOW_UF4_VECOFS + \
 151        XCHAL_WINDOW_VECTORS_VADDR, \
 152    [EXC_WINDOW_OVERFLOW8] = XCHAL_WINDOW_OF8_VECOFS + \
 153        XCHAL_WINDOW_VECTORS_VADDR, \
 154    [EXC_WINDOW_UNDERFLOW8] = XCHAL_WINDOW_UF8_VECOFS + \
 155        XCHAL_WINDOW_VECTORS_VADDR, \
 156    [EXC_WINDOW_OVERFLOW12] = XCHAL_WINDOW_OF12_VECOFS + \
 157        XCHAL_WINDOW_VECTORS_VADDR, \
 158    [EXC_WINDOW_UNDERFLOW12] = XCHAL_WINDOW_UF12_VECOFS + \
 159        XCHAL_WINDOW_VECTORS_VADDR,
 160 #else
 161 #define WINDOW_VECTORS
 162 #endif
 163
 164 #define EXCEPTION_VECTORS { \
 165         [EXC_RESET0] = XCHAL_RESET_VECTOR0_VADDR, \
 166         [EXC_RESET1] = XCHAL_RESET_VECTOR1_VADDR, \
 167         WINDOW_VECTORS \
 168         [EXC_KERNEL] = XCHAL_KERNEL_VECTOR_VADDR, \
 169         [EXC_USER] = XCHAL_USER_VECTOR_VADDR, \
 170         [EXC_DOUBLE] = XCHAL_DOUBLEEXC_VECTOR_VADDR, \
 171         [EXC_DEBUG] = XCHAL_DEBUG_VECTOR_VADDR, \
 172     }
 173
 174 #define INTERRUPT_VECTORS { \
 175         0, \
 176         0, \
 177         XCHAL_INTLEVEL2_VECTOR_VADDR, \
 178         XCHAL_INTLEVEL3_VECTOR_VADDR, \
 179         XCHAL_INTLEVEL4_VECTOR_VADDR, \
 180         XCHAL_INTLEVEL5_VECTOR_VADDR, \
 181         XCHAL_INTLEVEL6_VECTOR_VADDR, \
 182         XCHAL_INTLEVEL7_VECTOR_VADDR, \
 183     }
 184
 185 #define LEVEL_MASKS { \
 186         [1] = XCHAL_INTLEVEL1_MASK, \
 187         [2] = XCHAL_INTLEVEL2_MASK, \
 188         [3] = XCHAL_INTLEVEL3_MASK, \
 189         [4] = XCHAL_INTLEVEL4_MASK, \
 190         [5] = XCHAL_INTLEVEL5_MASK, \
 191         [6] = XCHAL_INTLEVEL6_MASK, \
 192         [7] = XCHAL_INTLEVEL7_MASK, \
 193     }
 194
 195 #define INTTYPE_MASKS { \
 196         [INTTYPE_EDGE] = XCHAL_INTTYPE_MASK_EXTERN_EDGE, \
 197         [INTTYPE_NMI] = XCHAL_INTTYPE_MASK_NMI, \
 198         [INTTYPE_SOFTWARE] = XCHAL_INTTYPE_MASK_SOFTWARE, \
 199     }
 200
 201 #define XTHAL_INTTYPE_EXTERN_LEVEL INTTYPE_LEVEL
 202 #define XTHAL_INTTYPE_EXTERN_EDGE INTTYPE_EDGE
 203 #define XTHAL_INTTYPE_NMI INTTYPE_NMI
 204 #define XTHAL_INTTYPE_SOFTWARE INTTYPE_SOFTWARE
 205 #define XTHAL_INTTYPE_TIMER INTTYPE_TIMER
 206 #define XTHAL_INTTYPE_TBD1 INTTYPE_DEBUG
 207 #define XTHAL_INTTYPE_TBD2 INTTYPE_WRITE_ERR
 208 #define XTHAL_INTTYPE_WRITE_ERROR INTTYPE_WRITE_ERR
 209 #define XTHAL_INTTYPE_PROFILING INTTYPE_PROFILING
 210 #define XTHAL_INTTYPE_IDMA_DONE INTTYPE_IDMA_DONE
 211 #define XTHAL_INTTYPE_IDMA_ERR INTTYPE_IDMA_ERR
 212 #define XTHAL_INTTYPE_GS_ERR INTTYPE_GS_ERR
 213
 214
 215 #define INTERRUPT(i) { \
 216         .level = XCHAL_INT ## i ## _LEVEL, \
 217         .inttype = XCHAL_INT ## i ## _TYPE, \
 218     }
 219
 220 #define INTERRUPTS { \
 221         [0] = INTERRUPT(0), \
 222         [1] = INTERRUPT(1), \
 223         [2] = INTERRUPT(2), \
 224         [3] = INTERRUPT(3), \
 225         [4] = INTERRUPT(4), \
 226         [5] = INTERRUPT(5), \
 227         [6] = INTERRUPT(6), \
 228         [7] = INTERRUPT(7), \
 229         [8] = INTERRUPT(8), \
 230         [9] = INTERRUPT(9), \
 231         [10] = INTERRUPT(10), \
 232         [11] = INTERRUPT(11), \
 233         [12] = INTERRUPT(12), \
 234         [13] = INTERRUPT(13), \
 235         [14] = INTERRUPT(14), \
 236         [15] = INTERRUPT(15), \
 237         [16] = INTERRUPT(16), \
 238         [17] = INTERRUPT(17), \
 239         [18] = INTERRUPT(18), \
 240         [19] = INTERRUPT(19), \
 241         [20] = INTERRUPT(20), \
 242         [21] = INTERRUPT(21), \
 243         [22] = INTERRUPT(22), \
 244         [23] = INTERRUPT(23), \
 245         [24] = INTERRUPT(24), \
 246         [25] = INTERRUPT(25), \
 247         [26] = INTERRUPT(26), \
 248         [27] = INTERRUPT(27), \
 249         [28] = INTERRUPT(28), \
 250         [29] = INTERRUPT(29), \
 251         [30] = INTERRUPT(30), \
 252         [31] = INTERRUPT(31), \
 253     }
 254
 255 #define TIMERINTS { \
 256         [0] = XCHAL_TIMER0_INTERRUPT, \
 257         [1] = XCHAL_TIMER1_INTERRUPT, \
 258         [2] = XCHAL_TIMER2_INTERRUPT, \
 259     }
 260
 261 #define EXTINTS { \
 262         [0] = XCHAL_EXTINT0_NUM, \
 263         [1] = XCHAL_EXTINT1_NUM, \
 264         [2] = XCHAL_EXTINT2_NUM, \
 265         [3] = XCHAL_EXTINT3_NUM, \
 266         [4] = XCHAL_EXTINT4_NUM, \
 267         [5] = XCHAL_EXTINT5_NUM, \
 268         [6] = XCHAL_EXTINT6_NUM, \
 269         [7] = XCHAL_EXTINT7_NUM, \
 270         [8] = XCHAL_EXTINT8_NUM, \
 271         [9] = XCHAL_EXTINT9_NUM, \
 272         [10] = XCHAL_EXTINT10_NUM, \
 273         [11] = XCHAL_EXTINT11_NUM, \
 274         [12] = XCHAL_EXTINT12_NUM, \
 275         [13] = XCHAL_EXTINT13_NUM, \
 276         [14] = XCHAL_EXTINT14_NUM, \
 277         [15] = XCHAL_EXTINT15_NUM, \
 278         [16] = XCHAL_EXTINT16_NUM, \
 279         [17] = XCHAL_EXTINT17_NUM, \
 280         [18] = XCHAL_EXTINT18_NUM, \
 281         [19] = XCHAL_EXTINT19_NUM, \
 282         [20] = XCHAL_EXTINT20_NUM, \
 283         [21] = XCHAL_EXTINT21_NUM, \
 284         [22] = XCHAL_EXTINT22_NUM, \
 285         [23] = XCHAL_EXTINT23_NUM, \
 286         [24] = XCHAL_EXTINT24_NUM, \
 287         [25] = XCHAL_EXTINT25_NUM, \
 288         [26] = XCHAL_EXTINT26_NUM, \
 289         [27] = XCHAL_EXTINT27_NUM, \
 290         [28] = XCHAL_EXTINT28_NUM, \
 291         [29] = XCHAL_EXTINT29_NUM, \
 292         [30] = XCHAL_EXTINT30_NUM, \
 293         [31] = XCHAL_EXTINT31_NUM, \
 294     }
 295
 296 #define EXCEPTIONS_SECTION \
 297     .excm_level = XCHAL_EXCM_LEVEL, \
 298     .vecbase = XCHAL_VECBASE_RESET_VADDR, \
 299     .exception_vector = EXCEPTION_VECTORS
 300
 301 #define INTERRUPTS_SECTION \
 302     .ninterrupt = XCHAL_NUM_INTERRUPTS, \
 303     .nlevel = XCHAL_NUM_INTLEVELS, \
 304     .interrupt_vector = INTERRUPT_VECTORS, \
 305     .level_mask = LEVEL_MASKS, \
 306     .inttype_mask = INTTYPE_MASKS, \
 307     .interrupt = INTERRUPTS, \
 308     .nccompare = XCHAL_NUM_TIMERS, \
 309     .timerint = TIMERINTS, \
 310     .nextint = XCHAL_NUM_EXTINTERRUPTS, \
 311     .extint = EXTINTS
 312
 313 #if XCHAL_HAVE_PTP_MMU
 314
 315 #define TLB_TEMPLATE(ways, refill_way_size, way56) { \
 316         .nways = ways, \
 317         .way_size = { \
 318             (refill_way_size), (refill_way_size), \
 319             (refill_way_size), (refill_way_size), \
 320             4, (way56) ? 4 : 2, (way56) ? 8 : 2, 1, 1, 1, \
 321         }, \
 322         .varway56 = (way56), \
 323         .nrefillentries = (refill_way_size) * 4, \
 324     }
 325
 326 #define ITLB(varway56) \
 327     TLB_TEMPLATE(7, 1 << XCHAL_ITLB_ARF_ENTRIES_LOG2, varway56)
 328
 329 #define DTLB(varway56) \
 330     TLB_TEMPLATE(10, 1 << XCHAL_DTLB_ARF_ENTRIES_LOG2, varway56)
 331
 332 #define TLB_SECTION \
 333     .itlb = ITLB(XCHAL_HAVE_SPANNING_WAY), \
 334     .dtlb = DTLB(XCHAL_HAVE_SPANNING_WAY)
 335
 336 #ifndef XCHAL_SYSROM0_PADDR
 337 #define XCHAL_SYSROM0_PADDR 0xfe000000
 338 #define XCHAL_SYSROM0_SIZE  0x02000000
 339 #endif
 340
 341 #ifndef XCHAL_SYSRAM0_PADDR
 342 #define XCHAL_SYSRAM0_PADDR 0x00000000
 343 #define XCHAL_SYSRAM0_SIZE  0x08000000
 344 #endif
 345
 346 #elif XCHAL_HAVE_XLT_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR
 347
 348 #define TLB_TEMPLATE { \
 349         .nways = 1, \
 350         .way_size = { \
 351             8, \
 352         } \
 353     }
 354
 355 #define TLB_SECTION \
 356     .itlb = TLB_TEMPLATE, \
 357     .dtlb = TLB_TEMPLATE
 358
 359 #ifndef XCHAL_SYSROM0_PADDR
 360 #define XCHAL_SYSROM0_PADDR 0x50000000
 361 #define XCHAL_SYSROM0_SIZE  0x04000000
 362 #endif
 363
 364 #ifndef XCHAL_SYSRAM0_PADDR
 365 #define XCHAL_SYSRAM0_PADDR 0x60000000
 366 #define XCHAL_SYSRAM0_SIZE  0x04000000
 367 #endif
 368
 369 #elif XCHAL_HAVE_MPU
 370
 371 #ifndef XTENSA_MPU_BG_MAP
 372 #define XTENSA_MPU_BG_MAP (xtensa_mpu_entry []){\
 373     { .vaddr = 0, .attr = 0x00006700, }, \
 374 }
 375 #endif
 376
 377 #define TLB_SECTION \
 378     .mpu_align = XCHAL_MPU_ALIGN, \
 379     .n_mpu_fg_segments = XCHAL_MPU_ENTRIES, \
 380     .n_mpu_bg_segments = 1, \
 381     .mpu_bg = XTENSA_MPU_BG_MAP
 382
 383 #ifndef XCHAL_SYSROM0_PADDR
 384 #define XCHAL_SYSROM0_PADDR 0x50000000
 385 #define XCHAL_SYSROM0_SIZE  0x04000000
 386 #endif
 387
 388 #ifndef XCHAL_SYSRAM0_PADDR
 389 #define XCHAL_SYSRAM0_PADDR 0x60000000
 390 #define XCHAL_SYSRAM0_SIZE  0x04000000
 391 #endif
 392
 393 #else
 394
 395 #ifndef XCHAL_SYSROM0_PADDR
 396 #define XCHAL_SYSROM0_PADDR 0x50000000
 397 #define XCHAL_SYSROM0_SIZE  0x04000000
 398 #endif
 399
 400 #ifndef XCHAL_SYSRAM0_PADDR
 401 #define XCHAL_SYSRAM0_PADDR 0x60000000
 402 #define XCHAL_SYSRAM0_SIZE  0x04000000
 403 #endif
 404
 405 #endif
 406
 407 #if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0)
 408 #define REGISTER_CORE(core) \
 409     static void __attribute__((constructor)) register_core(void) \
 410     { \
 411         static XtensaConfigList node = { \
 412             .config = &core, \
 413         }; \
 414         xtensa_register_core(&node); \
 415     }
 416 #else
 417 #define REGISTER_CORE(core)
 418 #endif
 419
 420 #define DEBUG_SECTION \
 421     .debug_level = XCHAL_DEBUGLEVEL, \
 422     .nibreak = XCHAL_NUM_IBREAK, \
 423     .ndbreak = XCHAL_NUM_DBREAK
 424
 425 #define CACHE_SECTION \
 426     .icache_ways = XCHAL_ICACHE_WAYS, \
 427     .dcache_ways = XCHAL_DCACHE_WAYS, \
 428     .dcache_line_bytes = XCHAL_DCACHE_LINESIZE, \
 429     .memctl_mask = \
 430         (XCHAL_ICACHE_SIZE ? MEMCTL_IUSEWAYS_MASK : 0) | \
 431         (XCHAL_DCACHE_SIZE ? \
 432          MEMCTL_DALLOCWAYS_MASK | MEMCTL_DUSEWAYS_MASK : 0) | \
 433         MEMCTL_ISNP | MEMCTL_DSNP | \
 434         (XCHAL_HAVE_LOOPS && XCHAL_LOOP_BUFFER_SIZE ? MEMCTL_IL0EN : 0)
 435
 436 #define MEM_LOCATION(name, n) \
 437     { \
 438         .addr = XCHAL_ ## name ## n ## _PADDR, \
 439         .size = XCHAL_ ## name ## n ## _SIZE, \
 440     }
 441
 442 #define MEM_SECTIONS(name) \
 443     MEM_LOCATION(name, 0), \
 444     MEM_LOCATION(name, 1), \
 445     MEM_LOCATION(name, 2), \
 446     MEM_LOCATION(name, 3)
 447
 448 #define MEM_SECTION(name) \
 449     .num = XCHAL_NUM_ ## name, \
 450     .location = { \
 451         MEM_SECTIONS(name) \
 452     }
 453
 454 #define SYSMEM_SECTION(name) \
 455     .num = 1, \
 456     .location = { \
 457         { \
 458             .addr = XCHAL_ ## name ## 0_PADDR, \
 459             .size = XCHAL_ ## name ## 0_SIZE, \
 460         } \
 461     }
 462
 463 #define LOCAL_MEMORIES_SECTION \
 464     .instrom = { \
 465         MEM_SECTION(INSTROM) \
 466     }, \
 467     .instram = { \
 468         MEM_SECTION(INSTRAM) \
 469     }, \
 470     .datarom = { \
 471         MEM_SECTION(DATAROM) \
 472     }, \
 473     .dataram = { \
 474         MEM_SECTION(DATARAM) \
 475     }, \
 476     .sysrom = { \
 477         SYSMEM_SECTION(SYSROM) \
 478     }, \
 479     .sysram = { \
 480         SYSMEM_SECTION(SYSRAM) \
 481     }
 482
 483 #define CONFIG_SECTION \
 484     .configid = { \
 485         XCHAL_HW_CONFIGID0, \
 486         XCHAL_HW_CONFIGID1, \
 487     }
 488
 489 #define DEFAULT_SECTIONS \
 490     .options = XTENSA_OPTIONS, \
 491     .nareg = XCHAL_NUM_AREGS, \
 492     .ndepc = (XCHAL_XEA_VERSION >= 2), \
 493     .inst_fetch_width = XCHAL_INST_FETCH_WIDTH, \
 494     .max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE, \
 495     EXCEPTIONS_SECTION, \
 496     INTERRUPTS_SECTION, \
 497     TLB_SECTION, \
 498     DEBUG_SECTION, \
 499     CACHE_SECTION, \
 500     LOCAL_MEMORIES_SECTION, \
 501     CONFIG_SECTION
 502
 503
 504 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 2
 505 #define XCHAL_INTLEVEL2_VECTOR_VADDR 0
 506 #endif
 507 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 3
 508 #define XCHAL_INTLEVEL3_VECTOR_VADDR 0
 509 #endif
 510 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 4
 511 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0
 512 #endif
 513 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 5
 514 #define XCHAL_INTLEVEL5_VECTOR_VADDR 0
 515 #endif
 516 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 6
 517 #define XCHAL_INTLEVEL6_VECTOR_VADDR 0
 518 #endif
 519 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 7
 520 #define XCHAL_INTLEVEL7_VECTOR_VADDR 0
 521 #endif
 522
 523
 524 #if XCHAL_NUM_INTERRUPTS <= 0
 525 #define XCHAL_INT0_LEVEL 0
 526 #define XCHAL_INT0_TYPE 0
 527 #endif
 528 #if XCHAL_NUM_INTERRUPTS <= 1
 529 #define XCHAL_INT1_LEVEL 0
 530 #define XCHAL_INT1_TYPE 0
 531 #endif
 532 #if XCHAL_NUM_INTERRUPTS <= 2
 533 #define XCHAL_INT2_LEVEL 0
 534 #define XCHAL_INT2_TYPE 0
 535 #endif
 536 #if XCHAL_NUM_INTERRUPTS <= 3
 537 #define XCHAL_INT3_LEVEL 0
 538 #define XCHAL_INT3_TYPE 0
 539 #endif
 540 #if XCHAL_NUM_INTERRUPTS <= 4
 541 #define XCHAL_INT4_LEVEL 0
 542 #define XCHAL_INT4_TYPE 0
 543 #endif
 544 #if XCHAL_NUM_INTERRUPTS <= 5
 545 #define XCHAL_INT5_LEVEL 0
 546 #define XCHAL_INT5_TYPE 0
 547 #endif
 548 #if XCHAL_NUM_INTERRUPTS <= 6
 549 #define XCHAL_INT6_LEVEL 0
 550 #define XCHAL_INT6_TYPE 0
 551 #endif
 552 #if XCHAL_NUM_INTERRUPTS <= 7
 553 #define XCHAL_INT7_LEVEL 0
 554 #define XCHAL_INT7_TYPE 0
 555 #endif
 556 #if XCHAL_NUM_INTERRUPTS <= 8
 557 #define XCHAL_INT8_LEVEL 0
 558 #define XCHAL_INT8_TYPE 0
 559 #endif
 560 #if XCHAL_NUM_INTERRUPTS <= 9
 561 #define XCHAL_INT9_LEVEL 0
 562 #define XCHAL_INT9_TYPE 0
 563 #endif
 564 #if XCHAL_NUM_INTERRUPTS <= 10
 565 #define XCHAL_INT10_LEVEL 0
 566 #define XCHAL_INT10_TYPE 0
 567 #endif
 568 #if XCHAL_NUM_INTERRUPTS <= 11
 569 #define XCHAL_INT11_LEVEL 0
 570 #define XCHAL_INT11_TYPE 0
 571 #endif
 572 #if XCHAL_NUM_INTERRUPTS <= 12
 573 #define XCHAL_INT12_LEVEL 0
 574 #define XCHAL_INT12_TYPE 0
 575 #endif
 576 #if XCHAL_NUM_INTERRUPTS <= 13
 577 #define XCHAL_INT13_LEVEL 0
 578 #define XCHAL_INT13_TYPE 0
 579 #endif
 580 #if XCHAL_NUM_INTERRUPTS <= 14
 581 #define XCHAL_INT14_LEVEL 0
 582 #define XCHAL_INT14_TYPE 0
 583 #endif
 584 #if XCHAL_NUM_INTERRUPTS <= 15
 585 #define XCHAL_INT15_LEVEL 0
 586 #define XCHAL_INT15_TYPE 0
 587 #endif
 588 #if XCHAL_NUM_INTERRUPTS <= 16
 589 #define XCHAL_INT16_LEVEL 0
 590 #define XCHAL_INT16_TYPE 0
 591 #endif
 592 #if XCHAL_NUM_INTERRUPTS <= 17
 593 #define XCHAL_INT17_LEVEL 0
 594 #define XCHAL_INT17_TYPE 0
 595 #endif
 596 #if XCHAL_NUM_INTERRUPTS <= 18
 597 #define XCHAL_INT18_LEVEL 0
 598 #define XCHAL_INT18_TYPE 0
 599 #endif
 600 #if XCHAL_NUM_INTERRUPTS <= 19
 601 #define XCHAL_INT19_LEVEL 0
 602 #define XCHAL_INT19_TYPE 0
 603 #endif
 604 #if XCHAL_NUM_INTERRUPTS <= 20
 605 #define XCHAL_INT20_LEVEL 0
 606 #define XCHAL_INT20_TYPE 0
 607 #endif
 608 #if XCHAL_NUM_INTERRUPTS <= 21
 609 #define XCHAL_INT21_LEVEL 0
 610 #define XCHAL_INT21_TYPE 0
 611 #endif
 612 #if XCHAL_NUM_INTERRUPTS <= 22
 613 #define XCHAL_INT22_LEVEL 0
 614 #define XCHAL_INT22_TYPE 0
 615 #endif
 616 #if XCHAL_NUM_INTERRUPTS <= 23
 617 #define XCHAL_INT23_LEVEL 0
 618 #define XCHAL_INT23_TYPE 0
 619 #endif
 620 #if XCHAL_NUM_INTERRUPTS <= 24
 621 #define XCHAL_INT24_LEVEL 0
 622 #define XCHAL_INT24_TYPE 0
 623 #endif
 624 #if XCHAL_NUM_INTERRUPTS <= 25
 625 #define XCHAL_INT25_LEVEL 0
 626 #define XCHAL_INT25_TYPE 0
 627 #endif
 628 #if XCHAL_NUM_INTERRUPTS <= 26
 629 #define XCHAL_INT26_LEVEL 0
 630 #define XCHAL_INT26_TYPE 0
 631 #endif
 632 #if XCHAL_NUM_INTERRUPTS <= 27
 633 #define XCHAL_INT27_LEVEL 0
 634 #define XCHAL_INT27_TYPE 0
 635 #endif
 636 #if XCHAL_NUM_INTERRUPTS <= 28
 637 #define XCHAL_INT28_LEVEL 0
 638 #define XCHAL_INT28_TYPE 0
 639 #endif
 640 #if XCHAL_NUM_INTERRUPTS <= 29
 641 #define XCHAL_INT29_LEVEL 0
 642 #define XCHAL_INT29_TYPE 0
 643 #endif
 644 #if XCHAL_NUM_INTERRUPTS <= 30
 645 #define XCHAL_INT30_LEVEL 0
 646 #define XCHAL_INT30_TYPE 0
 647 #endif
 648 #if XCHAL_NUM_INTERRUPTS <= 31
 649 #define XCHAL_INT31_LEVEL 0
 650 #define XCHAL_INT31_TYPE 0
 651 #endif
 652
 653
 654 #if XCHAL_NUM_EXTINTERRUPTS <= 0
 655 #define XCHAL_EXTINT0_NUM 0
 656 #endif
 657 #if XCHAL_NUM_EXTINTERRUPTS <= 1
 658 #define XCHAL_EXTINT1_NUM 0
 659 #endif
 660 #if XCHAL_NUM_EXTINTERRUPTS <= 2
 661 #define XCHAL_EXTINT2_NUM 0
 662 #endif
 663 #if XCHAL_NUM_EXTINTERRUPTS <= 3
 664 #define XCHAL_EXTINT3_NUM 0
 665 #endif
 666 #if XCHAL_NUM_EXTINTERRUPTS <= 4
 667 #define XCHAL_EXTINT4_NUM 0
 668 #endif
 669 #if XCHAL_NUM_EXTINTERRUPTS <= 5
 670 #define XCHAL_EXTINT5_NUM 0
 671 #endif
 672 #if XCHAL_NUM_EXTINTERRUPTS <= 6
 673 #define XCHAL_EXTINT6_NUM 0
 674 #endif
 675 #if XCHAL_NUM_EXTINTERRUPTS <= 7
 676 #define XCHAL_EXTINT7_NUM 0
 677 #endif
 678 #if XCHAL_NUM_EXTINTERRUPTS <= 8
 679 #define XCHAL_EXTINT8_NUM 0
 680 #endif
 681 #if XCHAL_NUM_EXTINTERRUPTS <= 9
 682 #define XCHAL_EXTINT9_NUM 0
 683 #endif
 684 #if XCHAL_NUM_EXTINTERRUPTS <= 10
 685 #define XCHAL_EXTINT10_NUM 0
 686 #endif
 687 #if XCHAL_NUM_EXTINTERRUPTS <= 11
 688 #define XCHAL_EXTINT11_NUM 0
 689 #endif
 690 #if XCHAL_NUM_EXTINTERRUPTS <= 12
 691 #define XCHAL_EXTINT12_NUM 0
 692 #endif
 693 #if XCHAL_NUM_EXTINTERRUPTS <= 13
 694 #define XCHAL_EXTINT13_NUM 0
 695 #endif
 696 #if XCHAL_NUM_EXTINTERRUPTS <= 14
 697 #define XCHAL_EXTINT14_NUM 0
 698 #endif
 699 #if XCHAL_NUM_EXTINTERRUPTS <= 15
 700 #define XCHAL_EXTINT15_NUM 0
 701 #endif
 702 #if XCHAL_NUM_EXTINTERRUPTS <= 16
 703 #define XCHAL_EXTINT16_NUM 0
 704 #endif
 705 #if XCHAL_NUM_EXTINTERRUPTS <= 17
 706 #define XCHAL_EXTINT17_NUM 0
 707 #endif
 708 #if XCHAL_NUM_EXTINTERRUPTS <= 18
 709 #define XCHAL_EXTINT18_NUM 0
 710 #endif
 711 #if XCHAL_NUM_EXTINTERRUPTS <= 19
 712 #define XCHAL_EXTINT19_NUM 0
 713 #endif
 714 #if XCHAL_NUM_EXTINTERRUPTS <= 20
 715 #define XCHAL_EXTINT20_NUM 0
 716 #endif
 717 #if XCHAL_NUM_EXTINTERRUPTS <= 21
 718 #define XCHAL_EXTINT21_NUM 0
 719 #endif
 720 #if XCHAL_NUM_EXTINTERRUPTS <= 22
 721 #define XCHAL_EXTINT22_NUM 0
 722 #endif
 723 #if XCHAL_NUM_EXTINTERRUPTS <= 23
 724 #define XCHAL_EXTINT23_NUM 0
 725 #endif
 726 #if XCHAL_NUM_EXTINTERRUPTS <= 24
 727 #define XCHAL_EXTINT24_NUM 0
 728 #endif
 729 #if XCHAL_NUM_EXTINTERRUPTS <= 25
 730 #define XCHAL_EXTINT25_NUM 0
 731 #endif
 732 #if XCHAL_NUM_EXTINTERRUPTS <= 26
 733 #define XCHAL_EXTINT26_NUM 0
 734 #endif
 735 #if XCHAL_NUM_EXTINTERRUPTS <= 27
 736 #define XCHAL_EXTINT27_NUM 0
 737 #endif
 738 #if XCHAL_NUM_EXTINTERRUPTS <= 28
 739 #define XCHAL_EXTINT28_NUM 0
 740 #endif
 741 #if XCHAL_NUM_EXTINTERRUPTS <= 29
 742 #define XCHAL_EXTINT29_NUM 0
 743 #endif
 744 #if XCHAL_NUM_EXTINTERRUPTS <= 30
 745 #define XCHAL_EXTINT30_NUM 0
 746 #endif
 747 #if XCHAL_NUM_EXTINTERRUPTS <= 31
 748 #define XCHAL_EXTINT31_NUM 0
 749 #endif
 750
 751
 752 #define XTHAL_TIMER_UNCONFIGURED 0
 753
 754 #if XCHAL_NUM_INSTROM < 1
 755 #define XCHAL_INSTROM0_PADDR 0
 756 #define XCHAL_INSTROM0_SIZE 0
 757 #endif
 758 #if XCHAL_NUM_INSTROM < 2
 759 #define XCHAL_INSTROM1_PADDR 0
 760 #define XCHAL_INSTROM1_SIZE 0
 761 #endif
 762 #if XCHAL_NUM_INSTROM < 3
 763 #define XCHAL_INSTROM2_PADDR 0
 764 #define XCHAL_INSTROM2_SIZE 0
 765 #endif
 766 #if XCHAL_NUM_INSTROM < 4
 767 #define XCHAL_INSTROM3_PADDR 0
 768 #define XCHAL_INSTROM3_SIZE 0
 769 #endif
 770 #if XCHAL_NUM_INSTROM > MAX_NMEMORY
 771 #error XCHAL_NUM_INSTROM > MAX_NMEMORY
 772 #endif
 773
 774 #if XCHAL_NUM_INSTRAM < 1
 775 #define XCHAL_INSTRAM0_PADDR 0
 776 #define XCHAL_INSTRAM0_SIZE 0
 777 #endif
 778 #if XCHAL_NUM_INSTRAM < 2
 779 #define XCHAL_INSTRAM1_PADDR 0
 780 #define XCHAL_INSTRAM1_SIZE 0
 781 #endif
 782 #if XCHAL_NUM_INSTRAM < 3
 783 #define XCHAL_INSTRAM2_PADDR 0
 784 #define XCHAL_INSTRAM2_SIZE 0
 785 #endif
 786 #if XCHAL_NUM_INSTRAM < 4
 787 #define XCHAL_INSTRAM3_PADDR 0
 788 #define XCHAL_INSTRAM3_SIZE 0
 789 #endif
 790 #if XCHAL_NUM_INSTRAM > MAX_NMEMORY
 791 #error XCHAL_NUM_INSTRAM > MAX_NMEMORY
 792 #endif
 793
 794 #if XCHAL_NUM_DATAROM < 1
 795 #define XCHAL_DATAROM0_PADDR 0
 796 #define XCHAL_DATAROM0_SIZE 0
 797 #endif
 798 #if XCHAL_NUM_DATAROM < 2
 799 #define XCHAL_DATAROM1_PADDR 0
 800 #define XCHAL_DATAROM1_SIZE 0
 801 #endif
 802 #if XCHAL_NUM_DATAROM < 3
 803 #define XCHAL_DATAROM2_PADDR 0
 804 #define XCHAL_DATAROM2_SIZE 0
 805 #endif
 806 #if XCHAL_NUM_DATAROM < 4
 807 #define XCHAL_DATAROM3_PADDR 0
 808 #define XCHAL_DATAROM3_SIZE 0
 809 #endif
 810 #if XCHAL_NUM_DATAROM > MAX_NMEMORY
 811 #error XCHAL_NUM_DATAROM > MAX_NMEMORY
 812 #endif
 813
 814 #if XCHAL_NUM_DATARAM < 1
 815 #define XCHAL_DATARAM0_PADDR 0
 816 #define XCHAL_DATARAM0_SIZE 0
 817 #endif
 818 #if XCHAL_NUM_DATARAM < 2
 819 #define XCHAL_DATARAM1_PADDR 0
 820 #define XCHAL_DATARAM1_SIZE 0
 821 #endif
 822 #if XCHAL_NUM_DATARAM < 3
 823 #define XCHAL_DATARAM2_PADDR 0
 824 #define XCHAL_DATARAM2_SIZE 0
 825 #endif
 826 #if XCHAL_NUM_DATARAM < 4
 827 #define XCHAL_DATARAM3_PADDR 0
 828 #define XCHAL_DATARAM3_SIZE 0
 829 #endif
 830 #if XCHAL_NUM_DATARAM > MAX_NMEMORY
 831 #error XCHAL_NUM_DATARAM > MAX_NMEMORY
 832 #endif