2 * PowerPC emulation for qemu: main translation routines.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
24 #include "disas/disas.h"
25 #include "exec/exec-all.h"
27 #include "tcg-op-gvec.h"
28 #include "qemu/host-utils.h"
29 #include "exec/cpu_ldst.h"
31 #include "exec/helper-proto.h"
32 #include "exec/helper-gen.h"
34 #include "trace-tcg.h"
35 #include "exec/translator.h"
37 #include "qemu/atomic128.h"
40 #define CPU_SINGLE_STEP 0x1
41 #define CPU_BRANCH_STEP 0x2
42 #define GDBSTUB_SINGLE_STEP 0x4
44 /* Include definitions for instructions classes and implementations flags */
45 /* #define PPC_DEBUG_DISAS */
46 /* #define DO_PPC_STATISTICS */
48 #ifdef PPC_DEBUG_DISAS
49 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
51 # define LOG_DISAS(...) do { } while (0)
53 /*****************************************************************************/
54 /* Code translation helpers */
56 /* global register indexes */
57 static char cpu_reg_names
[10 * 3 + 22 * 4 /* GPR */
58 + 10 * 4 + 22 * 5 /* SPE GPRh */
60 static TCGv cpu_gpr
[32];
61 static TCGv cpu_gprh
[32];
62 static TCGv_i32 cpu_crf
[8];
67 #if defined(TARGET_PPC64)
70 static TCGv cpu_xer
, cpu_so
, cpu_ov
, cpu_ca
, cpu_ov32
, cpu_ca32
;
71 static TCGv cpu_reserve
;
72 static TCGv cpu_reserve_val
;
73 static TCGv cpu_fpscr
;
74 static TCGv_i32 cpu_access_type
;
76 #include "exec/gen-icount.h"
78 void ppc_translate_init(void)
82 size_t cpu_reg_names_size
;
85 cpu_reg_names_size
= sizeof(cpu_reg_names
);
87 for (i
= 0; i
< 8; i
++) {
88 snprintf(p
, cpu_reg_names_size
, "crf%d", i
);
89 cpu_crf
[i
] = tcg_global_mem_new_i32(cpu_env
,
90 offsetof(CPUPPCState
, crf
[i
]), p
);
92 cpu_reg_names_size
-= 5;
95 for (i
= 0; i
< 32; i
++) {
96 snprintf(p
, cpu_reg_names_size
, "r%d", i
);
97 cpu_gpr
[i
] = tcg_global_mem_new(cpu_env
,
98 offsetof(CPUPPCState
, gpr
[i
]), p
);
99 p
+= (i
< 10) ? 3 : 4;
100 cpu_reg_names_size
-= (i
< 10) ? 3 : 4;
101 snprintf(p
, cpu_reg_names_size
, "r%dH", i
);
102 cpu_gprh
[i
] = tcg_global_mem_new(cpu_env
,
103 offsetof(CPUPPCState
, gprh
[i
]), p
);
104 p
+= (i
< 10) ? 4 : 5;
105 cpu_reg_names_size
-= (i
< 10) ? 4 : 5;
108 cpu_nip
= tcg_global_mem_new(cpu_env
,
109 offsetof(CPUPPCState
, nip
), "nip");
111 cpu_msr
= tcg_global_mem_new(cpu_env
,
112 offsetof(CPUPPCState
, msr
), "msr");
114 cpu_ctr
= tcg_global_mem_new(cpu_env
,
115 offsetof(CPUPPCState
, ctr
), "ctr");
117 cpu_lr
= tcg_global_mem_new(cpu_env
,
118 offsetof(CPUPPCState
, lr
), "lr");
120 #if defined(TARGET_PPC64)
121 cpu_cfar
= tcg_global_mem_new(cpu_env
,
122 offsetof(CPUPPCState
, cfar
), "cfar");
125 cpu_xer
= tcg_global_mem_new(cpu_env
,
126 offsetof(CPUPPCState
, xer
), "xer");
127 cpu_so
= tcg_global_mem_new(cpu_env
,
128 offsetof(CPUPPCState
, so
), "SO");
129 cpu_ov
= tcg_global_mem_new(cpu_env
,
130 offsetof(CPUPPCState
, ov
), "OV");
131 cpu_ca
= tcg_global_mem_new(cpu_env
,
132 offsetof(CPUPPCState
, ca
), "CA");
133 cpu_ov32
= tcg_global_mem_new(cpu_env
,
134 offsetof(CPUPPCState
, ov32
), "OV32");
135 cpu_ca32
= tcg_global_mem_new(cpu_env
,
136 offsetof(CPUPPCState
, ca32
), "CA32");
138 cpu_reserve
= tcg_global_mem_new(cpu_env
,
139 offsetof(CPUPPCState
, reserve_addr
),
141 cpu_reserve_val
= tcg_global_mem_new(cpu_env
,
142 offsetof(CPUPPCState
, reserve_val
),
145 cpu_fpscr
= tcg_global_mem_new(cpu_env
,
146 offsetof(CPUPPCState
, fpscr
), "fpscr");
148 cpu_access_type
= tcg_global_mem_new_i32(cpu_env
,
149 offsetof(CPUPPCState
, access_type
),
153 /* internal defines */
154 struct DisasContext
{
155 DisasContextBase base
;
158 /* Routine used to access memory */
159 bool pr
, hv
, dr
, le_mode
;
161 bool need_access_type
;
164 /* Translation flags */
165 TCGMemOp default_tcg_memop_mask
;
166 #if defined(TARGET_PPC64)
171 bool altivec_enabled
;
176 ppc_spr_t
*spr_cb
; /* Needed to check rights for mfspr/mtspr */
177 int singlestep_enabled
;
179 uint64_t insns_flags
;
180 uint64_t insns_flags2
;
183 /* Return true iff byteswap is needed in a scalar memop */
184 static inline bool need_byteswap(const DisasContext
*ctx
)
186 #if defined(TARGET_WORDS_BIGENDIAN)
189 return !ctx
->le_mode
;
193 /* True when active word size < size of target_long. */
195 # define NARROW_MODE(C) (!(C)->sf_mode)
197 # define NARROW_MODE(C) 0
200 struct opc_handler_t
{
201 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
203 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
205 /* instruction type */
207 /* extended instruction type */
210 void (*handler
)(DisasContext
*ctx
);
211 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
214 #if defined(DO_PPC_STATISTICS)
219 /* SPR load/store helpers */
220 static inline void gen_load_spr(TCGv t
, int reg
)
222 tcg_gen_ld_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
225 static inline void gen_store_spr(int reg
, TCGv t
)
227 tcg_gen_st_tl(t
, cpu_env
, offsetof(CPUPPCState
, spr
[reg
]));
230 static inline void gen_set_access_type(DisasContext
*ctx
, int access_type
)
232 if (ctx
->need_access_type
&& ctx
->access_type
!= access_type
) {
233 tcg_gen_movi_i32(cpu_access_type
, access_type
);
234 ctx
->access_type
= access_type
;
238 static inline void gen_update_nip(DisasContext
*ctx
, target_ulong nip
)
240 if (NARROW_MODE(ctx
)) {
243 tcg_gen_movi_tl(cpu_nip
, nip
);
246 static void gen_exception_err(DisasContext
*ctx
, uint32_t excp
, uint32_t error
)
251 * These are all synchronous exceptions, we set the PC back to the
252 * faulting instruction
254 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
255 gen_update_nip(ctx
, ctx
->base
.pc_next
- 4);
257 t0
= tcg_const_i32(excp
);
258 t1
= tcg_const_i32(error
);
259 gen_helper_raise_exception_err(cpu_env
, t0
, t1
);
260 tcg_temp_free_i32(t0
);
261 tcg_temp_free_i32(t1
);
262 ctx
->exception
= (excp
);
265 static void gen_exception(DisasContext
*ctx
, uint32_t excp
)
270 * These are all synchronous exceptions, we set the PC back to the
271 * faulting instruction
273 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
274 gen_update_nip(ctx
, ctx
->base
.pc_next
- 4);
276 t0
= tcg_const_i32(excp
);
277 gen_helper_raise_exception(cpu_env
, t0
);
278 tcg_temp_free_i32(t0
);
279 ctx
->exception
= (excp
);
282 static void gen_exception_nip(DisasContext
*ctx
, uint32_t excp
,
287 gen_update_nip(ctx
, nip
);
288 t0
= tcg_const_i32(excp
);
289 gen_helper_raise_exception(cpu_env
, t0
);
290 tcg_temp_free_i32(t0
);
291 ctx
->exception
= (excp
);
295 * Tells the caller what is the appropriate exception to generate and prepares
296 * SPR registers for this exception.
298 * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or
299 * POWERPC_EXCP_DEBUG (on BookE).
301 static uint32_t gen_prep_dbgex(DisasContext
*ctx
)
303 if (ctx
->flags
& POWERPC_FLAG_DE
) {
304 target_ulong dbsr
= 0;
305 if (ctx
->singlestep_enabled
& CPU_SINGLE_STEP
) {
308 /* Must have been branch */
311 TCGv t0
= tcg_temp_new();
312 gen_load_spr(t0
, SPR_BOOKE_DBSR
);
313 tcg_gen_ori_tl(t0
, t0
, dbsr
);
314 gen_store_spr(SPR_BOOKE_DBSR
, t0
);
316 return POWERPC_EXCP_DEBUG
;
318 return POWERPC_EXCP_TRACE
;
322 static void gen_debug_exception(DisasContext
*ctx
)
327 * These are all synchronous exceptions, we set the PC back to the
328 * faulting instruction
330 if ((ctx
->exception
!= POWERPC_EXCP_BRANCH
) &&
331 (ctx
->exception
!= POWERPC_EXCP_SYNC
)) {
332 gen_update_nip(ctx
, ctx
->base
.pc_next
);
334 t0
= tcg_const_i32(EXCP_DEBUG
);
335 gen_helper_raise_exception(cpu_env
, t0
);
336 tcg_temp_free_i32(t0
);
339 static inline void gen_inval_exception(DisasContext
*ctx
, uint32_t error
)
341 /* Will be converted to program check if needed */
342 gen_exception_err(ctx
, POWERPC_EXCP_HV_EMU
, POWERPC_EXCP_INVAL
| error
);
345 static inline void gen_priv_exception(DisasContext
*ctx
, uint32_t error
)
347 gen_exception_err(ctx
, POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_PRIV
| error
);
350 static inline void gen_hvpriv_exception(DisasContext
*ctx
, uint32_t error
)
352 /* Will be converted to program check if needed */
353 gen_exception_err(ctx
, POWERPC_EXCP_HV_EMU
, POWERPC_EXCP_PRIV
| error
);
356 /* Stop translation */
357 static inline void gen_stop_exception(DisasContext
*ctx
)
359 gen_update_nip(ctx
, ctx
->base
.pc_next
);
360 ctx
->exception
= POWERPC_EXCP_STOP
;
363 #ifndef CONFIG_USER_ONLY
364 /* No need to update nip here, as execution flow will change */
365 static inline void gen_sync_exception(DisasContext
*ctx
)
367 ctx
->exception
= POWERPC_EXCP_SYNC
;
371 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
372 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
374 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
375 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
377 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
378 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
380 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
381 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
383 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \
384 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
386 #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \
387 GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2)
389 typedef struct opcode_t
{
390 unsigned char opc1
, opc2
, opc3
, opc4
;
391 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
392 unsigned char pad
[4];
394 opc_handler_t handler
;
398 /* Helpers for priv. check */
401 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \
404 #if defined(CONFIG_USER_ONLY)
405 #define CHK_HV GEN_PRIV
406 #define CHK_SV GEN_PRIV
407 #define CHK_HVRM GEN_PRIV
411 if (unlikely(ctx->pr || !ctx->hv)) { \
417 if (unlikely(ctx->pr)) { \
423 if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \
431 /*****************************************************************************/
432 /* PowerPC instructions table */
434 #if defined(DO_PPC_STATISTICS)
435 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
445 .handler = &gen_##name, \
446 .oname = stringify(name), \
448 .oname = stringify(name), \
450 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
461 .handler = &gen_##name, \
462 .oname = stringify(name), \
464 .oname = stringify(name), \
466 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
476 .handler = &gen_##name, \
481 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
491 .handler = &gen_##name, \
492 .oname = stringify(name), \
494 .oname = stringify(name), \
496 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
506 .handler = &gen_##name, \
512 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
522 .handler = &gen_##name, \
524 .oname = stringify(name), \
526 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
537 .handler = &gen_##name, \
539 .oname = stringify(name), \
541 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
551 .handler = &gen_##name, \
555 #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \
565 .handler = &gen_##name, \
567 .oname = stringify(name), \
569 #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \
579 .handler = &gen_##name, \
585 /* Invalid instruction */
586 static void gen_invalid(DisasContext
*ctx
)
588 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
591 static opc_handler_t invalid_handler
= {
592 .inval1
= 0xFFFFFFFF,
593 .inval2
= 0xFFFFFFFF,
596 .handler
= gen_invalid
,
599 /*** Integer comparison ***/
601 static inline void gen_op_cmp(TCGv arg0
, TCGv arg1
, int s
, int crf
)
603 TCGv t0
= tcg_temp_new();
604 TCGv t1
= tcg_temp_new();
605 TCGv_i32 t
= tcg_temp_new_i32();
607 tcg_gen_movi_tl(t0
, CRF_EQ
);
608 tcg_gen_movi_tl(t1
, CRF_LT
);
609 tcg_gen_movcond_tl((s
? TCG_COND_LT
: TCG_COND_LTU
),
610 t0
, arg0
, arg1
, t1
, t0
);
611 tcg_gen_movi_tl(t1
, CRF_GT
);
612 tcg_gen_movcond_tl((s
? TCG_COND_GT
: TCG_COND_GTU
),
613 t0
, arg0
, arg1
, t1
, t0
);
615 tcg_gen_trunc_tl_i32(t
, t0
);
616 tcg_gen_trunc_tl_i32(cpu_crf
[crf
], cpu_so
);
617 tcg_gen_or_i32(cpu_crf
[crf
], cpu_crf
[crf
], t
);
621 tcg_temp_free_i32(t
);
624 static inline void gen_op_cmpi(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
626 TCGv t0
= tcg_const_tl(arg1
);
627 gen_op_cmp(arg0
, t0
, s
, crf
);
631 static inline void gen_op_cmp32(TCGv arg0
, TCGv arg1
, int s
, int crf
)
637 tcg_gen_ext32s_tl(t0
, arg0
);
638 tcg_gen_ext32s_tl(t1
, arg1
);
640 tcg_gen_ext32u_tl(t0
, arg0
);
641 tcg_gen_ext32u_tl(t1
, arg1
);
643 gen_op_cmp(t0
, t1
, s
, crf
);
648 static inline void gen_op_cmpi32(TCGv arg0
, target_ulong arg1
, int s
, int crf
)
650 TCGv t0
= tcg_const_tl(arg1
);
651 gen_op_cmp32(arg0
, t0
, s
, crf
);
655 static inline void gen_set_Rc0(DisasContext
*ctx
, TCGv reg
)
657 if (NARROW_MODE(ctx
)) {
658 gen_op_cmpi32(reg
, 0, 1, 0);
660 gen_op_cmpi(reg
, 0, 1, 0);
665 static void gen_cmp(DisasContext
*ctx
)
667 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
668 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
669 1, crfD(ctx
->opcode
));
671 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
672 1, crfD(ctx
->opcode
));
677 static void gen_cmpi(DisasContext
*ctx
)
679 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
680 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
681 1, crfD(ctx
->opcode
));
683 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], SIMM(ctx
->opcode
),
684 1, crfD(ctx
->opcode
));
689 static void gen_cmpl(DisasContext
*ctx
)
691 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
692 gen_op_cmp(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
693 0, crfD(ctx
->opcode
));
695 gen_op_cmp32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
696 0, crfD(ctx
->opcode
));
701 static void gen_cmpli(DisasContext
*ctx
)
703 if ((ctx
->opcode
& 0x00200000) && (ctx
->insns_flags
& PPC_64B
)) {
704 gen_op_cmpi(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
705 0, crfD(ctx
->opcode
));
707 gen_op_cmpi32(cpu_gpr
[rA(ctx
->opcode
)], UIMM(ctx
->opcode
),
708 0, crfD(ctx
->opcode
));
712 /* cmprb - range comparison: isupper, isaplha, islower*/
713 static void gen_cmprb(DisasContext
*ctx
)
715 TCGv_i32 src1
= tcg_temp_new_i32();
716 TCGv_i32 src2
= tcg_temp_new_i32();
717 TCGv_i32 src2lo
= tcg_temp_new_i32();
718 TCGv_i32 src2hi
= tcg_temp_new_i32();
719 TCGv_i32 crf
= cpu_crf
[crfD(ctx
->opcode
)];
721 tcg_gen_trunc_tl_i32(src1
, cpu_gpr
[rA(ctx
->opcode
)]);
722 tcg_gen_trunc_tl_i32(src2
, cpu_gpr
[rB(ctx
->opcode
)]);
724 tcg_gen_andi_i32(src1
, src1
, 0xFF);
725 tcg_gen_ext8u_i32(src2lo
, src2
);
726 tcg_gen_shri_i32(src2
, src2
, 8);
727 tcg_gen_ext8u_i32(src2hi
, src2
);
729 tcg_gen_setcond_i32(TCG_COND_LEU
, src2lo
, src2lo
, src1
);
730 tcg_gen_setcond_i32(TCG_COND_LEU
, src2hi
, src1
, src2hi
);
731 tcg_gen_and_i32(crf
, src2lo
, src2hi
);
733 if (ctx
->opcode
& 0x00200000) {
734 tcg_gen_shri_i32(src2
, src2
, 8);
735 tcg_gen_ext8u_i32(src2lo
, src2
);
736 tcg_gen_shri_i32(src2
, src2
, 8);
737 tcg_gen_ext8u_i32(src2hi
, src2
);
738 tcg_gen_setcond_i32(TCG_COND_LEU
, src2lo
, src2lo
, src1
);
739 tcg_gen_setcond_i32(TCG_COND_LEU
, src2hi
, src1
, src2hi
);
740 tcg_gen_and_i32(src2lo
, src2lo
, src2hi
);
741 tcg_gen_or_i32(crf
, crf
, src2lo
);
743 tcg_gen_shli_i32(crf
, crf
, CRF_GT_BIT
);
744 tcg_temp_free_i32(src1
);
745 tcg_temp_free_i32(src2
);
746 tcg_temp_free_i32(src2lo
);
747 tcg_temp_free_i32(src2hi
);
750 #if defined(TARGET_PPC64)
752 static void gen_cmpeqb(DisasContext
*ctx
)
754 gen_helper_cmpeqb(cpu_crf
[crfD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
755 cpu_gpr
[rB(ctx
->opcode
)]);
759 /* isel (PowerPC 2.03 specification) */
760 static void gen_isel(DisasContext
*ctx
)
762 uint32_t bi
= rC(ctx
->opcode
);
763 uint32_t mask
= 0x08 >> (bi
& 0x03);
764 TCGv t0
= tcg_temp_new();
767 tcg_gen_extu_i32_tl(t0
, cpu_crf
[bi
>> 2]);
768 tcg_gen_andi_tl(t0
, t0
, mask
);
770 zr
= tcg_const_tl(0);
771 tcg_gen_movcond_tl(TCG_COND_NE
, cpu_gpr
[rD(ctx
->opcode
)], t0
, zr
,
772 rA(ctx
->opcode
) ? cpu_gpr
[rA(ctx
->opcode
)] : zr
,
773 cpu_gpr
[rB(ctx
->opcode
)]);
778 /* cmpb: PowerPC 2.05 specification */
779 static void gen_cmpb(DisasContext
*ctx
)
781 gen_helper_cmpb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
782 cpu_gpr
[rB(ctx
->opcode
)]);
785 /*** Integer arithmetic ***/
787 static inline void gen_op_arith_compute_ov(DisasContext
*ctx
, TCGv arg0
,
788 TCGv arg1
, TCGv arg2
, int sub
)
790 TCGv t0
= tcg_temp_new();
792 tcg_gen_xor_tl(cpu_ov
, arg0
, arg2
);
793 tcg_gen_xor_tl(t0
, arg1
, arg2
);
795 tcg_gen_and_tl(cpu_ov
, cpu_ov
, t0
);
797 tcg_gen_andc_tl(cpu_ov
, cpu_ov
, t0
);
800 if (NARROW_MODE(ctx
)) {
801 tcg_gen_extract_tl(cpu_ov
, cpu_ov
, 31, 1);
802 if (is_isa300(ctx
)) {
803 tcg_gen_mov_tl(cpu_ov32
, cpu_ov
);
806 if (is_isa300(ctx
)) {
807 tcg_gen_extract_tl(cpu_ov32
, cpu_ov
, 31, 1);
809 tcg_gen_extract_tl(cpu_ov
, cpu_ov
, TARGET_LONG_BITS
- 1, 1);
811 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
814 static inline void gen_op_arith_compute_ca32(DisasContext
*ctx
,
815 TCGv res
, TCGv arg0
, TCGv arg1
,
820 if (!is_isa300(ctx
)) {
826 tcg_gen_eqv_tl(t0
, arg0
, arg1
);
828 tcg_gen_xor_tl(t0
, arg0
, arg1
);
830 tcg_gen_xor_tl(t0
, t0
, res
);
831 tcg_gen_extract_tl(ca32
, t0
, 32, 1);
835 /* Common add function */
836 static inline void gen_op_arith_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
837 TCGv arg2
, TCGv ca
, TCGv ca32
,
838 bool add_ca
, bool compute_ca
,
839 bool compute_ov
, bool compute_rc0
)
843 if (compute_ca
|| compute_ov
) {
848 if (NARROW_MODE(ctx
)) {
850 * Caution: a non-obvious corner case of the spec is that
851 * we must produce the *entire* 64-bit addition, but
852 * produce the carry into bit 32.
854 TCGv t1
= tcg_temp_new();
855 tcg_gen_xor_tl(t1
, arg1
, arg2
); /* add without carry */
856 tcg_gen_add_tl(t0
, arg1
, arg2
);
858 tcg_gen_add_tl(t0
, t0
, ca
);
860 tcg_gen_xor_tl(ca
, t0
, t1
); /* bits changed w/ carry */
862 tcg_gen_extract_tl(ca
, ca
, 32, 1);
863 if (is_isa300(ctx
)) {
864 tcg_gen_mov_tl(ca32
, ca
);
867 TCGv zero
= tcg_const_tl(0);
869 tcg_gen_add2_tl(t0
, ca
, arg1
, zero
, ca
, zero
);
870 tcg_gen_add2_tl(t0
, ca
, t0
, ca
, arg2
, zero
);
872 tcg_gen_add2_tl(t0
, ca
, arg1
, zero
, arg2
, zero
);
874 gen_op_arith_compute_ca32(ctx
, t0
, arg1
, arg2
, ca32
, 0);
878 tcg_gen_add_tl(t0
, arg1
, arg2
);
880 tcg_gen_add_tl(t0
, t0
, ca
);
885 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 0);
887 if (unlikely(compute_rc0
)) {
888 gen_set_Rc0(ctx
, t0
);
892 tcg_gen_mov_tl(ret
, t0
);
896 /* Add functions with two operands */
897 #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \
898 static void glue(gen_, name)(DisasContext *ctx) \
900 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
901 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
903 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
905 /* Add functions with one operand and one immediate */
906 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \
907 add_ca, compute_ca, compute_ov) \
908 static void glue(gen_, name)(DisasContext *ctx) \
910 TCGv t0 = tcg_const_tl(const_val); \
911 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
912 cpu_gpr[rA(ctx->opcode)], t0, \
914 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
918 /* add add. addo addo. */
919 GEN_INT_ARITH_ADD(add
, 0x08, cpu_ca
, 0, 0, 0)
920 GEN_INT_ARITH_ADD(addo
, 0x18, cpu_ca
, 0, 0, 1)
921 /* addc addc. addco addco. */
922 GEN_INT_ARITH_ADD(addc
, 0x00, cpu_ca
, 0, 1, 0)
923 GEN_INT_ARITH_ADD(addco
, 0x10, cpu_ca
, 0, 1, 1)
924 /* adde adde. addeo addeo. */
925 GEN_INT_ARITH_ADD(adde
, 0x04, cpu_ca
, 1, 1, 0)
926 GEN_INT_ARITH_ADD(addeo
, 0x14, cpu_ca
, 1, 1, 1)
927 /* addme addme. addmeo addmeo. */
928 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, cpu_ca
, 1, 1, 0)
929 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, cpu_ca
, 1, 1, 1)
931 GEN_INT_ARITH_ADD(addex
, 0x05, cpu_ov
, 1, 1, 0);
932 /* addze addze. addzeo addzeo.*/
933 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, cpu_ca
, 1, 1, 0)
934 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, cpu_ca
, 1, 1, 1)
936 static void gen_addi(DisasContext
*ctx
)
938 target_long simm
= SIMM(ctx
->opcode
);
940 if (rA(ctx
->opcode
) == 0) {
942 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
);
944 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)],
945 cpu_gpr
[rA(ctx
->opcode
)], simm
);
949 static inline void gen_op_addic(DisasContext
*ctx
, bool compute_rc0
)
951 TCGv c
= tcg_const_tl(SIMM(ctx
->opcode
));
952 gen_op_arith_add(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
953 c
, cpu_ca
, cpu_ca32
, 0, 1, 0, compute_rc0
);
957 static void gen_addic(DisasContext
*ctx
)
959 gen_op_addic(ctx
, 0);
962 static void gen_addic_(DisasContext
*ctx
)
964 gen_op_addic(ctx
, 1);
968 static void gen_addis(DisasContext
*ctx
)
970 target_long simm
= SIMM(ctx
->opcode
);
972 if (rA(ctx
->opcode
) == 0) {
974 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
<< 16);
976 tcg_gen_addi_tl(cpu_gpr
[rD(ctx
->opcode
)],
977 cpu_gpr
[rA(ctx
->opcode
)], simm
<< 16);
982 static void gen_addpcis(DisasContext
*ctx
)
984 target_long d
= DX(ctx
->opcode
);
986 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], ctx
->base
.pc_next
+ (d
<< 16));
989 static inline void gen_op_arith_divw(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
990 TCGv arg2
, int sign
, int compute_ov
)
992 TCGv_i32 t0
= tcg_temp_new_i32();
993 TCGv_i32 t1
= tcg_temp_new_i32();
994 TCGv_i32 t2
= tcg_temp_new_i32();
995 TCGv_i32 t3
= tcg_temp_new_i32();
997 tcg_gen_trunc_tl_i32(t0
, arg1
);
998 tcg_gen_trunc_tl_i32(t1
, arg2
);
1000 tcg_gen_setcondi_i32(TCG_COND_EQ
, t2
, t0
, INT_MIN
);
1001 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, -1);
1002 tcg_gen_and_i32(t2
, t2
, t3
);
1003 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, 0);
1004 tcg_gen_or_i32(t2
, t2
, t3
);
1005 tcg_gen_movi_i32(t3
, 0);
1006 tcg_gen_movcond_i32(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1007 tcg_gen_div_i32(t3
, t0
, t1
);
1008 tcg_gen_extu_i32_tl(ret
, t3
);
1010 tcg_gen_setcondi_i32(TCG_COND_EQ
, t2
, t1
, 0);
1011 tcg_gen_movi_i32(t3
, 0);
1012 tcg_gen_movcond_i32(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1013 tcg_gen_divu_i32(t3
, t0
, t1
);
1014 tcg_gen_extu_i32_tl(ret
, t3
);
1017 tcg_gen_extu_i32_tl(cpu_ov
, t2
);
1018 if (is_isa300(ctx
)) {
1019 tcg_gen_extu_i32_tl(cpu_ov32
, t2
);
1021 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1023 tcg_temp_free_i32(t0
);
1024 tcg_temp_free_i32(t1
);
1025 tcg_temp_free_i32(t2
);
1026 tcg_temp_free_i32(t3
);
1028 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1029 gen_set_Rc0(ctx
, ret
);
1033 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
1034 static void glue(gen_, name)(DisasContext *ctx) \
1036 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1037 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1038 sign, compute_ov); \
1040 /* divwu divwu. divwuo divwuo. */
1041 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0);
1042 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1);
1043 /* divw divw. divwo divwo. */
1044 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0);
1045 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1);
1047 /* div[wd]eu[o][.] */
1048 #define GEN_DIVE(name, hlpr, compute_ov) \
1049 static void gen_##name(DisasContext *ctx) \
1051 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
1052 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
1053 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1054 tcg_temp_free_i32(t0); \
1055 if (unlikely(Rc(ctx->opcode) != 0)) { \
1056 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
1060 GEN_DIVE(divweu
, divweu
, 0);
1061 GEN_DIVE(divweuo
, divweu
, 1);
1062 GEN_DIVE(divwe
, divwe
, 0);
1063 GEN_DIVE(divweo
, divwe
, 1);
1065 #if defined(TARGET_PPC64)
1066 static inline void gen_op_arith_divd(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1067 TCGv arg2
, int sign
, int compute_ov
)
1069 TCGv_i64 t0
= tcg_temp_new_i64();
1070 TCGv_i64 t1
= tcg_temp_new_i64();
1071 TCGv_i64 t2
= tcg_temp_new_i64();
1072 TCGv_i64 t3
= tcg_temp_new_i64();
1074 tcg_gen_mov_i64(t0
, arg1
);
1075 tcg_gen_mov_i64(t1
, arg2
);
1077 tcg_gen_setcondi_i64(TCG_COND_EQ
, t2
, t0
, INT64_MIN
);
1078 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, -1);
1079 tcg_gen_and_i64(t2
, t2
, t3
);
1080 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, 0);
1081 tcg_gen_or_i64(t2
, t2
, t3
);
1082 tcg_gen_movi_i64(t3
, 0);
1083 tcg_gen_movcond_i64(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1084 tcg_gen_div_i64(ret
, t0
, t1
);
1086 tcg_gen_setcondi_i64(TCG_COND_EQ
, t2
, t1
, 0);
1087 tcg_gen_movi_i64(t3
, 0);
1088 tcg_gen_movcond_i64(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1089 tcg_gen_divu_i64(ret
, t0
, t1
);
1092 tcg_gen_mov_tl(cpu_ov
, t2
);
1093 if (is_isa300(ctx
)) {
1094 tcg_gen_mov_tl(cpu_ov32
, t2
);
1096 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1098 tcg_temp_free_i64(t0
);
1099 tcg_temp_free_i64(t1
);
1100 tcg_temp_free_i64(t2
);
1101 tcg_temp_free_i64(t3
);
1103 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1104 gen_set_Rc0(ctx
, ret
);
1108 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1109 static void glue(gen_, name)(DisasContext *ctx) \
1111 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1112 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1113 sign, compute_ov); \
1115 /* divdu divdu. divduo divduo. */
1116 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0);
1117 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1);
1118 /* divd divd. divdo divdo. */
1119 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0);
1120 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1);
1122 GEN_DIVE(divdeu
, divdeu
, 0);
1123 GEN_DIVE(divdeuo
, divdeu
, 1);
1124 GEN_DIVE(divde
, divde
, 0);
1125 GEN_DIVE(divdeo
, divde
, 1);
1128 static inline void gen_op_arith_modw(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1129 TCGv arg2
, int sign
)
1131 TCGv_i32 t0
= tcg_temp_new_i32();
1132 TCGv_i32 t1
= tcg_temp_new_i32();
1134 tcg_gen_trunc_tl_i32(t0
, arg1
);
1135 tcg_gen_trunc_tl_i32(t1
, arg2
);
1137 TCGv_i32 t2
= tcg_temp_new_i32();
1138 TCGv_i32 t3
= tcg_temp_new_i32();
1139 tcg_gen_setcondi_i32(TCG_COND_EQ
, t2
, t0
, INT_MIN
);
1140 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, -1);
1141 tcg_gen_and_i32(t2
, t2
, t3
);
1142 tcg_gen_setcondi_i32(TCG_COND_EQ
, t3
, t1
, 0);
1143 tcg_gen_or_i32(t2
, t2
, t3
);
1144 tcg_gen_movi_i32(t3
, 0);
1145 tcg_gen_movcond_i32(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1146 tcg_gen_rem_i32(t3
, t0
, t1
);
1147 tcg_gen_ext_i32_tl(ret
, t3
);
1148 tcg_temp_free_i32(t2
);
1149 tcg_temp_free_i32(t3
);
1151 TCGv_i32 t2
= tcg_const_i32(1);
1152 TCGv_i32 t3
= tcg_const_i32(0);
1153 tcg_gen_movcond_i32(TCG_COND_EQ
, t1
, t1
, t3
, t2
, t1
);
1154 tcg_gen_remu_i32(t3
, t0
, t1
);
1155 tcg_gen_extu_i32_tl(ret
, t3
);
1156 tcg_temp_free_i32(t2
);
1157 tcg_temp_free_i32(t3
);
1159 tcg_temp_free_i32(t0
);
1160 tcg_temp_free_i32(t1
);
1163 #define GEN_INT_ARITH_MODW(name, opc3, sign) \
1164 static void glue(gen_, name)(DisasContext *ctx) \
1166 gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \
1167 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1171 GEN_INT_ARITH_MODW(moduw
, 0x08, 0);
1172 GEN_INT_ARITH_MODW(modsw
, 0x18, 1);
1174 #if defined(TARGET_PPC64)
1175 static inline void gen_op_arith_modd(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1176 TCGv arg2
, int sign
)
1178 TCGv_i64 t0
= tcg_temp_new_i64();
1179 TCGv_i64 t1
= tcg_temp_new_i64();
1181 tcg_gen_mov_i64(t0
, arg1
);
1182 tcg_gen_mov_i64(t1
, arg2
);
1184 TCGv_i64 t2
= tcg_temp_new_i64();
1185 TCGv_i64 t3
= tcg_temp_new_i64();
1186 tcg_gen_setcondi_i64(TCG_COND_EQ
, t2
, t0
, INT64_MIN
);
1187 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, -1);
1188 tcg_gen_and_i64(t2
, t2
, t3
);
1189 tcg_gen_setcondi_i64(TCG_COND_EQ
, t3
, t1
, 0);
1190 tcg_gen_or_i64(t2
, t2
, t3
);
1191 tcg_gen_movi_i64(t3
, 0);
1192 tcg_gen_movcond_i64(TCG_COND_NE
, t1
, t2
, t3
, t2
, t1
);
1193 tcg_gen_rem_i64(ret
, t0
, t1
);
1194 tcg_temp_free_i64(t2
);
1195 tcg_temp_free_i64(t3
);
1197 TCGv_i64 t2
= tcg_const_i64(1);
1198 TCGv_i64 t3
= tcg_const_i64(0);
1199 tcg_gen_movcond_i64(TCG_COND_EQ
, t1
, t1
, t3
, t2
, t1
);
1200 tcg_gen_remu_i64(ret
, t0
, t1
);
1201 tcg_temp_free_i64(t2
);
1202 tcg_temp_free_i64(t3
);
1204 tcg_temp_free_i64(t0
);
1205 tcg_temp_free_i64(t1
);
1208 #define GEN_INT_ARITH_MODD(name, opc3, sign) \
1209 static void glue(gen_, name)(DisasContext *ctx) \
1211 gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \
1212 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1216 GEN_INT_ARITH_MODD(modud
, 0x08, 0);
1217 GEN_INT_ARITH_MODD(modsd
, 0x18, 1);
1221 static void gen_mulhw(DisasContext
*ctx
)
1223 TCGv_i32 t0
= tcg_temp_new_i32();
1224 TCGv_i32 t1
= tcg_temp_new_i32();
1226 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1227 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1228 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
1229 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
1230 tcg_temp_free_i32(t0
);
1231 tcg_temp_free_i32(t1
);
1232 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1233 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1237 /* mulhwu mulhwu. */
1238 static void gen_mulhwu(DisasContext
*ctx
)
1240 TCGv_i32 t0
= tcg_temp_new_i32();
1241 TCGv_i32 t1
= tcg_temp_new_i32();
1243 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1244 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1245 tcg_gen_mulu2_i32(t0
, t1
, t0
, t1
);
1246 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
1247 tcg_temp_free_i32(t0
);
1248 tcg_temp_free_i32(t1
);
1249 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1250 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1255 static void gen_mullw(DisasContext
*ctx
)
1257 #if defined(TARGET_PPC64)
1259 t0
= tcg_temp_new_i64();
1260 t1
= tcg_temp_new_i64();
1261 tcg_gen_ext32s_tl(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1262 tcg_gen_ext32s_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1263 tcg_gen_mul_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
1267 tcg_gen_mul_i32(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1268 cpu_gpr
[rB(ctx
->opcode
)]);
1270 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1271 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1275 /* mullwo mullwo. */
1276 static void gen_mullwo(DisasContext
*ctx
)
1278 TCGv_i32 t0
= tcg_temp_new_i32();
1279 TCGv_i32 t1
= tcg_temp_new_i32();
1281 tcg_gen_trunc_tl_i32(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
1282 tcg_gen_trunc_tl_i32(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
1283 tcg_gen_muls2_i32(t0
, t1
, t0
, t1
);
1284 #if defined(TARGET_PPC64)
1285 tcg_gen_concat_i32_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
, t1
);
1287 tcg_gen_mov_i32(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1290 tcg_gen_sari_i32(t0
, t0
, 31);
1291 tcg_gen_setcond_i32(TCG_COND_NE
, t0
, t0
, t1
);
1292 tcg_gen_extu_i32_tl(cpu_ov
, t0
);
1293 if (is_isa300(ctx
)) {
1294 tcg_gen_mov_tl(cpu_ov32
, cpu_ov
);
1296 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1298 tcg_temp_free_i32(t0
);
1299 tcg_temp_free_i32(t1
);
1300 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1301 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1306 static void gen_mulli(DisasContext
*ctx
)
1308 tcg_gen_muli_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1312 #if defined(TARGET_PPC64)
1314 static void gen_mulhd(DisasContext
*ctx
)
1316 TCGv lo
= tcg_temp_new();
1317 tcg_gen_muls2_tl(lo
, cpu_gpr
[rD(ctx
->opcode
)],
1318 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1320 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1321 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1325 /* mulhdu mulhdu. */
1326 static void gen_mulhdu(DisasContext
*ctx
)
1328 TCGv lo
= tcg_temp_new();
1329 tcg_gen_mulu2_tl(lo
, cpu_gpr
[rD(ctx
->opcode
)],
1330 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1332 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1333 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1338 static void gen_mulld(DisasContext
*ctx
)
1340 tcg_gen_mul_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1341 cpu_gpr
[rB(ctx
->opcode
)]);
1342 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1343 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1347 /* mulldo mulldo. */
1348 static void gen_mulldo(DisasContext
*ctx
)
1350 TCGv_i64 t0
= tcg_temp_new_i64();
1351 TCGv_i64 t1
= tcg_temp_new_i64();
1353 tcg_gen_muls2_i64(t0
, t1
, cpu_gpr
[rA(ctx
->opcode
)],
1354 cpu_gpr
[rB(ctx
->opcode
)]);
1355 tcg_gen_mov_i64(cpu_gpr
[rD(ctx
->opcode
)], t0
);
1357 tcg_gen_sari_i64(t0
, t0
, 63);
1358 tcg_gen_setcond_i64(TCG_COND_NE
, cpu_ov
, t0
, t1
);
1359 if (is_isa300(ctx
)) {
1360 tcg_gen_mov_tl(cpu_ov32
, cpu_ov
);
1362 tcg_gen_or_tl(cpu_so
, cpu_so
, cpu_ov
);
1364 tcg_temp_free_i64(t0
);
1365 tcg_temp_free_i64(t1
);
1367 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1368 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1373 /* Common subf function */
1374 static inline void gen_op_arith_subf(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
1375 TCGv arg2
, bool add_ca
, bool compute_ca
,
1376 bool compute_ov
, bool compute_rc0
)
1380 if (compute_ca
|| compute_ov
) {
1381 t0
= tcg_temp_new();
1385 /* dest = ~arg1 + arg2 [+ ca]. */
1386 if (NARROW_MODE(ctx
)) {
1388 * Caution: a non-obvious corner case of the spec is that
1389 * we must produce the *entire* 64-bit addition, but
1390 * produce the carry into bit 32.
1392 TCGv inv1
= tcg_temp_new();
1393 TCGv t1
= tcg_temp_new();
1394 tcg_gen_not_tl(inv1
, arg1
);
1396 tcg_gen_add_tl(t0
, arg2
, cpu_ca
);
1398 tcg_gen_addi_tl(t0
, arg2
, 1);
1400 tcg_gen_xor_tl(t1
, arg2
, inv1
); /* add without carry */
1401 tcg_gen_add_tl(t0
, t0
, inv1
);
1402 tcg_temp_free(inv1
);
1403 tcg_gen_xor_tl(cpu_ca
, t0
, t1
); /* bits changes w/ carry */
1405 tcg_gen_extract_tl(cpu_ca
, cpu_ca
, 32, 1);
1406 if (is_isa300(ctx
)) {
1407 tcg_gen_mov_tl(cpu_ca32
, cpu_ca
);
1409 } else if (add_ca
) {
1410 TCGv zero
, inv1
= tcg_temp_new();
1411 tcg_gen_not_tl(inv1
, arg1
);
1412 zero
= tcg_const_tl(0);
1413 tcg_gen_add2_tl(t0
, cpu_ca
, arg2
, zero
, cpu_ca
, zero
);
1414 tcg_gen_add2_tl(t0
, cpu_ca
, t0
, cpu_ca
, inv1
, zero
);
1415 gen_op_arith_compute_ca32(ctx
, t0
, inv1
, arg2
, cpu_ca32
, 0);
1416 tcg_temp_free(zero
);
1417 tcg_temp_free(inv1
);
1419 tcg_gen_setcond_tl(TCG_COND_GEU
, cpu_ca
, arg2
, arg1
);
1420 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1421 gen_op_arith_compute_ca32(ctx
, t0
, arg1
, arg2
, cpu_ca32
, 1);
1423 } else if (add_ca
) {
1425 * Since we're ignoring carry-out, we can simplify the
1426 * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1.
1428 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1429 tcg_gen_add_tl(t0
, t0
, cpu_ca
);
1430 tcg_gen_subi_tl(t0
, t0
, 1);
1432 tcg_gen_sub_tl(t0
, arg2
, arg1
);
1436 gen_op_arith_compute_ov(ctx
, t0
, arg1
, arg2
, 1);
1438 if (unlikely(compute_rc0
)) {
1439 gen_set_Rc0(ctx
, t0
);
1443 tcg_gen_mov_tl(ret
, t0
);
1447 /* Sub functions with Two operands functions */
1448 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1449 static void glue(gen_, name)(DisasContext *ctx) \
1451 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1452 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1453 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1455 /* Sub functions with one operand and one immediate */
1456 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1457 add_ca, compute_ca, compute_ov) \
1458 static void glue(gen_, name)(DisasContext *ctx) \
1460 TCGv t0 = tcg_const_tl(const_val); \
1461 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1462 cpu_gpr[rA(ctx->opcode)], t0, \
1463 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1464 tcg_temp_free(t0); \
1466 /* subf subf. subfo subfo. */
1467 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
1468 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
1469 /* subfc subfc. subfco subfco. */
1470 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
1471 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
1472 /* subfe subfe. subfeo subfo. */
1473 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
1474 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
1475 /* subfme subfme. subfmeo subfmeo. */
1476 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
1477 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
1478 /* subfze subfze. subfzeo subfzeo.*/
1479 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
1480 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
1483 static void gen_subfic(DisasContext
*ctx
)
1485 TCGv c
= tcg_const_tl(SIMM(ctx
->opcode
));
1486 gen_op_arith_subf(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1491 /* neg neg. nego nego. */
1492 static inline void gen_op_arith_neg(DisasContext
*ctx
, bool compute_ov
)
1494 TCGv zero
= tcg_const_tl(0);
1495 gen_op_arith_subf(ctx
, cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
1496 zero
, 0, 0, compute_ov
, Rc(ctx
->opcode
));
1497 tcg_temp_free(zero
);
1500 static void gen_neg(DisasContext
*ctx
)
1502 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
1503 if (unlikely(Rc(ctx
->opcode
))) {
1504 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
1508 static void gen_nego(DisasContext
*ctx
)
1510 gen_op_arith_neg(ctx
, 1);
1513 /*** Integer logical ***/
1514 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1515 static void glue(gen_, name)(DisasContext *ctx) \
1517 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1518 cpu_gpr[rB(ctx->opcode)]); \
1519 if (unlikely(Rc(ctx->opcode) != 0)) \
1520 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1523 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1524 static void glue(gen_, name)(DisasContext *ctx) \
1526 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1527 if (unlikely(Rc(ctx->opcode) != 0)) \
1528 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1532 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
);
1534 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
);
1537 static void gen_andi_(DisasContext
*ctx
)
1539 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
1541 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1545 static void gen_andis_(DisasContext
*ctx
)
1547 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
1548 UIMM(ctx
->opcode
) << 16);
1549 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1553 static void gen_cntlzw(DisasContext
*ctx
)
1555 TCGv_i32 t
= tcg_temp_new_i32();
1557 tcg_gen_trunc_tl_i32(t
, cpu_gpr
[rS(ctx
->opcode
)]);
1558 tcg_gen_clzi_i32(t
, t
, 32);
1559 tcg_gen_extu_i32_tl(cpu_gpr
[rA(ctx
->opcode
)], t
);
1560 tcg_temp_free_i32(t
);
1562 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1563 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1568 static void gen_cnttzw(DisasContext
*ctx
)
1570 TCGv_i32 t
= tcg_temp_new_i32();
1572 tcg_gen_trunc_tl_i32(t
, cpu_gpr
[rS(ctx
->opcode
)]);
1573 tcg_gen_ctzi_i32(t
, t
, 32);
1574 tcg_gen_extu_i32_tl(cpu_gpr
[rA(ctx
->opcode
)], t
);
1575 tcg_temp_free_i32(t
);
1577 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1578 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1583 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
);
1584 /* extsb & extsb. */
1585 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
);
1586 /* extsh & extsh. */
1587 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
);
1589 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
);
1591 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
);
1593 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1594 static void gen_pause(DisasContext
*ctx
)
1596 TCGv_i32 t0
= tcg_const_i32(0);
1597 tcg_gen_st_i32(t0
, cpu_env
,
1598 -offsetof(PowerPCCPU
, env
) + offsetof(CPUState
, halted
));
1599 tcg_temp_free_i32(t0
);
1601 /* Stop translation, this gives other CPUs a chance to run */
1602 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->base
.pc_next
);
1604 #endif /* defined(TARGET_PPC64) */
1607 static void gen_or(DisasContext
*ctx
)
1611 rs
= rS(ctx
->opcode
);
1612 ra
= rA(ctx
->opcode
);
1613 rb
= rB(ctx
->opcode
);
1614 /* Optimisation for mr. ri case */
1615 if (rs
!= ra
|| rs
!= rb
) {
1617 tcg_gen_or_tl(cpu_gpr
[ra
], cpu_gpr
[rs
], cpu_gpr
[rb
]);
1619 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rs
]);
1621 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1622 gen_set_Rc0(ctx
, cpu_gpr
[ra
]);
1624 } else if (unlikely(Rc(ctx
->opcode
) != 0)) {
1625 gen_set_Rc0(ctx
, cpu_gpr
[rs
]);
1626 #if defined(TARGET_PPC64)
1627 } else if (rs
!= 0) { /* 0 is nop */
1632 /* Set process priority to low */
1636 /* Set process priority to medium-low */
1640 /* Set process priority to normal */
1643 #if !defined(CONFIG_USER_ONLY)
1646 /* Set process priority to very low */
1652 /* Set process priority to medium-hight */
1658 /* Set process priority to high */
1663 if (ctx
->hv
&& !ctx
->pr
) {
1664 /* Set process priority to very high */
1673 TCGv t0
= tcg_temp_new();
1674 gen_load_spr(t0
, SPR_PPR
);
1675 tcg_gen_andi_tl(t0
, t0
, ~0x001C000000000000ULL
);
1676 tcg_gen_ori_tl(t0
, t0
, ((uint64_t)prio
) << 50);
1677 gen_store_spr(SPR_PPR
, t0
);
1680 #if !defined(CONFIG_USER_ONLY)
1682 * Pause out of TCG otherwise spin loops with smt_low eat too
1683 * much CPU and the kernel hangs. This applies to all
1684 * encodings other than no-op, e.g., miso(rs=26), yield(27),
1685 * mdoio(29), mdoom(30), and all currently undefined.
1693 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
);
1696 static void gen_xor(DisasContext
*ctx
)
1698 /* Optimisation for "set to zero" case */
1699 if (rS(ctx
->opcode
) != rB(ctx
->opcode
)) {
1700 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
1701 cpu_gpr
[rB(ctx
->opcode
)]);
1703 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
1705 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1706 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1711 static void gen_ori(DisasContext
*ctx
)
1713 target_ulong uimm
= UIMM(ctx
->opcode
);
1715 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1718 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1722 static void gen_oris(DisasContext
*ctx
)
1724 target_ulong uimm
= UIMM(ctx
->opcode
);
1726 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1730 tcg_gen_ori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
1735 static void gen_xori(DisasContext
*ctx
)
1737 target_ulong uimm
= UIMM(ctx
->opcode
);
1739 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1743 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], uimm
);
1747 static void gen_xoris(DisasContext
*ctx
)
1749 target_ulong uimm
= UIMM(ctx
->opcode
);
1751 if (rS(ctx
->opcode
) == rA(ctx
->opcode
) && uimm
== 0) {
1755 tcg_gen_xori_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)],
1759 /* popcntb : PowerPC 2.03 specification */
1760 static void gen_popcntb(DisasContext
*ctx
)
1762 gen_helper_popcntb(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1765 static void gen_popcntw(DisasContext
*ctx
)
1767 #if defined(TARGET_PPC64)
1768 gen_helper_popcntw(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1770 tcg_gen_ctpop_i32(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1774 #if defined(TARGET_PPC64)
1775 /* popcntd: PowerPC 2.06 specification */
1776 static void gen_popcntd(DisasContext
*ctx
)
1778 tcg_gen_ctpop_i64(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)]);
1782 /* prtyw: PowerPC 2.05 specification */
1783 static void gen_prtyw(DisasContext
*ctx
)
1785 TCGv ra
= cpu_gpr
[rA(ctx
->opcode
)];
1786 TCGv rs
= cpu_gpr
[rS(ctx
->opcode
)];
1787 TCGv t0
= tcg_temp_new();
1788 tcg_gen_shri_tl(t0
, rs
, 16);
1789 tcg_gen_xor_tl(ra
, rs
, t0
);
1790 tcg_gen_shri_tl(t0
, ra
, 8);
1791 tcg_gen_xor_tl(ra
, ra
, t0
);
1792 tcg_gen_andi_tl(ra
, ra
, (target_ulong
)0x100000001ULL
);
1796 #if defined(TARGET_PPC64)
1797 /* prtyd: PowerPC 2.05 specification */
1798 static void gen_prtyd(DisasContext
*ctx
)
1800 TCGv ra
= cpu_gpr
[rA(ctx
->opcode
)];
1801 TCGv rs
= cpu_gpr
[rS(ctx
->opcode
)];
1802 TCGv t0
= tcg_temp_new();
1803 tcg_gen_shri_tl(t0
, rs
, 32);
1804 tcg_gen_xor_tl(ra
, rs
, t0
);
1805 tcg_gen_shri_tl(t0
, ra
, 16);
1806 tcg_gen_xor_tl(ra
, ra
, t0
);
1807 tcg_gen_shri_tl(t0
, ra
, 8);
1808 tcg_gen_xor_tl(ra
, ra
, t0
);
1809 tcg_gen_andi_tl(ra
, ra
, 1);
1814 #if defined(TARGET_PPC64)
1816 static void gen_bpermd(DisasContext
*ctx
)
1818 gen_helper_bpermd(cpu_gpr
[rA(ctx
->opcode
)],
1819 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
1823 #if defined(TARGET_PPC64)
1824 /* extsw & extsw. */
1825 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
);
1828 static void gen_cntlzd(DisasContext
*ctx
)
1830 tcg_gen_clzi_i64(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], 64);
1831 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1832 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1837 static void gen_cnttzd(DisasContext
*ctx
)
1839 tcg_gen_ctzi_i64(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], 64);
1840 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1841 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
1846 static void gen_darn(DisasContext
*ctx
)
1848 int l
= L(ctx
->opcode
);
1851 gen_helper_darn32(cpu_gpr
[rD(ctx
->opcode
)]);
1852 } else if (l
<= 2) {
1853 /* Return 64-bit random for both CRN and RRN */
1854 gen_helper_darn64(cpu_gpr
[rD(ctx
->opcode
)]);
1856 tcg_gen_movi_i64(cpu_gpr
[rD(ctx
->opcode
)], -1);
1861 /*** Integer rotate ***/
1863 /* rlwimi & rlwimi. */
1864 static void gen_rlwimi(DisasContext
*ctx
)
1866 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1867 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1868 uint32_t sh
= SH(ctx
->opcode
);
1869 uint32_t mb
= MB(ctx
->opcode
);
1870 uint32_t me
= ME(ctx
->opcode
);
1872 if (sh
== (31 - me
) && mb
<= me
) {
1873 tcg_gen_deposit_tl(t_ra
, t_ra
, t_rs
, sh
, me
- mb
+ 1);
1878 #if defined(TARGET_PPC64)
1882 mask
= MASK(mb
, me
);
1884 t1
= tcg_temp_new();
1885 if (mask
<= 0xffffffffu
) {
1886 TCGv_i32 t0
= tcg_temp_new_i32();
1887 tcg_gen_trunc_tl_i32(t0
, t_rs
);
1888 tcg_gen_rotli_i32(t0
, t0
, sh
);
1889 tcg_gen_extu_i32_tl(t1
, t0
);
1890 tcg_temp_free_i32(t0
);
1892 #if defined(TARGET_PPC64)
1893 tcg_gen_deposit_i64(t1
, t_rs
, t_rs
, 32, 32);
1894 tcg_gen_rotli_i64(t1
, t1
, sh
);
1896 g_assert_not_reached();
1900 tcg_gen_andi_tl(t1
, t1
, mask
);
1901 tcg_gen_andi_tl(t_ra
, t_ra
, ~mask
);
1902 tcg_gen_or_tl(t_ra
, t_ra
, t1
);
1905 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1906 gen_set_Rc0(ctx
, t_ra
);
1910 /* rlwinm & rlwinm. */
1911 static void gen_rlwinm(DisasContext
*ctx
)
1913 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1914 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1915 int sh
= SH(ctx
->opcode
);
1916 int mb
= MB(ctx
->opcode
);
1917 int me
= ME(ctx
->opcode
);
1918 int len
= me
- mb
+ 1;
1919 int rsh
= (32 - sh
) & 31;
1921 if (sh
!= 0 && len
> 0 && me
== (31 - sh
)) {
1922 tcg_gen_deposit_z_tl(t_ra
, t_rs
, sh
, len
);
1923 } else if (me
== 31 && rsh
+ len
<= 32) {
1924 tcg_gen_extract_tl(t_ra
, t_rs
, rsh
, len
);
1927 #if defined(TARGET_PPC64)
1931 mask
= MASK(mb
, me
);
1933 tcg_gen_andi_tl(t_ra
, t_rs
, mask
);
1934 } else if (mask
<= 0xffffffffu
) {
1935 TCGv_i32 t0
= tcg_temp_new_i32();
1936 tcg_gen_trunc_tl_i32(t0
, t_rs
);
1937 tcg_gen_rotli_i32(t0
, t0
, sh
);
1938 tcg_gen_andi_i32(t0
, t0
, mask
);
1939 tcg_gen_extu_i32_tl(t_ra
, t0
);
1940 tcg_temp_free_i32(t0
);
1942 #if defined(TARGET_PPC64)
1943 tcg_gen_deposit_i64(t_ra
, t_rs
, t_rs
, 32, 32);
1944 tcg_gen_rotli_i64(t_ra
, t_ra
, sh
);
1945 tcg_gen_andi_i64(t_ra
, t_ra
, mask
);
1947 g_assert_not_reached();
1951 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1952 gen_set_Rc0(ctx
, t_ra
);
1956 /* rlwnm & rlwnm. */
1957 static void gen_rlwnm(DisasContext
*ctx
)
1959 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
1960 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
1961 TCGv t_rb
= cpu_gpr
[rB(ctx
->opcode
)];
1962 uint32_t mb
= MB(ctx
->opcode
);
1963 uint32_t me
= ME(ctx
->opcode
);
1966 #if defined(TARGET_PPC64)
1970 mask
= MASK(mb
, me
);
1972 if (mask
<= 0xffffffffu
) {
1973 TCGv_i32 t0
= tcg_temp_new_i32();
1974 TCGv_i32 t1
= tcg_temp_new_i32();
1975 tcg_gen_trunc_tl_i32(t0
, t_rb
);
1976 tcg_gen_trunc_tl_i32(t1
, t_rs
);
1977 tcg_gen_andi_i32(t0
, t0
, 0x1f);
1978 tcg_gen_rotl_i32(t1
, t1
, t0
);
1979 tcg_gen_extu_i32_tl(t_ra
, t1
);
1980 tcg_temp_free_i32(t0
);
1981 tcg_temp_free_i32(t1
);
1983 #if defined(TARGET_PPC64)
1984 TCGv_i64 t0
= tcg_temp_new_i64();
1985 tcg_gen_andi_i64(t0
, t_rb
, 0x1f);
1986 tcg_gen_deposit_i64(t_ra
, t_rs
, t_rs
, 32, 32);
1987 tcg_gen_rotl_i64(t_ra
, t_ra
, t0
);
1988 tcg_temp_free_i64(t0
);
1990 g_assert_not_reached();
1994 tcg_gen_andi_tl(t_ra
, t_ra
, mask
);
1996 if (unlikely(Rc(ctx
->opcode
) != 0)) {
1997 gen_set_Rc0(ctx
, t_ra
);
2001 #if defined(TARGET_PPC64)
2002 #define GEN_PPC64_R2(name, opc1, opc2) \
2003 static void glue(gen_, name##0)(DisasContext *ctx) \
2005 gen_##name(ctx, 0); \
2008 static void glue(gen_, name##1)(DisasContext *ctx) \
2010 gen_##name(ctx, 1); \
2012 #define GEN_PPC64_R4(name, opc1, opc2) \
2013 static void glue(gen_, name##0)(DisasContext *ctx) \
2015 gen_##name(ctx, 0, 0); \
2018 static void glue(gen_, name##1)(DisasContext *ctx) \
2020 gen_##name(ctx, 0, 1); \
2023 static void glue(gen_, name##2)(DisasContext *ctx) \
2025 gen_##name(ctx, 1, 0); \
2028 static void glue(gen_, name##3)(DisasContext *ctx) \
2030 gen_##name(ctx, 1, 1); \
2033 static void gen_rldinm(DisasContext
*ctx
, int mb
, int me
, int sh
)
2035 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
2036 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
2037 int len
= me
- mb
+ 1;
2038 int rsh
= (64 - sh
) & 63;
2040 if (sh
!= 0 && len
> 0 && me
== (63 - sh
)) {
2041 tcg_gen_deposit_z_tl(t_ra
, t_rs
, sh
, len
);
2042 } else if (me
== 63 && rsh
+ len
<= 64) {
2043 tcg_gen_extract_tl(t_ra
, t_rs
, rsh
, len
);
2045 tcg_gen_rotli_tl(t_ra
, t_rs
, sh
);
2046 tcg_gen_andi_tl(t_ra
, t_ra
, MASK(mb
, me
));
2048 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2049 gen_set_Rc0(ctx
, t_ra
);
2053 /* rldicl - rldicl. */
2054 static inline void gen_rldicl(DisasContext
*ctx
, int mbn
, int shn
)
2058 sh
= SH(ctx
->opcode
) | (shn
<< 5);
2059 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2060 gen_rldinm(ctx
, mb
, 63, sh
);
2062 GEN_PPC64_R4(rldicl
, 0x1E, 0x00);
2064 /* rldicr - rldicr. */
2065 static inline void gen_rldicr(DisasContext
*ctx
, int men
, int shn
)
2069 sh
= SH(ctx
->opcode
) | (shn
<< 5);
2070 me
= MB(ctx
->opcode
) | (men
<< 5);
2071 gen_rldinm(ctx
, 0, me
, sh
);
2073 GEN_PPC64_R4(rldicr
, 0x1E, 0x02);
2075 /* rldic - rldic. */
2076 static inline void gen_rldic(DisasContext
*ctx
, int mbn
, int shn
)
2080 sh
= SH(ctx
->opcode
) | (shn
<< 5);
2081 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2082 gen_rldinm(ctx
, mb
, 63 - sh
, sh
);
2084 GEN_PPC64_R4(rldic
, 0x1E, 0x04);
2086 static void gen_rldnm(DisasContext
*ctx
, int mb
, int me
)
2088 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
2089 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
2090 TCGv t_rb
= cpu_gpr
[rB(ctx
->opcode
)];
2093 t0
= tcg_temp_new();
2094 tcg_gen_andi_tl(t0
, t_rb
, 0x3f);
2095 tcg_gen_rotl_tl(t_ra
, t_rs
, t0
);
2098 tcg_gen_andi_tl(t_ra
, t_ra
, MASK(mb
, me
));
2099 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2100 gen_set_Rc0(ctx
, t_ra
);
2104 /* rldcl - rldcl. */
2105 static inline void gen_rldcl(DisasContext
*ctx
, int mbn
)
2109 mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2110 gen_rldnm(ctx
, mb
, 63);
2112 GEN_PPC64_R2(rldcl
, 0x1E, 0x08);
2114 /* rldcr - rldcr. */
2115 static inline void gen_rldcr(DisasContext
*ctx
, int men
)
2119 me
= MB(ctx
->opcode
) | (men
<< 5);
2120 gen_rldnm(ctx
, 0, me
);
2122 GEN_PPC64_R2(rldcr
, 0x1E, 0x09);
2124 /* rldimi - rldimi. */
2125 static void gen_rldimi(DisasContext
*ctx
, int mbn
, int shn
)
2127 TCGv t_ra
= cpu_gpr
[rA(ctx
->opcode
)];
2128 TCGv t_rs
= cpu_gpr
[rS(ctx
->opcode
)];
2129 uint32_t sh
= SH(ctx
->opcode
) | (shn
<< 5);
2130 uint32_t mb
= MB(ctx
->opcode
) | (mbn
<< 5);
2131 uint32_t me
= 63 - sh
;
2134 tcg_gen_deposit_tl(t_ra
, t_ra
, t_rs
, sh
, me
- mb
+ 1);
2136 target_ulong mask
= MASK(mb
, me
);
2137 TCGv t1
= tcg_temp_new();
2139 tcg_gen_rotli_tl(t1
, t_rs
, sh
);
2140 tcg_gen_andi_tl(t1
, t1
, mask
);
2141 tcg_gen_andi_tl(t_ra
, t_ra
, ~mask
);
2142 tcg_gen_or_tl(t_ra
, t_ra
, t1
);
2145 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2146 gen_set_Rc0(ctx
, t_ra
);
2149 GEN_PPC64_R4(rldimi
, 0x1E, 0x06);
2152 /*** Integer shift ***/
2155 static void gen_slw(DisasContext
*ctx
)
2159 t0
= tcg_temp_new();
2160 /* AND rS with a mask that is 0 when rB >= 0x20 */
2161 #if defined(TARGET_PPC64)
2162 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
2163 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2165 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
2166 tcg_gen_sari_tl(t0
, t0
, 0x1f);
2168 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2169 t1
= tcg_temp_new();
2170 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
2171 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2174 tcg_gen_ext32u_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
2175 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2176 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2181 static void gen_sraw(DisasContext
*ctx
)
2183 gen_helper_sraw(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
2184 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2185 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2186 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2190 /* srawi & srawi. */
2191 static void gen_srawi(DisasContext
*ctx
)
2193 int sh
= SH(ctx
->opcode
);
2194 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
2195 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
2197 tcg_gen_ext32s_tl(dst
, src
);
2198 tcg_gen_movi_tl(cpu_ca
, 0);
2199 if (is_isa300(ctx
)) {
2200 tcg_gen_movi_tl(cpu_ca32
, 0);
2204 tcg_gen_ext32s_tl(dst
, src
);
2205 tcg_gen_andi_tl(cpu_ca
, dst
, (1ULL << sh
) - 1);
2206 t0
= tcg_temp_new();
2207 tcg_gen_sari_tl(t0
, dst
, TARGET_LONG_BITS
- 1);
2208 tcg_gen_and_tl(cpu_ca
, cpu_ca
, t0
);
2210 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_ca
, cpu_ca
, 0);
2211 if (is_isa300(ctx
)) {
2212 tcg_gen_mov_tl(cpu_ca32
, cpu_ca
);
2214 tcg_gen_sari_tl(dst
, dst
, sh
);
2216 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2217 gen_set_Rc0(ctx
, dst
);
2222 static void gen_srw(DisasContext
*ctx
)
2226 t0
= tcg_temp_new();
2227 /* AND rS with a mask that is 0 when rB >= 0x20 */
2228 #if defined(TARGET_PPC64)
2229 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x3a);
2230 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2232 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1a);
2233 tcg_gen_sari_tl(t0
, t0
, 0x1f);
2235 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2236 tcg_gen_ext32u_tl(t0
, t0
);
2237 t1
= tcg_temp_new();
2238 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1f);
2239 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2242 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2243 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2247 #if defined(TARGET_PPC64)
2249 static void gen_sld(DisasContext
*ctx
)
2253 t0
= tcg_temp_new();
2254 /* AND rS with a mask that is 0 when rB >= 0x40 */
2255 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
2256 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2257 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2258 t1
= tcg_temp_new();
2259 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
2260 tcg_gen_shl_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2263 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2264 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2269 static void gen_srad(DisasContext
*ctx
)
2271 gen_helper_srad(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
2272 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2273 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2274 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2277 /* sradi & sradi. */
2278 static inline void gen_sradi(DisasContext
*ctx
, int n
)
2280 int sh
= SH(ctx
->opcode
) + (n
<< 5);
2281 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
2282 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
2284 tcg_gen_mov_tl(dst
, src
);
2285 tcg_gen_movi_tl(cpu_ca
, 0);
2286 if (is_isa300(ctx
)) {
2287 tcg_gen_movi_tl(cpu_ca32
, 0);
2291 tcg_gen_andi_tl(cpu_ca
, src
, (1ULL << sh
) - 1);
2292 t0
= tcg_temp_new();
2293 tcg_gen_sari_tl(t0
, src
, TARGET_LONG_BITS
- 1);
2294 tcg_gen_and_tl(cpu_ca
, cpu_ca
, t0
);
2296 tcg_gen_setcondi_tl(TCG_COND_NE
, cpu_ca
, cpu_ca
, 0);
2297 if (is_isa300(ctx
)) {
2298 tcg_gen_mov_tl(cpu_ca32
, cpu_ca
);
2300 tcg_gen_sari_tl(dst
, src
, sh
);
2302 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2303 gen_set_Rc0(ctx
, dst
);
2307 static void gen_sradi0(DisasContext
*ctx
)
2312 static void gen_sradi1(DisasContext
*ctx
)
2317 /* extswsli & extswsli. */
2318 static inline void gen_extswsli(DisasContext
*ctx
, int n
)
2320 int sh
= SH(ctx
->opcode
) + (n
<< 5);
2321 TCGv dst
= cpu_gpr
[rA(ctx
->opcode
)];
2322 TCGv src
= cpu_gpr
[rS(ctx
->opcode
)];
2324 tcg_gen_ext32s_tl(dst
, src
);
2325 tcg_gen_shli_tl(dst
, dst
, sh
);
2326 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2327 gen_set_Rc0(ctx
, dst
);
2331 static void gen_extswsli0(DisasContext
*ctx
)
2333 gen_extswsli(ctx
, 0);
2336 static void gen_extswsli1(DisasContext
*ctx
)
2338 gen_extswsli(ctx
, 1);
2342 static void gen_srd(DisasContext
*ctx
)
2346 t0
= tcg_temp_new();
2347 /* AND rS with a mask that is 0 when rB >= 0x40 */
2348 tcg_gen_shli_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x39);
2349 tcg_gen_sari_tl(t0
, t0
, 0x3f);
2350 tcg_gen_andc_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
2351 t1
= tcg_temp_new();
2352 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x3f);
2353 tcg_gen_shr_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
2356 if (unlikely(Rc(ctx
->opcode
) != 0)) {
2357 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
2362 /*** Addressing modes ***/
2363 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2364 static inline void gen_addr_imm_index(DisasContext
*ctx
, TCGv EA
,
2367 target_long simm
= SIMM(ctx
->opcode
);
2370 if (rA(ctx
->opcode
) == 0) {
2371 if (NARROW_MODE(ctx
)) {
2372 simm
= (uint32_t)simm
;
2374 tcg_gen_movi_tl(EA
, simm
);
2375 } else if (likely(simm
!= 0)) {
2376 tcg_gen_addi_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], simm
);
2377 if (NARROW_MODE(ctx
)) {
2378 tcg_gen_ext32u_tl(EA
, EA
);
2381 if (NARROW_MODE(ctx
)) {
2382 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2384 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2389 static inline void gen_addr_reg_index(DisasContext
*ctx
, TCGv EA
)
2391 if (rA(ctx
->opcode
) == 0) {
2392 if (NARROW_MODE(ctx
)) {
2393 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2395 tcg_gen_mov_tl(EA
, cpu_gpr
[rB(ctx
->opcode
)]);
2398 tcg_gen_add_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
2399 if (NARROW_MODE(ctx
)) {
2400 tcg_gen_ext32u_tl(EA
, EA
);
2405 static inline void gen_addr_register(DisasContext
*ctx
, TCGv EA
)
2407 if (rA(ctx
->opcode
) == 0) {
2408 tcg_gen_movi_tl(EA
, 0);
2409 } else if (NARROW_MODE(ctx
)) {
2410 tcg_gen_ext32u_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2412 tcg_gen_mov_tl(EA
, cpu_gpr
[rA(ctx
->opcode
)]);
2416 static inline void gen_addr_add(DisasContext
*ctx
, TCGv ret
, TCGv arg1
,
2419 tcg_gen_addi_tl(ret
, arg1
, val
);
2420 if (NARROW_MODE(ctx
)) {
2421 tcg_gen_ext32u_tl(ret
, ret
);
2425 static inline void gen_align_no_le(DisasContext
*ctx
)
2427 gen_exception_err(ctx
, POWERPC_EXCP_ALIGN
,
2428 (ctx
->opcode
& 0x03FF0000) | POWERPC_EXCP_ALIGN_LE
);
2431 /*** Integer load ***/
2432 #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask)
2433 #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP))
2435 #define GEN_QEMU_LOAD_TL(ldop, op) \
2436 static void glue(gen_qemu_, ldop)(DisasContext *ctx, \
2440 tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \
2443 GEN_QEMU_LOAD_TL(ld8u
, DEF_MEMOP(MO_UB
))
2444 GEN_QEMU_LOAD_TL(ld16u
, DEF_MEMOP(MO_UW
))
2445 GEN_QEMU_LOAD_TL(ld16s
, DEF_MEMOP(MO_SW
))
2446 GEN_QEMU_LOAD_TL(ld32u
, DEF_MEMOP(MO_UL
))
2447 GEN_QEMU_LOAD_TL(ld32s
, DEF_MEMOP(MO_SL
))
2449 GEN_QEMU_LOAD_TL(ld16ur
, BSWAP_MEMOP(MO_UW
))
2450 GEN_QEMU_LOAD_TL(ld32ur
, BSWAP_MEMOP(MO_UL
))
2452 #define GEN_QEMU_LOAD_64(ldop, op) \
2453 static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \
2457 tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \
2460 GEN_QEMU_LOAD_64(ld8u
, DEF_MEMOP(MO_UB
))
2461 GEN_QEMU_LOAD_64(ld16u
, DEF_MEMOP(MO_UW
))
2462 GEN_QEMU_LOAD_64(ld32u
, DEF_MEMOP(MO_UL
))
2463 GEN_QEMU_LOAD_64(ld32s
, DEF_MEMOP(MO_SL
))
2464 GEN_QEMU_LOAD_64(ld64
, DEF_MEMOP(MO_Q
))
2466 #if defined(TARGET_PPC64)
2467 GEN_QEMU_LOAD_64(ld64ur
, BSWAP_MEMOP(MO_Q
))
2470 #define GEN_QEMU_STORE_TL(stop, op) \
2471 static void glue(gen_qemu_, stop)(DisasContext *ctx, \
2475 tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \
2478 GEN_QEMU_STORE_TL(st8
, DEF_MEMOP(MO_UB
))
2479 GEN_QEMU_STORE_TL(st16
, DEF_MEMOP(MO_UW
))
2480 GEN_QEMU_STORE_TL(st32
, DEF_MEMOP(MO_UL
))
2482 GEN_QEMU_STORE_TL(st16r
, BSWAP_MEMOP(MO_UW
))
2483 GEN_QEMU_STORE_TL(st32r
, BSWAP_MEMOP(MO_UL
))
2485 #define GEN_QEMU_STORE_64(stop, op) \
2486 static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \
2490 tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \
2493 GEN_QEMU_STORE_64(st8
, DEF_MEMOP(MO_UB
))
2494 GEN_QEMU_STORE_64(st16
, DEF_MEMOP(MO_UW
))
2495 GEN_QEMU_STORE_64(st32
, DEF_MEMOP(MO_UL
))
2496 GEN_QEMU_STORE_64(st64
, DEF_MEMOP(MO_Q
))
2498 #if defined(TARGET_PPC64)
2499 GEN_QEMU_STORE_64(st64r
, BSWAP_MEMOP(MO_Q
))
2502 #define GEN_LD(name, ldop, opc, type) \
2503 static void glue(gen_, name)(DisasContext *ctx) \
2506 gen_set_access_type(ctx, ACCESS_INT); \
2507 EA = tcg_temp_new(); \
2508 gen_addr_imm_index(ctx, EA, 0); \
2509 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2510 tcg_temp_free(EA); \
2513 #define GEN_LDU(name, ldop, opc, type) \
2514 static void glue(gen_, name##u)(DisasContext *ctx) \
2517 if (unlikely(rA(ctx->opcode) == 0 || \
2518 rA(ctx->opcode) == rD(ctx->opcode))) { \
2519 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2522 gen_set_access_type(ctx, ACCESS_INT); \
2523 EA = tcg_temp_new(); \
2524 if (type == PPC_64B) \
2525 gen_addr_imm_index(ctx, EA, 0x03); \
2527 gen_addr_imm_index(ctx, EA, 0); \
2528 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2529 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2530 tcg_temp_free(EA); \
2533 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2534 static void glue(gen_, name##ux)(DisasContext *ctx) \
2537 if (unlikely(rA(ctx->opcode) == 0 || \
2538 rA(ctx->opcode) == rD(ctx->opcode))) { \
2539 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2542 gen_set_access_type(ctx, ACCESS_INT); \
2543 EA = tcg_temp_new(); \
2544 gen_addr_reg_index(ctx, EA); \
2545 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2546 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2547 tcg_temp_free(EA); \
2550 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
2551 static void glue(gen_, name##x)(DisasContext *ctx) \
2555 gen_set_access_type(ctx, ACCESS_INT); \
2556 EA = tcg_temp_new(); \
2557 gen_addr_reg_index(ctx, EA); \
2558 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2559 tcg_temp_free(EA); \
2562 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2563 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2565 #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \
2566 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2568 #define GEN_LDS(name, ldop, op, type) \
2569 GEN_LD(name, ldop, op | 0x20, type); \
2570 GEN_LDU(name, ldop, op | 0x21, type); \
2571 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2572 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2574 /* lbz lbzu lbzux lbzx */
2575 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
);
2576 /* lha lhau lhaux lhax */
2577 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
);
2578 /* lhz lhzu lhzux lhzx */
2579 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
);
2580 /* lwz lwzu lwzux lwzx */
2581 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
);
2583 #define GEN_LDEPX(name, ldop, opc2, opc3) \
2584 static void glue(gen_, name##epx)(DisasContext *ctx) \
2588 gen_set_access_type(ctx, ACCESS_INT); \
2589 EA = tcg_temp_new(); \
2590 gen_addr_reg_index(ctx, EA); \
2591 tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\
2592 tcg_temp_free(EA); \
2595 GEN_LDEPX(lb
, DEF_MEMOP(MO_UB
), 0x1F, 0x02)
2596 GEN_LDEPX(lh
, DEF_MEMOP(MO_UW
), 0x1F, 0x08)
2597 GEN_LDEPX(lw
, DEF_MEMOP(MO_UL
), 0x1F, 0x00)
2598 #if defined(TARGET_PPC64)
2599 GEN_LDEPX(ld
, DEF_MEMOP(MO_Q
), 0x1D, 0x00)
2602 #if defined(TARGET_PPC64)
2604 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
);
2606 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
);
2608 GEN_LDUX(ld
, ld64_i64
, 0x15, 0x01, PPC_64B
);
2610 GEN_LDX(ld
, ld64_i64
, 0x15, 0x00, PPC_64B
);
2612 /* CI load/store variants */
2613 GEN_LDX_HVRM(ldcix
, ld64_i64
, 0x15, 0x1b, PPC_CILDST
)
2614 GEN_LDX_HVRM(lwzcix
, ld32u
, 0x15, 0x15, PPC_CILDST
)
2615 GEN_LDX_HVRM(lhzcix
, ld16u
, 0x15, 0x19, PPC_CILDST
)
2616 GEN_LDX_HVRM(lbzcix
, ld8u
, 0x15, 0x1a, PPC_CILDST
)
2618 static void gen_ld(DisasContext
*ctx
)
2621 if (Rc(ctx
->opcode
)) {
2622 if (unlikely(rA(ctx
->opcode
) == 0 ||
2623 rA(ctx
->opcode
) == rD(ctx
->opcode
))) {
2624 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2628 gen_set_access_type(ctx
, ACCESS_INT
);
2629 EA
= tcg_temp_new();
2630 gen_addr_imm_index(ctx
, EA
, 0x03);
2631 if (ctx
->opcode
& 0x02) {
2632 /* lwa (lwau is undefined) */
2633 gen_qemu_ld32s(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2636 gen_qemu_ld64_i64(ctx
, cpu_gpr
[rD(ctx
->opcode
)], EA
);
2638 if (Rc(ctx
->opcode
)) {
2639 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2645 static void gen_lq(DisasContext
*ctx
)
2650 /* lq is a legal user mode instruction starting in ISA 2.07 */
2651 bool legal_in_user_mode
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2652 bool le_is_supported
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2654 if (!legal_in_user_mode
&& ctx
->pr
) {
2655 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2659 if (!le_is_supported
&& ctx
->le_mode
) {
2660 gen_align_no_le(ctx
);
2663 ra
= rA(ctx
->opcode
);
2664 rd
= rD(ctx
->opcode
);
2665 if (unlikely((rd
& 1) || rd
== ra
)) {
2666 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2670 gen_set_access_type(ctx
, ACCESS_INT
);
2671 EA
= tcg_temp_new();
2672 gen_addr_imm_index(ctx
, EA
, 0x0F);
2674 /* Note that the low part is always in RD+1, even in LE mode. */
2675 lo
= cpu_gpr
[rd
+ 1];
2678 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
2679 if (HAVE_ATOMIC128
) {
2680 TCGv_i32 oi
= tcg_temp_new_i32();
2682 tcg_gen_movi_i32(oi
, make_memop_idx(MO_LEQ
, ctx
->mem_idx
));
2683 gen_helper_lq_le_parallel(lo
, cpu_env
, EA
, oi
);
2685 tcg_gen_movi_i32(oi
, make_memop_idx(MO_BEQ
, ctx
->mem_idx
));
2686 gen_helper_lq_be_parallel(lo
, cpu_env
, EA
, oi
);
2688 tcg_temp_free_i32(oi
);
2689 tcg_gen_ld_i64(hi
, cpu_env
, offsetof(CPUPPCState
, retxh
));
2691 /* Restart with exclusive lock. */
2692 gen_helper_exit_atomic(cpu_env
);
2693 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2695 } else if (ctx
->le_mode
) {
2696 tcg_gen_qemu_ld_i64(lo
, EA
, ctx
->mem_idx
, MO_LEQ
);
2697 gen_addr_add(ctx
, EA
, EA
, 8);
2698 tcg_gen_qemu_ld_i64(hi
, EA
, ctx
->mem_idx
, MO_LEQ
);
2700 tcg_gen_qemu_ld_i64(hi
, EA
, ctx
->mem_idx
, MO_BEQ
);
2701 gen_addr_add(ctx
, EA
, EA
, 8);
2702 tcg_gen_qemu_ld_i64(lo
, EA
, ctx
->mem_idx
, MO_BEQ
);
2708 /*** Integer store ***/
2709 #define GEN_ST(name, stop, opc, type) \
2710 static void glue(gen_, name)(DisasContext *ctx) \
2713 gen_set_access_type(ctx, ACCESS_INT); \
2714 EA = tcg_temp_new(); \
2715 gen_addr_imm_index(ctx, EA, 0); \
2716 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2717 tcg_temp_free(EA); \
2720 #define GEN_STU(name, stop, opc, type) \
2721 static void glue(gen_, stop##u)(DisasContext *ctx) \
2724 if (unlikely(rA(ctx->opcode) == 0)) { \
2725 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2728 gen_set_access_type(ctx, ACCESS_INT); \
2729 EA = tcg_temp_new(); \
2730 if (type == PPC_64B) \
2731 gen_addr_imm_index(ctx, EA, 0x03); \
2733 gen_addr_imm_index(ctx, EA, 0); \
2734 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2735 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2736 tcg_temp_free(EA); \
2739 #define GEN_STUX(name, stop, opc2, opc3, type) \
2740 static void glue(gen_, name##ux)(DisasContext *ctx) \
2743 if (unlikely(rA(ctx->opcode) == 0)) { \
2744 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2747 gen_set_access_type(ctx, ACCESS_INT); \
2748 EA = tcg_temp_new(); \
2749 gen_addr_reg_index(ctx, EA); \
2750 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2751 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2752 tcg_temp_free(EA); \
2755 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
2756 static void glue(gen_, name##x)(DisasContext *ctx) \
2760 gen_set_access_type(ctx, ACCESS_INT); \
2761 EA = tcg_temp_new(); \
2762 gen_addr_reg_index(ctx, EA); \
2763 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2764 tcg_temp_free(EA); \
2766 #define GEN_STX(name, stop, opc2, opc3, type) \
2767 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE)
2769 #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \
2770 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM)
2772 #define GEN_STS(name, stop, op, type) \
2773 GEN_ST(name, stop, op | 0x20, type); \
2774 GEN_STU(name, stop, op | 0x21, type); \
2775 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2776 GEN_STX(name, stop, 0x17, op | 0x00, type)
2778 /* stb stbu stbux stbx */
2779 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
);
2780 /* sth sthu sthux sthx */
2781 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
);
2782 /* stw stwu stwux stwx */
2783 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
);
2785 #define GEN_STEPX(name, stop, opc2, opc3) \
2786 static void glue(gen_, name##epx)(DisasContext *ctx) \
2790 gen_set_access_type(ctx, ACCESS_INT); \
2791 EA = tcg_temp_new(); \
2792 gen_addr_reg_index(ctx, EA); \
2793 tcg_gen_qemu_st_tl( \
2794 cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \
2795 tcg_temp_free(EA); \
2798 GEN_STEPX(stb
, DEF_MEMOP(MO_UB
), 0x1F, 0x06)
2799 GEN_STEPX(sth
, DEF_MEMOP(MO_UW
), 0x1F, 0x0C)
2800 GEN_STEPX(stw
, DEF_MEMOP(MO_UL
), 0x1F, 0x04)
2801 #if defined(TARGET_PPC64)
2802 GEN_STEPX(std
, DEF_MEMOP(MO_Q
), 0x1d, 0x04)
2805 #if defined(TARGET_PPC64)
2806 GEN_STUX(std
, st64_i64
, 0x15, 0x05, PPC_64B
);
2807 GEN_STX(std
, st64_i64
, 0x15, 0x04, PPC_64B
);
2808 GEN_STX_HVRM(stdcix
, st64_i64
, 0x15, 0x1f, PPC_CILDST
)
2809 GEN_STX_HVRM(stwcix
, st32
, 0x15, 0x1c, PPC_CILDST
)
2810 GEN_STX_HVRM(sthcix
, st16
, 0x15, 0x1d, PPC_CILDST
)
2811 GEN_STX_HVRM(stbcix
, st8
, 0x15, 0x1e, PPC_CILDST
)
2813 static void gen_std(DisasContext
*ctx
)
2818 rs
= rS(ctx
->opcode
);
2819 if ((ctx
->opcode
& 0x3) == 0x2) { /* stq */
2820 bool legal_in_user_mode
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2821 bool le_is_supported
= (ctx
->insns_flags2
& PPC2_LSQ_ISA207
) != 0;
2824 if (!(ctx
->insns_flags
& PPC_64BX
)) {
2825 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2828 if (!legal_in_user_mode
&& ctx
->pr
) {
2829 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_OPC
);
2833 if (!le_is_supported
&& ctx
->le_mode
) {
2834 gen_align_no_le(ctx
);
2838 if (unlikely(rs
& 1)) {
2839 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2842 gen_set_access_type(ctx
, ACCESS_INT
);
2843 EA
= tcg_temp_new();
2844 gen_addr_imm_index(ctx
, EA
, 0x03);
2846 /* Note that the low part is always in RS+1, even in LE mode. */
2847 lo
= cpu_gpr
[rs
+ 1];
2850 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
2851 if (HAVE_ATOMIC128
) {
2852 TCGv_i32 oi
= tcg_temp_new_i32();
2854 tcg_gen_movi_i32(oi
, make_memop_idx(MO_LEQ
, ctx
->mem_idx
));
2855 gen_helper_stq_le_parallel(cpu_env
, EA
, lo
, hi
, oi
);
2857 tcg_gen_movi_i32(oi
, make_memop_idx(MO_BEQ
, ctx
->mem_idx
));
2858 gen_helper_stq_be_parallel(cpu_env
, EA
, lo
, hi
, oi
);
2860 tcg_temp_free_i32(oi
);
2862 /* Restart with exclusive lock. */
2863 gen_helper_exit_atomic(cpu_env
);
2864 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2866 } else if (ctx
->le_mode
) {
2867 tcg_gen_qemu_st_i64(lo
, EA
, ctx
->mem_idx
, MO_LEQ
);
2868 gen_addr_add(ctx
, EA
, EA
, 8);
2869 tcg_gen_qemu_st_i64(hi
, EA
, ctx
->mem_idx
, MO_LEQ
);
2871 tcg_gen_qemu_st_i64(hi
, EA
, ctx
->mem_idx
, MO_BEQ
);
2872 gen_addr_add(ctx
, EA
, EA
, 8);
2873 tcg_gen_qemu_st_i64(lo
, EA
, ctx
->mem_idx
, MO_BEQ
);
2878 if (Rc(ctx
->opcode
)) {
2879 if (unlikely(rA(ctx
->opcode
) == 0)) {
2880 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
2884 gen_set_access_type(ctx
, ACCESS_INT
);
2885 EA
= tcg_temp_new();
2886 gen_addr_imm_index(ctx
, EA
, 0x03);
2887 gen_qemu_st64_i64(ctx
, cpu_gpr
[rs
], EA
);
2888 if (Rc(ctx
->opcode
)) {
2889 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], EA
);
2895 /*** Integer load and store with byte reverse ***/
2898 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
);
2901 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
);
2903 #if defined(TARGET_PPC64)
2905 GEN_LDX_E(ldbr
, ld64ur_i64
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
, CHK_NONE
);
2907 GEN_STX_E(stdbr
, st64r_i64
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
, CHK_NONE
);
2908 #endif /* TARGET_PPC64 */
2911 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
);
2913 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
);
2915 /*** Integer load and store multiple ***/
2918 static void gen_lmw(DisasContext
*ctx
)
2924 gen_align_no_le(ctx
);
2927 gen_set_access_type(ctx
, ACCESS_INT
);
2928 t0
= tcg_temp_new();
2929 t1
= tcg_const_i32(rD(ctx
->opcode
));
2930 gen_addr_imm_index(ctx
, t0
, 0);
2931 gen_helper_lmw(cpu_env
, t0
, t1
);
2933 tcg_temp_free_i32(t1
);
2937 static void gen_stmw(DisasContext
*ctx
)
2943 gen_align_no_le(ctx
);
2946 gen_set_access_type(ctx
, ACCESS_INT
);
2947 t0
= tcg_temp_new();
2948 t1
= tcg_const_i32(rS(ctx
->opcode
));
2949 gen_addr_imm_index(ctx
, t0
, 0);
2950 gen_helper_stmw(cpu_env
, t0
, t1
);
2952 tcg_temp_free_i32(t1
);
2955 /*** Integer load and store strings ***/
2959 * PowerPC32 specification says we must generate an exception if rA is
2960 * in the range of registers to be loaded. In an other hand, IBM says
2961 * this is valid, but rA won't be loaded. For now, I'll follow the
2964 static void gen_lswi(DisasContext
*ctx
)
2968 int nb
= NB(ctx
->opcode
);
2969 int start
= rD(ctx
->opcode
);
2970 int ra
= rA(ctx
->opcode
);
2974 gen_align_no_le(ctx
);
2980 nr
= DIV_ROUND_UP(nb
, 4);
2981 if (unlikely(lsw_reg_in_range(start
, nr
, ra
))) {
2982 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_LSWX
);
2985 gen_set_access_type(ctx
, ACCESS_INT
);
2986 t0
= tcg_temp_new();
2987 gen_addr_register(ctx
, t0
);
2988 t1
= tcg_const_i32(nb
);
2989 t2
= tcg_const_i32(start
);
2990 gen_helper_lsw(cpu_env
, t0
, t1
, t2
);
2992 tcg_temp_free_i32(t1
);
2993 tcg_temp_free_i32(t2
);
2997 static void gen_lswx(DisasContext
*ctx
)
3000 TCGv_i32 t1
, t2
, t3
;
3003 gen_align_no_le(ctx
);
3006 gen_set_access_type(ctx
, ACCESS_INT
);
3007 t0
= tcg_temp_new();
3008 gen_addr_reg_index(ctx
, t0
);
3009 t1
= tcg_const_i32(rD(ctx
->opcode
));
3010 t2
= tcg_const_i32(rA(ctx
->opcode
));
3011 t3
= tcg_const_i32(rB(ctx
->opcode
));
3012 gen_helper_lswx(cpu_env
, t0
, t1
, t2
, t3
);
3014 tcg_temp_free_i32(t1
);
3015 tcg_temp_free_i32(t2
);
3016 tcg_temp_free_i32(t3
);
3020 static void gen_stswi(DisasContext
*ctx
)
3024 int nb
= NB(ctx
->opcode
);
3027 gen_align_no_le(ctx
);
3030 gen_set_access_type(ctx
, ACCESS_INT
);
3031 t0
= tcg_temp_new();
3032 gen_addr_register(ctx
, t0
);
3036 t1
= tcg_const_i32(nb
);
3037 t2
= tcg_const_i32(rS(ctx
->opcode
));
3038 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
3040 tcg_temp_free_i32(t1
);
3041 tcg_temp_free_i32(t2
);
3045 static void gen_stswx(DisasContext
*ctx
)
3051 gen_align_no_le(ctx
);
3054 gen_set_access_type(ctx
, ACCESS_INT
);
3055 t0
= tcg_temp_new();
3056 gen_addr_reg_index(ctx
, t0
);
3057 t1
= tcg_temp_new_i32();
3058 tcg_gen_trunc_tl_i32(t1
, cpu_xer
);
3059 tcg_gen_andi_i32(t1
, t1
, 0x7F);
3060 t2
= tcg_const_i32(rS(ctx
->opcode
));
3061 gen_helper_stsw(cpu_env
, t0
, t1
, t2
);
3063 tcg_temp_free_i32(t1
);
3064 tcg_temp_free_i32(t2
);
3067 /*** Memory synchronisation ***/
3069 static void gen_eieio(DisasContext
*ctx
)
3071 TCGBar bar
= TCG_MO_LD_ST
;
3074 * POWER9 has a eieio instruction variant using bit 6 as a hint to
3075 * tell the CPU it is a store-forwarding barrier.
3077 if (ctx
->opcode
& 0x2000000) {
3079 * ISA says that "Reserved fields in instructions are ignored
3080 * by the processor". So ignore the bit 6 on non-POWER9 CPU but
3081 * as this is not an instruction software should be using,
3082 * complain to the user.
3084 if (!(ctx
->insns_flags2
& PPC2_ISA300
)) {
3085 qemu_log_mask(LOG_GUEST_ERROR
, "invalid eieio using bit 6 at @"
3086 TARGET_FMT_lx
"\n", ctx
->base
.pc_next
- 4);
3092 tcg_gen_mb(bar
| TCG_BAR_SC
);
3095 #if !defined(CONFIG_USER_ONLY)
3096 static inline void gen_check_tlb_flush(DisasContext
*ctx
, bool global
)
3101 if (!ctx
->lazy_tlb_flush
) {
3104 l
= gen_new_label();
3105 t
= tcg_temp_new_i32();
3106 tcg_gen_ld_i32(t
, cpu_env
, offsetof(CPUPPCState
, tlb_need_flush
));
3107 tcg_gen_brcondi_i32(TCG_COND_EQ
, t
, 0, l
);
3109 gen_helper_check_tlb_flush_global(cpu_env
);
3111 gen_helper_check_tlb_flush_local(cpu_env
);
3114 tcg_temp_free_i32(t
);
3117 static inline void gen_check_tlb_flush(DisasContext
*ctx
, bool global
) { }
3121 static void gen_isync(DisasContext
*ctx
)
3124 * We need to check for a pending TLB flush. This can only happen in
3125 * kernel mode however so check MSR_PR
3128 gen_check_tlb_flush(ctx
, false);
3130 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
3131 gen_stop_exception(ctx
);
3134 #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE))
3136 static void gen_load_locked(DisasContext
*ctx
, TCGMemOp memop
)
3138 TCGv gpr
= cpu_gpr
[rD(ctx
->opcode
)];
3139 TCGv t0
= tcg_temp_new();
3141 gen_set_access_type(ctx
, ACCESS_RES
);
3142 gen_addr_reg_index(ctx
, t0
);
3143 tcg_gen_qemu_ld_tl(gpr
, t0
, ctx
->mem_idx
, memop
| MO_ALIGN
);
3144 tcg_gen_mov_tl(cpu_reserve
, t0
);
3145 tcg_gen_mov_tl(cpu_reserve_val
, gpr
);
3146 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3150 #define LARX(name, memop) \
3151 static void gen_##name(DisasContext *ctx) \
3153 gen_load_locked(ctx, memop); \
3157 LARX(lbarx
, DEF_MEMOP(MO_UB
))
3158 LARX(lharx
, DEF_MEMOP(MO_UW
))
3159 LARX(lwarx
, DEF_MEMOP(MO_UL
))
3161 static void gen_fetch_inc_conditional(DisasContext
*ctx
, TCGMemOp memop
,
3162 TCGv EA
, TCGCond cond
, int addend
)
3164 TCGv t
= tcg_temp_new();
3165 TCGv t2
= tcg_temp_new();
3166 TCGv u
= tcg_temp_new();
3168 tcg_gen_qemu_ld_tl(t
, EA
, ctx
->mem_idx
, memop
);
3169 tcg_gen_addi_tl(t2
, EA
, MEMOP_GET_SIZE(memop
));
3170 tcg_gen_qemu_ld_tl(t2
, t2
, ctx
->mem_idx
, memop
);
3171 tcg_gen_addi_tl(u
, t
, addend
);
3173 /* E.g. for fetch and increment bounded... */
3174 /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */
3175 tcg_gen_movcond_tl(cond
, u
, t
, t2
, u
, t
);
3176 tcg_gen_qemu_st_tl(u
, EA
, ctx
->mem_idx
, memop
);
3178 /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */
3179 tcg_gen_movi_tl(u
, 1 << (MEMOP_GET_SIZE(memop
) * 8 - 1));
3180 tcg_gen_movcond_tl(cond
, cpu_gpr
[rD(ctx
->opcode
)], t
, t2
, t
, u
);
3187 static void gen_ld_atomic(DisasContext
*ctx
, TCGMemOp memop
)
3189 uint32_t gpr_FC
= FC(ctx
->opcode
);
3190 TCGv EA
= tcg_temp_new();
3191 int rt
= rD(ctx
->opcode
);
3195 gen_addr_register(ctx
, EA
);
3197 src
= cpu_gpr
[(rt
+ 1) & 31];
3199 need_serial
= false;
3202 case 0: /* Fetch and add */
3203 tcg_gen_atomic_fetch_add_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3205 case 1: /* Fetch and xor */
3206 tcg_gen_atomic_fetch_xor_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3208 case 2: /* Fetch and or */
3209 tcg_gen_atomic_fetch_or_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3211 case 3: /* Fetch and 'and' */
3212 tcg_gen_atomic_fetch_and_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3214 case 4: /* Fetch and max unsigned */
3215 tcg_gen_atomic_fetch_umax_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3217 case 5: /* Fetch and max signed */
3218 tcg_gen_atomic_fetch_smax_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3220 case 6: /* Fetch and min unsigned */
3221 tcg_gen_atomic_fetch_umin_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3223 case 7: /* Fetch and min signed */
3224 tcg_gen_atomic_fetch_smin_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3227 tcg_gen_atomic_xchg_tl(dst
, EA
, src
, ctx
->mem_idx
, memop
);
3230 case 16: /* Compare and swap not equal */
3231 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3234 TCGv t0
= tcg_temp_new();
3235 TCGv t1
= tcg_temp_new();
3237 tcg_gen_qemu_ld_tl(t0
, EA
, ctx
->mem_idx
, memop
);
3238 if ((memop
& MO_SIZE
) == MO_64
|| TARGET_LONG_BITS
== 32) {
3239 tcg_gen_mov_tl(t1
, src
);
3241 tcg_gen_ext32u_tl(t1
, src
);
3243 tcg_gen_movcond_tl(TCG_COND_NE
, t1
, t0
, t1
,
3244 cpu_gpr
[(rt
+ 2) & 31], t0
);
3245 tcg_gen_qemu_st_tl(t1
, EA
, ctx
->mem_idx
, memop
);
3246 tcg_gen_mov_tl(dst
, t0
);
3253 case 24: /* Fetch and increment bounded */
3254 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3257 gen_fetch_inc_conditional(ctx
, memop
, EA
, TCG_COND_NE
, 1);
3260 case 25: /* Fetch and increment equal */
3261 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3264 gen_fetch_inc_conditional(ctx
, memop
, EA
, TCG_COND_EQ
, 1);
3267 case 28: /* Fetch and decrement bounded */
3268 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3271 gen_fetch_inc_conditional(ctx
, memop
, EA
, TCG_COND_NE
, -1);
3276 /* invoke data storage error handler */
3277 gen_exception_err(ctx
, POWERPC_EXCP_DSI
, POWERPC_EXCP_INVAL
);
3282 /* Restart with exclusive lock. */
3283 gen_helper_exit_atomic(cpu_env
);
3284 ctx
->base
.is_jmp
= DISAS_NORETURN
;
3288 static void gen_lwat(DisasContext
*ctx
)
3290 gen_ld_atomic(ctx
, DEF_MEMOP(MO_UL
));
3294 static void gen_ldat(DisasContext
*ctx
)
3296 gen_ld_atomic(ctx
, DEF_MEMOP(MO_Q
));
3300 static void gen_st_atomic(DisasContext
*ctx
, TCGMemOp memop
)
3302 uint32_t gpr_FC
= FC(ctx
->opcode
);
3303 TCGv EA
= tcg_temp_new();
3306 gen_addr_register(ctx
, EA
);
3307 src
= cpu_gpr
[rD(ctx
->opcode
)];
3308 discard
= tcg_temp_new();
3312 case 0: /* add and Store */
3313 tcg_gen_atomic_add_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3315 case 1: /* xor and Store */
3316 tcg_gen_atomic_xor_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3318 case 2: /* Or and Store */
3319 tcg_gen_atomic_or_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3321 case 3: /* 'and' and Store */
3322 tcg_gen_atomic_and_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3324 case 4: /* Store max unsigned */
3325 tcg_gen_atomic_umax_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3327 case 5: /* Store max signed */
3328 tcg_gen_atomic_smax_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3330 case 6: /* Store min unsigned */
3331 tcg_gen_atomic_umin_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3333 case 7: /* Store min signed */
3334 tcg_gen_atomic_smin_fetch_tl(discard
, EA
, src
, ctx
->mem_idx
, memop
);
3336 case 24: /* Store twin */
3337 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3338 /* Restart with exclusive lock. */
3339 gen_helper_exit_atomic(cpu_env
);
3340 ctx
->base
.is_jmp
= DISAS_NORETURN
;
3342 TCGv t
= tcg_temp_new();
3343 TCGv t2
= tcg_temp_new();
3344 TCGv s
= tcg_temp_new();
3345 TCGv s2
= tcg_temp_new();
3346 TCGv ea_plus_s
= tcg_temp_new();
3348 tcg_gen_qemu_ld_tl(t
, EA
, ctx
->mem_idx
, memop
);
3349 tcg_gen_addi_tl(ea_plus_s
, EA
, MEMOP_GET_SIZE(memop
));
3350 tcg_gen_qemu_ld_tl(t2
, ea_plus_s
, ctx
->mem_idx
, memop
);
3351 tcg_gen_movcond_tl(TCG_COND_EQ
, s
, t
, t2
, src
, t
);
3352 tcg_gen_movcond_tl(TCG_COND_EQ
, s2
, t
, t2
, src
, t2
);
3353 tcg_gen_qemu_st_tl(s
, EA
, ctx
->mem_idx
, memop
);
3354 tcg_gen_qemu_st_tl(s2
, ea_plus_s
, ctx
->mem_idx
, memop
);
3356 tcg_temp_free(ea_plus_s
);
3364 /* invoke data storage error handler */
3365 gen_exception_err(ctx
, POWERPC_EXCP_DSI
, POWERPC_EXCP_INVAL
);
3367 tcg_temp_free(discard
);
3371 static void gen_stwat(DisasContext
*ctx
)
3373 gen_st_atomic(ctx
, DEF_MEMOP(MO_UL
));
3377 static void gen_stdat(DisasContext
*ctx
)
3379 gen_st_atomic(ctx
, DEF_MEMOP(MO_Q
));
3383 static void gen_conditional_store(DisasContext
*ctx
, TCGMemOp memop
)
3385 TCGLabel
*l1
= gen_new_label();
3386 TCGLabel
*l2
= gen_new_label();
3387 TCGv t0
= tcg_temp_new();
3388 int reg
= rS(ctx
->opcode
);
3390 gen_set_access_type(ctx
, ACCESS_RES
);
3391 gen_addr_reg_index(ctx
, t0
);
3392 tcg_gen_brcond_tl(TCG_COND_NE
, t0
, cpu_reserve
, l1
);
3395 t0
= tcg_temp_new();
3396 tcg_gen_atomic_cmpxchg_tl(t0
, cpu_reserve
, cpu_reserve_val
,
3397 cpu_gpr
[reg
], ctx
->mem_idx
,
3398 DEF_MEMOP(memop
) | MO_ALIGN
);
3399 tcg_gen_setcond_tl(TCG_COND_EQ
, t0
, t0
, cpu_reserve_val
);
3400 tcg_gen_shli_tl(t0
, t0
, CRF_EQ_BIT
);
3401 tcg_gen_or_tl(t0
, t0
, cpu_so
);
3402 tcg_gen_trunc_tl_i32(cpu_crf
[0], t0
);
3409 * Address mismatch implies failure. But we still need to provide
3410 * the memory barrier semantics of the instruction.
3412 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
3413 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
3416 tcg_gen_movi_tl(cpu_reserve
, -1);
3419 #define STCX(name, memop) \
3420 static void gen_##name(DisasContext *ctx) \
3422 gen_conditional_store(ctx, memop); \
3425 STCX(stbcx_
, DEF_MEMOP(MO_UB
))
3426 STCX(sthcx_
, DEF_MEMOP(MO_UW
))
3427 STCX(stwcx_
, DEF_MEMOP(MO_UL
))
3429 #if defined(TARGET_PPC64)
3431 LARX(ldarx
, DEF_MEMOP(MO_Q
))
3433 STCX(stdcx_
, DEF_MEMOP(MO_Q
))
3436 static void gen_lqarx(DisasContext
*ctx
)
3438 int rd
= rD(ctx
->opcode
);
3441 if (unlikely((rd
& 1) || (rd
== rA(ctx
->opcode
)) ||
3442 (rd
== rB(ctx
->opcode
)))) {
3443 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3447 gen_set_access_type(ctx
, ACCESS_RES
);
3448 EA
= tcg_temp_new();
3449 gen_addr_reg_index(ctx
, EA
);
3451 /* Note that the low part is always in RD+1, even in LE mode. */
3452 lo
= cpu_gpr
[rd
+ 1];
3455 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3456 if (HAVE_ATOMIC128
) {
3457 TCGv_i32 oi
= tcg_temp_new_i32();
3459 tcg_gen_movi_i32(oi
, make_memop_idx(MO_LEQ
| MO_ALIGN_16
,
3461 gen_helper_lq_le_parallel(lo
, cpu_env
, EA
, oi
);
3463 tcg_gen_movi_i32(oi
, make_memop_idx(MO_BEQ
| MO_ALIGN_16
,
3465 gen_helper_lq_be_parallel(lo
, cpu_env
, EA
, oi
);
3467 tcg_temp_free_i32(oi
);
3468 tcg_gen_ld_i64(hi
, cpu_env
, offsetof(CPUPPCState
, retxh
));
3470 /* Restart with exclusive lock. */
3471 gen_helper_exit_atomic(cpu_env
);
3472 ctx
->base
.is_jmp
= DISAS_NORETURN
;
3476 } else if (ctx
->le_mode
) {
3477 tcg_gen_qemu_ld_i64(lo
, EA
, ctx
->mem_idx
, MO_LEQ
| MO_ALIGN_16
);
3478 tcg_gen_mov_tl(cpu_reserve
, EA
);
3479 gen_addr_add(ctx
, EA
, EA
, 8);
3480 tcg_gen_qemu_ld_i64(hi
, EA
, ctx
->mem_idx
, MO_LEQ
);
3482 tcg_gen_qemu_ld_i64(hi
, EA
, ctx
->mem_idx
, MO_BEQ
| MO_ALIGN_16
);
3483 tcg_gen_mov_tl(cpu_reserve
, EA
);
3484 gen_addr_add(ctx
, EA
, EA
, 8);
3485 tcg_gen_qemu_ld_i64(lo
, EA
, ctx
->mem_idx
, MO_BEQ
);
3489 tcg_gen_st_tl(hi
, cpu_env
, offsetof(CPUPPCState
, reserve_val
));
3490 tcg_gen_st_tl(lo
, cpu_env
, offsetof(CPUPPCState
, reserve_val2
));
3494 static void gen_stqcx_(DisasContext
*ctx
)
3496 int rs
= rS(ctx
->opcode
);
3499 if (unlikely(rs
& 1)) {
3500 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3504 gen_set_access_type(ctx
, ACCESS_RES
);
3505 EA
= tcg_temp_new();
3506 gen_addr_reg_index(ctx
, EA
);
3508 /* Note that the low part is always in RS+1, even in LE mode. */
3509 lo
= cpu_gpr
[rs
+ 1];
3512 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
3513 if (HAVE_CMPXCHG128
) {
3514 TCGv_i32 oi
= tcg_const_i32(DEF_MEMOP(MO_Q
) | MO_ALIGN_16
);
3516 gen_helper_stqcx_le_parallel(cpu_crf
[0], cpu_env
,
3519 gen_helper_stqcx_be_parallel(cpu_crf
[0], cpu_env
,
3522 tcg_temp_free_i32(oi
);
3524 /* Restart with exclusive lock. */
3525 gen_helper_exit_atomic(cpu_env
);
3526 ctx
->base
.is_jmp
= DISAS_NORETURN
;
3530 TCGLabel
*lab_fail
= gen_new_label();
3531 TCGLabel
*lab_over
= gen_new_label();
3532 TCGv_i64 t0
= tcg_temp_new_i64();
3533 TCGv_i64 t1
= tcg_temp_new_i64();
3535 tcg_gen_brcond_tl(TCG_COND_NE
, EA
, cpu_reserve
, lab_fail
);
3538 gen_qemu_ld64_i64(ctx
, t0
, cpu_reserve
);
3539 tcg_gen_ld_i64(t1
, cpu_env
, (ctx
->le_mode
3540 ? offsetof(CPUPPCState
, reserve_val2
)
3541 : offsetof(CPUPPCState
, reserve_val
)));
3542 tcg_gen_brcond_i64(TCG_COND_NE
, t0
, t1
, lab_fail
);
3544 tcg_gen_addi_i64(t0
, cpu_reserve
, 8);
3545 gen_qemu_ld64_i64(ctx
, t0
, t0
);
3546 tcg_gen_ld_i64(t1
, cpu_env
, (ctx
->le_mode
3547 ? offsetof(CPUPPCState
, reserve_val
)
3548 : offsetof(CPUPPCState
, reserve_val2
)));
3549 tcg_gen_brcond_i64(TCG_COND_NE
, t0
, t1
, lab_fail
);
3552 gen_qemu_st64_i64(ctx
, ctx
->le_mode
? lo
: hi
, cpu_reserve
);
3553 tcg_gen_addi_i64(t0
, cpu_reserve
, 8);
3554 gen_qemu_st64_i64(ctx
, ctx
->le_mode
? hi
: lo
, t0
);
3556 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
3557 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], CRF_EQ
);
3558 tcg_gen_br(lab_over
);
3560 gen_set_label(lab_fail
);
3561 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
3563 gen_set_label(lab_over
);
3564 tcg_gen_movi_tl(cpu_reserve
, -1);
3565 tcg_temp_free_i64(t0
);
3566 tcg_temp_free_i64(t1
);
3569 #endif /* defined(TARGET_PPC64) */
3572 static void gen_sync(DisasContext
*ctx
)
3574 uint32_t l
= (ctx
->opcode
>> 21) & 3;
3577 * We may need to check for a pending TLB flush.
3579 * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32.
3581 * Additionally, this can only happen in kernel mode however so
3582 * check MSR_PR as well.
3584 if (((l
== 2) || !(ctx
->insns_flags
& PPC_64B
)) && !ctx
->pr
) {
3585 gen_check_tlb_flush(ctx
, true);
3587 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
3591 static void gen_wait(DisasContext
*ctx
)
3593 TCGv_i32 t0
= tcg_const_i32(1);
3594 tcg_gen_st_i32(t0
, cpu_env
,
3595 -offsetof(PowerPCCPU
, env
) + offsetof(CPUState
, halted
));
3596 tcg_temp_free_i32(t0
);
3597 /* Stop translation, as the CPU is supposed to sleep from now */
3598 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->base
.pc_next
);
3601 #if defined(TARGET_PPC64)
3602 static void gen_doze(DisasContext
*ctx
)
3604 #if defined(CONFIG_USER_ONLY)
3610 t
= tcg_const_i32(PPC_PM_DOZE
);
3611 gen_helper_pminsn(cpu_env
, t
);
3612 tcg_temp_free_i32(t
);
3613 /* Stop translation, as the CPU is supposed to sleep from now */
3614 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->base
.pc_next
);
3615 #endif /* defined(CONFIG_USER_ONLY) */
3618 static void gen_nap(DisasContext
*ctx
)
3620 #if defined(CONFIG_USER_ONLY)
3626 t
= tcg_const_i32(PPC_PM_NAP
);
3627 gen_helper_pminsn(cpu_env
, t
);
3628 tcg_temp_free_i32(t
);
3629 /* Stop translation, as the CPU is supposed to sleep from now */
3630 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->base
.pc_next
);
3631 #endif /* defined(CONFIG_USER_ONLY) */
3634 static void gen_stop(DisasContext
*ctx
)
3636 #if defined(CONFIG_USER_ONLY)
3642 t
= tcg_const_i32(PPC_PM_STOP
);
3643 gen_helper_pminsn(cpu_env
, t
);
3644 tcg_temp_free_i32(t
);
3645 /* Stop translation, as the CPU is supposed to sleep from now */
3646 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->base
.pc_next
);
3647 #endif /* defined(CONFIG_USER_ONLY) */
3650 static void gen_sleep(DisasContext
*ctx
)
3652 #if defined(CONFIG_USER_ONLY)
3658 t
= tcg_const_i32(PPC_PM_SLEEP
);
3659 gen_helper_pminsn(cpu_env
, t
);
3660 tcg_temp_free_i32(t
);
3661 /* Stop translation, as the CPU is supposed to sleep from now */
3662 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->base
.pc_next
);
3663 #endif /* defined(CONFIG_USER_ONLY) */
3666 static void gen_rvwinkle(DisasContext
*ctx
)
3668 #if defined(CONFIG_USER_ONLY)
3674 t
= tcg_const_i32(PPC_PM_RVWINKLE
);
3675 gen_helper_pminsn(cpu_env
, t
);
3676 tcg_temp_free_i32(t
);
3677 /* Stop translation, as the CPU is supposed to sleep from now */
3678 gen_exception_nip(ctx
, EXCP_HLT
, ctx
->base
.pc_next
);
3679 #endif /* defined(CONFIG_USER_ONLY) */
3681 #endif /* #if defined(TARGET_PPC64) */
3683 static inline void gen_update_cfar(DisasContext
*ctx
, target_ulong nip
)
3685 #if defined(TARGET_PPC64)
3686 if (ctx
->has_cfar
) {
3687 tcg_gen_movi_tl(cpu_cfar
, nip
);
3692 static inline bool use_goto_tb(DisasContext
*ctx
, target_ulong dest
)
3694 if (unlikely(ctx
->singlestep_enabled
)) {
3698 #ifndef CONFIG_USER_ONLY
3699 return (ctx
->base
.tb
->pc
& TARGET_PAGE_MASK
) == (dest
& TARGET_PAGE_MASK
);
3705 static void gen_lookup_and_goto_ptr(DisasContext
*ctx
)
3707 int sse
= ctx
->singlestep_enabled
;
3708 if (unlikely(sse
)) {
3709 if (sse
& GDBSTUB_SINGLE_STEP
) {
3710 gen_debug_exception(ctx
);
3711 } else if (sse
& (CPU_SINGLE_STEP
| CPU_BRANCH_STEP
)) {
3712 uint32_t excp
= gen_prep_dbgex(ctx
);
3713 gen_exception(ctx
, excp
);
3715 tcg_gen_exit_tb(NULL
, 0);
3717 tcg_gen_lookup_and_goto_ptr();
3722 static void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
3724 if (NARROW_MODE(ctx
)) {
3725 dest
= (uint32_t) dest
;
3727 if (use_goto_tb(ctx
, dest
)) {
3729 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3730 tcg_gen_exit_tb(ctx
->base
.tb
, n
);
3732 tcg_gen_movi_tl(cpu_nip
, dest
& ~3);
3733 gen_lookup_and_goto_ptr(ctx
);
3737 static inline void gen_setlr(DisasContext
*ctx
, target_ulong nip
)
3739 if (NARROW_MODE(ctx
)) {
3740 nip
= (uint32_t)nip
;
3742 tcg_gen_movi_tl(cpu_lr
, nip
);
3746 static void gen_b(DisasContext
*ctx
)
3748 target_ulong li
, target
;
3750 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3751 /* sign extend LI */
3752 li
= LI(ctx
->opcode
);
3753 li
= (li
^ 0x02000000) - 0x02000000;
3754 if (likely(AA(ctx
->opcode
) == 0)) {
3755 target
= ctx
->base
.pc_next
+ li
- 4;
3759 if (LK(ctx
->opcode
)) {
3760 gen_setlr(ctx
, ctx
->base
.pc_next
);
3762 gen_update_cfar(ctx
, ctx
->base
.pc_next
- 4);
3763 gen_goto_tb(ctx
, 0, target
);
3771 static void gen_bcond(DisasContext
*ctx
, int type
)
3773 uint32_t bo
= BO(ctx
->opcode
);
3776 ctx
->exception
= POWERPC_EXCP_BRANCH
;
3778 if (type
== BCOND_LR
|| type
== BCOND_CTR
|| type
== BCOND_TAR
) {
3779 target
= tcg_temp_local_new();
3780 if (type
== BCOND_CTR
) {
3781 tcg_gen_mov_tl(target
, cpu_ctr
);
3782 } else if (type
== BCOND_TAR
) {
3783 gen_load_spr(target
, SPR_TAR
);
3785 tcg_gen_mov_tl(target
, cpu_lr
);
3790 if (LK(ctx
->opcode
)) {
3791 gen_setlr(ctx
, ctx
->base
.pc_next
);
3793 l1
= gen_new_label();
3794 if ((bo
& 0x4) == 0) {
3795 /* Decrement and test CTR */
3796 TCGv temp
= tcg_temp_new();
3798 if (type
== BCOND_CTR
) {
3800 * All ISAs up to v3 describe this form of bcctr as invalid but
3801 * some processors, ie. 64-bit server processors compliant with
3802 * arch 2.x, do implement a "test and decrement" logic instead,
3803 * as described in their respective UMs. This logic involves CTR
3804 * to act as both the branch target and a counter, which makes
3805 * it basically useless and thus never used in real code.
3807 * This form was hence chosen to trigger extra micro-architectural
3808 * side-effect on real HW needed for the Spectre v2 workaround.
3809 * It is up to guests that implement such workaround, ie. linux, to
3810 * use this form in a way it just triggers the side-effect without
3811 * doing anything else harmful.
3813 if (unlikely(!is_book3s_arch2x(ctx
))) {
3814 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3815 tcg_temp_free(temp
);
3816 tcg_temp_free(target
);
3820 if (NARROW_MODE(ctx
)) {
3821 tcg_gen_ext32u_tl(temp
, cpu_ctr
);
3823 tcg_gen_mov_tl(temp
, cpu_ctr
);
3826 tcg_gen_brcondi_tl(TCG_COND_NE
, temp
, 0, l1
);
3828 tcg_gen_brcondi_tl(TCG_COND_EQ
, temp
, 0, l1
);
3830 tcg_gen_subi_tl(cpu_ctr
, cpu_ctr
, 1);
3832 tcg_gen_subi_tl(cpu_ctr
, cpu_ctr
, 1);
3833 if (NARROW_MODE(ctx
)) {
3834 tcg_gen_ext32u_tl(temp
, cpu_ctr
);
3836 tcg_gen_mov_tl(temp
, cpu_ctr
);
3839 tcg_gen_brcondi_tl(TCG_COND_NE
, temp
, 0, l1
);
3841 tcg_gen_brcondi_tl(TCG_COND_EQ
, temp
, 0, l1
);
3844 tcg_temp_free(temp
);
3846 if ((bo
& 0x10) == 0) {
3848 uint32_t bi
= BI(ctx
->opcode
);
3849 uint32_t mask
= 0x08 >> (bi
& 0x03);
3850 TCGv_i32 temp
= tcg_temp_new_i32();
3853 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3854 tcg_gen_brcondi_i32(TCG_COND_EQ
, temp
, 0, l1
);
3856 tcg_gen_andi_i32(temp
, cpu_crf
[bi
>> 2], mask
);
3857 tcg_gen_brcondi_i32(TCG_COND_NE
, temp
, 0, l1
);
3859 tcg_temp_free_i32(temp
);
3861 gen_update_cfar(ctx
, ctx
->base
.pc_next
- 4);
3862 if (type
== BCOND_IM
) {
3863 target_ulong li
= (target_long
)((int16_t)(BD(ctx
->opcode
)));
3864 if (likely(AA(ctx
->opcode
) == 0)) {
3865 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
+ li
- 4);
3867 gen_goto_tb(ctx
, 0, li
);
3870 if (NARROW_MODE(ctx
)) {
3871 tcg_gen_andi_tl(cpu_nip
, target
, (uint32_t)~3);
3873 tcg_gen_andi_tl(cpu_nip
, target
, ~3);
3875 gen_lookup_and_goto_ptr(ctx
);
3876 tcg_temp_free(target
);
3878 if ((bo
& 0x14) != 0x14) {
3879 /* fallthrough case */
3881 gen_goto_tb(ctx
, 1, ctx
->base
.pc_next
);
3885 static void gen_bc(DisasContext
*ctx
)
3887 gen_bcond(ctx
, BCOND_IM
);
3890 static void gen_bcctr(DisasContext
*ctx
)
3892 gen_bcond(ctx
, BCOND_CTR
);
3895 static void gen_bclr(DisasContext
*ctx
)
3897 gen_bcond(ctx
, BCOND_LR
);
3900 static void gen_bctar(DisasContext
*ctx
)
3902 gen_bcond(ctx
, BCOND_TAR
);
3905 /*** Condition register logical ***/
3906 #define GEN_CRLOGIC(name, tcg_op, opc) \
3907 static void glue(gen_, name)(DisasContext *ctx) \
3912 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3913 t0 = tcg_temp_new_i32(); \
3915 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3917 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3919 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3920 t1 = tcg_temp_new_i32(); \
3921 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3923 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3925 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3927 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3928 tcg_op(t0, t0, t1); \
3929 bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \
3930 tcg_gen_andi_i32(t0, t0, bitmask); \
3931 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3932 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3933 tcg_temp_free_i32(t0); \
3934 tcg_temp_free_i32(t1); \
3938 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08);
3940 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04);
3942 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09);
3944 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07);
3946 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01);
3948 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E);
3950 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D);
3952 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06);
3955 static void gen_mcrf(DisasContext
*ctx
)
3957 tcg_gen_mov_i32(cpu_crf
[crfD(ctx
->opcode
)], cpu_crf
[crfS(ctx
->opcode
)]);
3960 /*** System linkage ***/
3962 /* rfi (supervisor only) */
3963 static void gen_rfi(DisasContext
*ctx
)
3965 #if defined(CONFIG_USER_ONLY)
3969 * This instruction doesn't exist anymore on 64-bit server
3970 * processors compliant with arch 2.x
3972 if (is_book3s_arch2x(ctx
)) {
3973 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
3976 /* Restore CPU state */
3978 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
3981 gen_update_cfar(ctx
, ctx
->base
.pc_next
- 4);
3982 gen_helper_rfi(cpu_env
);
3983 gen_sync_exception(ctx
);
3984 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
3990 #if defined(TARGET_PPC64)
3991 static void gen_rfid(DisasContext
*ctx
)
3993 #if defined(CONFIG_USER_ONLY)
3996 /* Restore CPU state */
3998 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
4001 gen_update_cfar(ctx
, ctx
->base
.pc_next
- 4);
4002 gen_helper_rfid(cpu_env
);
4003 gen_sync_exception(ctx
);
4004 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
4010 static void gen_hrfid(DisasContext
*ctx
)
4012 #if defined(CONFIG_USER_ONLY)
4015 /* Restore CPU state */
4017 gen_helper_hrfid(cpu_env
);
4018 gen_sync_exception(ctx
);
4024 #if defined(CONFIG_USER_ONLY)
4025 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4027 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4029 static void gen_sc(DisasContext
*ctx
)
4033 lev
= (ctx
->opcode
>> 5) & 0x7F;
4034 gen_exception_err(ctx
, POWERPC_SYSCALL
, lev
);
4039 /* Check for unconditional traps (always or never) */
4040 static bool check_unconditional_trap(DisasContext
*ctx
)
4043 if (TO(ctx
->opcode
) == 0) {
4047 if (TO(ctx
->opcode
) == 31) {
4048 gen_exception_err(ctx
, POWERPC_EXCP_PROGRAM
, POWERPC_EXCP_TRAP
);
4055 static void gen_tw(DisasContext
*ctx
)
4059 if (check_unconditional_trap(ctx
)) {
4062 t0
= tcg_const_i32(TO(ctx
->opcode
));
4063 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
4065 tcg_temp_free_i32(t0
);
4069 static void gen_twi(DisasContext
*ctx
)
4074 if (check_unconditional_trap(ctx
)) {
4077 t0
= tcg_const_tl(SIMM(ctx
->opcode
));
4078 t1
= tcg_const_i32(TO(ctx
->opcode
));
4079 gen_helper_tw(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4081 tcg_temp_free_i32(t1
);
4084 #if defined(TARGET_PPC64)
4086 static void gen_td(DisasContext
*ctx
)
4090 if (check_unconditional_trap(ctx
)) {
4093 t0
= tcg_const_i32(TO(ctx
->opcode
));
4094 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
4096 tcg_temp_free_i32(t0
);
4100 static void gen_tdi(DisasContext
*ctx
)
4105 if (check_unconditional_trap(ctx
)) {
4108 t0
= tcg_const_tl(SIMM(ctx
->opcode
));
4109 t1
= tcg_const_i32(TO(ctx
->opcode
));
4110 gen_helper_td(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
4112 tcg_temp_free_i32(t1
);
4116 /*** Processor control ***/
4118 static void gen_read_xer(DisasContext
*ctx
, TCGv dst
)
4120 TCGv t0
= tcg_temp_new();
4121 TCGv t1
= tcg_temp_new();
4122 TCGv t2
= tcg_temp_new();
4123 tcg_gen_mov_tl(dst
, cpu_xer
);
4124 tcg_gen_shli_tl(t0
, cpu_so
, XER_SO
);
4125 tcg_gen_shli_tl(t1
, cpu_ov
, XER_OV
);
4126 tcg_gen_shli_tl(t2
, cpu_ca
, XER_CA
);
4127 tcg_gen_or_tl(t0
, t0
, t1
);
4128 tcg_gen_or_tl(dst
, dst
, t2
);
4129 tcg_gen_or_tl(dst
, dst
, t0
);
4130 if (is_isa300(ctx
)) {
4131 tcg_gen_shli_tl(t0
, cpu_ov32
, XER_OV32
);
4132 tcg_gen_or_tl(dst
, dst
, t0
);
4133 tcg_gen_shli_tl(t0
, cpu_ca32
, XER_CA32
);
4134 tcg_gen_or_tl(dst
, dst
, t0
);
4141 static void gen_write_xer(TCGv src
)
4143 /* Write all flags, while reading back check for isa300 */
4144 tcg_gen_andi_tl(cpu_xer
, src
,
4146 (1u << XER_OV
) | (1u << XER_OV32
) |
4147 (1u << XER_CA
) | (1u << XER_CA32
)));
4148 tcg_gen_extract_tl(cpu_ov32
, src
, XER_OV32
, 1);
4149 tcg_gen_extract_tl(cpu_ca32
, src
, XER_CA32
, 1);
4150 tcg_gen_extract_tl(cpu_so
, src
, XER_SO
, 1);
4151 tcg_gen_extract_tl(cpu_ov
, src
, XER_OV
, 1);
4152 tcg_gen_extract_tl(cpu_ca
, src
, XER_CA
, 1);
4156 static void gen_mcrxr(DisasContext
*ctx
)
4158 TCGv_i32 t0
= tcg_temp_new_i32();
4159 TCGv_i32 t1
= tcg_temp_new_i32();
4160 TCGv_i32 dst
= cpu_crf
[crfD(ctx
->opcode
)];
4162 tcg_gen_trunc_tl_i32(t0
, cpu_so
);
4163 tcg_gen_trunc_tl_i32(t1
, cpu_ov
);
4164 tcg_gen_trunc_tl_i32(dst
, cpu_ca
);
4165 tcg_gen_shli_i32(t0
, t0
, 3);
4166 tcg_gen_shli_i32(t1
, t1
, 2);
4167 tcg_gen_shli_i32(dst
, dst
, 1);
4168 tcg_gen_or_i32(dst
, dst
, t0
);
4169 tcg_gen_or_i32(dst
, dst
, t1
);
4170 tcg_temp_free_i32(t0
);
4171 tcg_temp_free_i32(t1
);
4173 tcg_gen_movi_tl(cpu_so
, 0);
4174 tcg_gen_movi_tl(cpu_ov
, 0);
4175 tcg_gen_movi_tl(cpu_ca
, 0);
4180 static void gen_mcrxrx(DisasContext
*ctx
)
4182 TCGv t0
= tcg_temp_new();
4183 TCGv t1
= tcg_temp_new();
4184 TCGv_i32 dst
= cpu_crf
[crfD(ctx
->opcode
)];
4186 /* copy OV and OV32 */
4187 tcg_gen_shli_tl(t0
, cpu_ov
, 1);
4188 tcg_gen_or_tl(t0
, t0
, cpu_ov32
);
4189 tcg_gen_shli_tl(t0
, t0
, 2);
4190 /* copy CA and CA32 */
4191 tcg_gen_shli_tl(t1
, cpu_ca
, 1);
4192 tcg_gen_or_tl(t1
, t1
, cpu_ca32
);
4193 tcg_gen_or_tl(t0
, t0
, t1
);
4194 tcg_gen_trunc_tl_i32(dst
, t0
);
4201 static void gen_mfcr(DisasContext
*ctx
)
4205 if (likely(ctx
->opcode
& 0x00100000)) {
4206 crm
= CRM(ctx
->opcode
);
4207 if (likely(crm
&& ((crm
& (crm
- 1)) == 0))) {
4209 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_crf
[7 - crn
]);
4210 tcg_gen_shli_tl(cpu_gpr
[rD(ctx
->opcode
)],
4211 cpu_gpr
[rD(ctx
->opcode
)], crn
* 4);
4214 TCGv_i32 t0
= tcg_temp_new_i32();
4215 tcg_gen_mov_i32(t0
, cpu_crf
[0]);
4216 tcg_gen_shli_i32(t0
, t0
, 4);
4217 tcg_gen_or_i32(t0
, t0
, cpu_crf
[1]);
4218 tcg_gen_shli_i32(t0
, t0
, 4);
4219 tcg_gen_or_i32(t0
, t0
, cpu_crf
[2]);
4220 tcg_gen_shli_i32(t0
, t0
, 4);
4221 tcg_gen_or_i32(t0
, t0
, cpu_crf
[3]);
4222 tcg_gen_shli_i32(t0
, t0
, 4);
4223 tcg_gen_or_i32(t0
, t0
, cpu_crf
[4]);
4224 tcg_gen_shli_i32(t0
, t0
, 4);
4225 tcg_gen_or_i32(t0
, t0
, cpu_crf
[5]);
4226 tcg_gen_shli_i32(t0
, t0
, 4);
4227 tcg_gen_or_i32(t0
, t0
, cpu_crf
[6]);
4228 tcg_gen_shli_i32(t0
, t0
, 4);
4229 tcg_gen_or_i32(t0
, t0
, cpu_crf
[7]);
4230 tcg_gen_extu_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4231 tcg_temp_free_i32(t0
);
4236 static void gen_mfmsr(DisasContext
*ctx
)
4239 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_msr
);
4242 static void spr_noaccess(DisasContext
*ctx
, int gprn
, int sprn
)
4245 sprn
= ((sprn
>> 5) & 0x1F) | ((sprn
& 0x1F) << 5);
4246 printf("ERROR: try to access SPR %d !\n", sprn
);
4249 #define SPR_NOACCESS (&spr_noaccess)
4252 static inline void gen_op_mfspr(DisasContext
*ctx
)
4254 void (*read_cb
)(DisasContext
*ctx
, int gprn
, int sprn
);
4255 uint32_t sprn
= SPR(ctx
->opcode
);
4257 #if defined(CONFIG_USER_ONLY)
4258 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
4261 read_cb
= ctx
->spr_cb
[sprn
].uea_read
;
4262 } else if (ctx
->hv
) {
4263 read_cb
= ctx
->spr_cb
[sprn
].hea_read
;
4265 read_cb
= ctx
->spr_cb
[sprn
].oea_read
;
4268 if (likely(read_cb
!= NULL
)) {
4269 if (likely(read_cb
!= SPR_NOACCESS
)) {
4270 (*read_cb
)(ctx
, rD(ctx
->opcode
), sprn
);
4272 /* Privilege exception */
4274 * This is a hack to avoid warnings when running Linux:
4275 * this OS breaks the PowerPC virtualisation model,
4276 * allowing userland application to read the PVR
4278 if (sprn
!= SPR_PVR
) {
4279 qemu_log_mask(LOG_GUEST_ERROR
, "Trying to read privileged spr "
4280 "%d (0x%03x) at " TARGET_FMT_lx
"\n", sprn
, sprn
,
4281 ctx
->base
.pc_next
- 4);
4283 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4286 /* ISA 2.07 defines these as no-ops */
4287 if ((ctx
->insns_flags2
& PPC2_ISA207S
) &&
4288 (sprn
>= 808 && sprn
<= 811)) {
4293 qemu_log_mask(LOG_GUEST_ERROR
,
4294 "Trying to read invalid spr %d (0x%03x) at "
4295 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->base
.pc_next
- 4);
4298 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can
4299 * generate a priv, a hv emu or a no-op
4303 gen_priv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4306 if (ctx
->pr
|| sprn
== 0 || sprn
== 4 || sprn
== 5 || sprn
== 6) {
4307 gen_hvpriv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4313 static void gen_mfspr(DisasContext
*ctx
)
4319 static void gen_mftb(DisasContext
*ctx
)
4325 static void gen_mtcrf(DisasContext
*ctx
)
4329 crm
= CRM(ctx
->opcode
);
4330 if (likely((ctx
->opcode
& 0x00100000))) {
4331 if (crm
&& ((crm
& (crm
- 1)) == 0)) {
4332 TCGv_i32 temp
= tcg_temp_new_i32();
4334 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
4335 tcg_gen_shri_i32(temp
, temp
, crn
* 4);
4336 tcg_gen_andi_i32(cpu_crf
[7 - crn
], temp
, 0xf);
4337 tcg_temp_free_i32(temp
);
4340 TCGv_i32 temp
= tcg_temp_new_i32();
4341 tcg_gen_trunc_tl_i32(temp
, cpu_gpr
[rS(ctx
->opcode
)]);
4342 for (crn
= 0 ; crn
< 8 ; crn
++) {
4343 if (crm
& (1 << crn
)) {
4344 tcg_gen_shri_i32(cpu_crf
[7 - crn
], temp
, crn
* 4);
4345 tcg_gen_andi_i32(cpu_crf
[7 - crn
], cpu_crf
[7 - crn
], 0xf);
4348 tcg_temp_free_i32(temp
);
4353 #if defined(TARGET_PPC64)
4354 static void gen_mtmsrd(DisasContext
*ctx
)
4358 #if !defined(CONFIG_USER_ONLY)
4359 if (ctx
->opcode
& 0x00010000) {
4360 /* Special form that does not need any synchronisation */
4361 TCGv t0
= tcg_temp_new();
4362 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)],
4363 (1 << MSR_RI
) | (1 << MSR_EE
));
4364 tcg_gen_andi_tl(cpu_msr
, cpu_msr
,
4365 ~(target_ulong
)((1 << MSR_RI
) | (1 << MSR_EE
)));
4366 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
4370 * XXX: we need to update nip before the store if we enter
4371 * power saving mode, we will exit the loop directly from
4374 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
4377 gen_update_nip(ctx
, ctx
->base
.pc_next
);
4378 gen_helper_store_msr(cpu_env
, cpu_gpr
[rS(ctx
->opcode
)]);
4379 /* Must stop the translation as machine state (may have) changed */
4380 /* Note that mtmsr is not always defined as context-synchronizing */
4381 gen_stop_exception(ctx
);
4382 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
4386 #endif /* !defined(CONFIG_USER_ONLY) */
4388 #endif /* defined(TARGET_PPC64) */
4390 static void gen_mtmsr(DisasContext
*ctx
)
4394 #if !defined(CONFIG_USER_ONLY)
4395 if (ctx
->opcode
& 0x00010000) {
4396 /* Special form that does not need any synchronisation */
4397 TCGv t0
= tcg_temp_new();
4398 tcg_gen_andi_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)],
4399 (1 << MSR_RI
) | (1 << MSR_EE
));
4400 tcg_gen_andi_tl(cpu_msr
, cpu_msr
,
4401 ~(target_ulong
)((1 << MSR_RI
) | (1 << MSR_EE
)));
4402 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
4405 TCGv msr
= tcg_temp_new();
4408 * XXX: we need to update nip before the store if we enter
4409 * power saving mode, we will exit the loop directly from
4412 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
4415 gen_update_nip(ctx
, ctx
->base
.pc_next
);
4416 #if defined(TARGET_PPC64)
4417 tcg_gen_deposit_tl(msr
, cpu_msr
, cpu_gpr
[rS(ctx
->opcode
)], 0, 32);
4419 tcg_gen_mov_tl(msr
, cpu_gpr
[rS(ctx
->opcode
)]);
4421 gen_helper_store_msr(cpu_env
, msr
);
4422 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
4426 /* Must stop the translation as machine state (may have) changed */
4427 /* Note that mtmsr is not always defined as context-synchronizing */
4428 gen_stop_exception(ctx
);
4434 static void gen_mtspr(DisasContext
*ctx
)
4436 void (*write_cb
)(DisasContext
*ctx
, int sprn
, int gprn
);
4437 uint32_t sprn
= SPR(ctx
->opcode
);
4439 #if defined(CONFIG_USER_ONLY)
4440 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
4443 write_cb
= ctx
->spr_cb
[sprn
].uea_write
;
4444 } else if (ctx
->hv
) {
4445 write_cb
= ctx
->spr_cb
[sprn
].hea_write
;
4447 write_cb
= ctx
->spr_cb
[sprn
].oea_write
;
4450 if (likely(write_cb
!= NULL
)) {
4451 if (likely(write_cb
!= SPR_NOACCESS
)) {
4452 (*write_cb
)(ctx
, sprn
, rS(ctx
->opcode
));
4454 /* Privilege exception */
4455 qemu_log_mask(LOG_GUEST_ERROR
, "Trying to write privileged spr "
4456 "%d (0x%03x) at " TARGET_FMT_lx
"\n", sprn
, sprn
,
4457 ctx
->base
.pc_next
- 4);
4458 gen_priv_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4461 /* ISA 2.07 defines these as no-ops */
4462 if ((ctx
->insns_flags2
& PPC2_ISA207S
) &&
4463 (sprn
>= 808 && sprn
<= 811)) {
4469 qemu_log_mask(LOG_GUEST_ERROR
,
4470 "Trying to write invalid spr %d (0x%03x) at "
4471 TARGET_FMT_lx
"\n", sprn
, sprn
, ctx
->base
.pc_next
- 4);
4475 * The behaviour depends on MSR:PR and SPR# bit 0x10, it can
4476 * generate a priv, a hv emu or a no-op
4480 gen_priv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4483 if (ctx
->pr
|| sprn
== 0) {
4484 gen_hvpriv_exception(ctx
, POWERPC_EXCP_INVAL_SPR
);
4490 #if defined(TARGET_PPC64)
4492 static void gen_setb(DisasContext
*ctx
)
4494 TCGv_i32 t0
= tcg_temp_new_i32();
4495 TCGv_i32 t8
= tcg_temp_new_i32();
4496 TCGv_i32 tm1
= tcg_temp_new_i32();
4497 int crf
= crfS(ctx
->opcode
);
4499 tcg_gen_setcondi_i32(TCG_COND_GEU
, t0
, cpu_crf
[crf
], 4);
4500 tcg_gen_movi_i32(t8
, 8);
4501 tcg_gen_movi_i32(tm1
, -1);
4502 tcg_gen_movcond_i32(TCG_COND_GEU
, t0
, cpu_crf
[crf
], t8
, tm1
, t0
);
4503 tcg_gen_ext_i32_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
4505 tcg_temp_free_i32(t0
);
4506 tcg_temp_free_i32(t8
);
4507 tcg_temp_free_i32(tm1
);
4511 /*** Cache management ***/
4514 static void gen_dcbf(DisasContext
*ctx
)
4516 /* XXX: specification says this is treated as a load by the MMU */
4518 gen_set_access_type(ctx
, ACCESS_CACHE
);
4519 t0
= tcg_temp_new();
4520 gen_addr_reg_index(ctx
, t0
);
4521 gen_qemu_ld8u(ctx
, t0
, t0
);
4525 /* dcbfep (external PID dcbf) */
4526 static void gen_dcbfep(DisasContext
*ctx
)
4528 /* XXX: specification says this is treated as a load by the MMU */
4531 gen_set_access_type(ctx
, ACCESS_CACHE
);
4532 t0
= tcg_temp_new();
4533 gen_addr_reg_index(ctx
, t0
);
4534 tcg_gen_qemu_ld_tl(t0
, t0
, PPC_TLB_EPID_LOAD
, DEF_MEMOP(MO_UB
));
4538 /* dcbi (Supervisor only) */
4539 static void gen_dcbi(DisasContext
*ctx
)
4541 #if defined(CONFIG_USER_ONLY)
4547 EA
= tcg_temp_new();
4548 gen_set_access_type(ctx
, ACCESS_CACHE
);
4549 gen_addr_reg_index(ctx
, EA
);
4550 val
= tcg_temp_new();
4551 /* XXX: specification says this should be treated as a store by the MMU */
4552 gen_qemu_ld8u(ctx
, val
, EA
);
4553 gen_qemu_st8(ctx
, val
, EA
);
4556 #endif /* defined(CONFIG_USER_ONLY) */
4560 static void gen_dcbst(DisasContext
*ctx
)
4562 /* XXX: specification say this is treated as a load by the MMU */
4564 gen_set_access_type(ctx
, ACCESS_CACHE
);
4565 t0
= tcg_temp_new();
4566 gen_addr_reg_index(ctx
, t0
);
4567 gen_qemu_ld8u(ctx
, t0
, t0
);
4571 /* dcbstep (dcbstep External PID version) */
4572 static void gen_dcbstep(DisasContext
*ctx
)
4574 /* XXX: specification say this is treated as a load by the MMU */
4576 gen_set_access_type(ctx
, ACCESS_CACHE
);
4577 t0
= tcg_temp_new();
4578 gen_addr_reg_index(ctx
, t0
);
4579 tcg_gen_qemu_ld_tl(t0
, t0
, PPC_TLB_EPID_LOAD
, DEF_MEMOP(MO_UB
));
4584 static void gen_dcbt(DisasContext
*ctx
)
4587 * interpreted as no-op
4588 * XXX: specification say this is treated as a load by the MMU but
4589 * does not generate any exception
4594 static void gen_dcbtep(DisasContext
*ctx
)
4597 * interpreted as no-op
4598 * XXX: specification say this is treated as a load by the MMU but
4599 * does not generate any exception
4604 static void gen_dcbtst(DisasContext
*ctx
)
4607 * interpreted as no-op
4608 * XXX: specification say this is treated as a load by the MMU but
4609 * does not generate any exception
4614 static void gen_dcbtstep(DisasContext
*ctx
)
4617 * interpreted as no-op
4618 * XXX: specification say this is treated as a load by the MMU but
4619 * does not generate any exception
4624 static void gen_dcbtls(DisasContext
*ctx
)
4626 /* Always fails locking the cache */
4627 TCGv t0
= tcg_temp_new();
4628 gen_load_spr(t0
, SPR_Exxx_L1CSR0
);
4629 tcg_gen_ori_tl(t0
, t0
, L1CSR0_CUL
);
4630 gen_store_spr(SPR_Exxx_L1CSR0
, t0
);
4635 static void gen_dcbz(DisasContext
*ctx
)
4640 gen_set_access_type(ctx
, ACCESS_CACHE
);
4641 tcgv_addr
= tcg_temp_new();
4642 tcgv_op
= tcg_const_i32(ctx
->opcode
& 0x03FF000);
4643 gen_addr_reg_index(ctx
, tcgv_addr
);
4644 gen_helper_dcbz(cpu_env
, tcgv_addr
, tcgv_op
);
4645 tcg_temp_free(tcgv_addr
);
4646 tcg_temp_free_i32(tcgv_op
);
4650 static void gen_dcbzep(DisasContext
*ctx
)
4655 gen_set_access_type(ctx
, ACCESS_CACHE
);
4656 tcgv_addr
= tcg_temp_new();
4657 tcgv_op
= tcg_const_i32(ctx
->opcode
& 0x03FF000);
4658 gen_addr_reg_index(ctx
, tcgv_addr
);
4659 gen_helper_dcbzep(cpu_env
, tcgv_addr
, tcgv_op
);
4660 tcg_temp_free(tcgv_addr
);
4661 tcg_temp_free_i32(tcgv_op
);
4665 static void gen_dst(DisasContext
*ctx
)
4667 if (rA(ctx
->opcode
) == 0) {
4668 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
4670 /* interpreted as no-op */
4675 static void gen_dstst(DisasContext
*ctx
)
4677 if (rA(ctx
->opcode
) == 0) {
4678 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
4680 /* interpreted as no-op */
4686 static void gen_dss(DisasContext
*ctx
)
4688 /* interpreted as no-op */
4692 static void gen_icbi(DisasContext
*ctx
)
4695 gen_set_access_type(ctx
, ACCESS_CACHE
);
4696 t0
= tcg_temp_new();
4697 gen_addr_reg_index(ctx
, t0
);
4698 gen_helper_icbi(cpu_env
, t0
);
4703 static void gen_icbiep(DisasContext
*ctx
)
4706 gen_set_access_type(ctx
, ACCESS_CACHE
);
4707 t0
= tcg_temp_new();
4708 gen_addr_reg_index(ctx
, t0
);
4709 gen_helper_icbiep(cpu_env
, t0
);
4715 static void gen_dcba(DisasContext
*ctx
)
4718 * interpreted as no-op
4719 * XXX: specification say this is treated as a store by the MMU
4720 * but does not generate any exception
4724 /*** Segment register manipulation ***/
4725 /* Supervisor only: */
4728 static void gen_mfsr(DisasContext
*ctx
)
4730 #if defined(CONFIG_USER_ONLY)
4736 t0
= tcg_const_tl(SR(ctx
->opcode
));
4737 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4739 #endif /* defined(CONFIG_USER_ONLY) */
4743 static void gen_mfsrin(DisasContext
*ctx
)
4745 #if defined(CONFIG_USER_ONLY)
4751 t0
= tcg_temp_new();
4752 tcg_gen_extract_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28, 4);
4753 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4755 #endif /* defined(CONFIG_USER_ONLY) */
4759 static void gen_mtsr(DisasContext
*ctx
)
4761 #if defined(CONFIG_USER_ONLY)
4767 t0
= tcg_const_tl(SR(ctx
->opcode
));
4768 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4770 #endif /* defined(CONFIG_USER_ONLY) */
4774 static void gen_mtsrin(DisasContext
*ctx
)
4776 #if defined(CONFIG_USER_ONLY)
4782 t0
= tcg_temp_new();
4783 tcg_gen_extract_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28, 4);
4784 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rD(ctx
->opcode
)]);
4786 #endif /* defined(CONFIG_USER_ONLY) */
4789 #if defined(TARGET_PPC64)
4790 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4793 static void gen_mfsr_64b(DisasContext
*ctx
)
4795 #if defined(CONFIG_USER_ONLY)
4801 t0
= tcg_const_tl(SR(ctx
->opcode
));
4802 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4804 #endif /* defined(CONFIG_USER_ONLY) */
4808 static void gen_mfsrin_64b(DisasContext
*ctx
)
4810 #if defined(CONFIG_USER_ONLY)
4816 t0
= tcg_temp_new();
4817 tcg_gen_extract_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28, 4);
4818 gen_helper_load_sr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
4820 #endif /* defined(CONFIG_USER_ONLY) */
4824 static void gen_mtsr_64b(DisasContext
*ctx
)
4826 #if defined(CONFIG_USER_ONLY)
4832 t0
= tcg_const_tl(SR(ctx
->opcode
));
4833 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4835 #endif /* defined(CONFIG_USER_ONLY) */
4839 static void gen_mtsrin_64b(DisasContext
*ctx
)
4841 #if defined(CONFIG_USER_ONLY)
4847 t0
= tcg_temp_new();
4848 tcg_gen_extract_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 28, 4);
4849 gen_helper_store_sr(cpu_env
, t0
, cpu_gpr
[rS(ctx
->opcode
)]);
4851 #endif /* defined(CONFIG_USER_ONLY) */
4855 static void gen_slbmte(DisasContext
*ctx
)
4857 #if defined(CONFIG_USER_ONLY)
4862 gen_helper_store_slb(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)],
4863 cpu_gpr
[rS(ctx
->opcode
)]);
4864 #endif /* defined(CONFIG_USER_ONLY) */
4867 static void gen_slbmfee(DisasContext
*ctx
)
4869 #if defined(CONFIG_USER_ONLY)
4874 gen_helper_load_slb_esid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4875 cpu_gpr
[rB(ctx
->opcode
)]);
4876 #endif /* defined(CONFIG_USER_ONLY) */
4879 static void gen_slbmfev(DisasContext
*ctx
)
4881 #if defined(CONFIG_USER_ONLY)
4886 gen_helper_load_slb_vsid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4887 cpu_gpr
[rB(ctx
->opcode
)]);
4888 #endif /* defined(CONFIG_USER_ONLY) */
4891 static void gen_slbfee_(DisasContext
*ctx
)
4893 #if defined(CONFIG_USER_ONLY)
4894 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4898 if (unlikely(ctx
->pr
)) {
4899 gen_inval_exception(ctx
, POWERPC_EXCP_PRIV_REG
);
4902 gen_helper_find_slb_vsid(cpu_gpr
[rS(ctx
->opcode
)], cpu_env
,
4903 cpu_gpr
[rB(ctx
->opcode
)]);
4904 l1
= gen_new_label();
4905 l2
= gen_new_label();
4906 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
4907 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rS(ctx
->opcode
)], -1, l1
);
4908 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], CRF_EQ
);
4911 tcg_gen_movi_tl(cpu_gpr
[rS(ctx
->opcode
)], 0);
4915 #endif /* defined(TARGET_PPC64) */
4917 /*** Lookaside buffer management ***/
4918 /* Optional & supervisor only: */
4921 static void gen_tlbia(DisasContext
*ctx
)
4923 #if defined(CONFIG_USER_ONLY)
4928 gen_helper_tlbia(cpu_env
);
4929 #endif /* defined(CONFIG_USER_ONLY) */
4933 static void gen_tlbiel(DisasContext
*ctx
)
4935 #if defined(CONFIG_USER_ONLY)
4940 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4941 #endif /* defined(CONFIG_USER_ONLY) */
4945 static void gen_tlbie(DisasContext
*ctx
)
4947 #if defined(CONFIG_USER_ONLY)
4953 CHK_SV
; /* If gtse is set then tlbie is supervisor privileged */
4955 CHK_HV
; /* Else hypervisor privileged */
4958 if (NARROW_MODE(ctx
)) {
4959 TCGv t0
= tcg_temp_new();
4960 tcg_gen_ext32u_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)]);
4961 gen_helper_tlbie(cpu_env
, t0
);
4964 gen_helper_tlbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
4966 t1
= tcg_temp_new_i32();
4967 tcg_gen_ld_i32(t1
, cpu_env
, offsetof(CPUPPCState
, tlb_need_flush
));
4968 tcg_gen_ori_i32(t1
, t1
, TLB_NEED_GLOBAL_FLUSH
);
4969 tcg_gen_st_i32(t1
, cpu_env
, offsetof(CPUPPCState
, tlb_need_flush
));
4970 tcg_temp_free_i32(t1
);
4971 #endif /* defined(CONFIG_USER_ONLY) */
4975 static void gen_tlbsync(DisasContext
*ctx
)
4977 #if defined(CONFIG_USER_ONLY)
4982 CHK_SV
; /* If gtse is set then tlbsync is supervisor privileged */
4984 CHK_HV
; /* Else hypervisor privileged */
4987 /* BookS does both ptesync and tlbsync make tlbsync a nop for server */
4988 if (ctx
->insns_flags
& PPC_BOOKE
) {
4989 gen_check_tlb_flush(ctx
, true);
4991 #endif /* defined(CONFIG_USER_ONLY) */
4994 #if defined(TARGET_PPC64)
4996 static void gen_slbia(DisasContext
*ctx
)
4998 #if defined(CONFIG_USER_ONLY)
5003 gen_helper_slbia(cpu_env
);
5004 #endif /* defined(CONFIG_USER_ONLY) */
5008 static void gen_slbie(DisasContext
*ctx
)
5010 #if defined(CONFIG_USER_ONLY)
5015 gen_helper_slbie(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5016 #endif /* defined(CONFIG_USER_ONLY) */
5020 static void gen_slbieg(DisasContext
*ctx
)
5022 #if defined(CONFIG_USER_ONLY)
5027 gen_helper_slbieg(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5028 #endif /* defined(CONFIG_USER_ONLY) */
5032 static void gen_slbsync(DisasContext
*ctx
)
5034 #if defined(CONFIG_USER_ONLY)
5038 gen_check_tlb_flush(ctx
, true);
5039 #endif /* defined(CONFIG_USER_ONLY) */
5042 #endif /* defined(TARGET_PPC64) */
5044 /*** External control ***/
5048 static void gen_eciwx(DisasContext
*ctx
)
5051 /* Should check EAR[E] ! */
5052 gen_set_access_type(ctx
, ACCESS_EXT
);
5053 t0
= tcg_temp_new();
5054 gen_addr_reg_index(ctx
, t0
);
5055 tcg_gen_qemu_ld_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, ctx
->mem_idx
,
5056 DEF_MEMOP(MO_UL
| MO_ALIGN
));
5061 static void gen_ecowx(DisasContext
*ctx
)
5064 /* Should check EAR[E] ! */
5065 gen_set_access_type(ctx
, ACCESS_EXT
);
5066 t0
= tcg_temp_new();
5067 gen_addr_reg_index(ctx
, t0
);
5068 tcg_gen_qemu_st_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
, ctx
->mem_idx
,
5069 DEF_MEMOP(MO_UL
| MO_ALIGN
));
5073 /* PowerPC 601 specific instructions */
5076 static void gen_abs(DisasContext
*ctx
)
5078 TCGLabel
*l1
= gen_new_label();
5079 TCGLabel
*l2
= gen_new_label();
5080 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
5081 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5084 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5086 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5087 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5092 static void gen_abso(DisasContext
*ctx
)
5094 TCGLabel
*l1
= gen_new_label();
5095 TCGLabel
*l2
= gen_new_label();
5096 TCGLabel
*l3
= gen_new_label();
5097 /* Start with XER OV disabled, the most likely case */
5098 tcg_gen_movi_tl(cpu_ov
, 0);
5099 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rA(ctx
->opcode
)], 0, l2
);
5100 tcg_gen_brcondi_tl(TCG_COND_NE
, cpu_gpr
[rA(ctx
->opcode
)], 0x80000000, l1
);
5101 tcg_gen_movi_tl(cpu_ov
, 1);
5102 tcg_gen_movi_tl(cpu_so
, 1);
5105 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5108 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5110 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5111 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5116 static void gen_clcs(DisasContext
*ctx
)
5118 TCGv_i32 t0
= tcg_const_i32(rA(ctx
->opcode
));
5119 gen_helper_clcs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5120 tcg_temp_free_i32(t0
);
5121 /* Rc=1 sets CR0 to an undefined state */
5125 static void gen_div(DisasContext
*ctx
)
5127 gen_helper_div(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5128 cpu_gpr
[rB(ctx
->opcode
)]);
5129 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5130 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5135 static void gen_divo(DisasContext
*ctx
)
5137 gen_helper_divo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5138 cpu_gpr
[rB(ctx
->opcode
)]);
5139 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5140 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5145 static void gen_divs(DisasContext
*ctx
)
5147 gen_helper_divs(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
5148 cpu_gpr
[rB(ctx
->opcode
)]);
5149 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5150 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5154 /* divso - divso. */
5155 static void gen_divso(DisasContext
*ctx
)
5157 gen_helper_divso(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
5158 cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
5159 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5160 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5165 static void gen_doz(DisasContext
*ctx
)
5167 TCGLabel
*l1
= gen_new_label();
5168 TCGLabel
*l2
= gen_new_label();
5169 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)],
5170 cpu_gpr
[rA(ctx
->opcode
)], l1
);
5171 tcg_gen_sub_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)],
5172 cpu_gpr
[rA(ctx
->opcode
)]);
5175 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
5177 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5178 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5183 static void gen_dozo(DisasContext
*ctx
)
5185 TCGLabel
*l1
= gen_new_label();
5186 TCGLabel
*l2
= gen_new_label();
5187 TCGv t0
= tcg_temp_new();
5188 TCGv t1
= tcg_temp_new();
5189 TCGv t2
= tcg_temp_new();
5190 /* Start with XER OV disabled, the most likely case */
5191 tcg_gen_movi_tl(cpu_ov
, 0);
5192 tcg_gen_brcond_tl(TCG_COND_GE
, cpu_gpr
[rB(ctx
->opcode
)],
5193 cpu_gpr
[rA(ctx
->opcode
)], l1
);
5194 tcg_gen_sub_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5195 tcg_gen_xor_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5196 tcg_gen_xor_tl(t2
, cpu_gpr
[rA(ctx
->opcode
)], t0
);
5197 tcg_gen_andc_tl(t1
, t1
, t2
);
5198 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], t0
);
5199 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
5200 tcg_gen_movi_tl(cpu_ov
, 1);
5201 tcg_gen_movi_tl(cpu_so
, 1);
5204 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
5209 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5210 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5215 static void gen_dozi(DisasContext
*ctx
)
5217 target_long simm
= SIMM(ctx
->opcode
);
5218 TCGLabel
*l1
= gen_new_label();
5219 TCGLabel
*l2
= gen_new_label();
5220 tcg_gen_brcondi_tl(TCG_COND_LT
, cpu_gpr
[rA(ctx
->opcode
)], simm
, l1
);
5221 tcg_gen_subfi_tl(cpu_gpr
[rD(ctx
->opcode
)], simm
, cpu_gpr
[rA(ctx
->opcode
)]);
5224 tcg_gen_movi_tl(cpu_gpr
[rD(ctx
->opcode
)], 0);
5226 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5227 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5231 /* lscbx - lscbx. */
5232 static void gen_lscbx(DisasContext
*ctx
)
5234 TCGv t0
= tcg_temp_new();
5235 TCGv_i32 t1
= tcg_const_i32(rD(ctx
->opcode
));
5236 TCGv_i32 t2
= tcg_const_i32(rA(ctx
->opcode
));
5237 TCGv_i32 t3
= tcg_const_i32(rB(ctx
->opcode
));
5239 gen_addr_reg_index(ctx
, t0
);
5240 gen_helper_lscbx(t0
, cpu_env
, t0
, t1
, t2
, t3
);
5241 tcg_temp_free_i32(t1
);
5242 tcg_temp_free_i32(t2
);
5243 tcg_temp_free_i32(t3
);
5244 tcg_gen_andi_tl(cpu_xer
, cpu_xer
, ~0x7F);
5245 tcg_gen_or_tl(cpu_xer
, cpu_xer
, t0
);
5246 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5247 gen_set_Rc0(ctx
, t0
);
5252 /* maskg - maskg. */
5253 static void gen_maskg(DisasContext
*ctx
)
5255 TCGLabel
*l1
= gen_new_label();
5256 TCGv t0
= tcg_temp_new();
5257 TCGv t1
= tcg_temp_new();
5258 TCGv t2
= tcg_temp_new();
5259 TCGv t3
= tcg_temp_new();
5260 tcg_gen_movi_tl(t3
, 0xFFFFFFFF);
5261 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5262 tcg_gen_andi_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 0x1F);
5263 tcg_gen_addi_tl(t2
, t0
, 1);
5264 tcg_gen_shr_tl(t2
, t3
, t2
);
5265 tcg_gen_shr_tl(t3
, t3
, t1
);
5266 tcg_gen_xor_tl(cpu_gpr
[rA(ctx
->opcode
)], t2
, t3
);
5267 tcg_gen_brcond_tl(TCG_COND_GE
, t0
, t1
, l1
);
5268 tcg_gen_neg_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5274 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5275 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5279 /* maskir - maskir. */
5280 static void gen_maskir(DisasContext
*ctx
)
5282 TCGv t0
= tcg_temp_new();
5283 TCGv t1
= tcg_temp_new();
5284 tcg_gen_and_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
5285 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
5286 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5289 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5290 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5295 static void gen_mul(DisasContext
*ctx
)
5297 TCGv_i64 t0
= tcg_temp_new_i64();
5298 TCGv_i64 t1
= tcg_temp_new_i64();
5299 TCGv t2
= tcg_temp_new();
5300 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
5301 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
5302 tcg_gen_mul_i64(t0
, t0
, t1
);
5303 tcg_gen_trunc_i64_tl(t2
, t0
);
5304 gen_store_spr(SPR_MQ
, t2
);
5305 tcg_gen_shri_i64(t1
, t0
, 32);
5306 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
5307 tcg_temp_free_i64(t0
);
5308 tcg_temp_free_i64(t1
);
5310 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5311 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5316 static void gen_mulo(DisasContext
*ctx
)
5318 TCGLabel
*l1
= gen_new_label();
5319 TCGv_i64 t0
= tcg_temp_new_i64();
5320 TCGv_i64 t1
= tcg_temp_new_i64();
5321 TCGv t2
= tcg_temp_new();
5322 /* Start with XER OV disabled, the most likely case */
5323 tcg_gen_movi_tl(cpu_ov
, 0);
5324 tcg_gen_extu_tl_i64(t0
, cpu_gpr
[rA(ctx
->opcode
)]);
5325 tcg_gen_extu_tl_i64(t1
, cpu_gpr
[rB(ctx
->opcode
)]);
5326 tcg_gen_mul_i64(t0
, t0
, t1
);
5327 tcg_gen_trunc_i64_tl(t2
, t0
);
5328 gen_store_spr(SPR_MQ
, t2
);
5329 tcg_gen_shri_i64(t1
, t0
, 32);
5330 tcg_gen_trunc_i64_tl(cpu_gpr
[rD(ctx
->opcode
)], t1
);
5331 tcg_gen_ext32s_i64(t1
, t0
);
5332 tcg_gen_brcond_i64(TCG_COND_EQ
, t0
, t1
, l1
);
5333 tcg_gen_movi_tl(cpu_ov
, 1);
5334 tcg_gen_movi_tl(cpu_so
, 1);
5336 tcg_temp_free_i64(t0
);
5337 tcg_temp_free_i64(t1
);
5339 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5340 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5345 static void gen_nabs(DisasContext
*ctx
)
5347 TCGLabel
*l1
= gen_new_label();
5348 TCGLabel
*l2
= gen_new_label();
5349 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
5350 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5353 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5355 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5356 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5360 /* nabso - nabso. */
5361 static void gen_nabso(DisasContext
*ctx
)
5363 TCGLabel
*l1
= gen_new_label();
5364 TCGLabel
*l2
= gen_new_label();
5365 tcg_gen_brcondi_tl(TCG_COND_GT
, cpu_gpr
[rA(ctx
->opcode
)], 0, l1
);
5366 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5369 tcg_gen_neg_tl(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5371 /* nabs never overflows */
5372 tcg_gen_movi_tl(cpu_ov
, 0);
5373 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5374 gen_set_Rc0(ctx
, cpu_gpr
[rD(ctx
->opcode
)]);
5379 static void gen_rlmi(DisasContext
*ctx
)
5381 uint32_t mb
= MB(ctx
->opcode
);
5382 uint32_t me
= ME(ctx
->opcode
);
5383 TCGv t0
= tcg_temp_new();
5384 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5385 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5386 tcg_gen_andi_tl(t0
, t0
, MASK(mb
, me
));
5387 tcg_gen_andi_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)],
5389 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)], t0
);
5391 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5392 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5397 static void gen_rrib(DisasContext
*ctx
)
5399 TCGv t0
= tcg_temp_new();
5400 TCGv t1
= tcg_temp_new();
5401 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5402 tcg_gen_movi_tl(t1
, 0x80000000);
5403 tcg_gen_shr_tl(t1
, t1
, t0
);
5404 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5405 tcg_gen_and_tl(t0
, t0
, t1
);
5406 tcg_gen_andc_tl(t1
, cpu_gpr
[rA(ctx
->opcode
)], t1
);
5407 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5410 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5411 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5416 static void gen_sle(DisasContext
*ctx
)
5418 TCGv t0
= tcg_temp_new();
5419 TCGv t1
= tcg_temp_new();
5420 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5421 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5422 tcg_gen_subfi_tl(t1
, 32, t1
);
5423 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5424 tcg_gen_or_tl(t1
, t0
, t1
);
5425 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5426 gen_store_spr(SPR_MQ
, t1
);
5429 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5430 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5435 static void gen_sleq(DisasContext
*ctx
)
5437 TCGv t0
= tcg_temp_new();
5438 TCGv t1
= tcg_temp_new();
5439 TCGv t2
= tcg_temp_new();
5440 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5441 tcg_gen_movi_tl(t2
, 0xFFFFFFFF);
5442 tcg_gen_shl_tl(t2
, t2
, t0
);
5443 tcg_gen_rotl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5444 gen_load_spr(t1
, SPR_MQ
);
5445 gen_store_spr(SPR_MQ
, t0
);
5446 tcg_gen_and_tl(t0
, t0
, t2
);
5447 tcg_gen_andc_tl(t1
, t1
, t2
);
5448 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5452 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5453 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5458 static void gen_sliq(DisasContext
*ctx
)
5460 int sh
= SH(ctx
->opcode
);
5461 TCGv t0
= tcg_temp_new();
5462 TCGv t1
= tcg_temp_new();
5463 tcg_gen_shli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5464 tcg_gen_shri_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5465 tcg_gen_or_tl(t1
, t0
, t1
);
5466 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5467 gen_store_spr(SPR_MQ
, t1
);
5470 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5471 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5475 /* slliq - slliq. */
5476 static void gen_slliq(DisasContext
*ctx
)
5478 int sh
= SH(ctx
->opcode
);
5479 TCGv t0
= tcg_temp_new();
5480 TCGv t1
= tcg_temp_new();
5481 tcg_gen_rotli_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5482 gen_load_spr(t1
, SPR_MQ
);
5483 gen_store_spr(SPR_MQ
, t0
);
5484 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
<< sh
));
5485 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
<< sh
));
5486 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5489 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5490 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5495 static void gen_sllq(DisasContext
*ctx
)
5497 TCGLabel
*l1
= gen_new_label();
5498 TCGLabel
*l2
= gen_new_label();
5499 TCGv t0
= tcg_temp_local_new();
5500 TCGv t1
= tcg_temp_local_new();
5501 TCGv t2
= tcg_temp_local_new();
5502 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5503 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5504 tcg_gen_shl_tl(t1
, t1
, t2
);
5505 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5506 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5507 gen_load_spr(t0
, SPR_MQ
);
5508 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5511 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5512 gen_load_spr(t2
, SPR_MQ
);
5513 tcg_gen_andc_tl(t1
, t2
, t1
);
5514 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5519 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5520 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5525 static void gen_slq(DisasContext
*ctx
)
5527 TCGLabel
*l1
= gen_new_label();
5528 TCGv t0
= tcg_temp_new();
5529 TCGv t1
= tcg_temp_new();
5530 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5531 tcg_gen_shl_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5532 tcg_gen_subfi_tl(t1
, 32, t1
);
5533 tcg_gen_shr_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5534 tcg_gen_or_tl(t1
, t0
, t1
);
5535 gen_store_spr(SPR_MQ
, t1
);
5536 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5537 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5538 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
5539 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
5543 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5544 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5548 /* sraiq - sraiq. */
5549 static void gen_sraiq(DisasContext
*ctx
)
5551 int sh
= SH(ctx
->opcode
);
5552 TCGLabel
*l1
= gen_new_label();
5553 TCGv t0
= tcg_temp_new();
5554 TCGv t1
= tcg_temp_new();
5555 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5556 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5557 tcg_gen_or_tl(t0
, t0
, t1
);
5558 gen_store_spr(SPR_MQ
, t0
);
5559 tcg_gen_movi_tl(cpu_ca
, 0);
5560 tcg_gen_brcondi_tl(TCG_COND_EQ
, t1
, 0, l1
);
5561 tcg_gen_brcondi_tl(TCG_COND_GE
, cpu_gpr
[rS(ctx
->opcode
)], 0, l1
);
5562 tcg_gen_movi_tl(cpu_ca
, 1);
5564 tcg_gen_sari_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], sh
);
5567 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5568 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5573 static void gen_sraq(DisasContext
*ctx
)
5575 TCGLabel
*l1
= gen_new_label();
5576 TCGLabel
*l2
= gen_new_label();
5577 TCGv t0
= tcg_temp_new();
5578 TCGv t1
= tcg_temp_local_new();
5579 TCGv t2
= tcg_temp_local_new();
5580 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5581 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5582 tcg_gen_sar_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5583 tcg_gen_subfi_tl(t2
, 32, t2
);
5584 tcg_gen_shl_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5585 tcg_gen_or_tl(t0
, t0
, t2
);
5586 gen_store_spr(SPR_MQ
, t0
);
5587 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5588 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l1
);
5589 tcg_gen_mov_tl(t2
, cpu_gpr
[rS(ctx
->opcode
)]);
5590 tcg_gen_sari_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 31);
5593 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t1
);
5594 tcg_gen_movi_tl(cpu_ca
, 0);
5595 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l2
);
5596 tcg_gen_brcondi_tl(TCG_COND_EQ
, t2
, 0, l2
);
5597 tcg_gen_movi_tl(cpu_ca
, 1);
5601 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5602 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5607 static void gen_sre(DisasContext
*ctx
)
5609 TCGv t0
= tcg_temp_new();
5610 TCGv t1
= tcg_temp_new();
5611 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5612 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5613 tcg_gen_subfi_tl(t1
, 32, t1
);
5614 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5615 tcg_gen_or_tl(t1
, t0
, t1
);
5616 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5617 gen_store_spr(SPR_MQ
, t1
);
5620 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5621 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5626 static void gen_srea(DisasContext
*ctx
)
5628 TCGv t0
= tcg_temp_new();
5629 TCGv t1
= tcg_temp_new();
5630 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5631 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5632 gen_store_spr(SPR_MQ
, t0
);
5633 tcg_gen_sar_tl(cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rS(ctx
->opcode
)], t1
);
5636 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5637 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5642 static void gen_sreq(DisasContext
*ctx
)
5644 TCGv t0
= tcg_temp_new();
5645 TCGv t1
= tcg_temp_new();
5646 TCGv t2
= tcg_temp_new();
5647 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5648 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5649 tcg_gen_shr_tl(t1
, t1
, t0
);
5650 tcg_gen_rotr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t0
);
5651 gen_load_spr(t2
, SPR_MQ
);
5652 gen_store_spr(SPR_MQ
, t0
);
5653 tcg_gen_and_tl(t0
, t0
, t1
);
5654 tcg_gen_andc_tl(t2
, t2
, t1
);
5655 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5659 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5660 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5665 static void gen_sriq(DisasContext
*ctx
)
5667 int sh
= SH(ctx
->opcode
);
5668 TCGv t0
= tcg_temp_new();
5669 TCGv t1
= tcg_temp_new();
5670 tcg_gen_shri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5671 tcg_gen_shli_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], 32 - sh
);
5672 tcg_gen_or_tl(t1
, t0
, t1
);
5673 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5674 gen_store_spr(SPR_MQ
, t1
);
5677 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5678 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5683 static void gen_srliq(DisasContext
*ctx
)
5685 int sh
= SH(ctx
->opcode
);
5686 TCGv t0
= tcg_temp_new();
5687 TCGv t1
= tcg_temp_new();
5688 tcg_gen_rotri_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], sh
);
5689 gen_load_spr(t1
, SPR_MQ
);
5690 gen_store_spr(SPR_MQ
, t0
);
5691 tcg_gen_andi_tl(t0
, t0
, (0xFFFFFFFFU
>> sh
));
5692 tcg_gen_andi_tl(t1
, t1
, ~(0xFFFFFFFFU
>> sh
));
5693 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5696 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5697 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5702 static void gen_srlq(DisasContext
*ctx
)
5704 TCGLabel
*l1
= gen_new_label();
5705 TCGLabel
*l2
= gen_new_label();
5706 TCGv t0
= tcg_temp_local_new();
5707 TCGv t1
= tcg_temp_local_new();
5708 TCGv t2
= tcg_temp_local_new();
5709 tcg_gen_andi_tl(t2
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5710 tcg_gen_movi_tl(t1
, 0xFFFFFFFF);
5711 tcg_gen_shr_tl(t2
, t1
, t2
);
5712 tcg_gen_andi_tl(t0
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5713 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5714 gen_load_spr(t0
, SPR_MQ
);
5715 tcg_gen_and_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t2
);
5718 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t2
);
5719 tcg_gen_and_tl(t0
, t0
, t2
);
5720 gen_load_spr(t1
, SPR_MQ
);
5721 tcg_gen_andc_tl(t1
, t1
, t2
);
5722 tcg_gen_or_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
, t1
);
5727 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5728 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5733 static void gen_srq(DisasContext
*ctx
)
5735 TCGLabel
*l1
= gen_new_label();
5736 TCGv t0
= tcg_temp_new();
5737 TCGv t1
= tcg_temp_new();
5738 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x1F);
5739 tcg_gen_shr_tl(t0
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5740 tcg_gen_subfi_tl(t1
, 32, t1
);
5741 tcg_gen_shl_tl(t1
, cpu_gpr
[rS(ctx
->opcode
)], t1
);
5742 tcg_gen_or_tl(t1
, t0
, t1
);
5743 gen_store_spr(SPR_MQ
, t1
);
5744 tcg_gen_andi_tl(t1
, cpu_gpr
[rB(ctx
->opcode
)], 0x20);
5745 tcg_gen_mov_tl(cpu_gpr
[rA(ctx
->opcode
)], t0
);
5746 tcg_gen_brcondi_tl(TCG_COND_EQ
, t0
, 0, l1
);
5747 tcg_gen_movi_tl(cpu_gpr
[rA(ctx
->opcode
)], 0);
5751 if (unlikely(Rc(ctx
->opcode
) != 0)) {
5752 gen_set_Rc0(ctx
, cpu_gpr
[rA(ctx
->opcode
)]);
5756 /* PowerPC 602 specific instructions */
5759 static void gen_dsa(DisasContext
*ctx
)
5762 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5766 static void gen_esa(DisasContext
*ctx
)
5769 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5773 static void gen_mfrom(DisasContext
*ctx
)
5775 #if defined(CONFIG_USER_ONLY)
5779 gen_helper_602_mfrom(cpu_gpr
[rD(ctx
->opcode
)], cpu_gpr
[rA(ctx
->opcode
)]);
5780 #endif /* defined(CONFIG_USER_ONLY) */
5783 /* 602 - 603 - G2 TLB management */
5786 static void gen_tlbld_6xx(DisasContext
*ctx
)
5788 #if defined(CONFIG_USER_ONLY)
5792 gen_helper_6xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5793 #endif /* defined(CONFIG_USER_ONLY) */
5797 static void gen_tlbli_6xx(DisasContext
*ctx
)
5799 #if defined(CONFIG_USER_ONLY)
5803 gen_helper_6xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5804 #endif /* defined(CONFIG_USER_ONLY) */
5807 /* 74xx TLB management */
5810 static void gen_tlbld_74xx(DisasContext
*ctx
)
5812 #if defined(CONFIG_USER_ONLY)
5816 gen_helper_74xx_tlbd(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5817 #endif /* defined(CONFIG_USER_ONLY) */
5821 static void gen_tlbli_74xx(DisasContext
*ctx
)
5823 #if defined(CONFIG_USER_ONLY)
5827 gen_helper_74xx_tlbi(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5828 #endif /* defined(CONFIG_USER_ONLY) */
5831 /* POWER instructions not in PowerPC 601 */
5834 static void gen_clf(DisasContext
*ctx
)
5836 /* Cache line flush: implemented as no-op */
5840 static void gen_cli(DisasContext
*ctx
)
5842 #if defined(CONFIG_USER_ONLY)
5845 /* Cache line invalidate: privileged and treated as no-op */
5847 #endif /* defined(CONFIG_USER_ONLY) */
5851 static void gen_dclst(DisasContext
*ctx
)
5853 /* Data cache line store: treated as no-op */
5856 static void gen_mfsri(DisasContext
*ctx
)
5858 #if defined(CONFIG_USER_ONLY)
5861 int ra
= rA(ctx
->opcode
);
5862 int rd
= rD(ctx
->opcode
);
5866 t0
= tcg_temp_new();
5867 gen_addr_reg_index(ctx
, t0
);
5868 tcg_gen_extract_tl(t0
, t0
, 28, 4);
5869 gen_helper_load_sr(cpu_gpr
[rd
], cpu_env
, t0
);
5871 if (ra
!= 0 && ra
!= rd
) {
5872 tcg_gen_mov_tl(cpu_gpr
[ra
], cpu_gpr
[rd
]);
5874 #endif /* defined(CONFIG_USER_ONLY) */
5877 static void gen_rac(DisasContext
*ctx
)
5879 #if defined(CONFIG_USER_ONLY)
5885 t0
= tcg_temp_new();
5886 gen_addr_reg_index(ctx
, t0
);
5887 gen_helper_rac(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
5889 #endif /* defined(CONFIG_USER_ONLY) */
5892 static void gen_rfsvc(DisasContext
*ctx
)
5894 #if defined(CONFIG_USER_ONLY)
5899 gen_helper_rfsvc(cpu_env
);
5900 gen_sync_exception(ctx
);
5901 #endif /* defined(CONFIG_USER_ONLY) */
5904 /* svc is not implemented for now */
5906 /* BookE specific instructions */
5908 /* XXX: not implemented on 440 ? */
5909 static void gen_mfapidi(DisasContext
*ctx
)
5912 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
5915 /* XXX: not implemented on 440 ? */
5916 static void gen_tlbiva(DisasContext
*ctx
)
5918 #if defined(CONFIG_USER_ONLY)
5924 t0
= tcg_temp_new();
5925 gen_addr_reg_index(ctx
, t0
);
5926 gen_helper_tlbiva(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
5928 #endif /* defined(CONFIG_USER_ONLY) */
5931 /* All 405 MAC instructions are translated here */
5932 static inline void gen_405_mulladd_insn(DisasContext
*ctx
, int opc2
, int opc3
,
5933 int ra
, int rb
, int rt
, int Rc
)
5937 t0
= tcg_temp_local_new();
5938 t1
= tcg_temp_local_new();
5940 switch (opc3
& 0x0D) {
5942 /* macchw - macchw. - macchwo - macchwo. */
5943 /* macchws - macchws. - macchwso - macchwso. */
5944 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5945 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5946 /* mulchw - mulchw. */
5947 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5948 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5949 tcg_gen_ext16s_tl(t1
, t1
);
5952 /* macchwu - macchwu. - macchwuo - macchwuo. */
5953 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5954 /* mulchwu - mulchwu. */
5955 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5956 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5957 tcg_gen_ext16u_tl(t1
, t1
);
5960 /* machhw - machhw. - machhwo - machhwo. */
5961 /* machhws - machhws. - machhwso - machhwso. */
5962 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5963 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5964 /* mulhhw - mulhhw. */
5965 tcg_gen_sari_tl(t0
, cpu_gpr
[ra
], 16);
5966 tcg_gen_ext16s_tl(t0
, t0
);
5967 tcg_gen_sari_tl(t1
, cpu_gpr
[rb
], 16);
5968 tcg_gen_ext16s_tl(t1
, t1
);
5971 /* machhwu - machhwu. - machhwuo - machhwuo. */
5972 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5973 /* mulhhwu - mulhhwu. */
5974 tcg_gen_shri_tl(t0
, cpu_gpr
[ra
], 16);
5975 tcg_gen_ext16u_tl(t0
, t0
);
5976 tcg_gen_shri_tl(t1
, cpu_gpr
[rb
], 16);
5977 tcg_gen_ext16u_tl(t1
, t1
);
5980 /* maclhw - maclhw. - maclhwo - maclhwo. */
5981 /* maclhws - maclhws. - maclhwso - maclhwso. */
5982 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5983 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5984 /* mullhw - mullhw. */
5985 tcg_gen_ext16s_tl(t0
, cpu_gpr
[ra
]);
5986 tcg_gen_ext16s_tl(t1
, cpu_gpr
[rb
]);
5989 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5990 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5991 /* mullhwu - mullhwu. */
5992 tcg_gen_ext16u_tl(t0
, cpu_gpr
[ra
]);
5993 tcg_gen_ext16u_tl(t1
, cpu_gpr
[rb
]);
5997 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5998 tcg_gen_mul_tl(t1
, t0
, t1
);
6000 /* nmultiply-and-accumulate (0x0E) */
6001 tcg_gen_sub_tl(t0
, cpu_gpr
[rt
], t1
);
6003 /* multiply-and-accumulate (0x0C) */
6004 tcg_gen_add_tl(t0
, cpu_gpr
[rt
], t1
);
6008 /* Check overflow and/or saturate */
6009 TCGLabel
*l1
= gen_new_label();
6012 /* Start with XER OV disabled, the most likely case */
6013 tcg_gen_movi_tl(cpu_ov
, 0);
6017 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t1
);
6018 tcg_gen_brcondi_tl(TCG_COND_GE
, t1
, 0, l1
);
6019 tcg_gen_xor_tl(t1
, cpu_gpr
[rt
], t0
);
6020 tcg_gen_brcondi_tl(TCG_COND_LT
, t1
, 0, l1
);
6023 tcg_gen_sari_tl(t0
, cpu_gpr
[rt
], 31);
6024 tcg_gen_xori_tl(t0
, t0
, 0x7fffffff);
6028 tcg_gen_brcond_tl(TCG_COND_GEU
, t0
, t1
, l1
);
6031 tcg_gen_movi_tl(t0
, UINT32_MAX
);
6035 /* Check overflow */
6036 tcg_gen_movi_tl(cpu_ov
, 1);
6037 tcg_gen_movi_tl(cpu_so
, 1);
6040 tcg_gen_mov_tl(cpu_gpr
[rt
], t0
);
6043 tcg_gen_mul_tl(cpu_gpr
[rt
], t0
, t1
);
6047 if (unlikely(Rc
) != 0) {
6049 gen_set_Rc0(ctx
, cpu_gpr
[rt
]);
6053 #define GEN_MAC_HANDLER(name, opc2, opc3) \
6054 static void glue(gen_, name)(DisasContext *ctx) \
6056 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
6057 rD(ctx->opcode), Rc(ctx->opcode)); \
6060 /* macchw - macchw. */
6061 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05);
6062 /* macchwo - macchwo. */
6063 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15);
6064 /* macchws - macchws. */
6065 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07);
6066 /* macchwso - macchwso. */
6067 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17);
6068 /* macchwsu - macchwsu. */
6069 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06);
6070 /* macchwsuo - macchwsuo. */
6071 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16);
6072 /* macchwu - macchwu. */
6073 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04);
6074 /* macchwuo - macchwuo. */
6075 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14);
6076 /* machhw - machhw. */
6077 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01);
6078 /* machhwo - machhwo. */
6079 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11);
6080 /* machhws - machhws. */
6081 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03);
6082 /* machhwso - machhwso. */
6083 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13);
6084 /* machhwsu - machhwsu. */
6085 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02);
6086 /* machhwsuo - machhwsuo. */
6087 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12);
6088 /* machhwu - machhwu. */
6089 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00);
6090 /* machhwuo - machhwuo. */
6091 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10);
6092 /* maclhw - maclhw. */
6093 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D);
6094 /* maclhwo - maclhwo. */
6095 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D);
6096 /* maclhws - maclhws. */
6097 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F);
6098 /* maclhwso - maclhwso. */
6099 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F);
6100 /* maclhwu - maclhwu. */
6101 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C);
6102 /* maclhwuo - maclhwuo. */
6103 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C);
6104 /* maclhwsu - maclhwsu. */
6105 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E);
6106 /* maclhwsuo - maclhwsuo. */
6107 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E);
6108 /* nmacchw - nmacchw. */
6109 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05);
6110 /* nmacchwo - nmacchwo. */
6111 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15);
6112 /* nmacchws - nmacchws. */
6113 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07);
6114 /* nmacchwso - nmacchwso. */
6115 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17);
6116 /* nmachhw - nmachhw. */
6117 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01);
6118 /* nmachhwo - nmachhwo. */
6119 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11);
6120 /* nmachhws - nmachhws. */
6121 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03);
6122 /* nmachhwso - nmachhwso. */
6123 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13);
6124 /* nmaclhw - nmaclhw. */
6125 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D);
6126 /* nmaclhwo - nmaclhwo. */
6127 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D);
6128 /* nmaclhws - nmaclhws. */
6129 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F);
6130 /* nmaclhwso - nmaclhwso. */
6131 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F);
6133 /* mulchw - mulchw. */
6134 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05);
6135 /* mulchwu - mulchwu. */
6136 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04);
6137 /* mulhhw - mulhhw. */
6138 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01);
6139 /* mulhhwu - mulhhwu. */
6140 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00);
6141 /* mullhw - mullhw. */
6142 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D);
6143 /* mullhwu - mullhwu. */
6144 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C);
6147 static void gen_mfdcr(DisasContext
*ctx
)
6149 #if defined(CONFIG_USER_ONLY)
6155 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
6156 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, dcrn
);
6157 tcg_temp_free(dcrn
);
6158 #endif /* defined(CONFIG_USER_ONLY) */
6162 static void gen_mtdcr(DisasContext
*ctx
)
6164 #if defined(CONFIG_USER_ONLY)
6170 dcrn
= tcg_const_tl(SPR(ctx
->opcode
));
6171 gen_helper_store_dcr(cpu_env
, dcrn
, cpu_gpr
[rS(ctx
->opcode
)]);
6172 tcg_temp_free(dcrn
);
6173 #endif /* defined(CONFIG_USER_ONLY) */
6177 /* XXX: not implemented on 440 ? */
6178 static void gen_mfdcrx(DisasContext
*ctx
)
6180 #if defined(CONFIG_USER_ONLY)
6184 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6185 cpu_gpr
[rA(ctx
->opcode
)]);
6186 /* Note: Rc update flag set leads to undefined state of Rc0 */
6187 #endif /* defined(CONFIG_USER_ONLY) */
6191 /* XXX: not implemented on 440 ? */
6192 static void gen_mtdcrx(DisasContext
*ctx
)
6194 #if defined(CONFIG_USER_ONLY)
6198 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6199 cpu_gpr
[rS(ctx
->opcode
)]);
6200 /* Note: Rc update flag set leads to undefined state of Rc0 */
6201 #endif /* defined(CONFIG_USER_ONLY) */
6204 /* mfdcrux (PPC 460) : user-mode access to DCR */
6205 static void gen_mfdcrux(DisasContext
*ctx
)
6207 gen_helper_load_dcr(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6208 cpu_gpr
[rA(ctx
->opcode
)]);
6209 /* Note: Rc update flag set leads to undefined state of Rc0 */
6212 /* mtdcrux (PPC 460) : user-mode access to DCR */
6213 static void gen_mtdcrux(DisasContext
*ctx
)
6215 gen_helper_store_dcr(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6216 cpu_gpr
[rS(ctx
->opcode
)]);
6217 /* Note: Rc update flag set leads to undefined state of Rc0 */
6221 static void gen_dccci(DisasContext
*ctx
)
6224 /* interpreted as no-op */
6228 static void gen_dcread(DisasContext
*ctx
)
6230 #if defined(CONFIG_USER_ONLY)
6236 gen_set_access_type(ctx
, ACCESS_CACHE
);
6237 EA
= tcg_temp_new();
6238 gen_addr_reg_index(ctx
, EA
);
6239 val
= tcg_temp_new();
6240 gen_qemu_ld32u(ctx
, val
, EA
);
6242 tcg_gen_mov_tl(cpu_gpr
[rD(ctx
->opcode
)], EA
);
6244 #endif /* defined(CONFIG_USER_ONLY) */
6248 static void gen_icbt_40x(DisasContext
*ctx
)
6251 * interpreted as no-op
6252 * XXX: specification say this is treated as a load by the MMU but
6253 * does not generate any exception
6258 static void gen_iccci(DisasContext
*ctx
)
6261 /* interpreted as no-op */
6265 static void gen_icread(DisasContext
*ctx
)
6268 /* interpreted as no-op */
6271 /* rfci (supervisor only) */
6272 static void gen_rfci_40x(DisasContext
*ctx
)
6274 #if defined(CONFIG_USER_ONLY)
6278 /* Restore CPU state */
6279 gen_helper_40x_rfci(cpu_env
);
6280 gen_sync_exception(ctx
);
6281 #endif /* defined(CONFIG_USER_ONLY) */
6284 static void gen_rfci(DisasContext
*ctx
)
6286 #if defined(CONFIG_USER_ONLY)
6290 /* Restore CPU state */
6291 gen_helper_rfci(cpu_env
);
6292 gen_sync_exception(ctx
);
6293 #endif /* defined(CONFIG_USER_ONLY) */
6296 /* BookE specific */
6298 /* XXX: not implemented on 440 ? */
6299 static void gen_rfdi(DisasContext
*ctx
)
6301 #if defined(CONFIG_USER_ONLY)
6305 /* Restore CPU state */
6306 gen_helper_rfdi(cpu_env
);
6307 gen_sync_exception(ctx
);
6308 #endif /* defined(CONFIG_USER_ONLY) */
6311 /* XXX: not implemented on 440 ? */
6312 static void gen_rfmci(DisasContext
*ctx
)
6314 #if defined(CONFIG_USER_ONLY)
6318 /* Restore CPU state */
6319 gen_helper_rfmci(cpu_env
);
6320 gen_sync_exception(ctx
);
6321 #endif /* defined(CONFIG_USER_ONLY) */
6324 /* TLB management - PowerPC 405 implementation */
6327 static void gen_tlbre_40x(DisasContext
*ctx
)
6329 #if defined(CONFIG_USER_ONLY)
6333 switch (rB(ctx
->opcode
)) {
6335 gen_helper_4xx_tlbre_hi(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6336 cpu_gpr
[rA(ctx
->opcode
)]);
6339 gen_helper_4xx_tlbre_lo(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6340 cpu_gpr
[rA(ctx
->opcode
)]);
6343 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6346 #endif /* defined(CONFIG_USER_ONLY) */
6349 /* tlbsx - tlbsx. */
6350 static void gen_tlbsx_40x(DisasContext
*ctx
)
6352 #if defined(CONFIG_USER_ONLY)
6358 t0
= tcg_temp_new();
6359 gen_addr_reg_index(ctx
, t0
);
6360 gen_helper_4xx_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
6362 if (Rc(ctx
->opcode
)) {
6363 TCGLabel
*l1
= gen_new_label();
6364 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
6365 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
6366 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
6369 #endif /* defined(CONFIG_USER_ONLY) */
6373 static void gen_tlbwe_40x(DisasContext
*ctx
)
6375 #if defined(CONFIG_USER_ONLY)
6380 switch (rB(ctx
->opcode
)) {
6382 gen_helper_4xx_tlbwe_hi(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6383 cpu_gpr
[rS(ctx
->opcode
)]);
6386 gen_helper_4xx_tlbwe_lo(cpu_env
, cpu_gpr
[rA(ctx
->opcode
)],
6387 cpu_gpr
[rS(ctx
->opcode
)]);
6390 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6393 #endif /* defined(CONFIG_USER_ONLY) */
6396 /* TLB management - PowerPC 440 implementation */
6399 static void gen_tlbre_440(DisasContext
*ctx
)
6401 #if defined(CONFIG_USER_ONLY)
6406 switch (rB(ctx
->opcode
)) {
6411 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
6412 gen_helper_440_tlbre(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
,
6413 t0
, cpu_gpr
[rA(ctx
->opcode
)]);
6414 tcg_temp_free_i32(t0
);
6418 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6421 #endif /* defined(CONFIG_USER_ONLY) */
6424 /* tlbsx - tlbsx. */
6425 static void gen_tlbsx_440(DisasContext
*ctx
)
6427 #if defined(CONFIG_USER_ONLY)
6433 t0
= tcg_temp_new();
6434 gen_addr_reg_index(ctx
, t0
);
6435 gen_helper_440_tlbsx(cpu_gpr
[rD(ctx
->opcode
)], cpu_env
, t0
);
6437 if (Rc(ctx
->opcode
)) {
6438 TCGLabel
*l1
= gen_new_label();
6439 tcg_gen_trunc_tl_i32(cpu_crf
[0], cpu_so
);
6440 tcg_gen_brcondi_tl(TCG_COND_EQ
, cpu_gpr
[rD(ctx
->opcode
)], -1, l1
);
6441 tcg_gen_ori_i32(cpu_crf
[0], cpu_crf
[0], 0x02);
6444 #endif /* defined(CONFIG_USER_ONLY) */
6448 static void gen_tlbwe_440(DisasContext
*ctx
)
6450 #if defined(CONFIG_USER_ONLY)
6454 switch (rB(ctx
->opcode
)) {
6459 TCGv_i32 t0
= tcg_const_i32(rB(ctx
->opcode
));
6460 gen_helper_440_tlbwe(cpu_env
, t0
, cpu_gpr
[rA(ctx
->opcode
)],
6461 cpu_gpr
[rS(ctx
->opcode
)]);
6462 tcg_temp_free_i32(t0
);
6466 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6469 #endif /* defined(CONFIG_USER_ONLY) */
6472 /* TLB management - PowerPC BookE 2.06 implementation */
6475 static void gen_tlbre_booke206(DisasContext
*ctx
)
6477 #if defined(CONFIG_USER_ONLY)
6481 gen_helper_booke206_tlbre(cpu_env
);
6482 #endif /* defined(CONFIG_USER_ONLY) */
6485 /* tlbsx - tlbsx. */
6486 static void gen_tlbsx_booke206(DisasContext
*ctx
)
6488 #if defined(CONFIG_USER_ONLY)
6494 if (rA(ctx
->opcode
)) {
6495 t0
= tcg_temp_new();
6496 tcg_gen_mov_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)]);
6498 t0
= tcg_const_tl(0);
6501 tcg_gen_add_tl(t0
, t0
, cpu_gpr
[rB(ctx
->opcode
)]);
6502 gen_helper_booke206_tlbsx(cpu_env
, t0
);
6504 #endif /* defined(CONFIG_USER_ONLY) */
6508 static void gen_tlbwe_booke206(DisasContext
*ctx
)
6510 #if defined(CONFIG_USER_ONLY)
6514 gen_helper_booke206_tlbwe(cpu_env
);
6515 #endif /* defined(CONFIG_USER_ONLY) */
6518 static void gen_tlbivax_booke206(DisasContext
*ctx
)
6520 #if defined(CONFIG_USER_ONLY)
6526 t0
= tcg_temp_new();
6527 gen_addr_reg_index(ctx
, t0
);
6528 gen_helper_booke206_tlbivax(cpu_env
, t0
);
6530 #endif /* defined(CONFIG_USER_ONLY) */
6533 static void gen_tlbilx_booke206(DisasContext
*ctx
)
6535 #if defined(CONFIG_USER_ONLY)
6541 t0
= tcg_temp_new();
6542 gen_addr_reg_index(ctx
, t0
);
6544 switch ((ctx
->opcode
>> 21) & 0x3) {
6546 gen_helper_booke206_tlbilx0(cpu_env
, t0
);
6549 gen_helper_booke206_tlbilx1(cpu_env
, t0
);
6552 gen_helper_booke206_tlbilx3(cpu_env
, t0
);
6555 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6560 #endif /* defined(CONFIG_USER_ONLY) */
6565 static void gen_wrtee(DisasContext
*ctx
)
6567 #if defined(CONFIG_USER_ONLY)
6573 t0
= tcg_temp_new();
6574 tcg_gen_andi_tl(t0
, cpu_gpr
[rD(ctx
->opcode
)], (1 << MSR_EE
));
6575 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6576 tcg_gen_or_tl(cpu_msr
, cpu_msr
, t0
);
6579 * Stop translation to have a chance to raise an exception if we
6580 * just set msr_ee to 1
6582 gen_stop_exception(ctx
);
6583 #endif /* defined(CONFIG_USER_ONLY) */
6587 static void gen_wrteei(DisasContext
*ctx
)
6589 #if defined(CONFIG_USER_ONLY)
6593 if (ctx
->opcode
& 0x00008000) {
6594 tcg_gen_ori_tl(cpu_msr
, cpu_msr
, (1 << MSR_EE
));
6595 /* Stop translation to have a chance to raise an exception */
6596 gen_stop_exception(ctx
);
6598 tcg_gen_andi_tl(cpu_msr
, cpu_msr
, ~(1 << MSR_EE
));
6600 #endif /* defined(CONFIG_USER_ONLY) */
6603 /* PowerPC 440 specific instructions */
6606 static void gen_dlmzb(DisasContext
*ctx
)
6608 TCGv_i32 t0
= tcg_const_i32(Rc(ctx
->opcode
));
6609 gen_helper_dlmzb(cpu_gpr
[rA(ctx
->opcode
)], cpu_env
,
6610 cpu_gpr
[rS(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)], t0
);
6611 tcg_temp_free_i32(t0
);
6614 /* mbar replaces eieio on 440 */
6615 static void gen_mbar(DisasContext
*ctx
)
6617 /* interpreted as no-op */
6620 /* msync replaces sync on 440 */
6621 static void gen_msync_4xx(DisasContext
*ctx
)
6623 /* Only e500 seems to treat reserved bits as invalid */
6624 if ((ctx
->insns_flags2
& PPC2_BOOKE206
) &&
6625 (ctx
->opcode
& 0x03FFF801)) {
6626 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
6628 /* otherwise interpreted as no-op */
6632 static void gen_icbt_440(DisasContext
*ctx
)
6635 * interpreted as no-op
6636 * XXX: specification say this is treated as a load by the MMU but
6637 * does not generate any exception
6641 /* Embedded.Processor Control */
6643 static void gen_msgclr(DisasContext
*ctx
)
6645 #if defined(CONFIG_USER_ONLY)
6649 if (is_book3s_arch2x(ctx
)) {
6650 gen_helper_book3s_msgclr(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
6652 gen_helper_msgclr(cpu_env
, cpu_gpr
[rB(ctx
->opcode
)]);
6654 #endif /* defined(CONFIG_USER_ONLY) */
6657 static void gen_msgsnd(DisasContext
*ctx
)
6659 #if defined(CONFIG_USER_ONLY)
6663 if (is_book3s_arch2x(ctx
)) {
6664 gen_helper_book3s_msgsnd(cpu_gpr
[rB(ctx
->opcode
)]);
6666 gen_helper_msgsnd(cpu_gpr
[rB(ctx
->opcode
)]);
6668 #endif /* defined(CONFIG_USER_ONLY) */
6671 static void gen_msgsync(DisasContext
*ctx
)
6673 #if defined(CONFIG_USER_ONLY)
6677 #endif /* defined(CONFIG_USER_ONLY) */
6678 /* interpreted as no-op */
6681 #if defined(TARGET_PPC64)
6682 static void gen_maddld(DisasContext
*ctx
)
6684 TCGv_i64 t1
= tcg_temp_new_i64();
6686 tcg_gen_mul_i64(t1
, cpu_gpr
[rA(ctx
->opcode
)], cpu_gpr
[rB(ctx
->opcode
)]);
6687 tcg_gen_add_i64(cpu_gpr
[rD(ctx
->opcode
)], t1
, cpu_gpr
[rC(ctx
->opcode
)]);
6688 tcg_temp_free_i64(t1
);
6691 /* maddhd maddhdu */
6692 static void gen_maddhd_maddhdu(DisasContext
*ctx
)
6694 TCGv_i64 lo
= tcg_temp_new_i64();
6695 TCGv_i64 hi
= tcg_temp_new_i64();
6696 TCGv_i64 t1
= tcg_temp_new_i64();
6698 if (Rc(ctx
->opcode
)) {
6699 tcg_gen_mulu2_i64(lo
, hi
, cpu_gpr
[rA(ctx
->opcode
)],
6700 cpu_gpr
[rB(ctx
->opcode
)]);
6701 tcg_gen_movi_i64(t1
, 0);
6703 tcg_gen_muls2_i64(lo
, hi
, cpu_gpr
[rA(ctx
->opcode
)],
6704 cpu_gpr
[rB(ctx
->opcode
)]);
6705 tcg_gen_sari_i64(t1
, cpu_gpr
[rC(ctx
->opcode
)], 63);
6707 tcg_gen_add2_i64(t1
, cpu_gpr
[rD(ctx
->opcode
)], lo
, hi
,
6708 cpu_gpr
[rC(ctx
->opcode
)], t1
);
6709 tcg_temp_free_i64(lo
);
6710 tcg_temp_free_i64(hi
);
6711 tcg_temp_free_i64(t1
);
6713 #endif /* defined(TARGET_PPC64) */
6715 static void gen_tbegin(DisasContext
*ctx
)
6717 if (unlikely(!ctx
->tm_enabled
)) {
6718 gen_exception_err(ctx
, POWERPC_EXCP_FU
, FSCR_IC_TM
);
6721 gen_helper_tbegin(cpu_env
);
6724 #define GEN_TM_NOOP(name) \
6725 static inline void gen_##name(DisasContext *ctx) \
6727 if (unlikely(!ctx->tm_enabled)) { \
6728 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6732 * Because tbegin always fails in QEMU, these user \
6733 * space instructions all have a simple implementation: \
6735 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6736 * = 0b0 || 0b00 || 0b0 \
6738 tcg_gen_movi_i32(cpu_crf[0], 0); \
6742 GEN_TM_NOOP(tabort
);
6743 GEN_TM_NOOP(tabortwc
);
6744 GEN_TM_NOOP(tabortwci
);
6745 GEN_TM_NOOP(tabortdc
);
6746 GEN_TM_NOOP(tabortdci
);
6749 static inline void gen_cp_abort(DisasContext
*ctx
)
6754 #define GEN_CP_PASTE_NOOP(name) \
6755 static inline void gen_##name(DisasContext *ctx) \
6758 * Generate invalid exception until we have an \
6759 * implementation of the copy paste facility \
6764 GEN_CP_PASTE_NOOP(copy
)
6765 GEN_CP_PASTE_NOOP(paste
)
6767 static void gen_tcheck(DisasContext
*ctx
)
6769 if (unlikely(!ctx
->tm_enabled
)) {
6770 gen_exception_err(ctx
, POWERPC_EXCP_FU
, FSCR_IC_TM
);
6774 * Because tbegin always fails, the tcheck implementation is
6777 * CR[CRF] = TDOOMED || MSR[TS] || 0b0
6778 * = 0b1 || 0b00 || 0b0
6780 tcg_gen_movi_i32(cpu_crf
[crfD(ctx
->opcode
)], 0x8);
6783 #if defined(CONFIG_USER_ONLY)
6784 #define GEN_TM_PRIV_NOOP(name) \
6785 static inline void gen_##name(DisasContext *ctx) \
6787 gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \
6792 #define GEN_TM_PRIV_NOOP(name) \
6793 static inline void gen_##name(DisasContext *ctx) \
6796 if (unlikely(!ctx->tm_enabled)) { \
6797 gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \
6801 * Because tbegin always fails, the implementation is \
6804 * CR[0] = 0b0 || MSR[TS] || 0b0 \
6805 * = 0b0 || 0b00 | 0b0 \
6807 tcg_gen_movi_i32(cpu_crf[0], 0); \
6812 GEN_TM_PRIV_NOOP(treclaim
);
6813 GEN_TM_PRIV_NOOP(trechkpt
);
6815 static inline void get_fpr(TCGv_i64 dst
, int regno
)
6817 tcg_gen_ld_i64(dst
, cpu_env
, fpr_offset(regno
));
6820 static inline void set_fpr(int regno
, TCGv_i64 src
)
6822 tcg_gen_st_i64(src
, cpu_env
, fpr_offset(regno
));
6825 static inline void get_avr64(TCGv_i64 dst
, int regno
, bool high
)
6827 tcg_gen_ld_i64(dst
, cpu_env
, avr64_offset(regno
, high
));
6830 static inline void set_avr64(int regno
, TCGv_i64 src
, bool high
)
6832 tcg_gen_st_i64(src
, cpu_env
, avr64_offset(regno
, high
));
6835 #include "translate/fp-impl.inc.c"
6837 #include "translate/vmx-impl.inc.c"
6839 #include "translate/vsx-impl.inc.c"
6841 #include "translate/dfp-impl.inc.c"
6843 #include "translate/spe-impl.inc.c"
6845 /* Handles lfdp, lxsd, lxssp */
6846 static void gen_dform39(DisasContext
*ctx
)
6848 switch (ctx
->opcode
& 0x3) {
6850 if (ctx
->insns_flags2
& PPC2_ISA205
) {
6851 return gen_lfdp(ctx
);
6855 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6856 return gen_lxsd(ctx
);
6860 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6861 return gen_lxssp(ctx
);
6865 return gen_invalid(ctx
);
6868 /* handles stfdp, lxv, stxsd, stxssp lxvx */
6869 static void gen_dform3D(DisasContext
*ctx
)
6871 if ((ctx
->opcode
& 3) == 1) { /* DQ-FORM */
6872 switch (ctx
->opcode
& 0x7) {
6874 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6875 return gen_lxv(ctx
);
6879 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6880 return gen_stxv(ctx
);
6884 } else { /* DS-FORM */
6885 switch (ctx
->opcode
& 0x3) {
6887 if (ctx
->insns_flags2
& PPC2_ISA205
) {
6888 return gen_stfdp(ctx
);
6892 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6893 return gen_stxsd(ctx
);
6896 case 3: /* stxssp */
6897 if (ctx
->insns_flags2
& PPC2_ISA300
) {
6898 return gen_stxssp(ctx
);
6903 return gen_invalid(ctx
);
6906 static opcode_t opcodes
[] = {
6907 GEN_HANDLER(invalid
, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE
),
6908 GEN_HANDLER(cmp
, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER
),
6909 GEN_HANDLER(cmpi
, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
6910 GEN_HANDLER(cmpl
, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER
),
6911 GEN_HANDLER(cmpli
, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER
),
6912 #if defined(TARGET_PPC64)
6913 GEN_HANDLER_E(cmpeqb
, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE
, PPC2_ISA300
),
6915 GEN_HANDLER_E(cmpb
, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE
, PPC2_ISA205
),
6916 GEN_HANDLER_E(cmprb
, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE
, PPC2_ISA300
),
6917 GEN_HANDLER(isel
, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL
),
6918 GEN_HANDLER(addi
, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6919 GEN_HANDLER(addic
, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6920 GEN_HANDLER2(addic_
, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6921 GEN_HANDLER(addis
, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6922 GEN_HANDLER_E(addpcis
, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA300
),
6923 GEN_HANDLER(mulhw
, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER
),
6924 GEN_HANDLER(mulhwu
, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER
),
6925 GEN_HANDLER(mullw
, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER
),
6926 GEN_HANDLER(mullwo
, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER
),
6927 GEN_HANDLER(mulli
, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6928 #if defined(TARGET_PPC64)
6929 GEN_HANDLER(mulld
, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B
),
6931 GEN_HANDLER(neg
, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER
),
6932 GEN_HANDLER(nego
, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER
),
6933 GEN_HANDLER(subfic
, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6934 GEN_HANDLER2(andi_
, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6935 GEN_HANDLER2(andis_
, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6936 GEN_HANDLER(cntlzw
, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER
),
6937 GEN_HANDLER_E(cnttzw
, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE
, PPC2_ISA300
),
6938 GEN_HANDLER_E(copy
, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE
, PPC2_ISA300
),
6939 GEN_HANDLER_E(cp_abort
, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE
, PPC2_ISA300
),
6940 GEN_HANDLER_E(paste
, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE
, PPC2_ISA300
),
6941 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER
),
6942 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER
),
6943 GEN_HANDLER(ori
, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6944 GEN_HANDLER(oris
, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6945 GEN_HANDLER(xori
, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6946 GEN_HANDLER(xoris
, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6947 GEN_HANDLER(popcntb
, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB
),
6948 GEN_HANDLER(popcntw
, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD
),
6949 GEN_HANDLER_E(prtyw
, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE
, PPC2_ISA205
),
6950 #if defined(TARGET_PPC64)
6951 GEN_HANDLER(popcntd
, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD
),
6952 GEN_HANDLER(cntlzd
, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B
),
6953 GEN_HANDLER_E(cnttzd
, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE
, PPC2_ISA300
),
6954 GEN_HANDLER_E(darn
, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE
, PPC2_ISA300
),
6955 GEN_HANDLER_E(prtyd
, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE
, PPC2_ISA205
),
6956 GEN_HANDLER_E(bpermd
, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE
, PPC2_PERM_ISA206
),
6958 GEN_HANDLER(rlwimi
, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6959 GEN_HANDLER(rlwinm
, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6960 GEN_HANDLER(rlwnm
, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6961 GEN_HANDLER(slw
, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER
),
6962 GEN_HANDLER(sraw
, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER
),
6963 GEN_HANDLER(srawi
, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER
),
6964 GEN_HANDLER(srw
, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER
),
6965 #if defined(TARGET_PPC64)
6966 GEN_HANDLER(sld
, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B
),
6967 GEN_HANDLER(srad
, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B
),
6968 GEN_HANDLER2(sradi0
, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B
),
6969 GEN_HANDLER2(sradi1
, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B
),
6970 GEN_HANDLER(srd
, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B
),
6971 GEN_HANDLER2_E(extswsli0
, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
6972 PPC_NONE
, PPC2_ISA300
),
6973 GEN_HANDLER2_E(extswsli1
, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
6974 PPC_NONE
, PPC2_ISA300
),
6976 #if defined(TARGET_PPC64)
6977 GEN_HANDLER(ld
, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B
),
6978 GEN_HANDLER(lq
, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX
),
6979 GEN_HANDLER(std
, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B
),
6981 /* handles lfdp, lxsd, lxssp */
6982 GEN_HANDLER_E(dform39
, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA205
),
6983 /* handles stfdp, lxv, stxsd, stxssp, stxv */
6984 GEN_HANDLER_E(dform3D
, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA205
),
6985 GEN_HANDLER(lmw
, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6986 GEN_HANDLER(stmw
, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER
),
6987 GEN_HANDLER(lswi
, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING
),
6988 GEN_HANDLER(lswx
, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING
),
6989 GEN_HANDLER(stswi
, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING
),
6990 GEN_HANDLER(stswx
, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING
),
6991 GEN_HANDLER(eieio
, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO
),
6992 GEN_HANDLER(isync
, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM
),
6993 GEN_HANDLER_E(lbarx
, 0x1F, 0x14, 0x01, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
6994 GEN_HANDLER_E(lharx
, 0x1F, 0x14, 0x03, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
6995 GEN_HANDLER(lwarx
, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES
),
6996 GEN_HANDLER_E(lwat
, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE
, PPC2_ISA300
),
6997 GEN_HANDLER_E(stwat
, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE
, PPC2_ISA300
),
6998 GEN_HANDLER_E(stbcx_
, 0x1F, 0x16, 0x15, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
6999 GEN_HANDLER_E(sthcx_
, 0x1F, 0x16, 0x16, 0, PPC_NONE
, PPC2_ATOMIC_ISA206
),
7000 GEN_HANDLER2(stwcx_
, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES
),
7001 #if defined(TARGET_PPC64)
7002 GEN_HANDLER_E(ldat
, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE
, PPC2_ISA300
),
7003 GEN_HANDLER_E(stdat
, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE
, PPC2_ISA300
),
7004 GEN_HANDLER(ldarx
, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B
),
7005 GEN_HANDLER_E(lqarx
, 0x1F, 0x14, 0x08, 0, PPC_NONE
, PPC2_LSQ_ISA207
),
7006 GEN_HANDLER2(stdcx_
, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B
),
7007 GEN_HANDLER_E(stqcx_
, 0x1F, 0x16, 0x05, 0, PPC_NONE
, PPC2_LSQ_ISA207
),
7009 GEN_HANDLER(sync
, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC
),
7010 GEN_HANDLER(wait
, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT
),
7011 GEN_HANDLER_E(wait
, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE
, PPC2_ISA300
),
7012 GEN_HANDLER(b
, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
7013 GEN_HANDLER(bc
, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
7014 GEN_HANDLER(bcctr
, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW
),
7015 GEN_HANDLER(bclr
, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW
),
7016 GEN_HANDLER_E(bctar
, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE
, PPC2_BCTAR_ISA207
),
7017 GEN_HANDLER(mcrf
, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER
),
7018 GEN_HANDLER(rfi
, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW
),
7019 #if defined(TARGET_PPC64)
7020 GEN_HANDLER(rfid
, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B
),
7021 GEN_HANDLER_E(stop
, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE
, PPC2_ISA300
),
7022 GEN_HANDLER_E(doze
, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
7023 GEN_HANDLER_E(nap
, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
7024 GEN_HANDLER_E(sleep
, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
7025 GEN_HANDLER_E(rvwinkle
, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE
, PPC2_PM_ISA206
),
7026 GEN_HANDLER(hrfid
, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H
),
7028 GEN_HANDLER(sc
, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW
),
7029 GEN_HANDLER(tw
, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW
),
7030 GEN_HANDLER(twi
, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW
),
7031 #if defined(TARGET_PPC64)
7032 GEN_HANDLER(td
, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B
),
7033 GEN_HANDLER(tdi
, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B
),
7035 GEN_HANDLER(mcrxr
, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC
),
7036 GEN_HANDLER(mfcr
, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC
),
7037 GEN_HANDLER(mfmsr
, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC
),
7038 GEN_HANDLER(mfspr
, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC
),
7039 GEN_HANDLER(mftb
, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB
),
7040 GEN_HANDLER(mtcrf
, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC
),
7041 #if defined(TARGET_PPC64)
7042 GEN_HANDLER(mtmsrd
, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B
),
7043 GEN_HANDLER_E(setb
, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE
, PPC2_ISA300
),
7044 GEN_HANDLER_E(mcrxrx
, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE
, PPC2_ISA300
),
7046 GEN_HANDLER(mtmsr
, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC
),
7047 GEN_HANDLER(mtspr
, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC
),
7048 GEN_HANDLER(dcbf
, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE
),
7049 GEN_HANDLER_E(dcbfep
, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE
, PPC2_BOOKE206
),
7050 GEN_HANDLER(dcbi
, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE
),
7051 GEN_HANDLER(dcbst
, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE
),
7052 GEN_HANDLER_E(dcbstep
, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE
, PPC2_BOOKE206
),
7053 GEN_HANDLER(dcbt
, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE
),
7054 GEN_HANDLER_E(dcbtep
, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE
, PPC2_BOOKE206
),
7055 GEN_HANDLER(dcbtst
, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE
),
7056 GEN_HANDLER_E(dcbtstep
, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE
, PPC2_BOOKE206
),
7057 GEN_HANDLER_E(dcbtls
, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE
, PPC2_BOOKE206
),
7058 GEN_HANDLER(dcbz
, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ
),
7059 GEN_HANDLER_E(dcbzep
, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE
, PPC2_BOOKE206
),
7060 GEN_HANDLER(dst
, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC
),
7061 GEN_HANDLER(dstst
, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC
),
7062 GEN_HANDLER(dss
, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC
),
7063 GEN_HANDLER(icbi
, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI
),
7064 GEN_HANDLER_E(icbiep
, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE
, PPC2_BOOKE206
),
7065 GEN_HANDLER(dcba
, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA
),
7066 GEN_HANDLER(mfsr
, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT
),
7067 GEN_HANDLER(mfsrin
, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT
),
7068 GEN_HANDLER(mtsr
, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT
),
7069 GEN_HANDLER(mtsrin
, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT
),
7070 #if defined(TARGET_PPC64)
7071 GEN_HANDLER2(mfsr_64b
, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B
),
7072 GEN_HANDLER2(mfsrin_64b
, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
7074 GEN_HANDLER2(mtsr_64b
, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B
),
7075 GEN_HANDLER2(mtsrin_64b
, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
7077 GEN_HANDLER2(slbmte
, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B
),
7078 GEN_HANDLER2(slbmfee
, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B
),
7079 GEN_HANDLER2(slbmfev
, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B
),
7080 GEN_HANDLER2(slbfee_
, "slbfee.", 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B
),
7082 GEN_HANDLER(tlbia
, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA
),
7084 * XXX Those instructions will need to be handled differently for
7085 * different ISA versions
7087 GEN_HANDLER(tlbiel
, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE
),
7088 GEN_HANDLER(tlbie
, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE
),
7089 GEN_HANDLER_E(tlbiel
, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE
, PPC2_ISA300
),
7090 GEN_HANDLER_E(tlbie
, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE
, PPC2_ISA300
),
7091 GEN_HANDLER(tlbsync
, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC
),
7092 #if defined(TARGET_PPC64)
7093 GEN_HANDLER(slbia
, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI
),
7094 GEN_HANDLER(slbie
, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI
),
7095 GEN_HANDLER_E(slbieg
, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE
, PPC2_ISA300
),
7096 GEN_HANDLER_E(slbsync
, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE
, PPC2_ISA300
),
7098 GEN_HANDLER(eciwx
, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN
),
7099 GEN_HANDLER(ecowx
, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN
),
7100 GEN_HANDLER(abs
, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR
),
7101 GEN_HANDLER(abso
, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR
),
7102 GEN_HANDLER(clcs
, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR
),
7103 GEN_HANDLER(div
, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR
),
7104 GEN_HANDLER(divo
, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR
),
7105 GEN_HANDLER(divs
, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR
),
7106 GEN_HANDLER(divso
, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR
),
7107 GEN_HANDLER(doz
, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR
),
7108 GEN_HANDLER(dozo
, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR
),
7109 GEN_HANDLER(dozi
, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
7110 GEN_HANDLER(lscbx
, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR
),
7111 GEN_HANDLER(maskg
, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR
),
7112 GEN_HANDLER(maskir
, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR
),
7113 GEN_HANDLER(mul
, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR
),
7114 GEN_HANDLER(mulo
, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR
),
7115 GEN_HANDLER(nabs
, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR
),
7116 GEN_HANDLER(nabso
, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR
),
7117 GEN_HANDLER(rlmi
, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR
),
7118 GEN_HANDLER(rrib
, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR
),
7119 GEN_HANDLER(sle
, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR
),
7120 GEN_HANDLER(sleq
, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR
),
7121 GEN_HANDLER(sliq
, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR
),
7122 GEN_HANDLER(slliq
, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR
),
7123 GEN_HANDLER(sllq
, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR
),
7124 GEN_HANDLER(slq
, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR
),
7125 GEN_HANDLER(sraiq
, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR
),
7126 GEN_HANDLER(sraq
, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR
),
7127 GEN_HANDLER(sre
, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR
),
7128 GEN_HANDLER(srea
, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR
),
7129 GEN_HANDLER(sreq
, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR
),
7130 GEN_HANDLER(sriq
, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR
),
7131 GEN_HANDLER(srliq
, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR
),
7132 GEN_HANDLER(srlq
, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR
),
7133 GEN_HANDLER(srq
, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR
),
7134 GEN_HANDLER(dsa
, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC
),
7135 GEN_HANDLER(esa
, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC
),
7136 GEN_HANDLER(mfrom
, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC
),
7137 GEN_HANDLER2(tlbld_6xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB
),
7138 GEN_HANDLER2(tlbli_6xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB
),
7139 GEN_HANDLER2(tlbld_74xx
, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB
),
7140 GEN_HANDLER2(tlbli_74xx
, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB
),
7141 GEN_HANDLER(clf
, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER
),
7142 GEN_HANDLER(cli
, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER
),
7143 GEN_HANDLER(dclst
, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER
),
7144 GEN_HANDLER(mfsri
, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER
),
7145 GEN_HANDLER(rac
, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER
),
7146 GEN_HANDLER(rfsvc
, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER
),
7147 GEN_HANDLER(lfq
, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
7148 GEN_HANDLER(lfqu
, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
7149 GEN_HANDLER(lfqux
, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2
),
7150 GEN_HANDLER(lfqx
, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2
),
7151 GEN_HANDLER(stfq
, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
7152 GEN_HANDLER(stfqu
, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2
),
7153 GEN_HANDLER(stfqux
, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2
),
7154 GEN_HANDLER(stfqx
, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2
),
7155 GEN_HANDLER(mfapidi
, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI
),
7156 GEN_HANDLER(tlbiva
, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA
),
7157 GEN_HANDLER(mfdcr
, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR
),
7158 GEN_HANDLER(mtdcr
, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR
),
7159 GEN_HANDLER(mfdcrx
, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX
),
7160 GEN_HANDLER(mtdcrx
, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX
),
7161 GEN_HANDLER(mfdcrux
, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX
),
7162 GEN_HANDLER(mtdcrux
, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX
),
7163 GEN_HANDLER(dccci
, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON
),
7164 GEN_HANDLER(dcread
, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON
),
7165 GEN_HANDLER2(icbt_40x
, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT
),
7166 GEN_HANDLER(iccci
, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON
),
7167 GEN_HANDLER(icread
, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON
),
7168 GEN_HANDLER2(rfci_40x
, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP
),
7169 GEN_HANDLER_E(rfci
, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE
, PPC2_BOOKE206
),
7170 GEN_HANDLER(rfdi
, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI
),
7171 GEN_HANDLER(rfmci
, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI
),
7172 GEN_HANDLER2(tlbre_40x
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB
),
7173 GEN_HANDLER2(tlbsx_40x
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB
),
7174 GEN_HANDLER2(tlbwe_40x
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB
),
7175 GEN_HANDLER2(tlbre_440
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE
),
7176 GEN_HANDLER2(tlbsx_440
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE
),
7177 GEN_HANDLER2(tlbwe_440
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE
),
7178 GEN_HANDLER2_E(tlbre_booke206
, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
7179 PPC_NONE
, PPC2_BOOKE206
),
7180 GEN_HANDLER2_E(tlbsx_booke206
, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
7181 PPC_NONE
, PPC2_BOOKE206
),
7182 GEN_HANDLER2_E(tlbwe_booke206
, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
7183 PPC_NONE
, PPC2_BOOKE206
),
7184 GEN_HANDLER2_E(tlbivax_booke206
, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
7185 PPC_NONE
, PPC2_BOOKE206
),
7186 GEN_HANDLER2_E(tlbilx_booke206
, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
7187 PPC_NONE
, PPC2_BOOKE206
),
7188 GEN_HANDLER2_E(msgsnd
, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
7189 PPC_NONE
, PPC2_PRCNTL
),
7190 GEN_HANDLER2_E(msgclr
, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
7191 PPC_NONE
, PPC2_PRCNTL
),
7192 GEN_HANDLER2_E(msgsync
, "msgsync", 0x1F, 0x16, 0x1B, 0x00000000,
7193 PPC_NONE
, PPC2_PRCNTL
),
7194 GEN_HANDLER(wrtee
, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE
),
7195 GEN_HANDLER(wrteei
, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE
),
7196 GEN_HANDLER(dlmzb
, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC
),
7197 GEN_HANDLER_E(mbar
, 0x1F, 0x16, 0x1a, 0x001FF801,
7198 PPC_BOOKE
, PPC2_BOOKE206
),
7199 GEN_HANDLER(msync_4xx
, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE
),
7200 GEN_HANDLER2_E(icbt_440
, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
7201 PPC_BOOKE
, PPC2_BOOKE206
),
7202 GEN_HANDLER2(icbt_440
, "icbt", 0x1F, 0x06, 0x08, 0x03E00001,
7204 GEN_HANDLER(lvsl
, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC
),
7205 GEN_HANDLER(lvsr
, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC
),
7206 GEN_HANDLER(mfvscr
, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC
),
7207 GEN_HANDLER(mtvscr
, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC
),
7208 GEN_HANDLER(vmladduhm
, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC
),
7209 #if defined(TARGET_PPC64)
7210 GEN_HANDLER_E(maddhd_maddhdu
, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE
,
7212 GEN_HANDLER_E(maddld
, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE
, PPC2_ISA300
),
7215 #undef GEN_INT_ARITH_ADD
7216 #undef GEN_INT_ARITH_ADD_CONST
7217 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
7218 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
7219 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
7220 add_ca, compute_ca, compute_ov) \
7221 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
7222 GEN_INT_ARITH_ADD(add
, 0x08, 0, 0, 0)
7223 GEN_INT_ARITH_ADD(addo
, 0x18, 0, 0, 1)
7224 GEN_INT_ARITH_ADD(addc
, 0x00, 0, 1, 0)
7225 GEN_INT_ARITH_ADD(addco
, 0x10, 0, 1, 1)
7226 GEN_INT_ARITH_ADD(adde
, 0x04, 1, 1, 0)
7227 GEN_INT_ARITH_ADD(addeo
, 0x14, 1, 1, 1)
7228 GEN_INT_ARITH_ADD_CONST(addme
, 0x07, -1LL, 1, 1, 0)
7229 GEN_INT_ARITH_ADD_CONST(addmeo
, 0x17, -1LL, 1, 1, 1)
7230 GEN_HANDLER_E(addex
, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE
, PPC2_ISA300
),
7231 GEN_INT_ARITH_ADD_CONST(addze
, 0x06, 0, 1, 1, 0)
7232 GEN_INT_ARITH_ADD_CONST(addzeo
, 0x16, 0, 1, 1, 1)
7234 #undef GEN_INT_ARITH_DIVW
7235 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
7236 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
7237 GEN_INT_ARITH_DIVW(divwu
, 0x0E, 0, 0),
7238 GEN_INT_ARITH_DIVW(divwuo
, 0x1E, 0, 1),
7239 GEN_INT_ARITH_DIVW(divw
, 0x0F, 1, 0),
7240 GEN_INT_ARITH_DIVW(divwo
, 0x1F, 1, 1),
7241 GEN_HANDLER_E(divwe
, 0x1F, 0x0B, 0x0D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7242 GEN_HANDLER_E(divweo
, 0x1F, 0x0B, 0x1D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7243 GEN_HANDLER_E(divweu
, 0x1F, 0x0B, 0x0C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7244 GEN_HANDLER_E(divweuo
, 0x1F, 0x0B, 0x1C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7245 GEN_HANDLER_E(modsw
, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE
, PPC2_ISA300
),
7246 GEN_HANDLER_E(moduw
, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE
, PPC2_ISA300
),
7248 #if defined(TARGET_PPC64)
7249 #undef GEN_INT_ARITH_DIVD
7250 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
7251 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
7252 GEN_INT_ARITH_DIVD(divdu
, 0x0E, 0, 0),
7253 GEN_INT_ARITH_DIVD(divduo
, 0x1E, 0, 1),
7254 GEN_INT_ARITH_DIVD(divd
, 0x0F, 1, 0),
7255 GEN_INT_ARITH_DIVD(divdo
, 0x1F, 1, 1),
7257 GEN_HANDLER_E(divdeu
, 0x1F, 0x09, 0x0C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7258 GEN_HANDLER_E(divdeuo
, 0x1F, 0x09, 0x1C, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7259 GEN_HANDLER_E(divde
, 0x1F, 0x09, 0x0D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7260 GEN_HANDLER_E(divdeo
, 0x1F, 0x09, 0x1D, 0, PPC_NONE
, PPC2_DIVE_ISA206
),
7261 GEN_HANDLER_E(modsd
, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE
, PPC2_ISA300
),
7262 GEN_HANDLER_E(modud
, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE
, PPC2_ISA300
),
7264 #undef GEN_INT_ARITH_MUL_HELPER
7265 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
7266 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
7267 GEN_INT_ARITH_MUL_HELPER(mulhdu
, 0x00),
7268 GEN_INT_ARITH_MUL_HELPER(mulhd
, 0x02),
7269 GEN_INT_ARITH_MUL_HELPER(mulldo
, 0x17),
7272 #undef GEN_INT_ARITH_SUBF
7273 #undef GEN_INT_ARITH_SUBF_CONST
7274 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
7275 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
7276 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
7277 add_ca, compute_ca, compute_ov) \
7278 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
7279 GEN_INT_ARITH_SUBF(subf
, 0x01, 0, 0, 0)
7280 GEN_INT_ARITH_SUBF(subfo
, 0x11, 0, 0, 1)
7281 GEN_INT_ARITH_SUBF(subfc
, 0x00, 0, 1, 0)
7282 GEN_INT_ARITH_SUBF(subfco
, 0x10, 0, 1, 1)
7283 GEN_INT_ARITH_SUBF(subfe
, 0x04, 1, 1, 0)
7284 GEN_INT_ARITH_SUBF(subfeo
, 0x14, 1, 1, 1)
7285 GEN_INT_ARITH_SUBF_CONST(subfme
, 0x07, -1LL, 1, 1, 0)
7286 GEN_INT_ARITH_SUBF_CONST(subfmeo
, 0x17, -1LL, 1, 1, 1)
7287 GEN_INT_ARITH_SUBF_CONST(subfze
, 0x06, 0, 1, 1, 0)
7288 GEN_INT_ARITH_SUBF_CONST(subfzeo
, 0x16, 0, 1, 1, 1)
7292 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
7293 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
7294 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
7295 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
7296 GEN_LOGICAL2(and, tcg_gen_and_tl
, 0x00, PPC_INTEGER
),
7297 GEN_LOGICAL2(andc
, tcg_gen_andc_tl
, 0x01, PPC_INTEGER
),
7298 GEN_LOGICAL2(eqv
, tcg_gen_eqv_tl
, 0x08, PPC_INTEGER
),
7299 GEN_LOGICAL1(extsb
, tcg_gen_ext8s_tl
, 0x1D, PPC_INTEGER
),
7300 GEN_LOGICAL1(extsh
, tcg_gen_ext16s_tl
, 0x1C, PPC_INTEGER
),
7301 GEN_LOGICAL2(nand
, tcg_gen_nand_tl
, 0x0E, PPC_INTEGER
),
7302 GEN_LOGICAL2(nor
, tcg_gen_nor_tl
, 0x03, PPC_INTEGER
),
7303 GEN_LOGICAL2(orc
, tcg_gen_orc_tl
, 0x0C, PPC_INTEGER
),
7304 #if defined(TARGET_PPC64)
7305 GEN_LOGICAL1(extsw
, tcg_gen_ext32s_tl
, 0x1E, PPC_64B
),
7308 #if defined(TARGET_PPC64)
7311 #define GEN_PPC64_R2(name, opc1, opc2) \
7312 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
7313 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
7315 #define GEN_PPC64_R4(name, opc1, opc2) \
7316 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
7317 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
7319 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
7321 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
7323 GEN_PPC64_R4(rldicl
, 0x1E, 0x00),
7324 GEN_PPC64_R4(rldicr
, 0x1E, 0x02),
7325 GEN_PPC64_R4(rldic
, 0x1E, 0x04),
7326 GEN_PPC64_R2(rldcl
, 0x1E, 0x08),
7327 GEN_PPC64_R2(rldcr
, 0x1E, 0x09),
7328 GEN_PPC64_R4(rldimi
, 0x1E, 0x06),
7336 #define GEN_LD(name, ldop, opc, type) \
7337 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
7338 #define GEN_LDU(name, ldop, opc, type) \
7339 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
7340 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
7341 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
7342 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \
7343 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
7344 #define GEN_LDS(name, ldop, op, type) \
7345 GEN_LD(name, ldop, op | 0x20, type) \
7346 GEN_LDU(name, ldop, op | 0x21, type) \
7347 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
7348 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
7350 GEN_LDS(lbz
, ld8u
, 0x02, PPC_INTEGER
)
7351 GEN_LDS(lha
, ld16s
, 0x0A, PPC_INTEGER
)
7352 GEN_LDS(lhz
, ld16u
, 0x08, PPC_INTEGER
)
7353 GEN_LDS(lwz
, ld32u
, 0x00, PPC_INTEGER
)
7354 #if defined(TARGET_PPC64)
7355 GEN_LDUX(lwa
, ld32s
, 0x15, 0x0B, PPC_64B
)
7356 GEN_LDX(lwa
, ld32s
, 0x15, 0x0A, PPC_64B
)
7357 GEN_LDUX(ld
, ld64_i64
, 0x15, 0x01, PPC_64B
)
7358 GEN_LDX(ld
, ld64_i64
, 0x15, 0x00, PPC_64B
)
7359 GEN_LDX_E(ldbr
, ld64ur_i64
, 0x14, 0x10, PPC_NONE
, PPC2_DBRX
, CHK_NONE
)
7361 /* HV/P7 and later only */
7362 GEN_LDX_HVRM(ldcix
, ld64_i64
, 0x15, 0x1b, PPC_CILDST
)
7363 GEN_LDX_HVRM(lwzcix
, ld32u
, 0x15, 0x18, PPC_CILDST
)
7364 GEN_LDX_HVRM(lhzcix
, ld16u
, 0x15, 0x19, PPC_CILDST
)
7365 GEN_LDX_HVRM(lbzcix
, ld8u
, 0x15, 0x1a, PPC_CILDST
)
7367 GEN_LDX(lhbr
, ld16ur
, 0x16, 0x18, PPC_INTEGER
)
7368 GEN_LDX(lwbr
, ld32ur
, 0x16, 0x10, PPC_INTEGER
)
7370 /* External PID based load */
7372 #define GEN_LDEPX(name, ldop, opc2, opc3) \
7373 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \
7374 0x00000001, PPC_NONE, PPC2_BOOKE206),
7376 GEN_LDEPX(lb
, DEF_MEMOP(MO_UB
), 0x1F, 0x02)
7377 GEN_LDEPX(lh
, DEF_MEMOP(MO_UW
), 0x1F, 0x08)
7378 GEN_LDEPX(lw
, DEF_MEMOP(MO_UL
), 0x1F, 0x00)
7379 #if defined(TARGET_PPC64)
7380 GEN_LDEPX(ld
, DEF_MEMOP(MO_Q
), 0x1D, 0x00)
7388 #define GEN_ST(name, stop, opc, type) \
7389 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
7390 #define GEN_STU(name, stop, opc, type) \
7391 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
7392 #define GEN_STUX(name, stop, opc2, opc3, type) \
7393 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
7394 #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \
7395 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2),
7396 #define GEN_STS(name, stop, op, type) \
7397 GEN_ST(name, stop, op | 0x20, type) \
7398 GEN_STU(name, stop, op | 0x21, type) \
7399 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
7400 GEN_STX(name, stop, 0x17, op | 0x00, type)
7402 GEN_STS(stb
, st8
, 0x06, PPC_INTEGER
)
7403 GEN_STS(sth
, st16
, 0x0C, PPC_INTEGER
)
7404 GEN_STS(stw
, st32
, 0x04, PPC_INTEGER
)
7405 #if defined(TARGET_PPC64)
7406 GEN_STUX(std
, st64_i64
, 0x15, 0x05, PPC_64B
)
7407 GEN_STX(std
, st64_i64
, 0x15, 0x04, PPC_64B
)
7408 GEN_STX_E(stdbr
, st64r_i64
, 0x14, 0x14, PPC_NONE
, PPC2_DBRX
, CHK_NONE
)
7409 GEN_STX_HVRM(stdcix
, st64_i64
, 0x15, 0x1f, PPC_CILDST
)
7410 GEN_STX_HVRM(stwcix
, st32
, 0x15, 0x1c, PPC_CILDST
)
7411 GEN_STX_HVRM(sthcix
, st16
, 0x15, 0x1d, PPC_CILDST
)
7412 GEN_STX_HVRM(stbcix
, st8
, 0x15, 0x1e, PPC_CILDST
)
7414 GEN_STX(sthbr
, st16r
, 0x16, 0x1C, PPC_INTEGER
)
7415 GEN_STX(stwbr
, st32r
, 0x16, 0x14, PPC_INTEGER
)
7418 #define GEN_STEPX(name, ldop, opc2, opc3) \
7419 GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \
7420 0x00000001, PPC_NONE, PPC2_BOOKE206),
7422 GEN_STEPX(stb
, DEF_MEMOP(MO_UB
), 0x1F, 0x06)
7423 GEN_STEPX(sth
, DEF_MEMOP(MO_UW
), 0x1F, 0x0C)
7424 GEN_STEPX(stw
, DEF_MEMOP(MO_UL
), 0x1F, 0x04)
7425 #if defined(TARGET_PPC64)
7426 GEN_STEPX(std
, DEF_MEMOP(MO_Q
), 0x1D, 0x04)
7430 #define GEN_CRLOGIC(name, tcg_op, opc) \
7431 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
7432 GEN_CRLOGIC(crand
, tcg_gen_and_i32
, 0x08),
7433 GEN_CRLOGIC(crandc
, tcg_gen_andc_i32
, 0x04),
7434 GEN_CRLOGIC(creqv
, tcg_gen_eqv_i32
, 0x09),
7435 GEN_CRLOGIC(crnand
, tcg_gen_nand_i32
, 0x07),
7436 GEN_CRLOGIC(crnor
, tcg_gen_nor_i32
, 0x01),
7437 GEN_CRLOGIC(cror
, tcg_gen_or_i32
, 0x0E),
7438 GEN_CRLOGIC(crorc
, tcg_gen_orc_i32
, 0x0D),
7439 GEN_CRLOGIC(crxor
, tcg_gen_xor_i32
, 0x06),
7441 #undef GEN_MAC_HANDLER
7442 #define GEN_MAC_HANDLER(name, opc2, opc3) \
7443 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
7444 GEN_MAC_HANDLER(macchw
, 0x0C, 0x05),
7445 GEN_MAC_HANDLER(macchwo
, 0x0C, 0x15),
7446 GEN_MAC_HANDLER(macchws
, 0x0C, 0x07),
7447 GEN_MAC_HANDLER(macchwso
, 0x0C, 0x17),
7448 GEN_MAC_HANDLER(macchwsu
, 0x0C, 0x06),
7449 GEN_MAC_HANDLER(macchwsuo
, 0x0C, 0x16),
7450 GEN_MAC_HANDLER(macchwu
, 0x0C, 0x04),
7451 GEN_MAC_HANDLER(macchwuo
, 0x0C, 0x14),
7452 GEN_MAC_HANDLER(machhw
, 0x0C, 0x01),
7453 GEN_MAC_HANDLER(machhwo
, 0x0C, 0x11),
7454 GEN_MAC_HANDLER(machhws
, 0x0C, 0x03),
7455 GEN_MAC_HANDLER(machhwso
, 0x0C, 0x13),
7456 GEN_MAC_HANDLER(machhwsu
, 0x0C, 0x02),
7457 GEN_MAC_HANDLER(machhwsuo
, 0x0C, 0x12),
7458 GEN_MAC_HANDLER(machhwu
, 0x0C, 0x00),
7459 GEN_MAC_HANDLER(machhwuo
, 0x0C, 0x10),
7460 GEN_MAC_HANDLER(maclhw
, 0x0C, 0x0D),
7461 GEN_MAC_HANDLER(maclhwo
, 0x0C, 0x1D),
7462 GEN_MAC_HANDLER(maclhws
, 0x0C, 0x0F),
7463 GEN_MAC_HANDLER(maclhwso
, 0x0C, 0x1F),
7464 GEN_MAC_HANDLER(maclhwu
, 0x0C, 0x0C),
7465 GEN_MAC_HANDLER(maclhwuo
, 0x0C, 0x1C),
7466 GEN_MAC_HANDLER(maclhwsu
, 0x0C, 0x0E),
7467 GEN_MAC_HANDLER(maclhwsuo
, 0x0C, 0x1E),
7468 GEN_MAC_HANDLER(nmacchw
, 0x0E, 0x05),
7469 GEN_MAC_HANDLER(nmacchwo
, 0x0E, 0x15),
7470 GEN_MAC_HANDLER(nmacchws
, 0x0E, 0x07),
7471 GEN_MAC_HANDLER(nmacchwso
, 0x0E, 0x17),
7472 GEN_MAC_HANDLER(nmachhw
, 0x0E, 0x01),
7473 GEN_MAC_HANDLER(nmachhwo
, 0x0E, 0x11),
7474 GEN_MAC_HANDLER(nmachhws
, 0x0E, 0x03),
7475 GEN_MAC_HANDLER(nmachhwso
, 0x0E, 0x13),
7476 GEN_MAC_HANDLER(nmaclhw
, 0x0E, 0x0D),
7477 GEN_MAC_HANDLER(nmaclhwo
, 0x0E, 0x1D),
7478 GEN_MAC_HANDLER(nmaclhws
, 0x0E, 0x0F),
7479 GEN_MAC_HANDLER(nmaclhwso
, 0x0E, 0x1F),
7480 GEN_MAC_HANDLER(mulchw
, 0x08, 0x05),
7481 GEN_MAC_HANDLER(mulchwu
, 0x08, 0x04),
7482 GEN_MAC_HANDLER(mulhhw
, 0x08, 0x01),
7483 GEN_MAC_HANDLER(mulhhwu
, 0x08, 0x00),
7484 GEN_MAC_HANDLER(mullhw
, 0x08, 0x0D),
7485 GEN_MAC_HANDLER(mullhwu
, 0x08, 0x0C),
7487 GEN_HANDLER2_E(tbegin
, "tbegin", 0x1F, 0x0E, 0x14, 0x01DFF800, \
7489 GEN_HANDLER2_E(tend
, "tend", 0x1F, 0x0E, 0x15, 0x01FFF800, \
7491 GEN_HANDLER2_E(tabort
, "tabort", 0x1F, 0x0E, 0x1C, 0x03E0F800, \
7493 GEN_HANDLER2_E(tabortwc
, "tabortwc", 0x1F, 0x0E, 0x18, 0x00000000, \
7495 GEN_HANDLER2_E(tabortwci
, "tabortwci", 0x1F, 0x0E, 0x1A, 0x00000000, \
7497 GEN_HANDLER2_E(tabortdc
, "tabortdc", 0x1F, 0x0E, 0x19, 0x00000000, \
7499 GEN_HANDLER2_E(tabortdci
, "tabortdci", 0x1F, 0x0E, 0x1B, 0x00000000, \
7501 GEN_HANDLER2_E(tsr
, "tsr", 0x1F, 0x0E, 0x17, 0x03DFF800, \
7503 GEN_HANDLER2_E(tcheck
, "tcheck", 0x1F, 0x0E, 0x16, 0x007FF800, \
7505 GEN_HANDLER2_E(treclaim
, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
7507 GEN_HANDLER2_E(trechkpt
, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
7510 #include "translate/fp-ops.inc.c"
7512 #include "translate/vmx-ops.inc.c"
7514 #include "translate/vsx-ops.inc.c"
7516 #include "translate/dfp-ops.inc.c"
7518 #include "translate/spe-ops.inc.c"
7521 #include "helper_regs.h"
7522 #include "translate_init.inc.c"
7524 /*****************************************************************************/
7525 /* Misc PowerPC helpers */
7526 void ppc_cpu_dump_state(CPUState
*cs
, FILE *f
, int flags
)
7531 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
7532 CPUPPCState
*env
= &cpu
->env
;
7535 qemu_fprintf(f
, "NIP " TARGET_FMT_lx
" LR " TARGET_FMT_lx
" CTR "
7536 TARGET_FMT_lx
" XER " TARGET_FMT_lx
" CPU#%d\n",
7537 env
->nip
, env
->lr
, env
->ctr
, cpu_read_xer(env
),
7539 qemu_fprintf(f
, "MSR " TARGET_FMT_lx
" HID0 " TARGET_FMT_lx
" HF "
7540 TARGET_FMT_lx
" iidx %d didx %d\n",
7541 env
->msr
, env
->spr
[SPR_HID0
],
7542 env
->hflags
, env
->immu_idx
, env
->dmmu_idx
);
7543 #if !defined(NO_TIMER_DUMP)
7544 qemu_fprintf(f
, "TB %08" PRIu32
" %08" PRIu64
7545 #if !defined(CONFIG_USER_ONLY)
7546 " DECR " TARGET_FMT_lu
7549 cpu_ppc_load_tbu(env
), cpu_ppc_load_tbl(env
)
7550 #if !defined(CONFIG_USER_ONLY)
7551 , cpu_ppc_load_decr(env
)
7555 for (i
= 0; i
< 32; i
++) {
7556 if ((i
& (RGPL
- 1)) == 0) {
7557 qemu_fprintf(f
, "GPR%02d", i
);
7559 qemu_fprintf(f
, " %016" PRIx64
, ppc_dump_gpr(env
, i
));
7560 if ((i
& (RGPL
- 1)) == (RGPL
- 1)) {
7561 qemu_fprintf(f
, "\n");
7564 qemu_fprintf(f
, "CR ");
7565 for (i
= 0; i
< 8; i
++)
7566 qemu_fprintf(f
, "%01x", env
->crf
[i
]);
7567 qemu_fprintf(f
, " [");
7568 for (i
= 0; i
< 8; i
++) {
7570 if (env
->crf
[i
] & 0x08) {
7572 } else if (env
->crf
[i
] & 0x04) {
7574 } else if (env
->crf
[i
] & 0x02) {
7577 qemu_fprintf(f
, " %c%c", a
, env
->crf
[i
] & 0x01 ? 'O' : ' ');
7579 qemu_fprintf(f
, " ] RES " TARGET_FMT_lx
"\n",
7582 if (flags
& CPU_DUMP_FPU
) {
7583 for (i
= 0; i
< 32; i
++) {
7584 if ((i
& (RFPL
- 1)) == 0) {
7585 qemu_fprintf(f
, "FPR%02d", i
);
7587 qemu_fprintf(f
, " %016" PRIx64
, *cpu_fpr_ptr(env
, i
));
7588 if ((i
& (RFPL
- 1)) == (RFPL
- 1)) {
7589 qemu_fprintf(f
, "\n");
7592 qemu_fprintf(f
, "FPSCR " TARGET_FMT_lx
"\n", env
->fpscr
);
7595 #if !defined(CONFIG_USER_ONLY)
7596 qemu_fprintf(f
, " SRR0 " TARGET_FMT_lx
" SRR1 " TARGET_FMT_lx
7597 " PVR " TARGET_FMT_lx
" VRSAVE " TARGET_FMT_lx
"\n",
7598 env
->spr
[SPR_SRR0
], env
->spr
[SPR_SRR1
],
7599 env
->spr
[SPR_PVR
], env
->spr
[SPR_VRSAVE
]);
7601 qemu_fprintf(f
, "SPRG0 " TARGET_FMT_lx
" SPRG1 " TARGET_FMT_lx
7602 " SPRG2 " TARGET_FMT_lx
" SPRG3 " TARGET_FMT_lx
"\n",
7603 env
->spr
[SPR_SPRG0
], env
->spr
[SPR_SPRG1
],
7604 env
->spr
[SPR_SPRG2
], env
->spr
[SPR_SPRG3
]);
7606 qemu_fprintf(f
, "SPRG4 " TARGET_FMT_lx
" SPRG5 " TARGET_FMT_lx
7607 " SPRG6 " TARGET_FMT_lx
" SPRG7 " TARGET_FMT_lx
"\n",
7608 env
->spr
[SPR_SPRG4
], env
->spr
[SPR_SPRG5
],
7609 env
->spr
[SPR_SPRG6
], env
->spr
[SPR_SPRG7
]);
7611 #if defined(TARGET_PPC64)
7612 if (env
->excp_model
== POWERPC_EXCP_POWER7
||
7613 env
->excp_model
== POWERPC_EXCP_POWER8
||
7614 env
->excp_model
== POWERPC_EXCP_POWER9
) {
7615 qemu_fprintf(f
, "HSRR0 " TARGET_FMT_lx
" HSRR1 " TARGET_FMT_lx
"\n",
7616 env
->spr
[SPR_HSRR0
], env
->spr
[SPR_HSRR1
]);
7619 if (env
->excp_model
== POWERPC_EXCP_BOOKE
) {
7620 qemu_fprintf(f
, "CSRR0 " TARGET_FMT_lx
" CSRR1 " TARGET_FMT_lx
7621 " MCSRR0 " TARGET_FMT_lx
" MCSRR1 " TARGET_FMT_lx
"\n",
7622 env
->spr
[SPR_BOOKE_CSRR0
], env
->spr
[SPR_BOOKE_CSRR1
],
7623 env
->spr
[SPR_BOOKE_MCSRR0
], env
->spr
[SPR_BOOKE_MCSRR1
]);
7625 qemu_fprintf(f
, " TCR " TARGET_FMT_lx
" TSR " TARGET_FMT_lx
7626 " ESR " TARGET_FMT_lx
" DEAR " TARGET_FMT_lx
"\n",
7627 env
->spr
[SPR_BOOKE_TCR
], env
->spr
[SPR_BOOKE_TSR
],
7628 env
->spr
[SPR_BOOKE_ESR
], env
->spr
[SPR_BOOKE_DEAR
]);
7630 qemu_fprintf(f
, " PIR " TARGET_FMT_lx
" DECAR " TARGET_FMT_lx
7631 " IVPR " TARGET_FMT_lx
" EPCR " TARGET_FMT_lx
"\n",
7632 env
->spr
[SPR_BOOKE_PIR
], env
->spr
[SPR_BOOKE_DECAR
],
7633 env
->spr
[SPR_BOOKE_IVPR
], env
->spr
[SPR_BOOKE_EPCR
]);
7635 qemu_fprintf(f
, " MCSR " TARGET_FMT_lx
" SPRG8 " TARGET_FMT_lx
7636 " EPR " TARGET_FMT_lx
"\n",
7637 env
->spr
[SPR_BOOKE_MCSR
], env
->spr
[SPR_BOOKE_SPRG8
],
7638 env
->spr
[SPR_BOOKE_EPR
]);
7641 qemu_fprintf(f
, " MCAR " TARGET_FMT_lx
" PID1 " TARGET_FMT_lx
7642 " PID2 " TARGET_FMT_lx
" SVR " TARGET_FMT_lx
"\n",
7643 env
->spr
[SPR_Exxx_MCAR
], env
->spr
[SPR_BOOKE_PID1
],
7644 env
->spr
[SPR_BOOKE_PID2
], env
->spr
[SPR_E500_SVR
]);
7647 * IVORs are left out as they are large and do not change often --
7648 * they can be read with "p $ivor0", "p $ivor1", etc.
7652 #if defined(TARGET_PPC64)
7653 if (env
->flags
& POWERPC_FLAG_CFAR
) {
7654 qemu_fprintf(f
, " CFAR " TARGET_FMT_lx
"\n", env
->cfar
);
7658 if (env
->spr_cb
[SPR_LPCR
].name
) {
7659 qemu_fprintf(f
, " LPCR " TARGET_FMT_lx
"\n", env
->spr
[SPR_LPCR
]);
7662 switch (env
->mmu_model
) {
7663 case POWERPC_MMU_32B
:
7664 case POWERPC_MMU_601
:
7665 case POWERPC_MMU_SOFT_6xx
:
7666 case POWERPC_MMU_SOFT_74xx
:
7667 #if defined(TARGET_PPC64)
7668 case POWERPC_MMU_64B
:
7669 case POWERPC_MMU_2_03
:
7670 case POWERPC_MMU_2_06
:
7671 case POWERPC_MMU_2_07
:
7672 case POWERPC_MMU_3_00
:
7674 if (env
->spr_cb
[SPR_SDR1
].name
) { /* SDR1 Exists */
7675 qemu_fprintf(f
, " SDR1 " TARGET_FMT_lx
" ", env
->spr
[SPR_SDR1
]);
7677 if (env
->spr_cb
[SPR_PTCR
].name
) { /* PTCR Exists */
7678 qemu_fprintf(f
, " PTCR " TARGET_FMT_lx
" ", env
->spr
[SPR_PTCR
]);
7680 qemu_fprintf(f
, " DAR " TARGET_FMT_lx
" DSISR " TARGET_FMT_lx
"\n",
7681 env
->spr
[SPR_DAR
], env
->spr
[SPR_DSISR
]);
7683 case POWERPC_MMU_BOOKE206
:
7684 qemu_fprintf(f
, " MAS0 " TARGET_FMT_lx
" MAS1 " TARGET_FMT_lx
7685 " MAS2 " TARGET_FMT_lx
" MAS3 " TARGET_FMT_lx
"\n",
7686 env
->spr
[SPR_BOOKE_MAS0
], env
->spr
[SPR_BOOKE_MAS1
],
7687 env
->spr
[SPR_BOOKE_MAS2
], env
->spr
[SPR_BOOKE_MAS3
]);
7689 qemu_fprintf(f
, " MAS4 " TARGET_FMT_lx
" MAS6 " TARGET_FMT_lx
7690 " MAS7 " TARGET_FMT_lx
" PID " TARGET_FMT_lx
"\n",
7691 env
->spr
[SPR_BOOKE_MAS4
], env
->spr
[SPR_BOOKE_MAS6
],
7692 env
->spr
[SPR_BOOKE_MAS7
], env
->spr
[SPR_BOOKE_PID
]);
7694 qemu_fprintf(f
, "MMUCFG " TARGET_FMT_lx
" TLB0CFG " TARGET_FMT_lx
7695 " TLB1CFG " TARGET_FMT_lx
"\n",
7696 env
->spr
[SPR_MMUCFG
], env
->spr
[SPR_BOOKE_TLB0CFG
],
7697 env
->spr
[SPR_BOOKE_TLB1CFG
]);
7708 void ppc_cpu_dump_statistics(CPUState
*cs
, int flags
)
7710 #if defined(DO_PPC_STATISTICS)
7711 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
7712 opc_handler_t
**t1
, **t2
, **t3
, *handler
;
7715 t1
= cpu
->env
.opcodes
;
7716 for (op1
= 0; op1
< 64; op1
++) {
7718 if (is_indirect_opcode(handler
)) {
7719 t2
= ind_table(handler
);
7720 for (op2
= 0; op2
< 32; op2
++) {
7722 if (is_indirect_opcode(handler
)) {
7723 t3
= ind_table(handler
);
7724 for (op3
= 0; op3
< 32; op3
++) {
7726 if (handler
->count
== 0) {
7729 qemu_printf("%02x %02x %02x (%02x %04d) %16s: "
7730 "%016" PRIx64
" %" PRId64
"\n",
7731 op1
, op2
, op3
, op1
, (op3
<< 5) | op2
,
7733 handler
->count
, handler
->count
);
7736 if (handler
->count
== 0) {
7739 qemu_printf("%02x %02x (%02x %04d) %16s: "
7740 "%016" PRIx64
" %" PRId64
"\n",
7741 op1
, op2
, op1
, op2
, handler
->oname
,
7742 handler
->count
, handler
->count
);
7746 if (handler
->count
== 0) {
7749 qemu_printf("%02x (%02x ) %16s: %016" PRIx64
7751 op1
, op1
, handler
->oname
,
7752 handler
->count
, handler
->count
);
7758 static void ppc_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
7760 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
7761 CPUPPCState
*env
= cs
->env_ptr
;
7764 ctx
->exception
= POWERPC_EXCP_NONE
;
7765 ctx
->spr_cb
= env
->spr_cb
;
7767 ctx
->mem_idx
= env
->dmmu_idx
;
7769 #if !defined(CONFIG_USER_ONLY)
7770 ctx
->hv
= msr_hv
|| !env
->has_hv_mode
;
7772 ctx
->insns_flags
= env
->insns_flags
;
7773 ctx
->insns_flags2
= env
->insns_flags2
;
7774 ctx
->access_type
= -1;
7775 ctx
->need_access_type
= !(env
->mmu_model
& POWERPC_MMU_64B
);
7776 ctx
->le_mode
= !!(env
->hflags
& (1 << MSR_LE
));
7777 ctx
->default_tcg_memop_mask
= ctx
->le_mode
? MO_LE
: MO_BE
;
7778 ctx
->flags
= env
->flags
;
7779 #if defined(TARGET_PPC64)
7780 ctx
->sf_mode
= msr_is_64bit(env
, env
->msr
);
7781 ctx
->has_cfar
= !!(env
->flags
& POWERPC_FLAG_CFAR
);
7783 ctx
->lazy_tlb_flush
= env
->mmu_model
== POWERPC_MMU_32B
7784 || env
->mmu_model
== POWERPC_MMU_601
7785 || (env
->mmu_model
& POWERPC_MMU_64B
);
7787 ctx
->fpu_enabled
= !!msr_fp
;
7788 if ((env
->flags
& POWERPC_FLAG_SPE
) && msr_spe
) {
7789 ctx
->spe_enabled
= !!msr_spe
;
7791 ctx
->spe_enabled
= false;
7793 if ((env
->flags
& POWERPC_FLAG_VRE
) && msr_vr
) {
7794 ctx
->altivec_enabled
= !!msr_vr
;
7796 ctx
->altivec_enabled
= false;
7798 if ((env
->flags
& POWERPC_FLAG_VSX
) && msr_vsx
) {
7799 ctx
->vsx_enabled
= !!msr_vsx
;
7801 ctx
->vsx_enabled
= false;
7803 #if defined(TARGET_PPC64)
7804 if ((env
->flags
& POWERPC_FLAG_TM
) && msr_tm
) {
7805 ctx
->tm_enabled
= !!msr_tm
;
7807 ctx
->tm_enabled
= false;
7810 ctx
->gtse
= !!(env
->spr
[SPR_LPCR
] & LPCR_GTSE
);
7811 if ((env
->flags
& POWERPC_FLAG_SE
) && msr_se
) {
7812 ctx
->singlestep_enabled
= CPU_SINGLE_STEP
;
7814 ctx
->singlestep_enabled
= 0;
7816 if ((env
->flags
& POWERPC_FLAG_BE
) && msr_be
) {
7817 ctx
->singlestep_enabled
|= CPU_BRANCH_STEP
;
7819 if ((env
->flags
& POWERPC_FLAG_DE
) && msr_de
) {
7820 ctx
->singlestep_enabled
= 0;
7821 target_ulong dbcr0
= env
->spr
[SPR_BOOKE_DBCR0
];
7822 if (dbcr0
& DBCR0_ICMP
) {
7823 ctx
->singlestep_enabled
|= CPU_SINGLE_STEP
;
7825 if (dbcr0
& DBCR0_BRT
) {
7826 ctx
->singlestep_enabled
|= CPU_BRANCH_STEP
;
7830 if (unlikely(ctx
->base
.singlestep_enabled
)) {
7831 ctx
->singlestep_enabled
|= GDBSTUB_SINGLE_STEP
;
7833 #if defined(DO_SINGLE_STEP) && 0
7834 /* Single step trace mode */
7838 bound
= -(ctx
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
7839 ctx
->base
.max_insns
= MIN(ctx
->base
.max_insns
, bound
);
7842 static void ppc_tr_tb_start(DisasContextBase
*db
, CPUState
*cs
)
7846 static void ppc_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cs
)
7848 tcg_gen_insn_start(dcbase
->pc_next
);
7851 static bool ppc_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cs
,
7852 const CPUBreakpoint
*bp
)
7854 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
7856 gen_debug_exception(ctx
);
7857 dcbase
->is_jmp
= DISAS_NORETURN
;
7859 * The address covered by the breakpoint must be included in
7860 * [tb->pc, tb->pc + tb->size) in order to for it to be properly
7861 * cleared -- thus we increment the PC here so that the logic
7862 * setting tb->size below does the right thing.
7864 ctx
->base
.pc_next
+= 4;
7868 static void ppc_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cs
)
7870 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
7871 CPUPPCState
*env
= cs
->env_ptr
;
7872 opc_handler_t
**table
, *handler
;
7874 LOG_DISAS("----------------\n");
7875 LOG_DISAS("nip=" TARGET_FMT_lx
" super=%d ir=%d\n",
7876 ctx
->base
.pc_next
, ctx
->mem_idx
, (int)msr_ir
);
7878 if (unlikely(need_byteswap(ctx
))) {
7879 ctx
->opcode
= bswap32(cpu_ldl_code(env
, ctx
->base
.pc_next
));
7881 ctx
->opcode
= cpu_ldl_code(env
, ctx
->base
.pc_next
);
7883 LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n",
7884 ctx
->opcode
, opc1(ctx
->opcode
), opc2(ctx
->opcode
),
7885 opc3(ctx
->opcode
), opc4(ctx
->opcode
),
7886 ctx
->le_mode
? "little" : "big");
7887 ctx
->base
.pc_next
+= 4;
7888 table
= env
->opcodes
;
7889 handler
= table
[opc1(ctx
->opcode
)];
7890 if (is_indirect_opcode(handler
)) {
7891 table
= ind_table(handler
);
7892 handler
= table
[opc2(ctx
->opcode
)];
7893 if (is_indirect_opcode(handler
)) {
7894 table
= ind_table(handler
);
7895 handler
= table
[opc3(ctx
->opcode
)];
7896 if (is_indirect_opcode(handler
)) {
7897 table
= ind_table(handler
);
7898 handler
= table
[opc4(ctx
->opcode
)];
7902 /* Is opcode *REALLY* valid ? */
7903 if (unlikely(handler
->handler
== &gen_invalid
)) {
7904 qemu_log_mask(LOG_GUEST_ERROR
, "invalid/unsupported opcode: "
7905 "%02x - %02x - %02x - %02x (%08x) "
7906 TARGET_FMT_lx
" %d\n",
7907 opc1(ctx
->opcode
), opc2(ctx
->opcode
),
7908 opc3(ctx
->opcode
), opc4(ctx
->opcode
),
7909 ctx
->opcode
, ctx
->base
.pc_next
- 4, (int)msr_ir
);
7913 if (unlikely(handler
->type
& (PPC_SPE
| PPC_SPE_SINGLE
| PPC_SPE_DOUBLE
)
7914 && Rc(ctx
->opcode
))) {
7915 inval
= handler
->inval2
;
7917 inval
= handler
->inval1
;
7920 if (unlikely((ctx
->opcode
& inval
) != 0)) {
7921 qemu_log_mask(LOG_GUEST_ERROR
, "invalid bits: %08x for opcode: "
7922 "%02x - %02x - %02x - %02x (%08x) "
7923 TARGET_FMT_lx
"\n", ctx
->opcode
& inval
,
7924 opc1(ctx
->opcode
), opc2(ctx
->opcode
),
7925 opc3(ctx
->opcode
), opc4(ctx
->opcode
),
7926 ctx
->opcode
, ctx
->base
.pc_next
- 4);
7927 gen_inval_exception(ctx
, POWERPC_EXCP_INVAL_INVAL
);
7928 ctx
->base
.is_jmp
= DISAS_NORETURN
;
7932 (*(handler
->handler
))(ctx
);
7933 #if defined(DO_PPC_STATISTICS)
7936 /* Check trace mode exceptions */
7937 if (unlikely(ctx
->singlestep_enabled
& CPU_SINGLE_STEP
&&
7938 (ctx
->base
.pc_next
<= 0x100 || ctx
->base
.pc_next
> 0xF00) &&
7939 ctx
->exception
!= POWERPC_SYSCALL
&&
7940 ctx
->exception
!= POWERPC_EXCP_TRAP
&&
7941 ctx
->exception
!= POWERPC_EXCP_BRANCH
)) {
7942 uint32_t excp
= gen_prep_dbgex(ctx
);
7943 gen_exception_nip(ctx
, excp
, ctx
->base
.pc_next
);
7946 if (tcg_check_temp_count()) {
7947 qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked "
7948 "temporaries\n", opc1(ctx
->opcode
), opc2(ctx
->opcode
),
7949 opc3(ctx
->opcode
), opc4(ctx
->opcode
), ctx
->opcode
);
7952 ctx
->base
.is_jmp
= ctx
->exception
== POWERPC_EXCP_NONE
?
7953 DISAS_NEXT
: DISAS_NORETURN
;
7956 static void ppc_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cs
)
7958 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
7960 if (ctx
->exception
== POWERPC_EXCP_NONE
) {
7961 gen_goto_tb(ctx
, 0, ctx
->base
.pc_next
);
7962 } else if (ctx
->exception
!= POWERPC_EXCP_BRANCH
) {
7963 if (unlikely(ctx
->base
.singlestep_enabled
)) {
7964 gen_debug_exception(ctx
);
7966 /* Generate the return instruction */
7967 tcg_gen_exit_tb(NULL
, 0);
7971 static void ppc_tr_disas_log(const DisasContextBase
*dcbase
, CPUState
*cs
)
7973 qemu_log("IN: %s\n", lookup_symbol(dcbase
->pc_first
));
7974 log_target_disas(cs
, dcbase
->pc_first
, dcbase
->tb
->size
);
7977 static const TranslatorOps ppc_tr_ops
= {
7978 .init_disas_context
= ppc_tr_init_disas_context
,
7979 .tb_start
= ppc_tr_tb_start
,
7980 .insn_start
= ppc_tr_insn_start
,
7981 .breakpoint_check
= ppc_tr_breakpoint_check
,
7982 .translate_insn
= ppc_tr_translate_insn
,
7983 .tb_stop
= ppc_tr_tb_stop
,
7984 .disas_log
= ppc_tr_disas_log
,
7987 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int max_insns
)
7991 translator_loop(&ppc_tr_ops
, &ctx
.base
, cs
, tb
, max_insns
);
7994 void restore_state_to_opc(CPUPPCState
*env
, TranslationBlock
*tb
,