2 * Inter-Thread Communication Unit emulation.
4 * Copyright (c) 2016 Imagination Technologies
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/units.h"
23 #include "qapi/error.h"
25 #include "exec/exec-all.h"
26 #include "hw/misc/mips_itu.h"
28 #define ITC_TAG_ADDRSPACE_SZ (ITC_ADDRESSMAP_NUM * 8)
29 /* Initialize as 4kB area to fit all 32 cells with default 128B grain.
30 Storage may be resized by the software. */
31 #define ITC_STORAGE_ADDRSPACE_SZ 0x1000
33 #define ITC_FIFO_NUM_MAX 16
34 #define ITC_SEMAPH_NUM_MAX 16
35 #define ITC_AM1_NUMENTRIES_OFS 20
37 #define ITC_CELL_PV_MAX_VAL 0xFFFF
39 #define ITC_CELL_TAG_FIFO_DEPTH 28
40 #define ITC_CELL_TAG_FIFO_PTR 18
41 #define ITC_CELL_TAG_FIFO 17
42 #define ITC_CELL_TAG_T 16
43 #define ITC_CELL_TAG_F 1
44 #define ITC_CELL_TAG_E 0
46 #define ITC_AM0_BASE_ADDRESS_MASK 0xFFFFFC00ULL
47 #define ITC_AM0_EN_MASK 0x1
49 #define ITC_AM1_ADDR_MASK_MASK 0x1FC00
50 #define ITC_AM1_ENTRY_GRAIN_MASK 0x7
52 typedef enum ITCView
{
62 #define ITC_ICR0_CELL_NUM 16
63 #define ITC_ICR0_BLK_GRAIN 8
64 #define ITC_ICR0_BLK_GRAIN_MASK 0x7
65 #define ITC_ICR0_ERR_AXI 2
66 #define ITC_ICR0_ERR_PARITY 1
67 #define ITC_ICR0_ERR_EXEC 0
69 MemoryRegion
*mips_itu_get_tag_region(MIPSITUState
*itu
)
74 static uint64_t itc_tag_read(void *opaque
, hwaddr addr
, unsigned size
)
76 MIPSITUState
*tag
= (MIPSITUState
*)opaque
;
77 uint64_t index
= addr
>> 3;
79 if (index
>= ITC_ADDRESSMAP_NUM
) {
80 qemu_log_mask(LOG_GUEST_ERROR
, "Read 0x%" PRIx64
"\n", addr
);
84 return tag
->ITCAddressMap
[index
];
87 void itc_reconfigure(MIPSITUState
*tag
)
89 uint64_t *am
= &tag
->ITCAddressMap
[0];
90 MemoryRegion
*mr
= &tag
->storage_io
;
91 hwaddr address
= am
[0] & ITC_AM0_BASE_ADDRESS_MASK
;
92 uint64_t size
= (1 * KiB
) + (am
[1] & ITC_AM1_ADDR_MASK_MASK
);
93 bool is_enabled
= (am
[0] & ITC_AM0_EN_MASK
) != 0;
95 if (tag
->saar_present
) {
96 address
= ((*(uint64_t *) tag
->saar
) & 0xFFFFFFFFE000ULL
) << 4;
97 size
= 1ULL << ((*(uint64_t *) tag
->saar
>> 1) & 0x1f);
98 is_enabled
= *(uint64_t *) tag
->saar
& 1;
101 memory_region_transaction_begin();
102 if (!(size
& (size
- 1))) {
103 memory_region_set_size(mr
, size
);
105 memory_region_set_address(mr
, address
);
106 memory_region_set_enabled(mr
, is_enabled
);
107 memory_region_transaction_commit();
110 static void itc_tag_write(void *opaque
, hwaddr addr
,
111 uint64_t data
, unsigned size
)
113 MIPSITUState
*tag
= (MIPSITUState
*)opaque
;
114 uint64_t *am
= &tag
->ITCAddressMap
[0];
115 uint64_t am_old
, mask
;
116 uint64_t index
= addr
>> 3;
120 mask
= ITC_AM0_BASE_ADDRESS_MASK
| ITC_AM0_EN_MASK
;
123 mask
= ITC_AM1_ADDR_MASK_MASK
| ITC_AM1_ENTRY_GRAIN_MASK
;
126 qemu_log_mask(LOG_GUEST_ERROR
, "Bad write 0x%" PRIx64
"\n", addr
);
131 am
[index
] = (data
& mask
) | (am_old
& ~mask
);
132 if (am_old
!= am
[index
]) {
133 itc_reconfigure(tag
);
137 static const MemoryRegionOps itc_tag_ops
= {
138 .read
= itc_tag_read
,
139 .write
= itc_tag_write
,
141 .max_access_size
= 8,
143 .endianness
= DEVICE_NATIVE_ENDIAN
,
146 static inline uint32_t get_num_cells(MIPSITUState
*s
)
148 return s
->num_fifo
+ s
->num_semaphores
;
151 static inline ITCView
get_itc_view(hwaddr addr
)
153 return (addr
>> 3) & 0xf;
156 static inline int get_cell_stride_shift(const MIPSITUState
*s
)
158 /* Minimum interval (for EntryGain = 0) is 128 B */
159 if (s
->saar_present
) {
160 return 7 + ((s
->icr0
>> ITC_ICR0_BLK_GRAIN
) &
161 ITC_ICR0_BLK_GRAIN_MASK
);
163 return 7 + (s
->ITCAddressMap
[1] & ITC_AM1_ENTRY_GRAIN_MASK
);
167 static inline ITCStorageCell
*get_cell(MIPSITUState
*s
,
170 uint32_t cell_idx
= addr
>> get_cell_stride_shift(s
);
171 uint32_t num_cells
= get_num_cells(s
);
173 if (cell_idx
>= num_cells
) {
174 cell_idx
= num_cells
- 1;
177 return &s
->cell
[cell_idx
];
180 static void wake_blocked_threads(ITCStorageCell
*c
)
184 if (cs
->halted
&& (c
->blocked_threads
& (1ULL << cs
->cpu_index
))) {
185 cpu_interrupt(cs
, CPU_INTERRUPT_WAKE
);
188 c
->blocked_threads
= 0;
191 static void QEMU_NORETURN
block_thread_and_exit(ITCStorageCell
*c
)
193 c
->blocked_threads
|= 1ULL << current_cpu
->cpu_index
;
194 current_cpu
->halted
= 1;
195 current_cpu
->exception_index
= EXCP_HLT
;
196 cpu_loop_exit_restore(current_cpu
, current_cpu
->mem_io_pc
);
199 /* ITC Bypass View */
201 static inline uint64_t view_bypass_read(ITCStorageCell
*c
)
204 return c
->data
[c
->fifo_out
];
210 static inline void view_bypass_write(ITCStorageCell
*c
, uint64_t val
)
212 if (c
->tag
.FIFO
&& (c
->tag
.FIFOPtr
> 0)) {
213 int idx
= (c
->fifo_out
+ c
->tag
.FIFOPtr
- 1) % ITC_CELL_DEPTH
;
217 /* ignore a write to the semaphore cell */
220 /* ITC Control View */
222 static inline uint64_t view_control_read(ITCStorageCell
*c
)
224 return ((uint64_t)c
->tag
.FIFODepth
<< ITC_CELL_TAG_FIFO_DEPTH
) |
225 (c
->tag
.FIFOPtr
<< ITC_CELL_TAG_FIFO_PTR
) |
226 (c
->tag
.FIFO
<< ITC_CELL_TAG_FIFO
) |
227 (c
->tag
.T
<< ITC_CELL_TAG_T
) |
228 (c
->tag
.E
<< ITC_CELL_TAG_E
) |
229 (c
->tag
.F
<< ITC_CELL_TAG_F
);
232 static inline void view_control_write(ITCStorageCell
*c
, uint64_t val
)
234 c
->tag
.T
= (val
>> ITC_CELL_TAG_T
) & 1;
235 c
->tag
.E
= (val
>> ITC_CELL_TAG_E
) & 1;
236 c
->tag
.F
= (val
>> ITC_CELL_TAG_F
) & 1;
243 /* ITC Empty/Full View */
245 static uint64_t view_ef_common_read(ITCStorageCell
*c
, bool blocking
)
255 if (blocking
&& c
->tag
.E
) {
256 block_thread_and_exit(c
);
259 if (c
->blocked_threads
) {
260 wake_blocked_threads(c
);
263 if (c
->tag
.FIFOPtr
> 0) {
264 ret
= c
->data
[c
->fifo_out
];
265 c
->fifo_out
= (c
->fifo_out
+ 1) % ITC_CELL_DEPTH
;
269 if (c
->tag
.FIFOPtr
== 0) {
276 static uint64_t view_ef_sync_read(ITCStorageCell
*c
)
278 return view_ef_common_read(c
, true);
281 static uint64_t view_ef_try_read(ITCStorageCell
*c
)
283 return view_ef_common_read(c
, false);
286 static inline void view_ef_common_write(ITCStorageCell
*c
, uint64_t val
,
295 if (blocking
&& c
->tag
.F
) {
296 block_thread_and_exit(c
);
299 if (c
->blocked_threads
) {
300 wake_blocked_threads(c
);
303 if (c
->tag
.FIFOPtr
< ITC_CELL_DEPTH
) {
304 int idx
= (c
->fifo_out
+ c
->tag
.FIFOPtr
) % ITC_CELL_DEPTH
;
309 if (c
->tag
.FIFOPtr
== ITC_CELL_DEPTH
) {
314 static void view_ef_sync_write(ITCStorageCell
*c
, uint64_t val
)
316 view_ef_common_write(c
, val
, true);
319 static void view_ef_try_write(ITCStorageCell
*c
, uint64_t val
)
321 view_ef_common_write(c
, val
, false);
326 static uint64_t view_pv_common_read(ITCStorageCell
*c
, bool blocking
)
328 uint64_t ret
= c
->data
[0];
334 if (c
->data
[0] > 0) {
336 } else if (blocking
) {
337 block_thread_and_exit(c
);
343 static uint64_t view_pv_sync_read(ITCStorageCell
*c
)
345 return view_pv_common_read(c
, true);
348 static uint64_t view_pv_try_read(ITCStorageCell
*c
)
350 return view_pv_common_read(c
, false);
353 static inline void view_pv_common_write(ITCStorageCell
*c
)
359 if (c
->data
[0] < ITC_CELL_PV_MAX_VAL
) {
363 if (c
->blocked_threads
) {
364 wake_blocked_threads(c
);
368 static void view_pv_sync_write(ITCStorageCell
*c
)
370 view_pv_common_write(c
);
373 static void view_pv_try_write(ITCStorageCell
*c
)
375 view_pv_common_write(c
);
378 static void raise_exception(int excp
)
380 current_cpu
->exception_index
= excp
;
381 cpu_loop_exit(current_cpu
);
384 static uint64_t itc_storage_read(void *opaque
, hwaddr addr
, unsigned size
)
386 MIPSITUState
*s
= (MIPSITUState
*)opaque
;
387 ITCStorageCell
*cell
= get_cell(s
, addr
);
388 ITCView view
= get_itc_view(addr
);
394 s
->icr0
|= 1 << ITC_ICR0_ERR_AXI
;
395 raise_exception(EXCP_DBE
);
401 ret
= view_bypass_read(cell
);
403 case ITCVIEW_CONTROL
:
404 ret
= view_control_read(cell
);
406 case ITCVIEW_EF_SYNC
:
407 ret
= view_ef_sync_read(cell
);
410 ret
= view_ef_try_read(cell
);
412 case ITCVIEW_PV_SYNC
:
413 ret
= view_pv_sync_read(cell
);
416 ret
= view_pv_try_read(cell
);
418 case ITCVIEW_PV_ICR0
:
422 qemu_log_mask(LOG_GUEST_ERROR
,
423 "itc_storage_read: Bad ITC View %d\n", (int)view
);
430 static void itc_storage_write(void *opaque
, hwaddr addr
, uint64_t data
,
433 MIPSITUState
*s
= (MIPSITUState
*)opaque
;
434 ITCStorageCell
*cell
= get_cell(s
, addr
);
435 ITCView view
= get_itc_view(addr
);
440 s
->icr0
|= 1 << ITC_ICR0_ERR_AXI
;
441 raise_exception(EXCP_DBE
);
447 view_bypass_write(cell
, data
);
449 case ITCVIEW_CONTROL
:
450 view_control_write(cell
, data
);
452 case ITCVIEW_EF_SYNC
:
453 view_ef_sync_write(cell
, data
);
456 view_ef_try_write(cell
, data
);
458 case ITCVIEW_PV_SYNC
:
459 view_pv_sync_write(cell
);
462 view_pv_try_write(cell
);
464 case ITCVIEW_PV_ICR0
:
466 /* clear ERROR bits */
467 s
->icr0
&= ~(data
& 0x7);
471 s
->icr0
|= data
& 0x700;
474 qemu_log_mask(LOG_GUEST_ERROR
,
475 "itc_storage_write: Bad ITC View %d\n", (int)view
);
481 static const MemoryRegionOps itc_storage_ops
= {
482 .read
= itc_storage_read
,
483 .write
= itc_storage_write
,
484 .endianness
= DEVICE_NATIVE_ENDIAN
,
487 static void itc_reset_cells(MIPSITUState
*s
)
491 memset(s
->cell
, 0, get_num_cells(s
) * sizeof(s
->cell
[0]));
493 for (i
= 0; i
< s
->num_fifo
; i
++) {
494 s
->cell
[i
].tag
.E
= 1;
495 s
->cell
[i
].tag
.FIFO
= 1;
496 s
->cell
[i
].tag
.FIFODepth
= ITC_CELL_DEPTH_SHIFT
;
500 static void mips_itu_init(Object
*obj
)
502 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
503 MIPSITUState
*s
= MIPS_ITU(obj
);
505 memory_region_init_io(&s
->storage_io
, OBJECT(s
), &itc_storage_ops
, s
,
506 "mips-itc-storage", ITC_STORAGE_ADDRSPACE_SZ
);
507 sysbus_init_mmio(sbd
, &s
->storage_io
);
509 memory_region_init_io(&s
->tag_io
, OBJECT(s
), &itc_tag_ops
, s
,
510 "mips-itc-tag", ITC_TAG_ADDRSPACE_SZ
);
513 static void mips_itu_realize(DeviceState
*dev
, Error
**errp
)
515 MIPSITUState
*s
= MIPS_ITU(dev
);
517 if (s
->num_fifo
> ITC_FIFO_NUM_MAX
) {
518 error_setg(errp
, "Exceed maximum number of FIFO cells: %d",
522 if (s
->num_semaphores
> ITC_SEMAPH_NUM_MAX
) {
523 error_setg(errp
, "Exceed maximum number of Semaphore cells: %d",
528 s
->cell
= g_new(ITCStorageCell
, get_num_cells(s
));
531 static void mips_itu_reset(DeviceState
*dev
)
533 MIPSITUState
*s
= MIPS_ITU(dev
);
535 if (s
->saar_present
) {
536 *(uint64_t *) s
->saar
= 0x11 << 1;
537 s
->icr0
= get_num_cells(s
) << ITC_ICR0_CELL_NUM
;
539 s
->ITCAddressMap
[0] = 0;
540 s
->ITCAddressMap
[1] =
541 ((ITC_STORAGE_ADDRSPACE_SZ
- 1) & ITC_AM1_ADDR_MASK_MASK
) |
542 (get_num_cells(s
) << ITC_AM1_NUMENTRIES_OFS
);
549 static Property mips_itu_properties
[] = {
550 DEFINE_PROP_INT32("num-fifo", MIPSITUState
, num_fifo
,
552 DEFINE_PROP_INT32("num-semaphores", MIPSITUState
, num_semaphores
,
554 DEFINE_PROP_BOOL("saar-present", MIPSITUState
, saar_present
, false),
555 DEFINE_PROP_END_OF_LIST(),
558 static void mips_itu_class_init(ObjectClass
*klass
, void *data
)
560 DeviceClass
*dc
= DEVICE_CLASS(klass
);
562 dc
->props
= mips_itu_properties
;
563 dc
->realize
= mips_itu_realize
;
564 dc
->reset
= mips_itu_reset
;
567 static const TypeInfo mips_itu_info
= {
568 .name
= TYPE_MIPS_ITU
,
569 .parent
= TYPE_SYS_BUS_DEVICE
,
570 .instance_size
= sizeof(MIPSITUState
),
571 .instance_init
= mips_itu_init
,
572 .class_init
= mips_itu_class_init
,
575 static void mips_itu_register_types(void)
577 type_register_static(&mips_itu_info
);
580 type_init(mips_itu_register_types
)