2 * QEMU ATI SVGA emulation
4 * Copyright (c) 2019 BALATON Zoltan
6 * This work is licensed under the GNU GPL license version 2 or later.
11 * This is very incomplete and only enough for Linux console and some
12 * unaccelerated X output at the moment.
13 * Currently it's little more than a frame buffer with minimal functions,
14 * other more advanced features of the hardware are yet to be implemented.
15 * We only aim for Rage 128 Pro (and some RV100) and 2D only at first,
16 * No 3D at all yet (maybe after 2D works, but feel free to improve it)
19 #include "qemu/osdep.h"
24 #include "qemu/error-report.h"
25 #include "qapi/error.h"
27 #include "ui/console.h"
30 #define ATI_DEBUG_HW_CURSOR 0
35 } ati_model_aliases
[] = {
36 { "rage128p", PCI_DEVICE_ID_ATI_RAGE128_PF
},
37 { "rv100", PCI_DEVICE_ID_ATI_RADEON_QY
},
40 enum { VGA_MODE
, EXT_MODE
};
42 static void ati_vga_switch_mode(ATIVGAState
*s
)
45 s
->mode
, !!(s
->regs
.crtc_gen_cntl
& CRTC2_EXT_DISP_EN
));
46 if (s
->regs
.crtc_gen_cntl
& CRTC2_EXT_DISP_EN
) {
47 /* Extended mode enabled */
49 if (s
->regs
.crtc_gen_cntl
& CRTC2_EN
) {
50 /* CRT controller enabled, use CRTC values */
51 uint32_t offs
= s
->regs
.crtc_offset
& 0x07ffffff;
52 int stride
= (s
->regs
.crtc_pitch
& 0x7ff) * 8;
56 if (s
->regs
.crtc_h_total_disp
== 0) {
57 s
->regs
.crtc_h_total_disp
= ((640 / 8) - 1) << 16;
59 if (s
->regs
.crtc_v_total_disp
== 0) {
60 s
->regs
.crtc_v_total_disp
= (480 - 1) << 16;
62 h
= ((s
->regs
.crtc_h_total_disp
>> 16) + 1) * 8;
63 v
= (s
->regs
.crtc_v_total_disp
>> 16) + 1;
64 switch (s
->regs
.crtc_gen_cntl
& CRTC_PIX_WIDTH_MASK
) {
65 case CRTC_PIX_WIDTH_4BPP
:
68 case CRTC_PIX_WIDTH_8BPP
:
71 case CRTC_PIX_WIDTH_15BPP
:
74 case CRTC_PIX_WIDTH_16BPP
:
77 case CRTC_PIX_WIDTH_24BPP
:
80 case CRTC_PIX_WIDTH_32BPP
:
84 qemu_log_mask(LOG_UNIMP
, "Unsupported bpp value\n");
87 DPRINTF("Switching to %dx%d %d %d @ %x\n", h
, v
, stride
, bpp
, offs
);
88 vbe_ioport_write_index(&s
->vga
, 0, VBE_DISPI_INDEX_ENABLE
);
89 vbe_ioport_write_data(&s
->vga
, 0, VBE_DISPI_DISABLED
);
90 /* reset VBE regs then set up mode */
91 s
->vga
.vbe_regs
[VBE_DISPI_INDEX_XRES
] = h
;
92 s
->vga
.vbe_regs
[VBE_DISPI_INDEX_YRES
] = v
;
93 s
->vga
.vbe_regs
[VBE_DISPI_INDEX_BPP
] = bpp
;
94 /* enable mode via ioport so it updates vga regs */
95 vbe_ioport_write_index(&s
->vga
, 0, VBE_DISPI_INDEX_ENABLE
);
96 vbe_ioport_write_data(&s
->vga
, 0, VBE_DISPI_ENABLED
|
97 VBE_DISPI_LFB_ENABLED
| VBE_DISPI_NOCLEARMEM
|
98 (s
->regs
.dac_cntl
& DAC_8BIT_EN
? VBE_DISPI_8BIT_DAC
: 0));
99 /* now set offset and stride after enable as that resets these */
101 vbe_ioport_write_index(&s
->vga
, 0, VBE_DISPI_INDEX_VIRT_WIDTH
);
102 vbe_ioport_write_data(&s
->vga
, 0, stride
);
103 if (offs
% stride
== 0) {
104 vbe_ioport_write_index(&s
->vga
, 0, VBE_DISPI_INDEX_Y_OFFSET
);
105 vbe_ioport_write_data(&s
->vga
, 0, offs
/ stride
);
107 /* FIXME what to do with this? */
108 error_report("VGA offset is not multiple of pitch, "
109 "expect bad picture");
114 /* VGA mode enabled */
116 vbe_ioport_write_index(&s
->vga
, 0, VBE_DISPI_INDEX_ENABLE
);
117 vbe_ioport_write_data(&s
->vga
, 0, VBE_DISPI_DISABLED
);
121 /* Used by host side hardware cursor */
122 static void ati_cursor_define(ATIVGAState
*s
)
128 if ((s
->regs
.cur_offset
& BIT(31)) || s
->cursor_guest_mode
) {
129 return; /* Do not update cursor if locked or rendered by guest */
131 /* FIXME handle cur_hv_offs correctly */
132 src
= s
->vga
.vram_ptr
+ (s
->regs
.crtc_offset
& 0x07ffffff) +
133 s
->regs
.cur_offset
- (s
->regs
.cur_hv_offs
>> 16) -
134 (s
->regs
.cur_hv_offs
& 0xffff) * 16;
135 for (i
= 0; i
< 64; i
++) {
136 for (j
= 0; j
< 8; j
++, idx
++) {
137 data
[idx
] = src
[i
* 16 + j
];
138 data
[512 + idx
] = src
[i
* 16 + j
+ 8];
142 s
->cursor
= cursor_alloc(64, 64);
144 cursor_set_mono(s
->cursor
, s
->regs
.cur_color1
, s
->regs
.cur_color0
,
145 &data
[512], 1, &data
[0]);
146 dpy_cursor_define(s
->vga
.con
, s
->cursor
);
149 /* Alternatively support guest rendered hardware cursor */
150 static void ati_cursor_invalidate(VGACommonState
*vga
)
152 ATIVGAState
*s
= container_of(vga
, ATIVGAState
, vga
);
153 int size
= (s
->regs
.crtc_gen_cntl
& CRTC2_CUR_EN
) ? 64 : 0;
155 if (s
->regs
.cur_offset
& BIT(31)) {
156 return; /* Do not update cursor if locked */
158 if (s
->cursor_size
!= size
||
159 vga
->hw_cursor_x
!= s
->regs
.cur_hv_pos
>> 16 ||
160 vga
->hw_cursor_y
!= (s
->regs
.cur_hv_pos
& 0xffff) ||
161 s
->cursor_offset
!= s
->regs
.cur_offset
- (s
->regs
.cur_hv_offs
>> 16) -
162 (s
->regs
.cur_hv_offs
& 0xffff) * 16) {
163 /* Remove old cursor then update and show new one if needed */
164 vga_invalidate_scanlines(vga
, vga
->hw_cursor_y
, vga
->hw_cursor_y
+ 63);
165 vga
->hw_cursor_x
= s
->regs
.cur_hv_pos
>> 16;
166 vga
->hw_cursor_y
= s
->regs
.cur_hv_pos
& 0xffff;
167 s
->cursor_offset
= s
->regs
.cur_offset
- (s
->regs
.cur_hv_offs
>> 16) -
168 (s
->regs
.cur_hv_offs
& 0xffff) * 16;
169 s
->cursor_size
= size
;
171 vga_invalidate_scanlines(vga
,
172 vga
->hw_cursor_y
, vga
->hw_cursor_y
+ 63);
177 static void ati_cursor_draw_line(VGACommonState
*vga
, uint8_t *d
, int scr_y
)
179 ATIVGAState
*s
= container_of(vga
, ATIVGAState
, vga
);
181 uint32_t *dp
= (uint32_t *)d
;
184 if (!(s
->regs
.crtc_gen_cntl
& CRTC2_CUR_EN
) ||
185 scr_y
< vga
->hw_cursor_y
|| scr_y
>= vga
->hw_cursor_y
+ 64 ||
186 scr_y
> s
->regs
.crtc_v_total_disp
>> 16) {
189 /* FIXME handle cur_hv_offs correctly */
190 src
= s
->vga
.vram_ptr
+ (s
->regs
.crtc_offset
& 0x07ffffff) +
191 s
->cursor_offset
+ (scr_y
- vga
->hw_cursor_y
) * 16;
192 dp
= &dp
[vga
->hw_cursor_x
];
193 h
= ((s
->regs
.crtc_h_total_disp
>> 16) + 1) * 8;
194 for (i
= 0; i
< 8; i
++) {
196 uint8_t abits
= src
[i
];
197 uint8_t xbits
= src
[i
+ 8];
198 for (j
= 0; j
< 8; j
++, abits
<<= 1, xbits
<<= 1) {
199 if (abits
& BIT(7)) {
200 if (xbits
& BIT(7)) {
201 color
= dp
[i
* 8 + j
] ^ 0xffffffff; /* complement */
203 continue; /* transparent, no change */
206 color
= (xbits
& BIT(7) ? s
->regs
.cur_color1
:
207 s
->regs
.cur_color0
) << 8 | 0xff;
209 if (vga
->hw_cursor_x
+ i
* 8 + j
>= h
) {
210 return; /* end of screen, don't span to next line */
212 dp
[i
* 8 + j
] = color
;
217 static inline uint64_t ati_reg_read_offs(uint32_t reg
, int offs
,
220 if (offs
== 0 && size
== 4) {
223 return extract32(reg
, offs
* BITS_PER_BYTE
, size
* BITS_PER_BYTE
);
227 static uint64_t ati_mm_read(void *opaque
, hwaddr addr
, unsigned int size
)
229 ATIVGAState
*s
= opaque
;
234 val
= s
->regs
.mm_index
;
236 case MM_DATA
... MM_DATA
+ 3:
237 /* indexed access to regs or memory */
238 if (s
->regs
.mm_index
& BIT(31)) {
239 uint32_t idx
= s
->regs
.mm_index
& ~BIT(31);
240 if (idx
<= s
->vga
.vram_size
- size
) {
241 val
= ldn_le_p(s
->vga
.vram_ptr
+ idx
, size
);
244 val
= ati_mm_read(s
, s
->regs
.mm_index
+ addr
- MM_DATA
, size
);
247 case BIOS_0_SCRATCH
... BUS_CNTL
- 1:
249 int i
= (addr
- BIOS_0_SCRATCH
) / 4;
250 if (s
->dev_id
== PCI_DEVICE_ID_ATI_RAGE128_PF
&& i
> 3) {
253 val
= ati_reg_read_offs(s
->regs
.bios_scratch
[i
],
254 addr
- (BIOS_0_SCRATCH
+ i
* 4), size
);
257 case CRTC_GEN_CNTL
... CRTC_GEN_CNTL
+ 3:
258 val
= ati_reg_read_offs(s
->regs
.crtc_gen_cntl
,
259 addr
- CRTC_GEN_CNTL
, size
);
261 case CRTC_EXT_CNTL
... CRTC_EXT_CNTL
+ 3:
262 val
= ati_reg_read_offs(s
->regs
.crtc_ext_cntl
,
263 addr
- CRTC_EXT_CNTL
, size
);
266 val
= s
->regs
.dac_cntl
;
268 /* case GPIO_MONID: FIXME hook up DDC I2C here */
270 /* FIXME unaligned access */
271 val
= vga_ioport_read(&s
->vga
, VGA_PEL_IR
) << 16;
272 val
|= vga_ioport_read(&s
->vga
, VGA_PEL_IW
) & 0xff;
275 val
= vga_ioport_read(&s
->vga
, VGA_PEL_D
);
278 val
= s
->vga
.vram_size
;
285 val
= 64; /* free CMDFIFO entries */
287 case CRTC_H_TOTAL_DISP
:
288 val
= s
->regs
.crtc_h_total_disp
;
290 case CRTC_H_SYNC_STRT_WID
:
291 val
= s
->regs
.crtc_h_sync_strt_wid
;
293 case CRTC_V_TOTAL_DISP
:
294 val
= s
->regs
.crtc_v_total_disp
;
296 case CRTC_V_SYNC_STRT_WID
:
297 val
= s
->regs
.crtc_v_sync_strt_wid
;
300 val
= s
->regs
.crtc_offset
;
302 case CRTC_OFFSET_CNTL
:
303 val
= s
->regs
.crtc_offset_cntl
;
306 val
= s
->regs
.crtc_pitch
;
308 case 0xf00 ... 0xfff:
309 val
= pci_default_read_config(&s
->dev
, addr
- 0xf00, size
);
312 val
= s
->regs
.cur_offset
;
314 case CUR_HORZ_VERT_POSN
:
315 val
= s
->regs
.cur_hv_pos
;
316 val
|= s
->regs
.cur_offset
& BIT(31);
318 case CUR_HORZ_VERT_OFF
:
319 val
= s
->regs
.cur_hv_offs
;
320 val
|= s
->regs
.cur_offset
& BIT(31);
323 val
= s
->regs
.cur_color0
;
326 val
= s
->regs
.cur_color1
;
329 val
= s
->regs
.dst_offset
;
332 val
= s
->regs
.dst_pitch
;
333 if (s
->dev_id
== PCI_DEVICE_ID_ATI_RAGE128_PF
) {
334 val
&= s
->regs
.dst_tile
<< 16;
338 val
= s
->regs
.dst_width
;
341 val
= s
->regs
.dst_height
;
355 case DP_GUI_MASTER_CNTL
:
356 val
= s
->regs
.dp_gui_master_cntl
;
359 val
= s
->regs
.src_offset
;
362 val
= s
->regs
.src_pitch
;
363 if (s
->dev_id
== PCI_DEVICE_ID_ATI_RAGE128_PF
) {
364 val
&= s
->regs
.src_tile
<< 16;
367 case DP_BRUSH_BKGD_CLR
:
368 val
= s
->regs
.dp_brush_bkgd_clr
;
370 case DP_BRUSH_FRGD_CLR
:
371 val
= s
->regs
.dp_brush_frgd_clr
;
373 case DP_SRC_FRGD_CLR
:
374 val
= s
->regs
.dp_src_frgd_clr
;
376 case DP_SRC_BKGD_CLR
:
377 val
= s
->regs
.dp_src_bkgd_clr
;
380 val
= s
->regs
.dp_cntl
;
383 val
= s
->regs
.dp_datatype
;
386 val
= s
->regs
.dp_mix
;
389 val
= s
->regs
.dp_write_mask
;
392 val
= s
->regs
.default_offset
;
395 val
= s
->regs
.default_pitch
;
397 case DEFAULT_SC_BOTTOM_RIGHT
:
398 val
= s
->regs
.default_sc_bottom_right
;
403 if (addr
< CUR_OFFSET
|| addr
> CUR_CLR1
|| ATI_DEBUG_HW_CURSOR
) {
404 trace_ati_mm_read(size
, addr
, ati_reg_name(addr
& ~3ULL), val
);
409 static inline void ati_reg_write_offs(uint32_t *reg
, int offs
,
410 uint64_t data
, unsigned int size
)
412 if (offs
== 0 && size
== 4) {
415 *reg
= deposit32(*reg
, offs
* BITS_PER_BYTE
, size
* BITS_PER_BYTE
,
420 static void ati_mm_write(void *opaque
, hwaddr addr
,
421 uint64_t data
, unsigned int size
)
423 ATIVGAState
*s
= opaque
;
425 if (addr
< CUR_OFFSET
|| addr
> CUR_CLR1
|| ATI_DEBUG_HW_CURSOR
) {
426 trace_ati_mm_write(size
, addr
, ati_reg_name(addr
& ~3ULL), data
);
430 s
->regs
.mm_index
= data
;
432 case MM_DATA
... MM_DATA
+ 3:
433 /* indexed access to regs or memory */
434 if (s
->regs
.mm_index
& BIT(31)) {
435 uint32_t idx
= s
->regs
.mm_index
& ~BIT(31);
436 if (idx
<= s
->vga
.vram_size
- size
) {
437 stn_le_p(s
->vga
.vram_ptr
+ idx
, size
, data
);
440 ati_mm_write(s
, s
->regs
.mm_index
+ addr
- MM_DATA
, data
, size
);
443 case BIOS_0_SCRATCH
... BUS_CNTL
- 1:
445 int i
= (addr
- BIOS_0_SCRATCH
) / 4;
446 if (s
->dev_id
== PCI_DEVICE_ID_ATI_RAGE128_PF
&& i
> 3) {
449 ati_reg_write_offs(&s
->regs
.bios_scratch
[i
],
450 addr
- (BIOS_0_SCRATCH
+ i
* 4), data
, size
);
453 case CRTC_GEN_CNTL
... CRTC_GEN_CNTL
+ 3:
455 uint32_t val
= s
->regs
.crtc_gen_cntl
;
456 ati_reg_write_offs(&s
->regs
.crtc_gen_cntl
,
457 addr
- CRTC_GEN_CNTL
, data
, size
);
458 if ((val
& CRTC2_CUR_EN
) != (s
->regs
.crtc_gen_cntl
& CRTC2_CUR_EN
)) {
459 if (s
->cursor_guest_mode
) {
460 s
->vga
.force_shadow
= !!(s
->regs
.crtc_gen_cntl
& CRTC2_CUR_EN
);
462 if (s
->regs
.crtc_gen_cntl
& CRTC2_CUR_EN
) {
463 ati_cursor_define(s
);
465 dpy_mouse_set(s
->vga
.con
, s
->regs
.cur_hv_pos
>> 16,
466 s
->regs
.cur_hv_pos
& 0xffff,
467 (s
->regs
.crtc_gen_cntl
& CRTC2_CUR_EN
) != 0);
470 if ((val
& (CRTC2_EXT_DISP_EN
| CRTC2_EN
)) !=
471 (s
->regs
.crtc_gen_cntl
& (CRTC2_EXT_DISP_EN
| CRTC2_EN
))) {
472 ati_vga_switch_mode(s
);
476 case CRTC_EXT_CNTL
... CRTC_EXT_CNTL
+ 3:
478 uint32_t val
= s
->regs
.crtc_ext_cntl
;
479 ati_reg_write_offs(&s
->regs
.crtc_ext_cntl
,
480 addr
- CRTC_EXT_CNTL
, data
, size
);
481 if (s
->regs
.crtc_ext_cntl
& CRT_CRTC_DISPLAY_DIS
) {
482 DPRINTF("Display disabled\n");
483 s
->vga
.ar_index
&= ~BIT(5);
485 DPRINTF("Display enabled\n");
486 s
->vga
.ar_index
|= BIT(5);
487 ati_vga_switch_mode(s
);
489 if ((val
& CRT_CRTC_DISPLAY_DIS
) !=
490 (s
->regs
.crtc_ext_cntl
& CRT_CRTC_DISPLAY_DIS
)) {
491 ati_vga_switch_mode(s
);
496 s
->regs
.dac_cntl
= data
& 0xffffe3ff;
497 s
->vga
.dac_8bit
= !!(data
& DAC_8BIT_EN
);
499 /* case GPIO_MONID: FIXME hook up DDC I2C here */
500 case PALETTE_INDEX
... PALETTE_INDEX
+ 3:
502 vga_ioport_write(&s
->vga
, VGA_PEL_IR
, (data
>> 16) & 0xff);
503 vga_ioport_write(&s
->vga
, VGA_PEL_IW
, data
& 0xff);
505 if (addr
== PALETTE_INDEX
) {
506 vga_ioport_write(&s
->vga
, VGA_PEL_IW
, data
& 0xff);
508 vga_ioport_write(&s
->vga
, VGA_PEL_IR
, data
& 0xff);
512 case PALETTE_DATA
... PALETTE_DATA
+ 3:
513 data
<<= addr
- PALETTE_DATA
;
514 data
= bswap32(data
) >> 8;
515 vga_ioport_write(&s
->vga
, VGA_PEL_D
, data
& 0xff);
517 vga_ioport_write(&s
->vga
, VGA_PEL_D
, data
& 0xff);
519 vga_ioport_write(&s
->vga
, VGA_PEL_D
, data
& 0xff);
521 case CRTC_H_TOTAL_DISP
:
522 s
->regs
.crtc_h_total_disp
= data
& 0x07ff07ff;
524 case CRTC_H_SYNC_STRT_WID
:
525 s
->regs
.crtc_h_sync_strt_wid
= data
& 0x17bf1fff;
527 case CRTC_V_TOTAL_DISP
:
528 s
->regs
.crtc_v_total_disp
= data
& 0x0fff0fff;
530 case CRTC_V_SYNC_STRT_WID
:
531 s
->regs
.crtc_v_sync_strt_wid
= data
& 0x9f0fff;
534 s
->regs
.crtc_offset
= data
& 0xc7ffffff;
536 case CRTC_OFFSET_CNTL
:
537 s
->regs
.crtc_offset_cntl
= data
; /* FIXME */
540 s
->regs
.crtc_pitch
= data
& 0x07ff07ff;
542 case 0xf00 ... 0xfff:
543 /* read-only copy of PCI config space so ignore writes */
546 if (s
->regs
.cur_offset
!= (data
& 0x87fffff0)) {
547 s
->regs
.cur_offset
= data
& 0x87fffff0;
548 ati_cursor_define(s
);
551 case CUR_HORZ_VERT_POSN
:
552 s
->regs
.cur_hv_pos
= data
& 0x3fff0fff;
553 if (data
& BIT(31)) {
554 s
->regs
.cur_offset
|= data
& BIT(31);
555 } else if (s
->regs
.cur_offset
& BIT(31)) {
556 s
->regs
.cur_offset
&= ~BIT(31);
557 ati_cursor_define(s
);
559 if (!s
->cursor_guest_mode
&&
560 (s
->regs
.crtc_gen_cntl
& CRTC2_CUR_EN
) && !(data
& BIT(31))) {
561 dpy_mouse_set(s
->vga
.con
, s
->regs
.cur_hv_pos
>> 16,
562 s
->regs
.cur_hv_pos
& 0xffff, 1);
565 case CUR_HORZ_VERT_OFF
:
566 s
->regs
.cur_hv_offs
= data
& 0x3f003f;
567 if (data
& BIT(31)) {
568 s
->regs
.cur_offset
|= data
& BIT(31);
569 } else if (s
->regs
.cur_offset
& BIT(31)) {
570 s
->regs
.cur_offset
&= ~BIT(31);
571 ati_cursor_define(s
);
575 if (s
->regs
.cur_color0
!= (data
& 0xffffff)) {
576 s
->regs
.cur_color0
= data
& 0xffffff;
577 ati_cursor_define(s
);
582 * Update cursor unconditionally here because some clients set up
583 * other registers before actually writing cursor data to memory at
584 * offset so we would miss cursor change unless always updating here
586 s
->regs
.cur_color1
= data
& 0xffffff;
587 ati_cursor_define(s
);
590 if (s
->dev_id
== PCI_DEVICE_ID_ATI_RAGE128_PF
) {
591 s
->regs
.dst_offset
= data
& 0xfffffff0;
593 s
->regs
.dst_offset
= data
& 0xfffffc00;
597 if (s
->dev_id
== PCI_DEVICE_ID_ATI_RAGE128_PF
) {
598 s
->regs
.dst_pitch
= data
& 0x3fff;
599 s
->regs
.dst_tile
= (data
>> 16) & 1;
601 s
->regs
.dst_pitch
= data
& 0x3ff0;
605 if (s
->dev_id
== PCI_DEVICE_ID_ATI_RADEON_QY
) {
606 s
->regs
.dst_tile
= data
& 3;
610 s
->regs
.dst_width
= data
& 0x3fff;
614 s
->regs
.dst_height
= data
& 0x3fff;
617 s
->regs
.src_x
= data
& 0x3fff;
620 s
->regs
.src_y
= data
& 0x3fff;
623 s
->regs
.dst_x
= data
& 0x3fff;
626 s
->regs
.dst_y
= data
& 0x3fff;
628 case SRC_PITCH_OFFSET
:
629 if (s
->dev_id
== PCI_DEVICE_ID_ATI_RAGE128_PF
) {
630 s
->regs
.src_offset
= (data
& 0x1fffff) << 5;
631 s
->regs
.src_pitch
= (data
>> 21) & 0x3ff;
632 s
->regs
.src_tile
= data
>> 31;
634 s
->regs
.src_offset
= (data
& 0x3fffff) << 11;
635 s
->regs
.src_pitch
= (data
& 0x3fc00000) >> 16;
636 s
->regs
.src_tile
= (data
>> 30) & 1;
639 case DST_PITCH_OFFSET
:
640 if (s
->dev_id
== PCI_DEVICE_ID_ATI_RAGE128_PF
) {
641 s
->regs
.dst_offset
= (data
& 0x1fffff) << 5;
642 s
->regs
.dst_pitch
= (data
>> 21) & 0x3ff;
643 s
->regs
.dst_tile
= data
>> 31;
645 s
->regs
.dst_offset
= (data
& 0x3fffff) << 11;
646 s
->regs
.dst_pitch
= (data
& 0x3fc00000) >> 16;
647 s
->regs
.dst_tile
= data
>> 30;
651 s
->regs
.src_x
= data
& 0x3fff;
652 s
->regs
.src_y
= (data
>> 16) & 0x3fff;
655 s
->regs
.dst_x
= data
& 0x3fff;
656 s
->regs
.dst_y
= (data
>> 16) & 0x3fff;
658 case DST_HEIGHT_WIDTH
:
659 s
->regs
.dst_width
= data
& 0x3fff;
660 s
->regs
.dst_height
= (data
>> 16) & 0x3fff;
663 case DP_GUI_MASTER_CNTL
:
664 s
->regs
.dp_gui_master_cntl
= data
& 0xf800000f;
665 s
->regs
.dp_datatype
= (data
& 0x0f00) >> 8 | (data
& 0x30f0) << 4 |
666 (data
& 0x4000) << 16;
667 s
->regs
.dp_mix
= (data
& GMC_ROP3_MASK
) | (data
& 0x7000000) >> 16;
670 s
->regs
.dst_x
= data
& 0x3fff;
671 s
->regs
.dst_width
= (data
>> 16) & 0x3fff;
675 s
->regs
.src_y
= data
& 0x3fff;
676 s
->regs
.src_x
= (data
>> 16) & 0x3fff;
679 s
->regs
.dst_y
= data
& 0x3fff;
680 s
->regs
.dst_x
= (data
>> 16) & 0x3fff;
682 case DST_WIDTH_HEIGHT
:
683 s
->regs
.dst_height
= data
& 0x3fff;
684 s
->regs
.dst_width
= (data
>> 16) & 0x3fff;
688 s
->regs
.dst_y
= data
& 0x3fff;
689 s
->regs
.dst_height
= (data
>> 16) & 0x3fff;
692 if (s
->dev_id
== PCI_DEVICE_ID_ATI_RAGE128_PF
) {
693 s
->regs
.src_offset
= data
& 0xfffffff0;
695 s
->regs
.src_offset
= data
& 0xfffffc00;
699 if (s
->dev_id
== PCI_DEVICE_ID_ATI_RAGE128_PF
) {
700 s
->regs
.src_pitch
= data
& 0x3fff;
701 s
->regs
.src_tile
= (data
>> 16) & 1;
703 s
->regs
.src_pitch
= data
& 0x3ff0;
706 case DP_BRUSH_BKGD_CLR
:
707 s
->regs
.dp_brush_bkgd_clr
= data
;
709 case DP_BRUSH_FRGD_CLR
:
710 s
->regs
.dp_brush_frgd_clr
= data
;
713 s
->regs
.dp_cntl
= data
;
716 s
->regs
.dp_datatype
= data
& 0xe0070f0f;
719 s
->regs
.dp_mix
= data
& 0x00ff0700;
722 s
->regs
.dp_write_mask
= data
;
725 data
&= (s
->dev_id
== PCI_DEVICE_ID_ATI_RAGE128_PF
?
726 0x03fffc00 : 0xfffffc00);
727 s
->regs
.default_offset
= data
;
730 if (s
->dev_id
== PCI_DEVICE_ID_ATI_RAGE128_PF
) {
731 s
->regs
.default_pitch
= data
& 0x103ff;
734 case DEFAULT_SC_BOTTOM_RIGHT
:
735 s
->regs
.default_sc_bottom_right
= data
& 0x3fff3fff;
742 static const MemoryRegionOps ati_mm_ops
= {
744 .write
= ati_mm_write
,
745 .endianness
= DEVICE_LITTLE_ENDIAN
,
748 static void ati_vga_realize(PCIDevice
*dev
, Error
**errp
)
750 ATIVGAState
*s
= ATI_VGA(dev
);
751 VGACommonState
*vga
= &s
->vga
;
755 for (i
= 0; i
< ARRAY_SIZE(ati_model_aliases
); i
++) {
756 if (!strcmp(s
->model
, ati_model_aliases
[i
].name
)) {
757 s
->dev_id
= ati_model_aliases
[i
].dev_id
;
761 if (i
>= ARRAY_SIZE(ati_model_aliases
)) {
762 warn_report("Unknown ATI VGA model name, "
763 "using default rage128p");
766 if (s
->dev_id
!= PCI_DEVICE_ID_ATI_RAGE128_PF
&&
767 s
->dev_id
!= PCI_DEVICE_ID_ATI_RADEON_QY
) {
768 error_setg(errp
, "Unknown ATI VGA device id, "
769 "only 0x5046 and 0x5159 are supported");
772 pci_set_word(dev
->config
+ PCI_DEVICE_ID
, s
->dev_id
);
774 if (s
->dev_id
== PCI_DEVICE_ID_ATI_RADEON_QY
&&
775 s
->vga
.vram_size_mb
< 16) {
776 warn_report("Too small video memory for device id");
777 s
->vga
.vram_size_mb
= 16;
781 vga_common_init(vga
, OBJECT(s
));
782 vga_init(vga
, OBJECT(s
), pci_address_space(dev
),
783 pci_address_space_io(dev
), true);
784 vga
->con
= graphic_console_init(DEVICE(s
), 0, s
->vga
.hw_ops
, &s
->vga
);
785 if (s
->cursor_guest_mode
) {
786 vga
->cursor_invalidate
= ati_cursor_invalidate
;
787 vga
->cursor_draw_line
= ati_cursor_draw_line
;
790 /* mmio register space */
791 memory_region_init_io(&s
->mm
, OBJECT(s
), &ati_mm_ops
, s
,
792 "ati.mmregs", 0x4000);
793 /* io space is alias to beginning of mmregs */
794 memory_region_init_alias(&s
->io
, OBJECT(s
), "ati.io", &s
->mm
, 0, 0x100);
796 pci_register_bar(dev
, 0, PCI_BASE_ADDRESS_MEM_PREFETCH
, &vga
->vram
);
797 pci_register_bar(dev
, 1, PCI_BASE_ADDRESS_SPACE_IO
, &s
->io
);
798 pci_register_bar(dev
, 2, PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->mm
);
801 static void ati_vga_reset(DeviceState
*dev
)
803 ATIVGAState
*s
= ATI_VGA(dev
);
806 vga_common_reset(&s
->vga
);
810 static void ati_vga_exit(PCIDevice
*dev
)
812 ATIVGAState
*s
= ATI_VGA(dev
);
814 graphic_console_close(s
->vga
.con
);
817 static Property ati_vga_properties
[] = {
818 DEFINE_PROP_UINT32("vgamem_mb", ATIVGAState
, vga
.vram_size_mb
, 16),
819 DEFINE_PROP_STRING("model", ATIVGAState
, model
),
820 DEFINE_PROP_UINT16("x-device-id", ATIVGAState
, dev_id
,
821 PCI_DEVICE_ID_ATI_RAGE128_PF
),
822 DEFINE_PROP_BOOL("guest_hwcursor", ATIVGAState
, cursor_guest_mode
, false),
823 DEFINE_PROP_END_OF_LIST()
826 static void ati_vga_class_init(ObjectClass
*klass
, void *data
)
828 DeviceClass
*dc
= DEVICE_CLASS(klass
);
829 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
831 dc
->reset
= ati_vga_reset
;
832 dc
->props
= ati_vga_properties
;
833 dc
->hotpluggable
= false;
834 set_bit(DEVICE_CATEGORY_DISPLAY
, dc
->categories
);
836 k
->class_id
= PCI_CLASS_DISPLAY_VGA
;
837 k
->vendor_id
= PCI_VENDOR_ID_ATI
;
838 k
->device_id
= PCI_DEVICE_ID_ATI_RAGE128_PF
;
839 k
->romfile
= "vgabios-stdvga.bin";
840 k
->realize
= ati_vga_realize
;
841 k
->exit
= ati_vga_exit
;
844 static const TypeInfo ati_vga_info
= {
845 .name
= TYPE_ATI_VGA
,
846 .parent
= TYPE_PCI_DEVICE
,
847 .instance_size
= sizeof(ATIVGAState
),
848 .class_init
= ati_vga_class_init
,
849 .interfaces
= (InterfaceInfo
[]) {
850 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
855 static void ati_vga_register_types(void)
857 type_register_static(&ati_vga_info
);
860 type_init(ati_vga_register_types
)