target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18
  19 #include <linux/kvm.h>
  20
  21 #include "qemu-common.h"
  22 #include "sysemu.h"
  23 #include "kvm.h"
  24 #include "cpu.h"
  25 #include "gdbstub.h"
  26 #include "host-utils.h"
  27 #include "hw/pc.h"
  28 #include "hw/apic.h"
  29 #include "ioport.h"
  30 #include "kvm_x86.h"
  31
  32 #ifdef CONFIG_KVM_PARA
  33 #include <linux/kvm_para.h>
  34 #endif
  35 //
  36 //#define DEBUG_KVM
  37
  38 #ifdef DEBUG_KVM
  39 #define DPRINTF(fmt, ...) \
  40     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  41 #else
  42 #define DPRINTF(fmt, ...) \
  43     do { } while (0)
  44 #endif
  45
  46 #define MSR_KVM_WALL_CLOCK  0x11
  47 #define MSR_KVM_SYSTEM_TIME 0x12
  48
  49 #ifndef BUS_MCEERR_AR
  50 #define BUS_MCEERR_AR 4
  51 #endif
  52 #ifndef BUS_MCEERR_AO
  53 #define BUS_MCEERR_AO 5
  54 #endif
  55
  56 #ifdef KVM_CAP_EXT_CPUID
  57
  58 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  59 {
  60     struct kvm_cpuid2 *cpuid;
  61     int r, size;
  62
  63     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  64     cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
  65     cpuid->nent = max;
  66     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  67     if (r == 0 && cpuid->nent >= max) {
  68         r = -E2BIG;
  69     }
  70     if (r < 0) {
  71         if (r == -E2BIG) {
  72             qemu_free(cpuid);
  73             return NULL;
  74         } else {
  75             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  76                     strerror(-r));
  77             exit(1);
  78         }
  79     }
  80     return cpuid;
  81 }
  82
  83 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
  84                                       uint32_t index, int reg)
  85 {
  86     struct kvm_cpuid2 *cpuid;
  87     int i, max;
  88     uint32_t ret = 0;
  89     uint32_t cpuid_1_edx;
  90
  91     if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
  92         return -1U;
  93     }
  94
  95     max = 1;
  96     while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
  97         max *= 2;
  98     }
  99
 100     for (i = 0; i < cpuid->nent; ++i) {
 101         if (cpuid->entries[i].function == function &&
 102             cpuid->entries[i].index == index) {
 103             switch (reg) {
 104             case R_EAX:
 105                 ret = cpuid->entries[i].eax;
 106                 break;
 107             case R_EBX:
 108                 ret = cpuid->entries[i].ebx;
 109                 break;
 110             case R_ECX:
 111                 ret = cpuid->entries[i].ecx;
 112                 break;
 113             case R_EDX:
 114                 ret = cpuid->entries[i].edx;
 115                 switch (function) {
 116                 case 1:
 117                     /* KVM before 2.6.30 misreports the following features */
 118                     ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 119                     break;
 120                 case 0x80000001:
 121                     /* On Intel, kvm returns cpuid according to the Intel spec,
 122                      * so add missing bits according to the AMD spec:
 123                      */
 124                     cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
 125                     ret |= cpuid_1_edx & 0x183f7ff;
 126                     break;
 127                 }
 128                 break;
 129             }
 130         }
 131     }
 132
 133     qemu_free(cpuid);
 134
 135     return ret;
 136 }
 137
 138 #else
 139
 140 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
 141                                       uint32_t index, int reg)
 142 {
 143     return -1U;
 144 }
 145
 146 #endif
 147
 148 #ifdef CONFIG_KVM_PARA
 149 struct kvm_para_features {
 150         int cap;
 151         int feature;
 152 } para_features[] = {
 153 #ifdef KVM_CAP_CLOCKSOURCE
 154         { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 155 #endif
 156 #ifdef KVM_CAP_NOP_IO_DELAY
 157         { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 158 #endif
 159 #ifdef KVM_CAP_PV_MMU
 160         { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 161 #endif
 162         { -1, -1 }
 163 };
 164
 165 static int get_para_features(CPUState *env)
 166 {
 167         int i, features = 0;
 168
 169         for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 170                 if (kvm_check_extension(env->kvm_state, para_features[i].cap))
 171                         features |= (1 << para_features[i].feature);
 172         }
 173
 174         return features;
 175 }
 176 #endif
 177
 178 #ifdef KVM_CAP_MCE
 179 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
 180                                      int *max_banks)
 181 {
 182     int r;
 183
 184     r = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_MCE);
 185     if (r > 0) {
 186         *max_banks = r;
 187         return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
 188     }
 189     return -ENOSYS;
 190 }
 191
 192 static int kvm_setup_mce(CPUState *env, uint64_t *mcg_cap)
 193 {
 194     return kvm_vcpu_ioctl(env, KVM_X86_SETUP_MCE, mcg_cap);
 195 }
 196
 197 static int kvm_set_mce(CPUState *env, struct kvm_x86_mce *m)
 198 {
 199     return kvm_vcpu_ioctl(env, KVM_X86_SET_MCE, m);
 200 }
 201
 202 static int kvm_get_msr(CPUState *env, struct kvm_msr_entry *msrs, int n)
 203 {
 204     struct kvm_msrs *kmsrs = qemu_malloc(sizeof *kmsrs + n * sizeof *msrs);
 205     int r;
 206
 207     kmsrs->nmsrs = n;
 208     memcpy(kmsrs->entries, msrs, n * sizeof *msrs);
 209     r = kvm_vcpu_ioctl(env, KVM_GET_MSRS, kmsrs);
 210     memcpy(msrs, kmsrs->entries, n * sizeof *msrs);
 211     free(kmsrs);
 212     return r;
 213 }
 214
 215 /* FIXME: kill this and kvm_get_msr, use env->mcg_status instead */
 216 static int kvm_mce_in_exception(CPUState *env)
 217 {
 218     struct kvm_msr_entry msr_mcg_status = {
 219         .index = MSR_MCG_STATUS,
 220     };
 221     int r;
 222
 223     r = kvm_get_msr(env, &msr_mcg_status, 1);
 224     if (r == -1 || r == 0) {
 225         return -1;
 226     }
 227     return !!(msr_mcg_status.data & MCG_STATUS_MCIP);
 228 }
 229
 230 struct kvm_x86_mce_data
 231 {
 232     CPUState *env;
 233     struct kvm_x86_mce *mce;
 234     int abort_on_error;
 235 };
 236
 237 static void kvm_do_inject_x86_mce(void *_data)
 238 {
 239     struct kvm_x86_mce_data *data = _data;
 240     int r;
 241
 242     /* If there is an MCE exception being processed, ignore this SRAO MCE */
 243     if ((data->env->mcg_cap & MCG_SER_P) &&
 244         !(data->mce->status & MCI_STATUS_AR)) {
 245         r = kvm_mce_in_exception(data->env);
 246         if (r == -1) {
 247             fprintf(stderr, "Failed to get MCE status\n");
 248         } else if (r) {
 249             return;
 250         }
 251     }
 252
 253     r = kvm_set_mce(data->env, data->mce);
 254     if (r < 0) {
 255         perror("kvm_set_mce FAILED");
 256         if (data->abort_on_error) {
 257             abort();
 258         }
 259     }
 260 }
 261 #endif
 262
 263 void kvm_inject_x86_mce(CPUState *cenv, int bank, uint64_t status,
 264                         uint64_t mcg_status, uint64_t addr, uint64_t misc,
 265                         int abort_on_error)
 266 {
 267 #ifdef KVM_CAP_MCE
 268     struct kvm_x86_mce mce = {
 269         .bank = bank,
 270         .status = status,
 271         .mcg_status = mcg_status,
 272         .addr = addr,
 273         .misc = misc,
 274     };
 275     struct kvm_x86_mce_data data = {
 276             .env = cenv,
 277             .mce = &mce,
 278     };
 279
 280     if (!cenv->mcg_cap) {
 281         fprintf(stderr, "MCE support is not enabled!\n");
 282         return;
 283     }
 284
 285     run_on_cpu(cenv, kvm_do_inject_x86_mce, &data);
 286 #else
 287     if (abort_on_error)
 288         abort();
 289 #endif
 290 }
 291
 292 int kvm_arch_init_vcpu(CPUState *env)
 293 {
 294     struct {
 295         struct kvm_cpuid2 cpuid;
 296         struct kvm_cpuid_entry2 entries[100];
 297     } __attribute__((packed)) cpuid_data;
 298     uint32_t limit, i, j, cpuid_i;
 299     uint32_t unused;
 300     struct kvm_cpuid_entry2 *c;
 301 #ifdef KVM_CPUID_SIGNATURE
 302     uint32_t signature[3];
 303 #endif
 304
 305     env->mp_state = KVM_MP_STATE_RUNNABLE;
 306
 307     env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
 308
 309     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 310     env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX);
 311     env->cpuid_ext_features |= i;
 312
 313     env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 314                                                              0, R_EDX);
 315     env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 316                                                              0, R_ECX);
 317     env->cpuid_svm_features  &= kvm_arch_get_supported_cpuid(env, 0x8000000A,
 318                                                              0, R_EDX);
 319
 320
 321     cpuid_i = 0;
 322
 323 #ifdef CONFIG_KVM_PARA
 324     /* Paravirtualization CPUIDs */
 325     memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 326     c = &cpuid_data.entries[cpuid_i++];
 327     memset(c, 0, sizeof(*c));
 328     c->function = KVM_CPUID_SIGNATURE;
 329     c->eax = 0;
 330     c->ebx = signature[0];
 331     c->ecx = signature[1];
 332     c->edx = signature[2];
 333
 334     c = &cpuid_data.entries[cpuid_i++];
 335     memset(c, 0, sizeof(*c));
 336     c->function = KVM_CPUID_FEATURES;
 337     c->eax = env->cpuid_kvm_features & get_para_features(env);
 338 #endif
 339
 340     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 341
 342     for (i = 0; i <= limit; i++) {
 343         c = &cpuid_data.entries[cpuid_i++];
 344
 345         switch (i) {
 346         case 2: {
 347             /* Keep reading function 2 till all the input is received */
 348             int times;
 349
 350             c->function = i;
 351             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 352                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 353             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 354             times = c->eax & 0xff;
 355
 356             for (j = 1; j < times; ++j) {
 357                 c = &cpuid_data.entries[cpuid_i++];
 358                 c->function = i;
 359                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 360                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 361             }
 362             break;
 363         }
 364         case 4:
 365         case 0xb:
 366         case 0xd:
 367             for (j = 0; ; j++) {
 368                 c->function = i;
 369                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 370                 c->index = j;
 371                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 372
 373                 if (i == 4 && c->eax == 0)
 374                     break;
 375                 if (i == 0xb && !(c->ecx & 0xff00))
 376                     break;
 377                 if (i == 0xd && c->eax == 0)
 378                     break;
 379
 380                 c = &cpuid_data.entries[cpuid_i++];
 381             }
 382             break;
 383         default:
 384             c->function = i;
 385             c->flags = 0;
 386             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 387             break;
 388         }
 389     }
 390     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 391
 392     for (i = 0x80000000; i <= limit; i++) {
 393         c = &cpuid_data.entries[cpuid_i++];
 394
 395         c->function = i;
 396         c->flags = 0;
 397         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 398     }
 399
 400     cpuid_data.cpuid.nent = cpuid_i;
 401
 402 #ifdef KVM_CAP_MCE
 403     if (((env->cpuid_version >> 8)&0xF) >= 6
 404         && (env->cpuid_features&(CPUID_MCE|CPUID_MCA)) == (CPUID_MCE|CPUID_MCA)
 405         && kvm_check_extension(env->kvm_state, KVM_CAP_MCE) > 0) {
 406         uint64_t mcg_cap;
 407         int banks;
 408
 409         if (kvm_get_mce_cap_supported(env->kvm_state, &mcg_cap, &banks))
 410             perror("kvm_get_mce_cap_supported FAILED");
 411         else {
 412             if (banks > MCE_BANKS_DEF)
 413                 banks = MCE_BANKS_DEF;
 414             mcg_cap &= MCE_CAP_DEF;
 415             mcg_cap |= banks;
 416             if (kvm_setup_mce(env, &mcg_cap))
 417                 perror("kvm_setup_mce FAILED");
 418             else
 419                 env->mcg_cap = mcg_cap;
 420         }
 421     }
 422 #endif
 423
 424     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 425 }
 426
 427 void kvm_arch_reset_vcpu(CPUState *env)
 428 {
 429     env->exception_injected = -1;
 430     env->interrupt_injected = -1;
 431     env->nmi_injected = 0;
 432     env->nmi_pending = 0;
 433     if (kvm_irqchip_in_kernel()) {
 434         env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE :
 435                                           KVM_MP_STATE_UNINITIALIZED;
 436     } else {
 437         env->mp_state = KVM_MP_STATE_RUNNABLE;
 438     }
 439 }
 440
 441 int has_msr_star;
 442 int has_msr_hsave_pa;
 443
 444 static void kvm_supported_msrs(CPUState *env)
 445 {
 446     static int kvm_supported_msrs;
 447     int ret;
 448
 449     /* first time */
 450     if (kvm_supported_msrs == 0) {
 451         struct kvm_msr_list msr_list, *kvm_msr_list;
 452
 453         kvm_supported_msrs = -1;
 454
 455         /* Obtain MSR list from KVM.  These are the MSRs that we must
 456          * save/restore */
 457         msr_list.nmsrs = 0;
 458         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
 459         if (ret < 0 && ret != -E2BIG) {
 460             return;
 461         }
 462         /* Old kernel modules had a bug and could write beyond the provided
 463            memory. Allocate at least a safe amount of 1K. */
 464         kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
 465                                               msr_list.nmsrs *
 466                                               sizeof(msr_list.indices[0])));
 467
 468         kvm_msr_list->nmsrs = msr_list.nmsrs;
 469         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 470         if (ret >= 0) {
 471             int i;
 472
 473             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 474                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 475                     has_msr_star = 1;
 476                     continue;
 477                 }
 478                 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
 479                     has_msr_hsave_pa = 1;
 480                     continue;
 481                 }
 482             }
 483         }
 484
 485         free(kvm_msr_list);
 486     }
 487
 488     return;
 489 }
 490
 491 static int kvm_has_msr_hsave_pa(CPUState *env)
 492 {
 493     kvm_supported_msrs(env);
 494     return has_msr_hsave_pa;
 495 }
 496
 497 static int kvm_has_msr_star(CPUState *env)
 498 {
 499     kvm_supported_msrs(env);
 500     return has_msr_star;
 501 }
 502
 503 static int kvm_init_identity_map_page(KVMState *s)
 504 {
 505 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
 506     int ret;
 507     uint64_t addr = 0xfffbc000;
 508
 509     if (!kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 510         return 0;
 511     }
 512
 513     ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &addr);
 514     if (ret < 0) {
 515         fprintf(stderr, "kvm_set_identity_map_addr: %s\n", strerror(ret));
 516         return ret;
 517     }
 518 #endif
 519     return 0;
 520 }
 521
 522 int kvm_arch_init(KVMState *s, int smp_cpus)
 523 {
 524     int ret;
 525
 526     /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
 527      * directly.  In order to use vm86 mode, a TSS is needed.  Since this
 528      * must be part of guest physical memory, we need to allocate it.  Older
 529      * versions of KVM just assumed that it would be at the end of physical
 530      * memory but that doesn't work with more than 4GB of memory.  We simply
 531      * refuse to work with those older versions of KVM. */
 532     ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
 533     if (ret <= 0) {
 534         fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
 535         return ret;
 536     }
 537
 538     /* this address is 3 pages before the bios, and the bios should present
 539      * as unavaible memory.  FIXME, need to ensure the e820 map deals with
 540      * this?
 541      */
 542     /*
 543      * Tell fw_cfg to notify the BIOS to reserve the range.
 544      */
 545     if (e820_add_entry(0xfffbc000, 0x4000, E820_RESERVED) < 0) {
 546         perror("e820_add_entry() table is full");
 547         exit(1);
 548     }
 549     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
 550     if (ret < 0) {
 551         return ret;
 552     }
 553
 554     return kvm_init_identity_map_page(s);
 555 }
 556
 557 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 558 {
 559     lhs->selector = rhs->selector;
 560     lhs->base = rhs->base;
 561     lhs->limit = rhs->limit;
 562     lhs->type = 3;
 563     lhs->present = 1;
 564     lhs->dpl = 3;
 565     lhs->db = 0;
 566     lhs->s = 1;
 567     lhs->l = 0;
 568     lhs->g = 0;
 569     lhs->avl = 0;
 570     lhs->unusable = 0;
 571 }
 572
 573 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 574 {
 575     unsigned flags = rhs->flags;
 576     lhs->selector = rhs->selector;
 577     lhs->base = rhs->base;
 578     lhs->limit = rhs->limit;
 579     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 580     lhs->present = (flags & DESC_P_MASK) != 0;
 581     lhs->dpl = rhs->selector & 3;
 582     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 583     lhs->s = (flags & DESC_S_MASK) != 0;
 584     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 585     lhs->g = (flags & DESC_G_MASK) != 0;
 586     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 587     lhs->unusable = 0;
 588 }
 589
 590 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 591 {
 592     lhs->selector = rhs->selector;
 593     lhs->base = rhs->base;
 594     lhs->limit = rhs->limit;
 595     lhs->flags =
 596         (rhs->type << DESC_TYPE_SHIFT)
 597         | (rhs->present * DESC_P_MASK)
 598         | (rhs->dpl << DESC_DPL_SHIFT)
 599         | (rhs->db << DESC_B_SHIFT)
 600         | (rhs->s * DESC_S_MASK)
 601         | (rhs->l << DESC_L_SHIFT)
 602         | (rhs->g * DESC_G_MASK)
 603         | (rhs->avl * DESC_AVL_MASK);
 604 }
 605
 606 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 607 {
 608     if (set)
 609         *kvm_reg = *qemu_reg;
 610     else
 611         *qemu_reg = *kvm_reg;
 612 }
 613
 614 static int kvm_getput_regs(CPUState *env, int set)
 615 {
 616     struct kvm_regs regs;
 617     int ret = 0;
 618
 619     if (!set) {
 620         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 621         if (ret < 0)
 622             return ret;
 623     }
 624
 625     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 626     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 627     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 628     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 629     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 630     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 631     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 632     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 633 #ifdef TARGET_X86_64
 634     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 635     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 636     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 637     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 638     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 639     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 640     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 641     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 642 #endif
 643
 644     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 645     kvm_getput_reg(&regs.rip, &env->eip, set);
 646
 647     if (set)
 648         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 649
 650     return ret;
 651 }
 652
 653 static int kvm_put_fpu(CPUState *env)
 654 {
 655     struct kvm_fpu fpu;
 656     int i;
 657
 658     memset(&fpu, 0, sizeof fpu);
 659     fpu.fsw = env->fpus & ~(7 << 11);
 660     fpu.fsw |= (env->fpstt & 7) << 11;
 661     fpu.fcw = env->fpuc;
 662     for (i = 0; i < 8; ++i)
 663         fpu.ftwx |= (!env->fptags[i]) << i;
 664     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 665     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 666     fpu.mxcsr = env->mxcsr;
 667
 668     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 669 }
 670
 671 #ifdef KVM_CAP_XSAVE
 672 #define XSAVE_CWD_RIP     2
 673 #define XSAVE_CWD_RDP     4
 674 #define XSAVE_MXCSR       6
 675 #define XSAVE_ST_SPACE    8
 676 #define XSAVE_XMM_SPACE   40
 677 #define XSAVE_XSTATE_BV   128
 678 #define XSAVE_YMMH_SPACE  144
 679 #endif
 680
 681 static int kvm_put_xsave(CPUState *env)
 682 {
 683 #ifdef KVM_CAP_XSAVE
 684     int i, r;
 685     struct kvm_xsave* xsave;
 686     uint16_t cwd, swd, twd, fop;
 687
 688     if (!kvm_has_xsave())
 689         return kvm_put_fpu(env);
 690
 691     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 692     memset(xsave, 0, sizeof(struct kvm_xsave));
 693     cwd = swd = twd = fop = 0;
 694     swd = env->fpus & ~(7 << 11);
 695     swd |= (env->fpstt & 7) << 11;
 696     cwd = env->fpuc;
 697     for (i = 0; i < 8; ++i)
 698         twd |= (!env->fptags[i]) << i;
 699     xsave->region[0] = (uint32_t)(swd << 16) + cwd;
 700     xsave->region[1] = (uint32_t)(fop << 16) + twd;
 701     memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
 702             sizeof env->fpregs);
 703     memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
 704             sizeof env->xmm_regs);
 705     xsave->region[XSAVE_MXCSR] = env->mxcsr;
 706     *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
 707     memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
 708             sizeof env->ymmh_regs);
 709     r = kvm_vcpu_ioctl(env, KVM_SET_XSAVE, xsave);
 710     qemu_free(xsave);
 711     return r;
 712 #else
 713     return kvm_put_fpu(env);
 714 #endif
 715 }
 716
 717 static int kvm_put_xcrs(CPUState *env)
 718 {
 719 #ifdef KVM_CAP_XCRS
 720     struct kvm_xcrs xcrs;
 721
 722     if (!kvm_has_xcrs())
 723         return 0;
 724
 725     xcrs.nr_xcrs = 1;
 726     xcrs.flags = 0;
 727     xcrs.xcrs[0].xcr = 0;
 728     xcrs.xcrs[0].value = env->xcr0;
 729     return kvm_vcpu_ioctl(env, KVM_SET_XCRS, &xcrs);
 730 #else
 731     return 0;
 732 #endif
 733 }
 734
 735 static int kvm_put_sregs(CPUState *env)
 736 {
 737     struct kvm_sregs sregs;
 738
 739     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 740     if (env->interrupt_injected >= 0) {
 741         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 742                 (uint64_t)1 << (env->interrupt_injected % 64);
 743     }
 744
 745     if ((env->eflags & VM_MASK)) {
 746             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 747             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 748             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 749             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 750             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 751             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 752     } else {
 753             set_seg(&sregs.cs, &env->segs[R_CS]);
 754             set_seg(&sregs.ds, &env->segs[R_DS]);
 755             set_seg(&sregs.es, &env->segs[R_ES]);
 756             set_seg(&sregs.fs, &env->segs[R_FS]);
 757             set_seg(&sregs.gs, &env->segs[R_GS]);
 758             set_seg(&sregs.ss, &env->segs[R_SS]);
 759
 760             if (env->cr[0] & CR0_PE_MASK) {
 761                 /* force ss cpl to cs cpl */
 762                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 763                         (sregs.cs.selector & 3);
 764                 sregs.ss.dpl = sregs.ss.selector & 3;
 765             }
 766     }
 767
 768     set_seg(&sregs.tr, &env->tr);
 769     set_seg(&sregs.ldt, &env->ldt);
 770
 771     sregs.idt.limit = env->idt.limit;
 772     sregs.idt.base = env->idt.base;
 773     sregs.gdt.limit = env->gdt.limit;
 774     sregs.gdt.base = env->gdt.base;
 775
 776     sregs.cr0 = env->cr[0];
 777     sregs.cr2 = env->cr[2];
 778     sregs.cr3 = env->cr[3];
 779     sregs.cr4 = env->cr[4];
 780
 781     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
 782     sregs.apic_base = cpu_get_apic_base(env->apic_state);
 783
 784     sregs.efer = env->efer;
 785
 786     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 787 }
 788
 789 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 790                               uint32_t index, uint64_t value)
 791 {
 792     entry->index = index;
 793     entry->data = value;
 794 }
 795
 796 static int kvm_put_msrs(CPUState *env, int level)
 797 {
 798     struct {
 799         struct kvm_msrs info;
 800         struct kvm_msr_entry entries[100];
 801     } msr_data;
 802     struct kvm_msr_entry *msrs = msr_data.entries;
 803     int n = 0;
 804
 805     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 806     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 807     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 808     if (kvm_has_msr_star(env))
 809         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 810     if (kvm_has_msr_hsave_pa(env))
 811         kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 812 #ifdef TARGET_X86_64
 813     /* FIXME if lm capable */
 814     kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 815     kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 816     kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 817     kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 818 #endif
 819     if (level == KVM_PUT_FULL_STATE) {
 820         kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 821         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
 822                           env->system_time_msr);
 823         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
 824     }
 825 #ifdef KVM_CAP_MCE
 826     if (env->mcg_cap) {
 827         int i;
 828         if (level == KVM_PUT_RESET_STATE)
 829             kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
 830         else if (level == KVM_PUT_FULL_STATE) {
 831             kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
 832             kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
 833             for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++)
 834                 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
 835         }
 836     }
 837 #endif
 838
 839     msr_data.info.nmsrs = n;
 840
 841     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 842
 843 }
 844
 845
 846 static int kvm_get_fpu(CPUState *env)
 847 {
 848     struct kvm_fpu fpu;
 849     int i, ret;
 850
 851     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 852     if (ret < 0)
 853         return ret;
 854
 855     env->fpstt = (fpu.fsw >> 11) & 7;
 856     env->fpus = fpu.fsw;
 857     env->fpuc = fpu.fcw;
 858     for (i = 0; i < 8; ++i)
 859         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 860     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 861     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 862     env->mxcsr = fpu.mxcsr;
 863
 864     return 0;
 865 }
 866
 867 static int kvm_get_xsave(CPUState *env)
 868 {
 869 #ifdef KVM_CAP_XSAVE
 870     struct kvm_xsave* xsave;
 871     int ret, i;
 872     uint16_t cwd, swd, twd, fop;
 873
 874     if (!kvm_has_xsave())
 875         return kvm_get_fpu(env);
 876
 877     xsave = qemu_memalign(4096, sizeof(struct kvm_xsave));
 878     ret = kvm_vcpu_ioctl(env, KVM_GET_XSAVE, xsave);
 879     if (ret < 0) {
 880         qemu_free(xsave);
 881         return ret;
 882     }
 883
 884     cwd = (uint16_t)xsave->region[0];
 885     swd = (uint16_t)(xsave->region[0] >> 16);
 886     twd = (uint16_t)xsave->region[1];
 887     fop = (uint16_t)(xsave->region[1] >> 16);
 888     env->fpstt = (swd >> 11) & 7;
 889     env->fpus = swd;
 890     env->fpuc = cwd;
 891     for (i = 0; i < 8; ++i)
 892         env->fptags[i] = !((twd >> i) & 1);
 893     env->mxcsr = xsave->region[XSAVE_MXCSR];
 894     memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
 895             sizeof env->fpregs);
 896     memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
 897             sizeof env->xmm_regs);
 898     env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
 899     memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
 900             sizeof env->ymmh_regs);
 901     qemu_free(xsave);
 902     return 0;
 903 #else
 904     return kvm_get_fpu(env);
 905 #endif
 906 }
 907
 908 static int kvm_get_xcrs(CPUState *env)
 909 {
 910 #ifdef KVM_CAP_XCRS
 911     int i, ret;
 912     struct kvm_xcrs xcrs;
 913
 914     if (!kvm_has_xcrs())
 915         return 0;
 916
 917     ret = kvm_vcpu_ioctl(env, KVM_GET_XCRS, &xcrs);
 918     if (ret < 0)
 919         return ret;
 920
 921     for (i = 0; i < xcrs.nr_xcrs; i++)
 922         /* Only support xcr0 now */
 923         if (xcrs.xcrs[0].xcr == 0) {
 924             env->xcr0 = xcrs.xcrs[0].value;
 925             break;
 926         }
 927     return 0;
 928 #else
 929     return 0;
 930 #endif
 931 }
 932
 933 static int kvm_get_sregs(CPUState *env)
 934 {
 935     struct kvm_sregs sregs;
 936     uint32_t hflags;
 937     int bit, i, ret;
 938
 939     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 940     if (ret < 0)
 941         return ret;
 942
 943     /* There can only be one pending IRQ set in the bitmap at a time, so try
 944        to find it and save its number instead (-1 for none). */
 945     env->interrupt_injected = -1;
 946     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
 947         if (sregs.interrupt_bitmap[i]) {
 948             bit = ctz64(sregs.interrupt_bitmap[i]);
 949             env->interrupt_injected = i * 64 + bit;
 950             break;
 951         }
 952     }
 953
 954     get_seg(&env->segs[R_CS], &sregs.cs);
 955     get_seg(&env->segs[R_DS], &sregs.ds);
 956     get_seg(&env->segs[R_ES], &sregs.es);
 957     get_seg(&env->segs[R_FS], &sregs.fs);
 958     get_seg(&env->segs[R_GS], &sregs.gs);
 959     get_seg(&env->segs[R_SS], &sregs.ss);
 960
 961     get_seg(&env->tr, &sregs.tr);
 962     get_seg(&env->ldt, &sregs.ldt);
 963
 964     env->idt.limit = sregs.idt.limit;
 965     env->idt.base = sregs.idt.base;
 966     env->gdt.limit = sregs.gdt.limit;
 967     env->gdt.base = sregs.gdt.base;
 968
 969     env->cr[0] = sregs.cr0;
 970     env->cr[2] = sregs.cr2;
 971     env->cr[3] = sregs.cr3;
 972     env->cr[4] = sregs.cr4;
 973
 974     cpu_set_apic_base(env->apic_state, sregs.apic_base);
 975
 976     env->efer = sregs.efer;
 977     //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
 978
 979 #define HFLAG_COPY_MASK ~( \
 980                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 981                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 982                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 983                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 984
 985
 986
 987     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 988     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 989     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 990             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 991     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 992     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 993             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 994
 995     if (env->efer & MSR_EFER_LMA) {
 996         hflags |= HF_LMA_MASK;
 997     }
 998
 999     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1000         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1001     } else {
1002         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1003                 (DESC_B_SHIFT - HF_CS32_SHIFT);
1004         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1005                 (DESC_B_SHIFT - HF_SS32_SHIFT);
1006         if (!(env->cr[0] & CR0_PE_MASK) ||
1007                    (env->eflags & VM_MASK) ||
1008                    !(hflags & HF_CS32_MASK)) {
1009                 hflags |= HF_ADDSEG_MASK;
1010             } else {
1011                 hflags |= ((env->segs[R_DS].base |
1012                                 env->segs[R_ES].base |
1013                                 env->segs[R_SS].base) != 0) <<
1014                     HF_ADDSEG_SHIFT;
1015             }
1016     }
1017     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1018
1019     return 0;
1020 }
1021
1022 static int kvm_get_msrs(CPUState *env)
1023 {
1024     struct {
1025         struct kvm_msrs info;
1026         struct kvm_msr_entry entries[100];
1027     } msr_data;
1028     struct kvm_msr_entry *msrs = msr_data.entries;
1029     int ret, i, n;
1030
1031     n = 0;
1032     msrs[n++].index = MSR_IA32_SYSENTER_CS;
1033     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1034     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1035     if (kvm_has_msr_star(env))
1036         msrs[n++].index = MSR_STAR;
1037     if (kvm_has_msr_hsave_pa(env))
1038         msrs[n++].index = MSR_VM_HSAVE_PA;
1039     msrs[n++].index = MSR_IA32_TSC;
1040 #ifdef TARGET_X86_64
1041     /* FIXME lm_capable_kernel */
1042     msrs[n++].index = MSR_CSTAR;
1043     msrs[n++].index = MSR_KERNELGSBASE;
1044     msrs[n++].index = MSR_FMASK;
1045     msrs[n++].index = MSR_LSTAR;
1046 #endif
1047     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1048     msrs[n++].index = MSR_KVM_WALL_CLOCK;
1049
1050 #ifdef KVM_CAP_MCE
1051     if (env->mcg_cap) {
1052         msrs[n++].index = MSR_MCG_STATUS;
1053         msrs[n++].index = MSR_MCG_CTL;
1054         for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++)
1055             msrs[n++].index = MSR_MC0_CTL + i;
1056     }
1057 #endif
1058
1059     msr_data.info.nmsrs = n;
1060     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
1061     if (ret < 0)
1062         return ret;
1063
1064     for (i = 0; i < ret; i++) {
1065         switch (msrs[i].index) {
1066         case MSR_IA32_SYSENTER_CS:
1067             env->sysenter_cs = msrs[i].data;
1068             break;
1069         case MSR_IA32_SYSENTER_ESP:
1070             env->sysenter_esp = msrs[i].data;
1071             break;
1072         case MSR_IA32_SYSENTER_EIP:
1073             env->sysenter_eip = msrs[i].data;
1074             break;
1075         case MSR_STAR:
1076             env->star = msrs[i].data;
1077             break;
1078 #ifdef TARGET_X86_64
1079         case MSR_CSTAR:
1080             env->cstar = msrs[i].data;
1081             break;
1082         case MSR_KERNELGSBASE:
1083             env->kernelgsbase = msrs[i].data;
1084             break;
1085         case MSR_FMASK:
1086             env->fmask = msrs[i].data;
1087             break;
1088         case MSR_LSTAR:
1089             env->lstar = msrs[i].data;
1090             break;
1091 #endif
1092         case MSR_IA32_TSC:
1093             env->tsc = msrs[i].data;
1094             break;
1095         case MSR_VM_HSAVE_PA:
1096             env->vm_hsave = msrs[i].data;
1097             break;
1098         case MSR_KVM_SYSTEM_TIME:
1099             env->system_time_msr = msrs[i].data;
1100             break;
1101         case MSR_KVM_WALL_CLOCK:
1102             env->wall_clock_msr = msrs[i].data;
1103             break;
1104 #ifdef KVM_CAP_MCE
1105         case MSR_MCG_STATUS:
1106             env->mcg_status = msrs[i].data;
1107             break;
1108         case MSR_MCG_CTL:
1109             env->mcg_ctl = msrs[i].data;
1110             break;
1111 #endif
1112         default:
1113 #ifdef KVM_CAP_MCE
1114             if (msrs[i].index >= MSR_MC0_CTL &&
1115                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1116                 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1117             }
1118 #endif
1119             break;
1120         }
1121     }
1122
1123     return 0;
1124 }
1125
1126 static int kvm_put_mp_state(CPUState *env)
1127 {
1128     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
1129
1130     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
1131 }
1132
1133 static int kvm_get_mp_state(CPUState *env)
1134 {
1135     struct kvm_mp_state mp_state;
1136     int ret;
1137
1138     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
1139     if (ret < 0) {
1140         return ret;
1141     }
1142     env->mp_state = mp_state.mp_state;
1143     return 0;
1144 }
1145
1146 static int kvm_put_vcpu_events(CPUState *env, int level)
1147 {
1148 #ifdef KVM_CAP_VCPU_EVENTS
1149     struct kvm_vcpu_events events;
1150
1151     if (!kvm_has_vcpu_events()) {
1152         return 0;
1153     }
1154
1155     events.exception.injected = (env->exception_injected >= 0);
1156     events.exception.nr = env->exception_injected;
1157     events.exception.has_error_code = env->has_error_code;
1158     events.exception.error_code = env->error_code;
1159
1160     events.interrupt.injected = (env->interrupt_injected >= 0);
1161     events.interrupt.nr = env->interrupt_injected;
1162     events.interrupt.soft = env->soft_interrupt;
1163
1164     events.nmi.injected = env->nmi_injected;
1165     events.nmi.pending = env->nmi_pending;
1166     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1167
1168     events.sipi_vector = env->sipi_vector;
1169
1170     events.flags = 0;
1171     if (level >= KVM_PUT_RESET_STATE) {
1172         events.flags |=
1173             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1174     }
1175
1176     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
1177 #else
1178     return 0;
1179 #endif
1180 }
1181
1182 static int kvm_get_vcpu_events(CPUState *env)
1183 {
1184 #ifdef KVM_CAP_VCPU_EVENTS
1185     struct kvm_vcpu_events events;
1186     int ret;
1187
1188     if (!kvm_has_vcpu_events()) {
1189         return 0;
1190     }
1191
1192     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
1193     if (ret < 0) {
1194        return ret;
1195     }
1196     env->exception_injected =
1197        events.exception.injected ? events.exception.nr : -1;
1198     env->has_error_code = events.exception.has_error_code;
1199     env->error_code = events.exception.error_code;
1200
1201     env->interrupt_injected =
1202         events.interrupt.injected ? events.interrupt.nr : -1;
1203     env->soft_interrupt = events.interrupt.soft;
1204
1205     env->nmi_injected = events.nmi.injected;
1206     env->nmi_pending = events.nmi.pending;
1207     if (events.nmi.masked) {
1208         env->hflags2 |= HF2_NMI_MASK;
1209     } else {
1210         env->hflags2 &= ~HF2_NMI_MASK;
1211     }
1212
1213     env->sipi_vector = events.sipi_vector;
1214 #endif
1215
1216     return 0;
1217 }
1218
1219 static int kvm_guest_debug_workarounds(CPUState *env)
1220 {
1221     int ret = 0;
1222 #ifdef KVM_CAP_SET_GUEST_DEBUG
1223     unsigned long reinject_trap = 0;
1224
1225     if (!kvm_has_vcpu_events()) {
1226         if (env->exception_injected == 1) {
1227             reinject_trap = KVM_GUESTDBG_INJECT_DB;
1228         } else if (env->exception_injected == 3) {
1229             reinject_trap = KVM_GUESTDBG_INJECT_BP;
1230         }
1231         env->exception_injected = -1;
1232     }
1233
1234     /*
1235      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1236      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1237      * by updating the debug state once again if single-stepping is on.
1238      * Another reason to call kvm_update_guest_debug here is a pending debug
1239      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1240      * reinject them via SET_GUEST_DEBUG.
1241      */
1242     if (reinject_trap ||
1243         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
1244         ret = kvm_update_guest_debug(env, reinject_trap);
1245     }
1246 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1247     return ret;
1248 }
1249
1250 static int kvm_put_debugregs(CPUState *env)
1251 {
1252 #ifdef KVM_CAP_DEBUGREGS
1253     struct kvm_debugregs dbgregs;
1254     int i;
1255
1256     if (!kvm_has_debugregs()) {
1257         return 0;
1258     }
1259
1260     for (i = 0; i < 4; i++) {
1261         dbgregs.db[i] = env->dr[i];
1262     }
1263     dbgregs.dr6 = env->dr[6];
1264     dbgregs.dr7 = env->dr[7];
1265     dbgregs.flags = 0;
1266
1267     return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
1268 #else
1269     return 0;
1270 #endif
1271 }
1272
1273 static int kvm_get_debugregs(CPUState *env)
1274 {
1275 #ifdef KVM_CAP_DEBUGREGS
1276     struct kvm_debugregs dbgregs;
1277     int i, ret;
1278
1279     if (!kvm_has_debugregs()) {
1280         return 0;
1281     }
1282
1283     ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
1284     if (ret < 0) {
1285        return ret;
1286     }
1287     for (i = 0; i < 4; i++) {
1288         env->dr[i] = dbgregs.db[i];
1289     }
1290     env->dr[4] = env->dr[6] = dbgregs.dr6;
1291     env->dr[5] = env->dr[7] = dbgregs.dr7;
1292 #endif
1293
1294     return 0;
1295 }
1296
1297 int kvm_arch_put_registers(CPUState *env, int level)
1298 {
1299     int ret;
1300
1301     assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1302
1303     ret = kvm_getput_regs(env, 1);
1304     if (ret < 0)
1305         return ret;
1306
1307     ret = kvm_put_xsave(env);
1308     if (ret < 0)
1309         return ret;
1310
1311     ret = kvm_put_xcrs(env);
1312     if (ret < 0)
1313         return ret;
1314
1315     ret = kvm_put_sregs(env);
1316     if (ret < 0)
1317         return ret;
1318
1319     ret = kvm_put_msrs(env, level);
1320     if (ret < 0)
1321         return ret;
1322
1323     if (level >= KVM_PUT_RESET_STATE) {
1324         ret = kvm_put_mp_state(env);
1325         if (ret < 0)
1326             return ret;
1327     }
1328
1329     ret = kvm_put_vcpu_events(env, level);
1330     if (ret < 0)
1331         return ret;
1332
1333     /* must be last */
1334     ret = kvm_guest_debug_workarounds(env);
1335     if (ret < 0)
1336         return ret;
1337
1338     ret = kvm_put_debugregs(env);
1339     if (ret < 0)
1340         return ret;
1341
1342     return 0;
1343 }
1344
1345 int kvm_arch_get_registers(CPUState *env)
1346 {
1347     int ret;
1348
1349     assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1350
1351     ret = kvm_getput_regs(env, 0);
1352     if (ret < 0)
1353         return ret;
1354
1355     ret = kvm_get_xsave(env);
1356     if (ret < 0)
1357         return ret;
1358
1359     ret = kvm_get_xcrs(env);
1360     if (ret < 0)
1361         return ret;
1362
1363     ret = kvm_get_sregs(env);
1364     if (ret < 0)
1365         return ret;
1366
1367     ret = kvm_get_msrs(env);
1368     if (ret < 0)
1369         return ret;
1370
1371     ret = kvm_get_mp_state(env);
1372     if (ret < 0)
1373         return ret;
1374
1375     ret = kvm_get_vcpu_events(env);
1376     if (ret < 0)
1377         return ret;
1378
1379     ret = kvm_get_debugregs(env);
1380     if (ret < 0)
1381         return ret;
1382
1383     return 0;
1384 }
1385
1386 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1387 {
1388     /* Try to inject an interrupt if the guest can accept it */
1389     if (run->ready_for_interrupt_injection &&
1390         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1391         (env->eflags & IF_MASK)) {
1392         int irq;
1393
1394         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1395         irq = cpu_get_pic_interrupt(env);
1396         if (irq >= 0) {
1397             struct kvm_interrupt intr;
1398             intr.irq = irq;
1399             /* FIXME: errors */
1400             DPRINTF("injected interrupt %d\n", irq);
1401             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1402         }
1403     }
1404
1405     /* If we have an interrupt but the guest is not ready to receive an
1406      * interrupt, request an interrupt window exit.  This will
1407      * cause a return to userspace as soon as the guest is ready to
1408      * receive interrupts. */
1409     if ((env->interrupt_request & CPU_INTERRUPT_HARD))
1410         run->request_interrupt_window = 1;
1411     else
1412         run->request_interrupt_window = 0;
1413
1414     DPRINTF("setting tpr\n");
1415     run->cr8 = cpu_get_apic_tpr(env->apic_state);
1416
1417     return 0;
1418 }
1419
1420 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
1421 {
1422     if (run->if_flag)
1423         env->eflags |= IF_MASK;
1424     else
1425         env->eflags &= ~IF_MASK;
1426
1427     cpu_set_apic_tpr(env->apic_state, run->cr8);
1428     cpu_set_apic_base(env->apic_state, run->apic_base);
1429
1430     return 0;
1431 }
1432
1433 int kvm_arch_process_irqchip_events(CPUState *env)
1434 {
1435     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1436         kvm_cpu_synchronize_state(env);
1437         do_cpu_init(env);
1438         env->exception_index = EXCP_HALTED;
1439     }
1440
1441     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1442         kvm_cpu_synchronize_state(env);
1443         do_cpu_sipi(env);
1444     }
1445
1446     return env->halted;
1447 }
1448
1449 static int kvm_handle_halt(CPUState *env)
1450 {
1451     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1452           (env->eflags & IF_MASK)) &&
1453         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1454         env->halted = 1;
1455         env->exception_index = EXCP_HLT;
1456         return 0;
1457     }
1458
1459     return 1;
1460 }
1461
1462 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
1463 {
1464     int ret = 0;
1465
1466     switch (run->exit_reason) {
1467     case KVM_EXIT_HLT:
1468         DPRINTF("handle_hlt\n");
1469         ret = kvm_handle_halt(env);
1470         break;
1471     }
1472
1473     return ret;
1474 }
1475
1476 #ifdef KVM_CAP_SET_GUEST_DEBUG
1477 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1478 {
1479     static const uint8_t int3 = 0xcc;
1480
1481     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1482         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
1483         return -EINVAL;
1484     return 0;
1485 }
1486
1487 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1488 {
1489     uint8_t int3;
1490
1491     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1492         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
1493         return -EINVAL;
1494     return 0;
1495 }
1496
1497 static struct {
1498     target_ulong addr;
1499     int len;
1500     int type;
1501 } hw_breakpoint[4];
1502
1503 static int nb_hw_breakpoint;
1504
1505 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1506 {
1507     int n;
1508
1509     for (n = 0; n < nb_hw_breakpoint; n++)
1510         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1511             (hw_breakpoint[n].len == len || len == -1))
1512             return n;
1513     return -1;
1514 }
1515
1516 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1517                                   target_ulong len, int type)
1518 {
1519     switch (type) {
1520     case GDB_BREAKPOINT_HW:
1521         len = 1;
1522         break;
1523     case GDB_WATCHPOINT_WRITE:
1524     case GDB_WATCHPOINT_ACCESS:
1525         switch (len) {
1526         case 1:
1527             break;
1528         case 2:
1529         case 4:
1530         case 8:
1531             if (addr & (len - 1))
1532                 return -EINVAL;
1533             break;
1534         default:
1535             return -EINVAL;
1536         }
1537         break;
1538     default:
1539         return -ENOSYS;
1540     }
1541
1542     if (nb_hw_breakpoint == 4)
1543         return -ENOBUFS;
1544
1545     if (find_hw_breakpoint(addr, len, type) >= 0)
1546         return -EEXIST;
1547
1548     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1549     hw_breakpoint[nb_hw_breakpoint].len = len;
1550     hw_breakpoint[nb_hw_breakpoint].type = type;
1551     nb_hw_breakpoint++;
1552
1553     return 0;
1554 }
1555
1556 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1557                                   target_ulong len, int type)
1558 {
1559     int n;
1560
1561     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1562     if (n < 0)
1563         return -ENOENT;
1564
1565     nb_hw_breakpoint--;
1566     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1567
1568     return 0;
1569 }
1570
1571 void kvm_arch_remove_all_hw_breakpoints(void)
1572 {
1573     nb_hw_breakpoint = 0;
1574 }
1575
1576 static CPUWatchpoint hw_watchpoint;
1577
1578 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1579 {
1580     int handle = 0;
1581     int n;
1582
1583     if (arch_info->exception == 1) {
1584         if (arch_info->dr6 & (1 << 14)) {
1585             if (cpu_single_env->singlestep_enabled)
1586                 handle = 1;
1587         } else {
1588             for (n = 0; n < 4; n++)
1589                 if (arch_info->dr6 & (1 << n))
1590                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1591                     case 0x0:
1592                         handle = 1;
1593                         break;
1594                     case 0x1:
1595                         handle = 1;
1596                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1597                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1598                         hw_watchpoint.flags = BP_MEM_WRITE;
1599                         break;
1600                     case 0x3:
1601                         handle = 1;
1602                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1603                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1604                         hw_watchpoint.flags = BP_MEM_ACCESS;
1605                         break;
1606                     }
1607         }
1608     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
1609         handle = 1;
1610
1611     if (!handle) {
1612         cpu_synchronize_state(cpu_single_env);
1613         assert(cpu_single_env->exception_injected == -1);
1614
1615         cpu_single_env->exception_injected = arch_info->exception;
1616         cpu_single_env->has_error_code = 0;
1617     }
1618
1619     return handle;
1620 }
1621
1622 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1623 {
1624     const uint8_t type_code[] = {
1625         [GDB_BREAKPOINT_HW] = 0x0,
1626         [GDB_WATCHPOINT_WRITE] = 0x1,
1627         [GDB_WATCHPOINT_ACCESS] = 0x3
1628     };
1629     const uint8_t len_code[] = {
1630         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1631     };
1632     int n;
1633
1634     if (kvm_sw_breakpoints_active(env))
1635         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1636
1637     if (nb_hw_breakpoint > 0) {
1638         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1639         dbg->arch.debugreg[7] = 0x0600;
1640         for (n = 0; n < nb_hw_breakpoint; n++) {
1641             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1642             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1643                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1644                 (len_code[hw_breakpoint[n].len] << (18 + n*4));
1645         }
1646     }
1647     /* Legal xcr0 for loading */
1648     env->xcr0 = 1;
1649 }
1650 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1651
1652 bool kvm_arch_stop_on_emulation_error(CPUState *env)
1653 {
1654       return !(env->cr[0] & CR0_PE_MASK) ||
1655               ((env->segs[R_CS].selector  & 3) != 3);
1656 }
1657
1658 static void hardware_memory_error(void)
1659 {
1660     fprintf(stderr, "Hardware memory error!\n");
1661     exit(1);
1662 }
1663
1664 #ifdef KVM_CAP_MCE
1665 static void kvm_mce_broadcast_rest(CPUState *env)
1666 {
1667     CPUState *cenv;
1668     int family, model, cpuver = env->cpuid_version;
1669
1670     family = (cpuver >> 8) & 0xf;
1671     model = ((cpuver >> 12) & 0xf0) + ((cpuver >> 4) & 0xf);
1672
1673     /* Broadcast MCA signal for processor version 06H_EH and above */
1674     if ((family == 6 && model >= 14) || family > 6) {
1675         for (cenv = first_cpu; cenv != NULL; cenv = cenv->next_cpu) {
1676             if (cenv == env) {
1677                 continue;
1678             }
1679             kvm_inject_x86_mce(cenv, 1, MCI_STATUS_VAL | MCI_STATUS_UC,
1680                                MCG_STATUS_MCIP | MCG_STATUS_RIPV, 0, 0, 1);
1681         }
1682     }
1683 }
1684 #endif
1685
1686 int kvm_on_sigbus_vcpu(CPUState *env, int code, void *addr)
1687 {
1688 #if defined(KVM_CAP_MCE)
1689     struct kvm_x86_mce mce = {
1690             .bank = 9,
1691     };
1692     void *vaddr;
1693     ram_addr_t ram_addr;
1694     target_phys_addr_t paddr;
1695     int r;
1696
1697     if ((env->mcg_cap & MCG_SER_P) && addr
1698         && (code == BUS_MCEERR_AR
1699             || code == BUS_MCEERR_AO)) {
1700         if (code == BUS_MCEERR_AR) {
1701             /* Fake an Intel architectural Data Load SRAR UCR */
1702             mce.status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1703                 | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1704                 | MCI_STATUS_AR | 0x134;
1705             mce.misc = (MCM_ADDR_PHYS << 6) | 0xc;
1706             mce.mcg_status = MCG_STATUS_MCIP | MCG_STATUS_EIPV;
1707         } else {
1708             /*
1709              * If there is an MCE excpetion being processed, ignore
1710              * this SRAO MCE
1711              */
1712             r = kvm_mce_in_exception(env);
1713             if (r == -1) {
1714                 fprintf(stderr, "Failed to get MCE status\n");
1715             } else if (r) {
1716                 return 0;
1717             }
1718             /* Fake an Intel architectural Memory scrubbing UCR */
1719             mce.status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1720                 | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1721                 | 0xc0;
1722             mce.misc = (MCM_ADDR_PHYS << 6) | 0xc;
1723             mce.mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV;
1724         }
1725         vaddr = (void *)addr;
1726         if (qemu_ram_addr_from_host(vaddr, &ram_addr) ||
1727             !kvm_physical_memory_addr_from_ram(env->kvm_state, ram_addr, &paddr)) {
1728             fprintf(stderr, "Hardware memory error for memory used by "
1729                     "QEMU itself instead of guest system!\n");
1730             /* Hope we are lucky for AO MCE */
1731             if (code == BUS_MCEERR_AO) {
1732                 return 0;
1733             } else {
1734                 hardware_memory_error();
1735             }
1736         }
1737         mce.addr = paddr;
1738         r = kvm_set_mce(env, &mce);
1739         if (r < 0) {
1740             fprintf(stderr, "kvm_set_mce: %s\n", strerror(errno));
1741             abort();
1742         }
1743         kvm_mce_broadcast_rest(env);
1744     } else
1745 #endif
1746     {
1747         if (code == BUS_MCEERR_AO) {
1748             return 0;
1749         } else if (code == BUS_MCEERR_AR) {
1750             hardware_memory_error();
1751         } else {
1752             return 1;
1753         }
1754     }
1755     return 0;
1756 }
1757
1758 int kvm_on_sigbus(int code, void *addr)
1759 {
1760 #if defined(KVM_CAP_MCE)
1761     if ((first_cpu->mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
1762         uint64_t status;
1763         void *vaddr;
1764         ram_addr_t ram_addr;
1765         target_phys_addr_t paddr;
1766
1767         /* Hope we are lucky for AO MCE */
1768         vaddr = addr;
1769         if (qemu_ram_addr_from_host(vaddr, &ram_addr) ||
1770             !kvm_physical_memory_addr_from_ram(first_cpu->kvm_state, ram_addr, &paddr)) {
1771             fprintf(stderr, "Hardware memory error for memory used by "
1772                     "QEMU itself instead of guest system!: %p\n", addr);
1773             return 0;
1774         }
1775         status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN
1776             | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S
1777             | 0xc0;
1778         kvm_inject_x86_mce(first_cpu, 9, status,
1779                            MCG_STATUS_MCIP | MCG_STATUS_RIPV, paddr,
1780                            (MCM_ADDR_PHYS << 6) | 0xc, 1);
1781         kvm_mce_broadcast_rest(first_cpu);
1782     } else
1783 #endif
1784     {
1785         if (code == BUS_MCEERR_AO) {
1786             return 0;
1787         } else if (code == BUS_MCEERR_AR) {
1788             hardware_memory_error();
1789         } else {
1790             return 1;
1791         }
1792     }
1793     return 0;
1794 }