target/openrisc/cpu.c

   1 /*
   2  * QEMU OpenRISC CPU
   3  *
   4  * Copyright (c) 2012 Jia Liu <proljc@gmail.com>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "qemu/qemu-print.h"
  23 #include "cpu.h"
  24 #include "qemu-common.h"
  25
  26 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
  27 {
  28     OpenRISCCPU *cpu = OPENRISC_CPU(cs);
  29
  30     cpu->env.pc = value;
  31     cpu->env.dflag = 0;
  32 }
  33
  34 static bool openrisc_cpu_has_work(CPUState *cs)
  35 {
  36     return cs->interrupt_request & (CPU_INTERRUPT_HARD |
  37                                     CPU_INTERRUPT_TIMER);
  38 }
  39
  40 static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info)
  41 {
  42     info->print_insn = print_insn_or1k;
  43 }
  44
  45 /* CPUClass::reset() */
  46 static void openrisc_cpu_reset(CPUState *s)
  47 {
  48     OpenRISCCPU *cpu = OPENRISC_CPU(s);
  49     OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
  50
  51     occ->parent_reset(s);
  52
  53     memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields));
  54
  55     cpu->env.pc = 0x100;
  56     cpu->env.sr = SR_FO | SR_SM;
  57     cpu->env.lock_addr = -1;
  58     s->exception_index = -1;
  59
  60     cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP |
  61                    UPR_PMP;
  62     cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))
  63                       | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
  64     cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2))
  65                       | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
  66
  67 #ifndef CONFIG_USER_ONLY
  68     cpu->env.picmr = 0x00000000;
  69     cpu->env.picsr = 0x00000000;
  70
  71     cpu->env.ttmr = 0x00000000;
  72 #endif
  73 }
  74
  75 static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
  76 {
  77     CPUState *cs = CPU(dev);
  78     OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
  79     Error *local_err = NULL;
  80
  81     cpu_exec_realizefn(cs, &local_err);
  82     if (local_err != NULL) {
  83         error_propagate(errp, local_err);
  84         return;
  85     }
  86
  87     qemu_init_vcpu(cs);
  88     cpu_reset(cs);
  89
  90     occ->parent_realize(dev, errp);
  91 }
  92
  93 static void openrisc_cpu_initfn(Object *obj)
  94 {
  95     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
  96
  97     cpu_set_cpustate_pointers(cpu);
  98 }
  99
 100 /* CPU models */
 101
 102 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model)
 103 {
 104     ObjectClass *oc;
 105     char *typename;
 106
 107     typename = g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model);
 108     oc = object_class_by_name(typename);
 109     g_free(typename);
 110     if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
 111                        object_class_is_abstract(oc))) {
 112         return NULL;
 113     }
 114     return oc;
 115 }
 116
 117 static void or1200_initfn(Object *obj)
 118 {
 119     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
 120
 121     cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |
 122                        CPUCFGR_EVBARP;
 123 }
 124
 125 static void openrisc_any_initfn(Object *obj)
 126 {
 127     OpenRISCCPU *cpu = OPENRISC_CPU(obj);
 128
 129     cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_EVBARP;
 130 }
 131
 132 static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
 133 {
 134     OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
 135     CPUClass *cc = CPU_CLASS(occ);
 136     DeviceClass *dc = DEVICE_CLASS(oc);
 137
 138     device_class_set_parent_realize(dc, openrisc_cpu_realizefn,
 139                                     &occ->parent_realize);
 140     occ->parent_reset = cc->reset;
 141     cc->reset = openrisc_cpu_reset;
 142
 143     cc->class_by_name = openrisc_cpu_class_by_name;
 144     cc->has_work = openrisc_cpu_has_work;
 145     cc->do_interrupt = openrisc_cpu_do_interrupt;
 146     cc->cpu_exec_interrupt = openrisc_cpu_exec_interrupt;
 147     cc->dump_state = openrisc_cpu_dump_state;
 148     cc->set_pc = openrisc_cpu_set_pc;
 149     cc->gdb_read_register = openrisc_cpu_gdb_read_register;
 150     cc->gdb_write_register = openrisc_cpu_gdb_write_register;
 151     cc->tlb_fill = openrisc_cpu_tlb_fill;
 152 #ifndef CONFIG_USER_ONLY
 153     cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
 154     dc->vmsd = &vmstate_openrisc_cpu;
 155 #endif
 156     cc->gdb_num_core_regs = 32 + 3;
 157     cc->tcg_initialize = openrisc_translate_init;
 158     cc->disas_set_info = openrisc_disas_set_info;
 159 }
 160
 161 /* Sort alphabetically by type name, except for "any". */
 162 static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b)
 163 {
 164     ObjectClass *class_a = (ObjectClass *)a;
 165     ObjectClass *class_b = (ObjectClass *)b;
 166     const char *name_a, *name_b;
 167
 168     name_a = object_class_get_name(class_a);
 169     name_b = object_class_get_name(class_b);
 170     if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) {
 171         return 1;
 172     } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) {
 173         return -1;
 174     } else {
 175         return strcmp(name_a, name_b);
 176     }
 177 }
 178
 179 static void openrisc_cpu_list_entry(gpointer data, gpointer user_data)
 180 {
 181     ObjectClass *oc = data;
 182     const char *typename;
 183     char *name;
 184
 185     typename = object_class_get_name(oc);
 186     name = g_strndup(typename,
 187                      strlen(typename) - strlen("-" TYPE_OPENRISC_CPU));
 188     qemu_printf("  %s\n", name);
 189     g_free(name);
 190 }
 191
 192 void cpu_openrisc_list(void)
 193 {
 194     GSList *list;
 195
 196     list = object_class_get_list(TYPE_OPENRISC_CPU, false);
 197     list = g_slist_sort(list, openrisc_cpu_list_compare);
 198     qemu_printf("Available CPUs:\n");
 199     g_slist_foreach(list, openrisc_cpu_list_entry, NULL);
 200     g_slist_free(list);
 201 }
 202
 203 #define DEFINE_OPENRISC_CPU_TYPE(cpu_model, initfn) \
 204     {                                               \
 205         .parent = TYPE_OPENRISC_CPU,                \
 206         .instance_init = initfn,                    \
 207         .name = OPENRISC_CPU_TYPE_NAME(cpu_model),  \
 208     }
 209
 210 static const TypeInfo openrisc_cpus_type_infos[] = {
 211     { /* base class should be registered first */
 212         .name = TYPE_OPENRISC_CPU,
 213         .parent = TYPE_CPU,
 214         .instance_size = sizeof(OpenRISCCPU),
 215         .instance_init = openrisc_cpu_initfn,
 216         .abstract = true,
 217         .class_size = sizeof(OpenRISCCPUClass),
 218         .class_init = openrisc_cpu_class_init,
 219     },
 220     DEFINE_OPENRISC_CPU_TYPE("or1200", or1200_initfn),
 221     DEFINE_OPENRISC_CPU_TYPE("any", openrisc_any_initfn),
 222 };
 223
 224 DEFINE_TYPES(openrisc_cpus_type_infos)