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kvm: i386: allow TSC to differ by NTP correction bounds without TSC scaling
[qemu/ar7.git] / target / i386 / kvm.c
blob6adbff3d7456d359c3916d3f879b3f2467b0e42a
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include "standard-headers/asm-x86/kvm_para.h"
22
23 #include "cpu.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/hw_accel.h"
26 #include "sysemu/kvm_int.h"
27 #include "sysemu/runstate.h"
28 #include "kvm_i386.h"
29 #include "hyperv.h"
30 #include "hyperv-proto.h"
31
32 #include "exec/gdbstub.h"
33 #include "qemu/host-utils.h"
34 #include "qemu/main-loop.h"
35 #include "qemu/config-file.h"
36 #include "qemu/error-report.h"
37 #include "hw/i386/x86.h"
38 #include "hw/i386/apic.h"
39 #include "hw/i386/apic_internal.h"
40 #include "hw/i386/apic-msidef.h"
41 #include "hw/i386/intel_iommu.h"
42 #include "hw/i386/x86-iommu.h"
43 #include "hw/i386/e820_memory_layout.h"
44
45 #include "hw/pci/pci.h"
46 #include "hw/pci/msi.h"
47 #include "hw/pci/msix.h"
48 #include "migration/blocker.h"
49 #include "exec/memattrs.h"
50 #include "trace.h"
51
52 //#define DEBUG_KVM
53
54 #ifdef DEBUG_KVM
55 #define DPRINTF(fmt, ...) \
56 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
57 #else
58 #define DPRINTF(fmt, ...) \
59 do { } while (0)
60 #endif
61
62 /* From arch/x86/kvm/lapic.h */
63 #define KVM_APIC_BUS_CYCLE_NS 1
64 #define KVM_APIC_BUS_FREQUENCY (1000000000ULL / KVM_APIC_BUS_CYCLE_NS)
65
66 #define MSR_KVM_WALL_CLOCK 0x11
67 #define MSR_KVM_SYSTEM_TIME 0x12
68
69 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
70 * 255 kvm_msr_entry structs */
71 #define MSR_BUF_SIZE 4096
72
73 static void kvm_init_msrs(X86CPU *cpu);
74
75 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
76 KVM_CAP_INFO(SET_TSS_ADDR),
77 KVM_CAP_INFO(EXT_CPUID),
78 KVM_CAP_INFO(MP_STATE),
79 KVM_CAP_LAST_INFO
80 };
81
82 static bool has_msr_star;
83 static bool has_msr_hsave_pa;
84 static bool has_msr_tsc_aux;
85 static bool has_msr_tsc_adjust;
86 static bool has_msr_tsc_deadline;
87 static bool has_msr_feature_control;
88 static bool has_msr_misc_enable;
89 static bool has_msr_smbase;
90 static bool has_msr_bndcfgs;
91 static int lm_capable_kernel;
92 static bool has_msr_hv_hypercall;
93 static bool has_msr_hv_crash;
94 static bool has_msr_hv_reset;
95 static bool has_msr_hv_vpindex;
96 static bool hv_vpindex_settable;
97 static bool has_msr_hv_runtime;
98 static bool has_msr_hv_synic;
99 static bool has_msr_hv_stimer;
100 static bool has_msr_hv_frequencies;
101 static bool has_msr_hv_reenlightenment;
102 static bool has_msr_xss;
103 static bool has_msr_umwait;
104 static bool has_msr_spec_ctrl;
105 static bool has_msr_tsx_ctrl;
106 static bool has_msr_virt_ssbd;
107 static bool has_msr_smi_count;
108 static bool has_msr_arch_capabs;
109 static bool has_msr_core_capabs;
110 static bool has_msr_vmx_vmfunc;
111 static bool has_msr_ucode_rev;
112 static bool has_msr_vmx_procbased_ctls2;
113 static bool has_msr_perf_capabs;
114
115 static uint32_t has_architectural_pmu_version;
116 static uint32_t num_architectural_pmu_gp_counters;
117 static uint32_t num_architectural_pmu_fixed_counters;
118
119 static int has_xsave;
120 static int has_xcrs;
121 static int has_pit_state2;
122 static int has_exception_payload;
123
124 static bool has_msr_mcg_ext_ctl;
125
126 static struct kvm_cpuid2 *cpuid_cache;
127 static struct kvm_msr_list *kvm_feature_msrs;
128
129 int kvm_has_pit_state2(void)
130 {
131 return has_pit_state2;
132 }
133
134 bool kvm_has_smm(void)
135 {
136 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
137 }
138
139 bool kvm_has_adjust_clock_stable(void)
140 {
141 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
142
143 return (ret == KVM_CLOCK_TSC_STABLE);
144 }
145
146 bool kvm_has_exception_payload(void)
147 {
148 return has_exception_payload;
149 }
150
151 bool kvm_allows_irq0_override(void)
152 {
153 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
154 }
155
156 static bool kvm_x2apic_api_set_flags(uint64_t flags)
157 {
158 KVMState *s = KVM_STATE(current_accel());
159
160 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
161 }
162
163 #define MEMORIZE(fn, _result) \
164 ({ \
165 static bool _memorized; \
166 \
167 if (_memorized) { \
168 return _result; \
169 } \
170 _memorized = true; \
171 _result = fn; \
172 })
173
174 static bool has_x2apic_api;
175
176 bool kvm_has_x2apic_api(void)
177 {
178 return has_x2apic_api;
179 }
180
181 bool kvm_enable_x2apic(void)
182 {
183 return MEMORIZE(
184 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
185 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
186 has_x2apic_api);
187 }
188
189 bool kvm_hv_vpindex_settable(void)
190 {
191 return hv_vpindex_settable;
192 }
193
194 static int kvm_get_tsc(CPUState *cs)
195 {
196 X86CPU *cpu = X86_CPU(cs);
197 CPUX86State *env = &cpu->env;
198 struct {
199 struct kvm_msrs info;
200 struct kvm_msr_entry entries[1];
201 } msr_data = {};
202 int ret;
203
204 if (env->tsc_valid) {
205 return 0;
206 }
207
208 memset(&msr_data, 0, sizeof(msr_data));
209 msr_data.info.nmsrs = 1;
210 msr_data.entries[0].index = MSR_IA32_TSC;
211 env->tsc_valid = !runstate_is_running();
212
213 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
214 if (ret < 0) {
215 return ret;
216 }
217
218 assert(ret == 1);
219 env->tsc = msr_data.entries[0].data;
220 return 0;
221 }
222
223 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
224 {
225 kvm_get_tsc(cpu);
226 }
227
228 void kvm_synchronize_all_tsc(void)
229 {
230 CPUState *cpu;
231
232 if (kvm_enabled()) {
233 CPU_FOREACH(cpu) {
234 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
235 }
236 }
237 }
238
239 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
240 {
241 struct kvm_cpuid2 *cpuid;
242 int r, size;
243
244 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
245 cpuid = g_malloc0(size);
246 cpuid->nent = max;
247 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
248 if (r == 0 && cpuid->nent >= max) {
249 r = -E2BIG;
250 }
251 if (r < 0) {
252 if (r == -E2BIG) {
253 g_free(cpuid);
254 return NULL;
255 } else {
256 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
257 strerror(-r));
258 exit(1);
259 }
260 }
261 return cpuid;
262 }
263
264 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
265 * for all entries.
266 */
267 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
268 {
269 struct kvm_cpuid2 *cpuid;
270 int max = 1;
271
272 if (cpuid_cache != NULL) {
273 return cpuid_cache;
274 }
275 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
276 max *= 2;
277 }
278 cpuid_cache = cpuid;
279 return cpuid;
280 }
281
282 static const struct kvm_para_features {
283 int cap;
284 int feature;
285 } para_features[] = {
286 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
287 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
288 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
289 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
290 };
291
292 static int get_para_features(KVMState *s)
293 {
294 int i, features = 0;
295
296 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
297 if (kvm_check_extension(s, para_features[i].cap)) {
298 features |= (1 << para_features[i].feature);
299 }
300 }
301
302 return features;
303 }
304
305 static bool host_tsx_blacklisted(void)
306 {
307 int family, model, stepping;\
308 char vendor[CPUID_VENDOR_SZ + 1];
309
310 host_vendor_fms(vendor, &family, &model, &stepping);
311
312 /* Check if we are running on a Haswell host known to have broken TSX */
313 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
314 (family == 6) &&
315 ((model == 63 && stepping < 4) ||
316 model == 60 || model == 69 || model == 70);
317 }
318
319 /* Returns the value for a specific register on the cpuid entry
320 */
321 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
322 {
323 uint32_t ret = 0;
324 switch (reg) {
325 case R_EAX:
326 ret = entry->eax;
327 break;
328 case R_EBX:
329 ret = entry->ebx;
330 break;
331 case R_ECX:
332 ret = entry->ecx;
333 break;
334 case R_EDX:
335 ret = entry->edx;
336 break;
337 }
338 return ret;
339 }
340
341 /* Find matching entry for function/index on kvm_cpuid2 struct
342 */
343 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
344 uint32_t function,
345 uint32_t index)
346 {
347 int i;
348 for (i = 0; i < cpuid->nent; ++i) {
349 if (cpuid->entries[i].function == function &&
350 cpuid->entries[i].index == index) {
351 return &cpuid->entries[i];
352 }
353 }
354 /* not found: */
355 return NULL;
356 }
357
358 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
359 uint32_t index, int reg)
360 {
361 struct kvm_cpuid2 *cpuid;
362 uint32_t ret = 0;
363 uint32_t cpuid_1_edx;
364 bool found = false;
365
366 cpuid = get_supported_cpuid(s);
367
368 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
369 if (entry) {
370 found = true;
371 ret = cpuid_entry_get_reg(entry, reg);
372 }
373
374 /* Fixups for the data returned by KVM, below */
375
376 if (function == 1 && reg == R_EDX) {
377 /* KVM before 2.6.30 misreports the following features */
378 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
379 } else if (function == 1 && reg == R_ECX) {
380 /* We can set the hypervisor flag, even if KVM does not return it on
381 * GET_SUPPORTED_CPUID
382 */
383 ret |= CPUID_EXT_HYPERVISOR;
384 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
385 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
386 * and the irqchip is in the kernel.
387 */
388 if (kvm_irqchip_in_kernel() &&
389 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
390 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
391 }
392
393 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
394 * without the in-kernel irqchip
395 */
396 if (!kvm_irqchip_in_kernel()) {
397 ret &= ~CPUID_EXT_X2APIC;
398 }
399
400 if (enable_cpu_pm) {
401 int disable_exits = kvm_check_extension(s,
402 KVM_CAP_X86_DISABLE_EXITS);
403
404 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
405 ret |= CPUID_EXT_MONITOR;
406 }
407 }
408 } else if (function == 6 && reg == R_EAX) {
409 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
410 } else if (function == 7 && index == 0 && reg == R_EBX) {
411 if (host_tsx_blacklisted()) {
412 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
413 }
414 } else if (function == 7 && index == 0 && reg == R_ECX) {
415 if (enable_cpu_pm) {
416 ret |= CPUID_7_0_ECX_WAITPKG;
417 } else {
418 ret &= ~CPUID_7_0_ECX_WAITPKG;
419 }
420 } else if (function == 7 && index == 0 && reg == R_EDX) {
421 /*
422 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
423 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
424 * returned by KVM_GET_MSR_INDEX_LIST.
425 */
426 if (!has_msr_arch_capabs) {
427 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES;
428 }
429 } else if (function == 0x80000001 && reg == R_ECX) {
430 /*
431 * It's safe to enable TOPOEXT even if it's not returned by
432 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
433 * us to keep CPU models including TOPOEXT runnable on older kernels.
434 */
435 ret |= CPUID_EXT3_TOPOEXT;
436 } else if (function == 0x80000001 && reg == R_EDX) {
437 /* On Intel, kvm returns cpuid according to the Intel spec,
438 * so add missing bits according to the AMD spec:
439 */
440 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
441 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
442 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
443 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
444 * be enabled without the in-kernel irqchip
445 */
446 if (!kvm_irqchip_in_kernel()) {
447 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
448 }
449 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
450 ret |= 1U << KVM_HINTS_REALTIME;
451 found = 1;
452 }
453
454 /* fallback for older kernels */
455 if ((function == KVM_CPUID_FEATURES) && !found) {
456 ret = get_para_features(s);
457 }
458
459 return ret;
460 }
461
462 uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
463 {
464 struct {
465 struct kvm_msrs info;
466 struct kvm_msr_entry entries[1];
467 } msr_data = {};
468 uint64_t value;
469 uint32_t ret, can_be_one, must_be_one;
470
471 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
472 return 0;
473 }
474
475 /* Check if requested MSR is supported feature MSR */
476 int i;
477 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
478 if (kvm_feature_msrs->indices[i] == index) {
479 break;
480 }
481 if (i == kvm_feature_msrs->nmsrs) {
482 return 0; /* if the feature MSR is not supported, simply return 0 */
483 }
484
485 msr_data.info.nmsrs = 1;
486 msr_data.entries[0].index = index;
487
488 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
489 if (ret != 1) {
490 error_report("KVM get MSR (index=0x%x) feature failed, %s",
491 index, strerror(-ret));
492 exit(1);
493 }
494
495 value = msr_data.entries[0].data;
496 switch (index) {
497 case MSR_IA32_VMX_PROCBASED_CTLS2:
498 if (!has_msr_vmx_procbased_ctls2) {
499 /* KVM forgot to add these bits for some time, do this ourselves. */
500 if (kvm_arch_get_supported_cpuid(s, 0xD, 1, R_ECX) &
501 CPUID_XSAVE_XSAVES) {
502 value |= (uint64_t)VMX_SECONDARY_EXEC_XSAVES << 32;
503 }
504 if (kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX) &
505 CPUID_EXT_RDRAND) {
506 value |= (uint64_t)VMX_SECONDARY_EXEC_RDRAND_EXITING << 32;
507 }
508 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
509 CPUID_7_0_EBX_INVPCID) {
510 value |= (uint64_t)VMX_SECONDARY_EXEC_ENABLE_INVPCID << 32;
511 }
512 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
513 CPUID_7_0_EBX_RDSEED) {
514 value |= (uint64_t)VMX_SECONDARY_EXEC_RDSEED_EXITING << 32;
515 }
516 if (kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX) &
517 CPUID_EXT2_RDTSCP) {
518 value |= (uint64_t)VMX_SECONDARY_EXEC_RDTSCP << 32;
519 }
520 }
521 /* fall through */
522 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
523 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
524 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
525 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
526 /*
527 * Return true for bits that can be one, but do not have to be one.
528 * The SDM tells us which bits could have a "must be one" setting,
529 * so we can do the opposite transformation in make_vmx_msr_value.
530 */
531 must_be_one = (uint32_t)value;
532 can_be_one = (uint32_t)(value >> 32);
533 return can_be_one & ~must_be_one;
534
535 default:
536 return value;
537 }
538 }
539
540 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
541 int *max_banks)
542 {
543 int r;
544
545 r = kvm_check_extension(s, KVM_CAP_MCE);
546 if (r > 0) {
547 *max_banks = r;
548 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
549 }
550 return -ENOSYS;
551 }
552
553 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
554 {
555 CPUState *cs = CPU(cpu);
556 CPUX86State *env = &cpu->env;
557 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
558 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
559 uint64_t mcg_status = MCG_STATUS_MCIP;
560 int flags = 0;
561
562 if (code == BUS_MCEERR_AR) {
563 status |= MCI_STATUS_AR | 0x134;
564 mcg_status |= MCG_STATUS_EIPV;
565 } else {
566 status |= 0xc0;
567 mcg_status |= MCG_STATUS_RIPV;
568 }
569
570 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
571 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
572 * guest kernel back into env->mcg_ext_ctl.
573 */
574 cpu_synchronize_state(cs);
575 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
576 mcg_status |= MCG_STATUS_LMCE;
577 flags = 0;
578 }
579
580 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
581 (MCM_ADDR_PHYS << 6) | 0xc, flags);
582 }
583
584 static void hardware_memory_error(void *host_addr)
585 {
586 error_report("QEMU got Hardware memory error at addr %p", host_addr);
587 exit(1);
588 }
589
590 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
591 {
592 X86CPU *cpu = X86_CPU(c);
593 CPUX86State *env = &cpu->env;
594 ram_addr_t ram_addr;
595 hwaddr paddr;
596
597 /* If we get an action required MCE, it has been injected by KVM
598 * while the VM was running. An action optional MCE instead should
599 * be coming from the main thread, which qemu_init_sigbus identifies
600 * as the "early kill" thread.
601 */
602 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
603
604 if ((env->mcg_cap & MCG_SER_P) && addr) {
605 ram_addr = qemu_ram_addr_from_host(addr);
606 if (ram_addr != RAM_ADDR_INVALID &&
607 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
608 kvm_hwpoison_page_add(ram_addr);
609 kvm_mce_inject(cpu, paddr, code);
610
611 /*
612 * Use different logging severity based on error type.
613 * If there is additional MCE reporting on the hypervisor, QEMU VA
614 * could be another source to identify the PA and MCE details.
615 */
616 if (code == BUS_MCEERR_AR) {
617 error_report("Guest MCE Memory Error at QEMU addr %p and "
618 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
619 addr, paddr, "BUS_MCEERR_AR");
620 } else {
621 warn_report("Guest MCE Memory Error at QEMU addr %p and "
622 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
623 addr, paddr, "BUS_MCEERR_AO");
624 }
625
626 return;
627 }
628
629 if (code == BUS_MCEERR_AO) {
630 warn_report("Hardware memory error at addr %p of type %s "
631 "for memory used by QEMU itself instead of guest system!",
632 addr, "BUS_MCEERR_AO");
633 }
634 }
635
636 if (code == BUS_MCEERR_AR) {
637 hardware_memory_error(addr);
638 }
639
640 /* Hope we are lucky for AO MCE */
641 }
642
643 static void kvm_reset_exception(CPUX86State *env)
644 {
645 env->exception_nr = -1;
646 env->exception_pending = 0;
647 env->exception_injected = 0;
648 env->exception_has_payload = false;
649 env->exception_payload = 0;
650 }
651
652 static void kvm_queue_exception(CPUX86State *env,
653 int32_t exception_nr,
654 uint8_t exception_has_payload,
655 uint64_t exception_payload)
656 {
657 assert(env->exception_nr == -1);
658 assert(!env->exception_pending);
659 assert(!env->exception_injected);
660 assert(!env->exception_has_payload);
661
662 env->exception_nr = exception_nr;
663
664 if (has_exception_payload) {
665 env->exception_pending = 1;
666
667 env->exception_has_payload = exception_has_payload;
668 env->exception_payload = exception_payload;
669 } else {
670 env->exception_injected = 1;
671
672 if (exception_nr == EXCP01_DB) {
673 assert(exception_has_payload);
674 env->dr[6] = exception_payload;
675 } else if (exception_nr == EXCP0E_PAGE) {
676 assert(exception_has_payload);
677 env->cr[2] = exception_payload;
678 } else {
679 assert(!exception_has_payload);
680 }
681 }
682 }
683
684 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
685 {
686 CPUX86State *env = &cpu->env;
687
688 if (!kvm_has_vcpu_events() && env->exception_nr == EXCP12_MCHK) {
689 unsigned int bank, bank_num = env->mcg_cap & 0xff;
690 struct kvm_x86_mce mce;
691
692 kvm_reset_exception(env);
693
694 /*
695 * There must be at least one bank in use if an MCE is pending.
696 * Find it and use its values for the event injection.
697 */
698 for (bank = 0; bank < bank_num; bank++) {
699 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
700 break;
701 }
702 }
703 assert(bank < bank_num);
704
705 mce.bank = bank;
706 mce.status = env->mce_banks[bank * 4 + 1];
707 mce.mcg_status = env->mcg_status;
708 mce.addr = env->mce_banks[bank * 4 + 2];
709 mce.misc = env->mce_banks[bank * 4 + 3];
710
711 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
712 }
713 return 0;
714 }
715
716 static void cpu_update_state(void *opaque, int running, RunState state)
717 {
718 CPUX86State *env = opaque;
719
720 if (running) {
721 env->tsc_valid = false;
722 }
723 }
724
725 unsigned long kvm_arch_vcpu_id(CPUState *cs)
726 {
727 X86CPU *cpu = X86_CPU(cs);
728 return cpu->apic_id;
729 }
730
731 #ifndef KVM_CPUID_SIGNATURE_NEXT
732 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
733 #endif
734
735 static bool hyperv_enabled(X86CPU *cpu)
736 {
737 CPUState *cs = CPU(cpu);
738 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
739 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) ||
740 cpu->hyperv_features || cpu->hyperv_passthrough);
741 }
742
743 /*
744 * Check whether target_freq is within conservative
745 * ntp correctable bounds (250ppm) of freq
746 */
747 static inline bool freq_within_bounds(int freq, int target_freq)
748 {
749 int max_freq = freq + (freq * 250 / 1000000);
750 int min_freq = freq - (freq * 250 / 1000000);
751
752 if (target_freq >= min_freq && target_freq <= max_freq) {
753 return true;
754 }
755
756 return false;
757 }
758
759 static int kvm_arch_set_tsc_khz(CPUState *cs)
760 {
761 X86CPU *cpu = X86_CPU(cs);
762 CPUX86State *env = &cpu->env;
763 int r, cur_freq;
764 bool set_ioctl = false;
765
766 if (!env->tsc_khz) {
767 return 0;
768 }
769
770 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
771 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : -ENOTSUP;
772
773 /*
774 * If TSC scaling is supported, attempt to set TSC frequency.
775 */
776 if (kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL)) {
777 set_ioctl = true;
778 }
779
780 /*
781 * If desired TSC frequency is within bounds of NTP correction,
782 * attempt to set TSC frequency.
783 */
784 if (cur_freq != -ENOTSUP && freq_within_bounds(cur_freq, env->tsc_khz)) {
785 set_ioctl = true;
786 }
787
788 r = set_ioctl ?
789 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
790 -ENOTSUP;
791
792 if (r < 0) {
793 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
794 * TSC frequency doesn't match the one we want.
795 */
796 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
797 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
798 -ENOTSUP;
799 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
800 warn_report("TSC frequency mismatch between "
801 "VM (%" PRId64 " kHz) and host (%d kHz), "
802 "and TSC scaling unavailable",
803 env->tsc_khz, cur_freq);
804 return r;
805 }
806 }
807
808 return 0;
809 }
810
811 static bool tsc_is_stable_and_known(CPUX86State *env)
812 {
813 if (!env->tsc_khz) {
814 return false;
815 }
816 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
817 || env->user_tsc_khz;
818 }
819
820 static struct {
821 const char *desc;
822 struct {
823 uint32_t fw;
824 uint32_t bits;
825 } flags[2];
826 uint64_t dependencies;
827 } kvm_hyperv_properties[] = {
828 [HYPERV_FEAT_RELAXED] = {
829 .desc = "relaxed timing (hv-relaxed)",
830 .flags = {
831 {.fw = FEAT_HYPERV_EAX,
832 .bits = HV_HYPERCALL_AVAILABLE},
833 {.fw = FEAT_HV_RECOMM_EAX,
834 .bits = HV_RELAXED_TIMING_RECOMMENDED}
835 }
836 },
837 [HYPERV_FEAT_VAPIC] = {
838 .desc = "virtual APIC (hv-vapic)",
839 .flags = {
840 {.fw = FEAT_HYPERV_EAX,
841 .bits = HV_HYPERCALL_AVAILABLE | HV_APIC_ACCESS_AVAILABLE},
842 {.fw = FEAT_HV_RECOMM_EAX,
843 .bits = HV_APIC_ACCESS_RECOMMENDED}
844 }
845 },
846 [HYPERV_FEAT_TIME] = {
847 .desc = "clocksources (hv-time)",
848 .flags = {
849 {.fw = FEAT_HYPERV_EAX,
850 .bits = HV_HYPERCALL_AVAILABLE | HV_TIME_REF_COUNT_AVAILABLE |
851 HV_REFERENCE_TSC_AVAILABLE}
852 }
853 },
854 [HYPERV_FEAT_CRASH] = {
855 .desc = "crash MSRs (hv-crash)",
856 .flags = {
857 {.fw = FEAT_HYPERV_EDX,
858 .bits = HV_GUEST_CRASH_MSR_AVAILABLE}
859 }
860 },
861 [HYPERV_FEAT_RESET] = {
862 .desc = "reset MSR (hv-reset)",
863 .flags = {
864 {.fw = FEAT_HYPERV_EAX,
865 .bits = HV_RESET_AVAILABLE}
866 }
867 },
868 [HYPERV_FEAT_VPINDEX] = {
869 .desc = "VP_INDEX MSR (hv-vpindex)",
870 .flags = {
871 {.fw = FEAT_HYPERV_EAX,
872 .bits = HV_VP_INDEX_AVAILABLE}
873 }
874 },
875 [HYPERV_FEAT_RUNTIME] = {
876 .desc = "VP_RUNTIME MSR (hv-runtime)",
877 .flags = {
878 {.fw = FEAT_HYPERV_EAX,
879 .bits = HV_VP_RUNTIME_AVAILABLE}
880 }
881 },
882 [HYPERV_FEAT_SYNIC] = {
883 .desc = "synthetic interrupt controller (hv-synic)",
884 .flags = {
885 {.fw = FEAT_HYPERV_EAX,
886 .bits = HV_SYNIC_AVAILABLE}
887 }
888 },
889 [HYPERV_FEAT_STIMER] = {
890 .desc = "synthetic timers (hv-stimer)",
891 .flags = {
892 {.fw = FEAT_HYPERV_EAX,
893 .bits = HV_SYNTIMERS_AVAILABLE}
894 },
895 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME)
896 },
897 [HYPERV_FEAT_FREQUENCIES] = {
898 .desc = "frequency MSRs (hv-frequencies)",
899 .flags = {
900 {.fw = FEAT_HYPERV_EAX,
901 .bits = HV_ACCESS_FREQUENCY_MSRS},
902 {.fw = FEAT_HYPERV_EDX,
903 .bits = HV_FREQUENCY_MSRS_AVAILABLE}
904 }
905 },
906 [HYPERV_FEAT_REENLIGHTENMENT] = {
907 .desc = "reenlightenment MSRs (hv-reenlightenment)",
908 .flags = {
909 {.fw = FEAT_HYPERV_EAX,
910 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL}
911 }
912 },
913 [HYPERV_FEAT_TLBFLUSH] = {
914 .desc = "paravirtualized TLB flush (hv-tlbflush)",
915 .flags = {
916 {.fw = FEAT_HV_RECOMM_EAX,
917 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED |
918 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
919 },
920 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
921 },
922 [HYPERV_FEAT_EVMCS] = {
923 .desc = "enlightened VMCS (hv-evmcs)",
924 .flags = {
925 {.fw = FEAT_HV_RECOMM_EAX,
926 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED}
927 },
928 .dependencies = BIT(HYPERV_FEAT_VAPIC)
929 },
930 [HYPERV_FEAT_IPI] = {
931 .desc = "paravirtualized IPI (hv-ipi)",
932 .flags = {
933 {.fw = FEAT_HV_RECOMM_EAX,
934 .bits = HV_CLUSTER_IPI_RECOMMENDED |
935 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
936 },
937 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
938 },
939 [HYPERV_FEAT_STIMER_DIRECT] = {
940 .desc = "direct mode synthetic timers (hv-stimer-direct)",
941 .flags = {
942 {.fw = FEAT_HYPERV_EDX,
943 .bits = HV_STIMER_DIRECT_MODE_AVAILABLE}
944 },
945 .dependencies = BIT(HYPERV_FEAT_STIMER)
946 },
947 };
948
949 static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max)
950 {
951 struct kvm_cpuid2 *cpuid;
952 int r, size;
953
954 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
955 cpuid = g_malloc0(size);
956 cpuid->nent = max;
957
958 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
959 if (r == 0 && cpuid->nent >= max) {
960 r = -E2BIG;
961 }
962 if (r < 0) {
963 if (r == -E2BIG) {
964 g_free(cpuid);
965 return NULL;
966 } else {
967 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
968 strerror(-r));
969 exit(1);
970 }
971 }
972 return cpuid;
973 }
974
975 /*
976 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
977 * for all entries.
978 */
979 static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs)
980 {
981 struct kvm_cpuid2 *cpuid;
982 int max = 7; /* 0x40000000..0x40000005, 0x4000000A */
983
984 /*
985 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
986 * -E2BIG, however, it doesn't report back the right size. Keep increasing
987 * it and re-trying until we succeed.
988 */
989 while ((cpuid = try_get_hv_cpuid(cs, max)) == NULL) {
990 max++;
991 }
992 return cpuid;
993 }
994
995 /*
996 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
997 * leaves from KVM_CAP_HYPERV* and present MSRs data.
998 */
999 static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs)
1000 {
1001 X86CPU *cpu = X86_CPU(cs);
1002 struct kvm_cpuid2 *cpuid;
1003 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm;
1004
1005 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
1006 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries));
1007 cpuid->nent = 2;
1008
1009 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
1010 entry_feat = &cpuid->entries[0];
1011 entry_feat->function = HV_CPUID_FEATURES;
1012
1013 entry_recomm = &cpuid->entries[1];
1014 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO;
1015 entry_recomm->ebx = cpu->hyperv_spinlock_attempts;
1016
1017 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) {
1018 entry_feat->eax |= HV_HYPERCALL_AVAILABLE;
1019 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE;
1020 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1021 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED;
1022 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED;
1023 }
1024
1025 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
1026 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE;
1027 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE;
1028 }
1029
1030 if (has_msr_hv_frequencies) {
1031 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
1032 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE;
1033 }
1034
1035 if (has_msr_hv_crash) {
1036 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE;
1037 }
1038
1039 if (has_msr_hv_reenlightenment) {
1040 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
1041 }
1042
1043 if (has_msr_hv_reset) {
1044 entry_feat->eax |= HV_RESET_AVAILABLE;
1045 }
1046
1047 if (has_msr_hv_vpindex) {
1048 entry_feat->eax |= HV_VP_INDEX_AVAILABLE;
1049 }
1050
1051 if (has_msr_hv_runtime) {
1052 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE;
1053 }
1054
1055 if (has_msr_hv_synic) {
1056 unsigned int cap = cpu->hyperv_synic_kvm_only ?
1057 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1058
1059 if (kvm_check_extension(cs->kvm_state, cap) > 0) {
1060 entry_feat->eax |= HV_SYNIC_AVAILABLE;
1061 }
1062 }
1063
1064 if (has_msr_hv_stimer) {
1065 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE;
1066 }
1067
1068 if (kvm_check_extension(cs->kvm_state,
1069 KVM_CAP_HYPERV_TLBFLUSH) > 0) {
1070 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
1071 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1072 }
1073
1074 if (kvm_check_extension(cs->kvm_state,
1075 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
1076 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
1077 }
1078
1079 if (kvm_check_extension(cs->kvm_state,
1080 KVM_CAP_HYPERV_SEND_IPI) > 0) {
1081 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED;
1082 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1083 }
1084
1085 return cpuid;
1086 }
1087
1088 static int hv_cpuid_get_fw(struct kvm_cpuid2 *cpuid, int fw, uint32_t *r)
1089 {
1090 struct kvm_cpuid_entry2 *entry;
1091 uint32_t func;
1092 int reg;
1093
1094 switch (fw) {
1095 case FEAT_HYPERV_EAX:
1096 reg = R_EAX;
1097 func = HV_CPUID_FEATURES;
1098 break;
1099 case FEAT_HYPERV_EDX:
1100 reg = R_EDX;
1101 func = HV_CPUID_FEATURES;
1102 break;
1103 case FEAT_HV_RECOMM_EAX:
1104 reg = R_EAX;
1105 func = HV_CPUID_ENLIGHTMENT_INFO;
1106 break;
1107 default:
1108 return -EINVAL;
1109 }
1110
1111 entry = cpuid_find_entry(cpuid, func, 0);
1112 if (!entry) {
1113 return -ENOENT;
1114 }
1115
1116 switch (reg) {
1117 case R_EAX:
1118 *r = entry->eax;
1119 break;
1120 case R_EDX:
1121 *r = entry->edx;
1122 break;
1123 default:
1124 return -EINVAL;
1125 }
1126
1127 return 0;
1128 }
1129
1130 static int hv_cpuid_check_and_set(CPUState *cs, struct kvm_cpuid2 *cpuid,
1131 int feature)
1132 {
1133 X86CPU *cpu = X86_CPU(cs);
1134 CPUX86State *env = &cpu->env;
1135 uint32_t r, fw, bits;
1136 uint64_t deps;
1137 int i, dep_feat;
1138
1139 if (!hyperv_feat_enabled(cpu, feature) && !cpu->hyperv_passthrough) {
1140 return 0;
1141 }
1142
1143 deps = kvm_hyperv_properties[feature].dependencies;
1144 while (deps) {
1145 dep_feat = ctz64(deps);
1146 if (!(hyperv_feat_enabled(cpu, dep_feat))) {
1147 fprintf(stderr,
1148 "Hyper-V %s requires Hyper-V %s\n",
1149 kvm_hyperv_properties[feature].desc,
1150 kvm_hyperv_properties[dep_feat].desc);
1151 return 1;
1152 }
1153 deps &= ~(1ull << dep_feat);
1154 }
1155
1156 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) {
1157 fw = kvm_hyperv_properties[feature].flags[i].fw;
1158 bits = kvm_hyperv_properties[feature].flags[i].bits;
1159
1160 if (!fw) {
1161 continue;
1162 }
1163
1164 if (hv_cpuid_get_fw(cpuid, fw, &r) || (r & bits) != bits) {
1165 if (hyperv_feat_enabled(cpu, feature)) {
1166 fprintf(stderr,
1167 "Hyper-V %s is not supported by kernel\n",
1168 kvm_hyperv_properties[feature].desc);
1169 return 1;
1170 } else {
1171 return 0;
1172 }
1173 }
1174
1175 env->features[fw] |= bits;
1176 }
1177
1178 if (cpu->hyperv_passthrough) {
1179 cpu->hyperv_features |= BIT(feature);
1180 }
1181
1182 return 0;
1183 }
1184
1185 /*
1186 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent in
1187 * case of success, errno < 0 in case of failure and 0 when no Hyper-V
1188 * extentions are enabled.
1189 */
1190 static int hyperv_handle_properties(CPUState *cs,
1191 struct kvm_cpuid_entry2 *cpuid_ent)
1192 {
1193 X86CPU *cpu = X86_CPU(cs);
1194 CPUX86State *env = &cpu->env;
1195 struct kvm_cpuid2 *cpuid;
1196 struct kvm_cpuid_entry2 *c;
1197 uint32_t signature[3];
1198 uint32_t cpuid_i = 0;
1199 int r;
1200
1201 if (!hyperv_enabled(cpu))
1202 return 0;
1203
1204 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ||
1205 cpu->hyperv_passthrough) {
1206 uint16_t evmcs_version;
1207
1208 r = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
1209 (uintptr_t)&evmcs_version);
1210
1211 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) && r) {
1212 fprintf(stderr, "Hyper-V %s is not supported by kernel\n",
1213 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc);
1214 return -ENOSYS;
1215 }
1216
1217 if (!r) {
1218 env->features[FEAT_HV_RECOMM_EAX] |=
1219 HV_ENLIGHTENED_VMCS_RECOMMENDED;
1220 env->features[FEAT_HV_NESTED_EAX] = evmcs_version;
1221 }
1222 }
1223
1224 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_CPUID) > 0) {
1225 cpuid = get_supported_hv_cpuid(cs);
1226 } else {
1227 cpuid = get_supported_hv_cpuid_legacy(cs);
1228 }
1229
1230 if (cpu->hyperv_passthrough) {
1231 memcpy(cpuid_ent, &cpuid->entries[0],
1232 cpuid->nent * sizeof(cpuid->entries[0]));
1233
1234 c = cpuid_find_entry(cpuid, HV_CPUID_FEATURES, 0);
1235 if (c) {
1236 env->features[FEAT_HYPERV_EAX] = c->eax;
1237 env->features[FEAT_HYPERV_EBX] = c->ebx;
1238 env->features[FEAT_HYPERV_EDX] = c->eax;
1239 }
1240 c = cpuid_find_entry(cpuid, HV_CPUID_ENLIGHTMENT_INFO, 0);
1241 if (c) {
1242 env->features[FEAT_HV_RECOMM_EAX] = c->eax;
1243
1244 /* hv-spinlocks may have been overriden */
1245 if (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) {
1246 c->ebx = cpu->hyperv_spinlock_attempts;
1247 }
1248 }
1249 c = cpuid_find_entry(cpuid, HV_CPUID_NESTED_FEATURES, 0);
1250 if (c) {
1251 env->features[FEAT_HV_NESTED_EAX] = c->eax;
1252 }
1253 }
1254
1255 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_ON) {
1256 env->features[FEAT_HV_RECOMM_EAX] |= HV_NO_NONARCH_CORESHARING;
1257 } else if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO) {
1258 c = cpuid_find_entry(cpuid, HV_CPUID_ENLIGHTMENT_INFO, 0);
1259 if (c) {
1260 env->features[FEAT_HV_RECOMM_EAX] |=
1261 c->eax & HV_NO_NONARCH_CORESHARING;
1262 }
1263 }
1264
1265 /* Features */
1266 r = hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RELAXED);
1267 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VAPIC);
1268 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TIME);
1269 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_CRASH);
1270 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RESET);
1271 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VPINDEX);
1272 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RUNTIME);
1273 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_SYNIC);
1274 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_STIMER);
1275 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_FREQUENCIES);
1276 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_REENLIGHTENMENT);
1277 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TLBFLUSH);
1278 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_EVMCS);
1279 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_IPI);
1280 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_STIMER_DIRECT);
1281
1282 /* Additional dependencies not covered by kvm_hyperv_properties[] */
1283 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1284 !cpu->hyperv_synic_kvm_only &&
1285 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
1286 fprintf(stderr, "Hyper-V %s requires Hyper-V %s\n",
1287 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc,
1288 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc);
1289 r |= 1;
1290 }
1291
1292 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1293 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1294
1295 if (r) {
1296 r = -ENOSYS;
1297 goto free;
1298 }
1299
1300 if (cpu->hyperv_passthrough) {
1301 /* We already copied all feature words from KVM as is */
1302 r = cpuid->nent;
1303 goto free;
1304 }
1305
1306 c = &cpuid_ent[cpuid_i++];
1307 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1308 if (!cpu->hyperv_vendor_id) {
1309 memcpy(signature, "Microsoft Hv", 12);
1310 } else {
1311 size_t len = strlen(cpu->hyperv_vendor_id);
1312
1313 if (len > 12) {
1314 error_report("hv-vendor-id truncated to 12 characters");
1315 len = 12;
1316 }
1317 memset(signature, 0, 12);
1318 memcpy(signature, cpu->hyperv_vendor_id, len);
1319 }
1320 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
1321 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
1322 c->ebx = signature[0];
1323 c->ecx = signature[1];
1324 c->edx = signature[2];
1325
1326 c = &cpuid_ent[cpuid_i++];
1327 c->function = HV_CPUID_INTERFACE;
1328 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
1329 c->eax = signature[0];
1330 c->ebx = 0;
1331 c->ecx = 0;
1332 c->edx = 0;
1333
1334 c = &cpuid_ent[cpuid_i++];
1335 c->function = HV_CPUID_VERSION;
1336 c->eax = 0x00001bbc;
1337 c->ebx = 0x00060001;
1338
1339 c = &cpuid_ent[cpuid_i++];
1340 c->function = HV_CPUID_FEATURES;
1341 c->eax = env->features[FEAT_HYPERV_EAX];
1342 c->ebx = env->features[FEAT_HYPERV_EBX];
1343 c->edx = env->features[FEAT_HYPERV_EDX];
1344
1345 c = &cpuid_ent[cpuid_i++];
1346 c->function = HV_CPUID_ENLIGHTMENT_INFO;
1347 c->eax = env->features[FEAT_HV_RECOMM_EAX];
1348 c->ebx = cpu->hyperv_spinlock_attempts;
1349
1350 c = &cpuid_ent[cpuid_i++];
1351 c->function = HV_CPUID_IMPLEMENT_LIMITS;
1352 c->eax = cpu->hv_max_vps;
1353 c->ebx = 0x40;
1354
1355 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1356 __u32 function;
1357
1358 /* Create zeroed 0x40000006..0x40000009 leaves */
1359 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1360 function < HV_CPUID_NESTED_FEATURES; function++) {
1361 c = &cpuid_ent[cpuid_i++];
1362 c->function = function;
1363 }
1364
1365 c = &cpuid_ent[cpuid_i++];
1366 c->function = HV_CPUID_NESTED_FEATURES;
1367 c->eax = env->features[FEAT_HV_NESTED_EAX];
1368 }
1369 r = cpuid_i;
1370
1371 free:
1372 g_free(cpuid);
1373
1374 return r;
1375 }
1376
1377 static Error *hv_passthrough_mig_blocker;
1378 static Error *hv_no_nonarch_cs_mig_blocker;
1379
1380 static int hyperv_init_vcpu(X86CPU *cpu)
1381 {
1382 CPUState *cs = CPU(cpu);
1383 Error *local_err = NULL;
1384 int ret;
1385
1386 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) {
1387 error_setg(&hv_passthrough_mig_blocker,
1388 "'hv-passthrough' CPU flag prevents migration, use explicit"
1389 " set of hv-* flags instead");
1390 ret = migrate_add_blocker(hv_passthrough_mig_blocker, &local_err);
1391 if (local_err) {
1392 error_report_err(local_err);
1393 error_free(hv_passthrough_mig_blocker);
1394 return ret;
1395 }
1396 }
1397
1398 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO &&
1399 hv_no_nonarch_cs_mig_blocker == NULL) {
1400 error_setg(&hv_no_nonarch_cs_mig_blocker,
1401 "'hv-no-nonarch-coresharing=auto' CPU flag prevents migration"
1402 " use explicit 'hv-no-nonarch-coresharing=on' instead (but"
1403 " make sure SMT is disabled and/or that vCPUs are properly"
1404 " pinned)");
1405 ret = migrate_add_blocker(hv_no_nonarch_cs_mig_blocker, &local_err);
1406 if (local_err) {
1407 error_report_err(local_err);
1408 error_free(hv_no_nonarch_cs_mig_blocker);
1409 return ret;
1410 }
1411 }
1412
1413 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
1414 /*
1415 * the kernel doesn't support setting vp_index; assert that its value
1416 * is in sync
1417 */
1418 struct {
1419 struct kvm_msrs info;
1420 struct kvm_msr_entry entries[1];
1421 } msr_data = {
1422 .info.nmsrs = 1,
1423 .entries[0].index = HV_X64_MSR_VP_INDEX,
1424 };
1425
1426 ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
1427 if (ret < 0) {
1428 return ret;
1429 }
1430 assert(ret == 1);
1431
1432 if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
1433 error_report("kernel's vp_index != QEMU's vp_index");
1434 return -ENXIO;
1435 }
1436 }
1437
1438 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
1439 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
1440 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1441 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
1442 if (ret < 0) {
1443 error_report("failed to turn on HyperV SynIC in KVM: %s",
1444 strerror(-ret));
1445 return ret;
1446 }
1447
1448 if (!cpu->hyperv_synic_kvm_only) {
1449 ret = hyperv_x86_synic_add(cpu);
1450 if (ret < 0) {
1451 error_report("failed to create HyperV SynIC: %s",
1452 strerror(-ret));
1453 return ret;
1454 }
1455 }
1456 }
1457
1458 return 0;
1459 }
1460
1461 static Error *invtsc_mig_blocker;
1462
1463 #define KVM_MAX_CPUID_ENTRIES 100
1464
1465 int kvm_arch_init_vcpu(CPUState *cs)
1466 {
1467 struct {
1468 struct kvm_cpuid2 cpuid;
1469 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
1470 } cpuid_data;
1471 /*
1472 * The kernel defines these structs with padding fields so there
1473 * should be no extra padding in our cpuid_data struct.
1474 */
1475 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
1476 sizeof(struct kvm_cpuid2) +
1477 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
1478
1479 X86CPU *cpu = X86_CPU(cs);
1480 CPUX86State *env = &cpu->env;
1481 uint32_t limit, i, j, cpuid_i;
1482 uint32_t unused;
1483 struct kvm_cpuid_entry2 *c;
1484 uint32_t signature[3];
1485 int kvm_base = KVM_CPUID_SIGNATURE;
1486 int max_nested_state_len;
1487 int r;
1488 Error *local_err = NULL;
1489
1490 memset(&cpuid_data, 0, sizeof(cpuid_data));
1491
1492 cpuid_i = 0;
1493
1494 r = kvm_arch_set_tsc_khz(cs);
1495 if (r < 0) {
1496 return r;
1497 }
1498
1499 /* vcpu's TSC frequency is either specified by user, or following
1500 * the value used by KVM if the former is not present. In the
1501 * latter case, we query it from KVM and record in env->tsc_khz,
1502 * so that vcpu's TSC frequency can be migrated later via this field.
1503 */
1504 if (!env->tsc_khz) {
1505 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
1506 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
1507 -ENOTSUP;
1508 if (r > 0) {
1509 env->tsc_khz = r;
1510 }
1511 }
1512
1513 env->apic_bus_freq = KVM_APIC_BUS_FREQUENCY;
1514
1515 /* Paravirtualization CPUIDs */
1516 r = hyperv_handle_properties(cs, cpuid_data.entries);
1517 if (r < 0) {
1518 return r;
1519 } else if (r > 0) {
1520 cpuid_i = r;
1521 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
1522 has_msr_hv_hypercall = true;
1523 }
1524
1525 if (cpu->expose_kvm) {
1526 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1527 c = &cpuid_data.entries[cpuid_i++];
1528 c->function = KVM_CPUID_SIGNATURE | kvm_base;
1529 c->eax = KVM_CPUID_FEATURES | kvm_base;
1530 c->ebx = signature[0];
1531 c->ecx = signature[1];
1532 c->edx = signature[2];
1533
1534 c = &cpuid_data.entries[cpuid_i++];
1535 c->function = KVM_CPUID_FEATURES | kvm_base;
1536 c->eax = env->features[FEAT_KVM];
1537 c->edx = env->features[FEAT_KVM_HINTS];
1538 }
1539
1540 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
1541
1542 for (i = 0; i <= limit; i++) {
1543 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1544 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1545 abort();
1546 }
1547 c = &cpuid_data.entries[cpuid_i++];
1548
1549 switch (i) {
1550 case 2: {
1551 /* Keep reading function 2 till all the input is received */
1552 int times;
1553
1554 c->function = i;
1555 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1556 KVM_CPUID_FLAG_STATE_READ_NEXT;
1557 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1558 times = c->eax & 0xff;
1559
1560 for (j = 1; j < times; ++j) {
1561 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1562 fprintf(stderr, "cpuid_data is full, no space for "
1563 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1564 abort();
1565 }
1566 c = &cpuid_data.entries[cpuid_i++];
1567 c->function = i;
1568 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1569 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1570 }
1571 break;
1572 }
1573 case 0x1f:
1574 if (env->nr_dies < 2) {
1575 break;
1576 }
1577 case 4:
1578 case 0xb:
1579 case 0xd:
1580 for (j = 0; ; j++) {
1581 if (i == 0xd && j == 64) {
1582 break;
1583 }
1584
1585 if (i == 0x1f && j == 64) {
1586 break;
1587 }
1588
1589 c->function = i;
1590 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1591 c->index = j;
1592 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1593
1594 if (i == 4 && c->eax == 0) {
1595 break;
1596 }
1597 if (i == 0xb && !(c->ecx & 0xff00)) {
1598 break;
1599 }
1600 if (i == 0x1f && !(c->ecx & 0xff00)) {
1601 break;
1602 }
1603 if (i == 0xd && c->eax == 0) {
1604 continue;
1605 }
1606 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1607 fprintf(stderr, "cpuid_data is full, no space for "
1608 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1609 abort();
1610 }
1611 c = &cpuid_data.entries[cpuid_i++];
1612 }
1613 break;
1614 case 0x7:
1615 case 0x14: {
1616 uint32_t times;
1617
1618 c->function = i;
1619 c->index = 0;
1620 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1621 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1622 times = c->eax;
1623
1624 for (j = 1; j <= times; ++j) {
1625 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1626 fprintf(stderr, "cpuid_data is full, no space for "
1627 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1628 abort();
1629 }
1630 c = &cpuid_data.entries[cpuid_i++];
1631 c->function = i;
1632 c->index = j;
1633 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1634 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1635 }
1636 break;
1637 }
1638 default:
1639 c->function = i;
1640 c->flags = 0;
1641 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1642 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
1643 /*
1644 * KVM already returns all zeroes if a CPUID entry is missing,
1645 * so we can omit it and avoid hitting KVM's 80-entry limit.
1646 */
1647 cpuid_i--;
1648 }
1649 break;
1650 }
1651 }
1652
1653 if (limit >= 0x0a) {
1654 uint32_t eax, edx;
1655
1656 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1657
1658 has_architectural_pmu_version = eax & 0xff;
1659 if (has_architectural_pmu_version > 0) {
1660 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
1661
1662 /* Shouldn't be more than 32, since that's the number of bits
1663 * available in EBX to tell us _which_ counters are available.
1664 * Play it safe.
1665 */
1666 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1667 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1668 }
1669
1670 if (has_architectural_pmu_version > 1) {
1671 num_architectural_pmu_fixed_counters = edx & 0x1f;
1672
1673 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1674 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1675 }
1676 }
1677 }
1678 }
1679
1680 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
1681
1682 for (i = 0x80000000; i <= limit; i++) {
1683 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1684 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1685 abort();
1686 }
1687 c = &cpuid_data.entries[cpuid_i++];
1688
1689 switch (i) {
1690 case 0x8000001d:
1691 /* Query for all AMD cache information leaves */
1692 for (j = 0; ; j++) {
1693 c->function = i;
1694 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1695 c->index = j;
1696 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1697
1698 if (c->eax == 0) {
1699 break;
1700 }
1701 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1702 fprintf(stderr, "cpuid_data is full, no space for "
1703 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1704 abort();
1705 }
1706 c = &cpuid_data.entries[cpuid_i++];
1707 }
1708 break;
1709 default:
1710 c->function = i;
1711 c->flags = 0;
1712 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1713 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
1714 /*
1715 * KVM already returns all zeroes if a CPUID entry is missing,
1716 * so we can omit it and avoid hitting KVM's 80-entry limit.
1717 */
1718 cpuid_i--;
1719 }
1720 break;
1721 }
1722 }
1723
1724 /* Call Centaur's CPUID instructions they are supported. */
1725 if (env->cpuid_xlevel2 > 0) {
1726 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1727
1728 for (i = 0xC0000000; i <= limit; i++) {
1729 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1730 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1731 abort();
1732 }
1733 c = &cpuid_data.entries[cpuid_i++];
1734
1735 c->function = i;
1736 c->flags = 0;
1737 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1738 }
1739 }
1740
1741 cpuid_data.cpuid.nent = cpuid_i;
1742
1743 if (((env->cpuid_version >> 8)&0xF) >= 6
1744 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
1745 (CPUID_MCE | CPUID_MCA)
1746 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
1747 uint64_t mcg_cap, unsupported_caps;
1748 int banks;
1749 int ret;
1750
1751 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
1752 if (ret < 0) {
1753 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1754 return ret;
1755 }
1756
1757 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
1758 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
1759 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
1760 return -ENOTSUP;
1761 }
1762
1763 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1764 if (unsupported_caps) {
1765 if (unsupported_caps & MCG_LMCE_P) {
1766 error_report("kvm: LMCE not supported");
1767 return -ENOTSUP;
1768 }
1769 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1770 unsupported_caps);
1771 }
1772
1773 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1774 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
1775 if (ret < 0) {
1776 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1777 return ret;
1778 }
1779 }
1780
1781 cpu->vmsentry = qemu_add_vm_change_state_handler(cpu_update_state, env);
1782
1783 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1784 if (c) {
1785 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1786 !!(c->ecx & CPUID_EXT_SMX);
1787 }
1788
1789 if (env->mcg_cap & MCG_LMCE_P) {
1790 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1791 }
1792
1793 if (!env->user_tsc_khz) {
1794 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1795 invtsc_mig_blocker == NULL) {
1796 error_setg(&invtsc_mig_blocker,
1797 "State blocked by non-migratable CPU device"
1798 " (invtsc flag)");
1799 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1800 if (local_err) {
1801 error_report_err(local_err);
1802 error_free(invtsc_mig_blocker);
1803 return r;
1804 }
1805 }
1806 }
1807
1808 if (cpu->vmware_cpuid_freq
1809 /* Guests depend on 0x40000000 to detect this feature, so only expose
1810 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1811 && cpu->expose_kvm
1812 && kvm_base == KVM_CPUID_SIGNATURE
1813 /* TSC clock must be stable and known for this feature. */
1814 && tsc_is_stable_and_known(env)) {
1815
1816 c = &cpuid_data.entries[cpuid_i++];
1817 c->function = KVM_CPUID_SIGNATURE | 0x10;
1818 c->eax = env->tsc_khz;
1819 c->ebx = env->apic_bus_freq / 1000; /* Hz to KHz */
1820 c->ecx = c->edx = 0;
1821
1822 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1823 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1824 }
1825
1826 cpuid_data.cpuid.nent = cpuid_i;
1827
1828 cpuid_data.cpuid.padding = 0;
1829 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1830 if (r) {
1831 goto fail;
1832 }
1833
1834 if (has_xsave) {
1835 env->xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1836 memset(env->xsave_buf, 0, sizeof(struct kvm_xsave));
1837 }
1838
1839 max_nested_state_len = kvm_max_nested_state_length();
1840 if (max_nested_state_len > 0) {
1841 assert(max_nested_state_len >= offsetof(struct kvm_nested_state, data));
1842
1843 if (cpu_has_vmx(env)) {
1844 struct kvm_vmx_nested_state_hdr *vmx_hdr;
1845
1846 env->nested_state = g_malloc0(max_nested_state_len);
1847 env->nested_state->size = max_nested_state_len;
1848 env->nested_state->format = KVM_STATE_NESTED_FORMAT_VMX;
1849
1850 vmx_hdr = &env->nested_state->hdr.vmx;
1851 vmx_hdr->vmxon_pa = -1ull;
1852 vmx_hdr->vmcs12_pa = -1ull;
1853 }
1854 }
1855
1856 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
1857
1858 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1859 has_msr_tsc_aux = false;
1860 }
1861
1862 kvm_init_msrs(cpu);
1863
1864 r = hyperv_init_vcpu(cpu);
1865 if (r) {
1866 goto fail;
1867 }
1868
1869 return 0;
1870
1871 fail:
1872 migrate_del_blocker(invtsc_mig_blocker);
1873
1874 return r;
1875 }
1876
1877 int kvm_arch_destroy_vcpu(CPUState *cs)
1878 {
1879 X86CPU *cpu = X86_CPU(cs);
1880 CPUX86State *env = &cpu->env;
1881
1882 if (cpu->kvm_msr_buf) {
1883 g_free(cpu->kvm_msr_buf);
1884 cpu->kvm_msr_buf = NULL;
1885 }
1886
1887 if (env->nested_state) {
1888 g_free(env->nested_state);
1889 env->nested_state = NULL;
1890 }
1891
1892 qemu_del_vm_change_state_handler(cpu->vmsentry);
1893
1894 return 0;
1895 }
1896
1897 void kvm_arch_reset_vcpu(X86CPU *cpu)
1898 {
1899 CPUX86State *env = &cpu->env;
1900
1901 env->xcr0 = 1;
1902 if (kvm_irqchip_in_kernel()) {
1903 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
1904 KVM_MP_STATE_UNINITIALIZED;
1905 } else {
1906 env->mp_state = KVM_MP_STATE_RUNNABLE;
1907 }
1908
1909 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
1910 int i;
1911 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1912 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1913 }
1914
1915 hyperv_x86_synic_reset(cpu);
1916 }
1917 /* enabled by default */
1918 env->poll_control_msr = 1;
1919 }
1920
1921 void kvm_arch_do_init_vcpu(X86CPU *cpu)
1922 {
1923 CPUX86State *env = &cpu->env;
1924
1925 /* APs get directly into wait-for-SIPI state. */
1926 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1927 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1928 }
1929 }
1930
1931 static int kvm_get_supported_feature_msrs(KVMState *s)
1932 {
1933 int ret = 0;
1934
1935 if (kvm_feature_msrs != NULL) {
1936 return 0;
1937 }
1938
1939 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
1940 return 0;
1941 }
1942
1943 struct kvm_msr_list msr_list;
1944
1945 msr_list.nmsrs = 0;
1946 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
1947 if (ret < 0 && ret != -E2BIG) {
1948 error_report("Fetch KVM feature MSR list failed: %s",
1949 strerror(-ret));
1950 return ret;
1951 }
1952
1953 assert(msr_list.nmsrs > 0);
1954 kvm_feature_msrs = (struct kvm_msr_list *) \
1955 g_malloc0(sizeof(msr_list) +
1956 msr_list.nmsrs * sizeof(msr_list.indices[0]));
1957
1958 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
1959 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
1960
1961 if (ret < 0) {
1962 error_report("Fetch KVM feature MSR list failed: %s",
1963 strerror(-ret));
1964 g_free(kvm_feature_msrs);
1965 kvm_feature_msrs = NULL;
1966 return ret;
1967 }
1968
1969 return 0;
1970 }
1971
1972 static int kvm_get_supported_msrs(KVMState *s)
1973 {
1974 int ret = 0;
1975 struct kvm_msr_list msr_list, *kvm_msr_list;
1976
1977 /*
1978 * Obtain MSR list from KVM. These are the MSRs that we must
1979 * save/restore.
1980 */
1981 msr_list.nmsrs = 0;
1982 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1983 if (ret < 0 && ret != -E2BIG) {
1984 return ret;
1985 }
1986 /*
1987 * Old kernel modules had a bug and could write beyond the provided
1988 * memory. Allocate at least a safe amount of 1K.
1989 */
1990 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1991 msr_list.nmsrs *
1992 sizeof(msr_list.indices[0])));
1993
1994 kvm_msr_list->nmsrs = msr_list.nmsrs;
1995 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1996 if (ret >= 0) {
1997 int i;
1998
1999 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
2000 switch (kvm_msr_list->indices[i]) {
2001 case MSR_STAR:
2002 has_msr_star = true;
2003 break;
2004 case MSR_VM_HSAVE_PA:
2005 has_msr_hsave_pa = true;
2006 break;
2007 case MSR_TSC_AUX:
2008 has_msr_tsc_aux = true;
2009 break;
2010 case MSR_TSC_ADJUST:
2011 has_msr_tsc_adjust = true;
2012 break;
2013 case MSR_IA32_TSCDEADLINE:
2014 has_msr_tsc_deadline = true;
2015 break;
2016 case MSR_IA32_SMBASE:
2017 has_msr_smbase = true;
2018 break;
2019 case MSR_SMI_COUNT:
2020 has_msr_smi_count = true;
2021 break;
2022 case MSR_IA32_MISC_ENABLE:
2023 has_msr_misc_enable = true;
2024 break;
2025 case MSR_IA32_BNDCFGS:
2026 has_msr_bndcfgs = true;
2027 break;
2028 case MSR_IA32_XSS:
2029 has_msr_xss = true;
2030 break;
2031 case MSR_IA32_UMWAIT_CONTROL:
2032 has_msr_umwait = true;
2033 break;
2034 case HV_X64_MSR_CRASH_CTL:
2035 has_msr_hv_crash = true;
2036 break;
2037 case HV_X64_MSR_RESET:
2038 has_msr_hv_reset = true;
2039 break;
2040 case HV_X64_MSR_VP_INDEX:
2041 has_msr_hv_vpindex = true;
2042 break;
2043 case HV_X64_MSR_VP_RUNTIME:
2044 has_msr_hv_runtime = true;
2045 break;
2046 case HV_X64_MSR_SCONTROL:
2047 has_msr_hv_synic = true;
2048 break;
2049 case HV_X64_MSR_STIMER0_CONFIG:
2050 has_msr_hv_stimer = true;
2051 break;
2052 case HV_X64_MSR_TSC_FREQUENCY:
2053 has_msr_hv_frequencies = true;
2054 break;
2055 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2056 has_msr_hv_reenlightenment = true;
2057 break;
2058 case MSR_IA32_SPEC_CTRL:
2059 has_msr_spec_ctrl = true;
2060 break;
2061 case MSR_IA32_TSX_CTRL:
2062 has_msr_tsx_ctrl = true;
2063 break;
2064 case MSR_VIRT_SSBD:
2065 has_msr_virt_ssbd = true;
2066 break;
2067 case MSR_IA32_ARCH_CAPABILITIES:
2068 has_msr_arch_capabs = true;
2069 break;
2070 case MSR_IA32_CORE_CAPABILITY:
2071 has_msr_core_capabs = true;
2072 break;
2073 case MSR_IA32_PERF_CAPABILITIES:
2074 has_msr_perf_capabs = true;
2075 break;
2076 case MSR_IA32_VMX_VMFUNC:
2077 has_msr_vmx_vmfunc = true;
2078 break;
2079 case MSR_IA32_UCODE_REV:
2080 has_msr_ucode_rev = true;
2081 break;
2082 case MSR_IA32_VMX_PROCBASED_CTLS2:
2083 has_msr_vmx_procbased_ctls2 = true;
2084 break;
2085 }
2086 }
2087 }
2088
2089 g_free(kvm_msr_list);
2090
2091 return ret;
2092 }
2093
2094 static Notifier smram_machine_done;
2095 static KVMMemoryListener smram_listener;
2096 static AddressSpace smram_address_space;
2097 static MemoryRegion smram_as_root;
2098 static MemoryRegion smram_as_mem;
2099
2100 static void register_smram_listener(Notifier *n, void *unused)
2101 {
2102 MemoryRegion *smram =
2103 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2104
2105 /* Outer container... */
2106 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
2107 memory_region_set_enabled(&smram_as_root, true);
2108
2109 /* ... with two regions inside: normal system memory with low
2110 * priority, and...
2111 */
2112 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
2113 get_system_memory(), 0, ~0ull);
2114 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
2115 memory_region_set_enabled(&smram_as_mem, true);
2116
2117 if (smram) {
2118 /* ... SMRAM with higher priority */
2119 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
2120 memory_region_set_enabled(smram, true);
2121 }
2122
2123 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
2124 kvm_memory_listener_register(kvm_state, &smram_listener,
2125 &smram_address_space, 1);
2126 }
2127
2128 int kvm_arch_init(MachineState *ms, KVMState *s)
2129 {
2130 uint64_t identity_base = 0xfffbc000;
2131 uint64_t shadow_mem;
2132 int ret;
2133 struct utsname utsname;
2134
2135 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
2136 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
2137 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
2138
2139 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
2140
2141 has_exception_payload = kvm_check_extension(s, KVM_CAP_EXCEPTION_PAYLOAD);
2142 if (has_exception_payload) {
2143 ret = kvm_vm_enable_cap(s, KVM_CAP_EXCEPTION_PAYLOAD, 0, true);
2144 if (ret < 0) {
2145 error_report("kvm: Failed to enable exception payload cap: %s",
2146 strerror(-ret));
2147 return ret;
2148 }
2149 }
2150
2151 ret = kvm_get_supported_msrs(s);
2152 if (ret < 0) {
2153 return ret;
2154 }
2155
2156 kvm_get_supported_feature_msrs(s);
2157
2158 uname(&utsname);
2159 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
2160
2161 /*
2162 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
2163 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
2164 * Since these must be part of guest physical memory, we need to allocate
2165 * them, both by setting their start addresses in the kernel and by
2166 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
2167 *
2168 * Older KVM versions may not support setting the identity map base. In
2169 * that case we need to stick with the default, i.e. a 256K maximum BIOS
2170 * size.
2171 */
2172 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
2173 /* Allows up to 16M BIOSes. */
2174 identity_base = 0xfeffc000;
2175
2176 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
2177 if (ret < 0) {
2178 return ret;
2179 }
2180 }
2181
2182 /* Set TSS base one page after EPT identity map. */
2183 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
2184 if (ret < 0) {
2185 return ret;
2186 }
2187
2188 /* Tell fw_cfg to notify the BIOS to reserve the range. */
2189 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
2190 if (ret < 0) {
2191 fprintf(stderr, "e820_add_entry() table is full\n");
2192 return ret;
2193 }
2194
2195 shadow_mem = object_property_get_int(OBJECT(s), "kvm-shadow-mem", &error_abort);
2196 if (shadow_mem != -1) {
2197 shadow_mem /= 4096;
2198 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
2199 if (ret < 0) {
2200 return ret;
2201 }
2202 }
2203
2204 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
2205 object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE) &&
2206 x86_machine_is_smm_enabled(X86_MACHINE(ms))) {
2207 smram_machine_done.notify = register_smram_listener;
2208 qemu_add_machine_init_done_notifier(&smram_machine_done);
2209 }
2210
2211 if (enable_cpu_pm) {
2212 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
2213 int ret;
2214
2215 /* Work around for kernel header with a typo. TODO: fix header and drop. */
2216 #if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
2217 #define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
2218 #endif
2219 if (disable_exits) {
2220 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
2221 KVM_X86_DISABLE_EXITS_HLT |
2222 KVM_X86_DISABLE_EXITS_PAUSE |
2223 KVM_X86_DISABLE_EXITS_CSTATE);
2224 }
2225
2226 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
2227 disable_exits);
2228 if (ret < 0) {
2229 error_report("kvm: guest stopping CPU not supported: %s",
2230 strerror(-ret));
2231 }
2232 }
2233
2234 return 0;
2235 }
2236
2237 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2238 {
2239 lhs->selector = rhs->selector;
2240 lhs->base = rhs->base;
2241 lhs->limit = rhs->limit;
2242 lhs->type = 3;
2243 lhs->present = 1;
2244 lhs->dpl = 3;
2245 lhs->db = 0;
2246 lhs->s = 1;
2247 lhs->l = 0;
2248 lhs->g = 0;
2249 lhs->avl = 0;
2250 lhs->unusable = 0;
2251 }
2252
2253 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2254 {
2255 unsigned flags = rhs->flags;
2256 lhs->selector = rhs->selector;
2257 lhs->base = rhs->base;
2258 lhs->limit = rhs->limit;
2259 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
2260 lhs->present = (flags & DESC_P_MASK) != 0;
2261 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
2262 lhs->db = (flags >> DESC_B_SHIFT) & 1;
2263 lhs->s = (flags & DESC_S_MASK) != 0;
2264 lhs->l = (flags >> DESC_L_SHIFT) & 1;
2265 lhs->g = (flags & DESC_G_MASK) != 0;
2266 lhs->avl = (flags & DESC_AVL_MASK) != 0;
2267 lhs->unusable = !lhs->present;
2268 lhs->padding = 0;
2269 }
2270
2271 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
2272 {
2273 lhs->selector = rhs->selector;
2274 lhs->base = rhs->base;
2275 lhs->limit = rhs->limit;
2276 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
2277 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
2278 (rhs->dpl << DESC_DPL_SHIFT) |
2279 (rhs->db << DESC_B_SHIFT) |
2280 (rhs->s * DESC_S_MASK) |
2281 (rhs->l << DESC_L_SHIFT) |
2282 (rhs->g * DESC_G_MASK) |
2283 (rhs->avl * DESC_AVL_MASK);
2284 }
2285
2286 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
2287 {
2288 if (set) {
2289 *kvm_reg = *qemu_reg;
2290 } else {
2291 *qemu_reg = *kvm_reg;
2292 }
2293 }
2294
2295 static int kvm_getput_regs(X86CPU *cpu, int set)
2296 {
2297 CPUX86State *env = &cpu->env;
2298 struct kvm_regs regs;
2299 int ret = 0;
2300
2301 if (!set) {
2302 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
2303 if (ret < 0) {
2304 return ret;
2305 }
2306 }
2307
2308 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
2309 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
2310 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
2311 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
2312 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
2313 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
2314 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
2315 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
2316 #ifdef TARGET_X86_64
2317 kvm_getput_reg(&regs.r8, &env->regs[8], set);
2318 kvm_getput_reg(&regs.r9, &env->regs[9], set);
2319 kvm_getput_reg(&regs.r10, &env->regs[10], set);
2320 kvm_getput_reg(&regs.r11, &env->regs[11], set);
2321 kvm_getput_reg(&regs.r12, &env->regs[12], set);
2322 kvm_getput_reg(&regs.r13, &env->regs[13], set);
2323 kvm_getput_reg(&regs.r14, &env->regs[14], set);
2324 kvm_getput_reg(&regs.r15, &env->regs[15], set);
2325 #endif
2326
2327 kvm_getput_reg(&regs.rflags, &env->eflags, set);
2328 kvm_getput_reg(&regs.rip, &env->eip, set);
2329
2330 if (set) {
2331 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
2332 }
2333
2334 return ret;
2335 }
2336
2337 static int kvm_put_fpu(X86CPU *cpu)
2338 {
2339 CPUX86State *env = &cpu->env;
2340 struct kvm_fpu fpu;
2341 int i;
2342
2343 memset(&fpu, 0, sizeof fpu);
2344 fpu.fsw = env->fpus & ~(7 << 11);
2345 fpu.fsw |= (env->fpstt & 7) << 11;
2346 fpu.fcw = env->fpuc;
2347 fpu.last_opcode = env->fpop;
2348 fpu.last_ip = env->fpip;
2349 fpu.last_dp = env->fpdp;
2350 for (i = 0; i < 8; ++i) {
2351 fpu.ftwx |= (!env->fptags[i]) << i;
2352 }
2353 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
2354 for (i = 0; i < CPU_NB_REGS; i++) {
2355 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
2356 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
2357 }
2358 fpu.mxcsr = env->mxcsr;
2359
2360 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
2361 }
2362
2363 #define XSAVE_FCW_FSW 0
2364 #define XSAVE_FTW_FOP 1
2365 #define XSAVE_CWD_RIP 2
2366 #define XSAVE_CWD_RDP 4
2367 #define XSAVE_MXCSR 6
2368 #define XSAVE_ST_SPACE 8
2369 #define XSAVE_XMM_SPACE 40
2370 #define XSAVE_XSTATE_BV 128
2371 #define XSAVE_YMMH_SPACE 144
2372 #define XSAVE_BNDREGS 240
2373 #define XSAVE_BNDCSR 256
2374 #define XSAVE_OPMASK 272
2375 #define XSAVE_ZMM_Hi256 288
2376 #define XSAVE_Hi16_ZMM 416
2377 #define XSAVE_PKRU 672
2378
2379 #define XSAVE_BYTE_OFFSET(word_offset) \
2380 ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
2381
2382 #define ASSERT_OFFSET(word_offset, field) \
2383 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
2384 offsetof(X86XSaveArea, field))
2385
2386 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
2387 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
2388 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
2389 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
2390 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
2391 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
2392 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
2393 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
2394 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
2395 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
2396 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
2397 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
2398 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
2399 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
2400 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
2401
2402 static int kvm_put_xsave(X86CPU *cpu)
2403 {
2404 CPUX86State *env = &cpu->env;
2405 X86XSaveArea *xsave = env->xsave_buf;
2406
2407 if (!has_xsave) {
2408 return kvm_put_fpu(cpu);
2409 }
2410 x86_cpu_xsave_all_areas(cpu, xsave);
2411
2412 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
2413 }
2414
2415 static int kvm_put_xcrs(X86CPU *cpu)
2416 {
2417 CPUX86State *env = &cpu->env;
2418 struct kvm_xcrs xcrs = {};
2419
2420 if (!has_xcrs) {
2421 return 0;
2422 }
2423
2424 xcrs.nr_xcrs = 1;
2425 xcrs.flags = 0;
2426 xcrs.xcrs[0].xcr = 0;
2427 xcrs.xcrs[0].value = env->xcr0;
2428 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
2429 }
2430
2431 static int kvm_put_sregs(X86CPU *cpu)
2432 {
2433 CPUX86State *env = &cpu->env;
2434 struct kvm_sregs sregs;
2435
2436 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
2437 if (env->interrupt_injected >= 0) {
2438 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
2439 (uint64_t)1 << (env->interrupt_injected % 64);
2440 }
2441
2442 if ((env->eflags & VM_MASK)) {
2443 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
2444 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
2445 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
2446 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
2447 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
2448 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
2449 } else {
2450 set_seg(&sregs.cs, &env->segs[R_CS]);
2451 set_seg(&sregs.ds, &env->segs[R_DS]);
2452 set_seg(&sregs.es, &env->segs[R_ES]);
2453 set_seg(&sregs.fs, &env->segs[R_FS]);
2454 set_seg(&sregs.gs, &env->segs[R_GS]);
2455 set_seg(&sregs.ss, &env->segs[R_SS]);
2456 }
2457
2458 set_seg(&sregs.tr, &env->tr);
2459 set_seg(&sregs.ldt, &env->ldt);
2460
2461 sregs.idt.limit = env->idt.limit;
2462 sregs.idt.base = env->idt.base;
2463 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
2464 sregs.gdt.limit = env->gdt.limit;
2465 sregs.gdt.base = env->gdt.base;
2466 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
2467
2468 sregs.cr0 = env->cr[0];
2469 sregs.cr2 = env->cr[2];
2470 sregs.cr3 = env->cr[3];
2471 sregs.cr4 = env->cr[4];
2472
2473 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
2474 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
2475
2476 sregs.efer = env->efer;
2477
2478 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
2479 }
2480
2481 static void kvm_msr_buf_reset(X86CPU *cpu)
2482 {
2483 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
2484 }
2485
2486 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
2487 {
2488 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
2489 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
2490 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
2491
2492 assert((void *)(entry + 1) <= limit);
2493
2494 entry->index = index;
2495 entry->reserved = 0;
2496 entry->data = value;
2497 msrs->nmsrs++;
2498 }
2499
2500 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
2501 {
2502 kvm_msr_buf_reset(cpu);
2503 kvm_msr_entry_add(cpu, index, value);
2504
2505 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2506 }
2507
2508 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
2509 {
2510 int ret;
2511
2512 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
2513 assert(ret == 1);
2514 }
2515
2516 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
2517 {
2518 CPUX86State *env = &cpu->env;
2519 int ret;
2520
2521 if (!has_msr_tsc_deadline) {
2522 return 0;
2523 }
2524
2525 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
2526 if (ret < 0) {
2527 return ret;
2528 }
2529
2530 assert(ret == 1);
2531 return 0;
2532 }
2533
2534 /*
2535 * Provide a separate write service for the feature control MSR in order to
2536 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
2537 * before writing any other state because forcibly leaving nested mode
2538 * invalidates the VCPU state.
2539 */
2540 static int kvm_put_msr_feature_control(X86CPU *cpu)
2541 {
2542 int ret;
2543
2544 if (!has_msr_feature_control) {
2545 return 0;
2546 }
2547
2548 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
2549 cpu->env.msr_ia32_feature_control);
2550 if (ret < 0) {
2551 return ret;
2552 }
2553
2554 assert(ret == 1);
2555 return 0;
2556 }
2557
2558 static uint64_t make_vmx_msr_value(uint32_t index, uint32_t features)
2559 {
2560 uint32_t default1, can_be_one, can_be_zero;
2561 uint32_t must_be_one;
2562
2563 switch (index) {
2564 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2565 default1 = 0x00000016;
2566 break;
2567 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2568 default1 = 0x0401e172;
2569 break;
2570 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2571 default1 = 0x000011ff;
2572 break;
2573 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2574 default1 = 0x00036dff;
2575 break;
2576 case MSR_IA32_VMX_PROCBASED_CTLS2:
2577 default1 = 0;
2578 break;
2579 default:
2580 abort();
2581 }
2582
2583 /* If a feature bit is set, the control can be either set or clear.
2584 * Otherwise the value is limited to either 0 or 1 by default1.
2585 */
2586 can_be_one = features | default1;
2587 can_be_zero = features | ~default1;
2588 must_be_one = ~can_be_zero;
2589
2590 /*
2591 * Bit 0:31 -> 0 if the control bit can be zero (i.e. 1 if it must be one).
2592 * Bit 32:63 -> 1 if the control bit can be one.
2593 */
2594 return must_be_one | (((uint64_t)can_be_one) << 32);
2595 }
2596
2597 #define VMCS12_MAX_FIELD_INDEX (0x17)
2598
2599 static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f)
2600 {
2601 uint64_t kvm_vmx_basic =
2602 kvm_arch_get_supported_msr_feature(kvm_state,
2603 MSR_IA32_VMX_BASIC);
2604
2605 if (!kvm_vmx_basic) {
2606 /* If the kernel doesn't support VMX feature (kvm_intel.nested=0),
2607 * then kvm_vmx_basic will be 0 and KVM_SET_MSR will fail.
2608 */
2609 return;
2610 }
2611
2612 uint64_t kvm_vmx_misc =
2613 kvm_arch_get_supported_msr_feature(kvm_state,
2614 MSR_IA32_VMX_MISC);
2615 uint64_t kvm_vmx_ept_vpid =
2616 kvm_arch_get_supported_msr_feature(kvm_state,
2617 MSR_IA32_VMX_EPT_VPID_CAP);
2618
2619 /*
2620 * If the guest is 64-bit, a value of 1 is allowed for the host address
2621 * space size vmexit control.
2622 */
2623 uint64_t fixed_vmx_exit = f[FEAT_8000_0001_EDX] & CPUID_EXT2_LM
2624 ? (uint64_t)VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE << 32 : 0;
2625
2626 /*
2627 * Bits 0-30, 32-44 and 50-53 come from the host. KVM should
2628 * not change them for backwards compatibility.
2629 */
2630 uint64_t fixed_vmx_basic = kvm_vmx_basic &
2631 (MSR_VMX_BASIC_VMCS_REVISION_MASK |
2632 MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK |
2633 MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK);
2634
2635 /*
2636 * Same for bits 0-4 and 25-27. Bits 16-24 (CR3 target count) can
2637 * change in the future but are always zero for now, clear them to be
2638 * future proof. Bits 32-63 in theory could change, though KVM does
2639 * not support dual-monitor treatment and probably never will; mask
2640 * them out as well.
2641 */
2642 uint64_t fixed_vmx_misc = kvm_vmx_misc &
2643 (MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK |
2644 MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK);
2645
2646 /*
2647 * EPT memory types should not change either, so we do not bother
2648 * adding features for them.
2649 */
2650 uint64_t fixed_vmx_ept_mask =
2651 (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_ENABLE_EPT ?
2652 MSR_VMX_EPT_UC | MSR_VMX_EPT_WB : 0);
2653 uint64_t fixed_vmx_ept_vpid = kvm_vmx_ept_vpid & fixed_vmx_ept_mask;
2654
2655 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
2656 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
2657 f[FEAT_VMX_PROCBASED_CTLS]));
2658 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PINBASED_CTLS,
2659 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PINBASED_CTLS,
2660 f[FEAT_VMX_PINBASED_CTLS]));
2661 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_EXIT_CTLS,
2662 make_vmx_msr_value(MSR_IA32_VMX_TRUE_EXIT_CTLS,
2663 f[FEAT_VMX_EXIT_CTLS]) | fixed_vmx_exit);
2664 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_ENTRY_CTLS,
2665 make_vmx_msr_value(MSR_IA32_VMX_TRUE_ENTRY_CTLS,
2666 f[FEAT_VMX_ENTRY_CTLS]));
2667 kvm_msr_entry_add(cpu, MSR_IA32_VMX_PROCBASED_CTLS2,
2668 make_vmx_msr_value(MSR_IA32_VMX_PROCBASED_CTLS2,
2669 f[FEAT_VMX_SECONDARY_CTLS]));
2670 kvm_msr_entry_add(cpu, MSR_IA32_VMX_EPT_VPID_CAP,
2671 f[FEAT_VMX_EPT_VPID_CAPS] | fixed_vmx_ept_vpid);
2672 kvm_msr_entry_add(cpu, MSR_IA32_VMX_BASIC,
2673 f[FEAT_VMX_BASIC] | fixed_vmx_basic);
2674 kvm_msr_entry_add(cpu, MSR_IA32_VMX_MISC,
2675 f[FEAT_VMX_MISC] | fixed_vmx_misc);
2676 if (has_msr_vmx_vmfunc) {
2677 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMFUNC, f[FEAT_VMX_VMFUNC]);
2678 }
2679
2680 /*
2681 * Just to be safe, write these with constant values. The CRn_FIXED1
2682 * MSRs are generated by KVM based on the vCPU's CPUID.
2683 */
2684 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR0_FIXED0,
2685 CR0_PE_MASK | CR0_PG_MASK | CR0_NE_MASK);
2686 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR4_FIXED0,
2687 CR4_VMXE_MASK);
2688 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM,
2689 VMCS12_MAX_FIELD_INDEX << 1);
2690 }
2691
2692 static void kvm_msr_entry_add_perf(X86CPU *cpu, FeatureWordArray f)
2693 {
2694 uint64_t kvm_perf_cap =
2695 kvm_arch_get_supported_msr_feature(kvm_state,
2696 MSR_IA32_PERF_CAPABILITIES);
2697
2698 if (kvm_perf_cap) {
2699 kvm_msr_entry_add(cpu, MSR_IA32_PERF_CAPABILITIES,
2700 kvm_perf_cap & f[FEAT_PERF_CAPABILITIES]);
2701 }
2702 }
2703
2704 static int kvm_buf_set_msrs(X86CPU *cpu)
2705 {
2706 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2707 if (ret < 0) {
2708 return ret;
2709 }
2710
2711 if (ret < cpu->kvm_msr_buf->nmsrs) {
2712 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2713 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2714 (uint32_t)e->index, (uint64_t)e->data);
2715 }
2716
2717 assert(ret == cpu->kvm_msr_buf->nmsrs);
2718 return 0;
2719 }
2720
2721 static void kvm_init_msrs(X86CPU *cpu)
2722 {
2723 CPUX86State *env = &cpu->env;
2724
2725 kvm_msr_buf_reset(cpu);
2726 if (has_msr_arch_capabs) {
2727 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
2728 env->features[FEAT_ARCH_CAPABILITIES]);
2729 }
2730
2731 if (has_msr_core_capabs) {
2732 kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
2733 env->features[FEAT_CORE_CAPABILITY]);
2734 }
2735
2736 if (has_msr_perf_capabs && cpu->enable_pmu) {
2737 kvm_msr_entry_add_perf(cpu, env->features);
2738 }
2739
2740 if (has_msr_ucode_rev) {
2741 kvm_msr_entry_add(cpu, MSR_IA32_UCODE_REV, cpu->ucode_rev);
2742 }
2743
2744 /*
2745 * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but
2746 * all kernels with MSR features should have them.
2747 */
2748 if (kvm_feature_msrs && cpu_has_vmx(env)) {
2749 kvm_msr_entry_add_vmx(cpu, env->features);
2750 }
2751
2752 assert(kvm_buf_set_msrs(cpu) == 0);
2753 }
2754
2755 static int kvm_put_msrs(X86CPU *cpu, int level)
2756 {
2757 CPUX86State *env = &cpu->env;
2758 int i;
2759
2760 kvm_msr_buf_reset(cpu);
2761
2762 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
2763 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
2764 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
2765 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
2766 if (has_msr_star) {
2767 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
2768 }
2769 if (has_msr_hsave_pa) {
2770 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
2771 }
2772 if (has_msr_tsc_aux) {
2773 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
2774 }
2775 if (has_msr_tsc_adjust) {
2776 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
2777 }
2778 if (has_msr_misc_enable) {
2779 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
2780 env->msr_ia32_misc_enable);
2781 }
2782 if (has_msr_smbase) {
2783 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
2784 }
2785 if (has_msr_smi_count) {
2786 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
2787 }
2788 if (has_msr_bndcfgs) {
2789 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
2790 }
2791 if (has_msr_xss) {
2792 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
2793 }
2794 if (has_msr_umwait) {
2795 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, env->umwait);
2796 }
2797 if (has_msr_spec_ctrl) {
2798 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
2799 }
2800 if (has_msr_tsx_ctrl) {
2801 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, env->tsx_ctrl);
2802 }
2803 if (has_msr_virt_ssbd) {
2804 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
2805 }
2806
2807 #ifdef TARGET_X86_64
2808 if (lm_capable_kernel) {
2809 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
2810 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
2811 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
2812 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
2813 }
2814 #endif
2815
2816 /*
2817 * The following MSRs have side effects on the guest or are too heavy
2818 * for normal writeback. Limit them to reset or full state updates.
2819 */
2820 if (level >= KVM_PUT_RESET_STATE) {
2821 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
2822 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
2823 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
2824 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2825 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
2826 }
2827 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2828 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
2829 }
2830 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2831 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
2832 }
2833
2834 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
2835 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, env->poll_control_msr);
2836 }
2837
2838 if (has_architectural_pmu_version > 0) {
2839 if (has_architectural_pmu_version > 1) {
2840 /* Stop the counter. */
2841 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2842 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2843 }
2844
2845 /* Set the counter values. */
2846 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
2847 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
2848 env->msr_fixed_counters[i]);
2849 }
2850 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
2851 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
2852 env->msr_gp_counters[i]);
2853 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
2854 env->msr_gp_evtsel[i]);
2855 }
2856 if (has_architectural_pmu_version > 1) {
2857 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
2858 env->msr_global_status);
2859 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
2860 env->msr_global_ovf_ctrl);
2861
2862 /* Now start the PMU. */
2863 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
2864 env->msr_fixed_ctr_ctrl);
2865 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
2866 env->msr_global_ctrl);
2867 }
2868 }
2869 /*
2870 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
2871 * only sync them to KVM on the first cpu
2872 */
2873 if (current_cpu == first_cpu) {
2874 if (has_msr_hv_hypercall) {
2875 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
2876 env->msr_hv_guest_os_id);
2877 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
2878 env->msr_hv_hypercall);
2879 }
2880 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
2881 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
2882 env->msr_hv_tsc);
2883 }
2884 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
2885 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
2886 env->msr_hv_reenlightenment_control);
2887 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
2888 env->msr_hv_tsc_emulation_control);
2889 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
2890 env->msr_hv_tsc_emulation_status);
2891 }
2892 }
2893 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
2894 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
2895 env->msr_hv_vapic);
2896 }
2897 if (has_msr_hv_crash) {
2898 int j;
2899
2900 for (j = 0; j < HV_CRASH_PARAMS; j++)
2901 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
2902 env->msr_hv_crash_params[j]);
2903
2904 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
2905 }
2906 if (has_msr_hv_runtime) {
2907 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
2908 }
2909 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)
2910 && hv_vpindex_settable) {
2911 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
2912 hyperv_vp_index(CPU(cpu)));
2913 }
2914 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
2915 int j;
2916
2917 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
2918
2919 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
2920 env->msr_hv_synic_control);
2921 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
2922 env->msr_hv_synic_evt_page);
2923 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
2924 env->msr_hv_synic_msg_page);
2925
2926 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
2927 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
2928 env->msr_hv_synic_sint[j]);
2929 }
2930 }
2931 if (has_msr_hv_stimer) {
2932 int j;
2933
2934 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
2935 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
2936 env->msr_hv_stimer_config[j]);
2937 }
2938
2939 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
2940 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
2941 env->msr_hv_stimer_count[j]);
2942 }
2943 }
2944 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2945 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
2946
2947 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
2948 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
2949 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
2950 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
2951 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
2952 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
2953 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
2954 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
2955 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
2956 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
2957 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
2958 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
2959 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2960 /* The CPU GPs if we write to a bit above the physical limit of
2961 * the host CPU (and KVM emulates that)
2962 */
2963 uint64_t mask = env->mtrr_var[i].mask;
2964 mask &= phys_mask;
2965
2966 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
2967 env->mtrr_var[i].base);
2968 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
2969 }
2970 }
2971 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2972 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
2973 0x14, 1, R_EAX) & 0x7;
2974
2975 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
2976 env->msr_rtit_ctrl);
2977 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
2978 env->msr_rtit_status);
2979 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
2980 env->msr_rtit_output_base);
2981 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
2982 env->msr_rtit_output_mask);
2983 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
2984 env->msr_rtit_cr3_match);
2985 for (i = 0; i < addr_num; i++) {
2986 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
2987 env->msr_rtit_addrs[i]);
2988 }
2989 }
2990
2991 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
2992 * kvm_put_msr_feature_control. */
2993 }
2994
2995 if (env->mcg_cap) {
2996 int i;
2997
2998 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
2999 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
3000 if (has_msr_mcg_ext_ctl) {
3001 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
3002 }
3003 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
3004 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
3005 }
3006 }
3007
3008 return kvm_buf_set_msrs(cpu);
3009 }
3010
3011
3012 static int kvm_get_fpu(X86CPU *cpu)
3013 {
3014 CPUX86State *env = &cpu->env;
3015 struct kvm_fpu fpu;
3016 int i, ret;
3017
3018 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
3019 if (ret < 0) {
3020 return ret;
3021 }
3022
3023 env->fpstt = (fpu.fsw >> 11) & 7;
3024 env->fpus = fpu.fsw;
3025 env->fpuc = fpu.fcw;
3026 env->fpop = fpu.last_opcode;
3027 env->fpip = fpu.last_ip;
3028 env->fpdp = fpu.last_dp;
3029 for (i = 0; i < 8; ++i) {
3030 env->fptags[i] = !((fpu.ftwx >> i) & 1);
3031 }
3032 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
3033 for (i = 0; i < CPU_NB_REGS; i++) {
3034 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
3035 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
3036 }
3037 env->mxcsr = fpu.mxcsr;
3038
3039 return 0;
3040 }
3041
3042 static int kvm_get_xsave(X86CPU *cpu)
3043 {
3044 CPUX86State *env = &cpu->env;
3045 X86XSaveArea *xsave = env->xsave_buf;
3046 int ret;
3047
3048 if (!has_xsave) {
3049 return kvm_get_fpu(cpu);
3050 }
3051
3052 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
3053 if (ret < 0) {
3054 return ret;
3055 }
3056 x86_cpu_xrstor_all_areas(cpu, xsave);
3057
3058 return 0;
3059 }
3060
3061 static int kvm_get_xcrs(X86CPU *cpu)
3062 {
3063 CPUX86State *env = &cpu->env;
3064 int i, ret;
3065 struct kvm_xcrs xcrs;
3066
3067 if (!has_xcrs) {
3068 return 0;
3069 }
3070
3071 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
3072 if (ret < 0) {
3073 return ret;
3074 }
3075
3076 for (i = 0; i < xcrs.nr_xcrs; i++) {
3077 /* Only support xcr0 now */
3078 if (xcrs.xcrs[i].xcr == 0) {
3079 env->xcr0 = xcrs.xcrs[i].value;
3080 break;
3081 }
3082 }
3083 return 0;
3084 }
3085
3086 static int kvm_get_sregs(X86CPU *cpu)
3087 {
3088 CPUX86State *env = &cpu->env;
3089 struct kvm_sregs sregs;
3090 int bit, i, ret;
3091
3092 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
3093 if (ret < 0) {
3094 return ret;
3095 }
3096
3097 /* There can only be one pending IRQ set in the bitmap at a time, so try
3098 to find it and save its number instead (-1 for none). */
3099 env->interrupt_injected = -1;
3100 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
3101 if (sregs.interrupt_bitmap[i]) {
3102 bit = ctz64(sregs.interrupt_bitmap[i]);
3103 env->interrupt_injected = i * 64 + bit;
3104 break;
3105 }
3106 }
3107
3108 get_seg(&env->segs[R_CS], &sregs.cs);
3109 get_seg(&env->segs[R_DS], &sregs.ds);
3110 get_seg(&env->segs[R_ES], &sregs.es);
3111 get_seg(&env->segs[R_FS], &sregs.fs);
3112 get_seg(&env->segs[R_GS], &sregs.gs);
3113 get_seg(&env->segs[R_SS], &sregs.ss);
3114
3115 get_seg(&env->tr, &sregs.tr);
3116 get_seg(&env->ldt, &sregs.ldt);
3117
3118 env->idt.limit = sregs.idt.limit;
3119 env->idt.base = sregs.idt.base;
3120 env->gdt.limit = sregs.gdt.limit;
3121 env->gdt.base = sregs.gdt.base;
3122
3123 env->cr[0] = sregs.cr0;
3124 env->cr[2] = sregs.cr2;
3125 env->cr[3] = sregs.cr3;
3126 env->cr[4] = sregs.cr4;
3127
3128 env->efer = sregs.efer;
3129
3130 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
3131 x86_update_hflags(env);
3132
3133 return 0;
3134 }
3135
3136 static int kvm_get_msrs(X86CPU *cpu)
3137 {
3138 CPUX86State *env = &cpu->env;
3139 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
3140 int ret, i;
3141 uint64_t mtrr_top_bits;
3142
3143 kvm_msr_buf_reset(cpu);
3144
3145 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
3146 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
3147 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
3148 kvm_msr_entry_add(cpu, MSR_PAT, 0);
3149 if (has_msr_star) {
3150 kvm_msr_entry_add(cpu, MSR_STAR, 0);
3151 }
3152 if (has_msr_hsave_pa) {
3153 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
3154 }
3155 if (has_msr_tsc_aux) {
3156 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
3157 }
3158 if (has_msr_tsc_adjust) {
3159 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
3160 }
3161 if (has_msr_tsc_deadline) {
3162 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
3163 }
3164 if (has_msr_misc_enable) {
3165 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
3166 }
3167 if (has_msr_smbase) {
3168 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
3169 }
3170 if (has_msr_smi_count) {
3171 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
3172 }
3173 if (has_msr_feature_control) {
3174 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
3175 }
3176 if (has_msr_bndcfgs) {
3177 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
3178 }
3179 if (has_msr_xss) {
3180 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
3181 }
3182 if (has_msr_umwait) {
3183 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, 0);
3184 }
3185 if (has_msr_spec_ctrl) {
3186 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
3187 }
3188 if (has_msr_tsx_ctrl) {
3189 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, 0);
3190 }
3191 if (has_msr_virt_ssbd) {
3192 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
3193 }
3194 if (!env->tsc_valid) {
3195 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
3196 env->tsc_valid = !runstate_is_running();
3197 }
3198
3199 #ifdef TARGET_X86_64
3200 if (lm_capable_kernel) {
3201 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
3202 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
3203 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
3204 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
3205 }
3206 #endif
3207 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
3208 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
3209 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
3210 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
3211 }
3212 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
3213 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
3214 }
3215 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
3216 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
3217 }
3218 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
3219 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1);
3220 }
3221 if (has_architectural_pmu_version > 0) {
3222 if (has_architectural_pmu_version > 1) {
3223 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
3224 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
3225 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
3226 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
3227 }
3228 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
3229 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
3230 }
3231 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
3232 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
3233 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
3234 }
3235 }
3236
3237 if (env->mcg_cap) {
3238 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
3239 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
3240 if (has_msr_mcg_ext_ctl) {
3241 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
3242 }
3243 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
3244 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
3245 }
3246 }
3247
3248 if (has_msr_hv_hypercall) {
3249 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
3250 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
3251 }
3252 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
3253 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
3254 }
3255 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
3256 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
3257 }
3258 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
3259 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
3260 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
3261 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
3262 }
3263 if (has_msr_hv_crash) {
3264 int j;
3265
3266 for (j = 0; j < HV_CRASH_PARAMS; j++) {
3267 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
3268 }
3269 }
3270 if (has_msr_hv_runtime) {
3271 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
3272 }
3273 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
3274 uint32_t msr;
3275
3276 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
3277 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
3278 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
3279 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
3280 kvm_msr_entry_add(cpu, msr, 0);
3281 }
3282 }
3283 if (has_msr_hv_stimer) {
3284 uint32_t msr;
3285
3286 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
3287 msr++) {
3288 kvm_msr_entry_add(cpu, msr, 0);
3289 }
3290 }
3291 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
3292 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
3293 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
3294 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
3295 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
3296 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
3297 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
3298 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
3299 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
3300 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
3301 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
3302 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
3303 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
3304 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
3305 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
3306 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
3307 }
3308 }
3309
3310 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
3311 int addr_num =
3312 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
3313
3314 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
3315 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
3316 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
3317 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
3318 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
3319 for (i = 0; i < addr_num; i++) {
3320 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
3321 }
3322 }
3323
3324 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
3325 if (ret < 0) {
3326 return ret;
3327 }
3328
3329 if (ret < cpu->kvm_msr_buf->nmsrs) {
3330 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
3331 error_report("error: failed to get MSR 0x%" PRIx32,
3332 (uint32_t)e->index);
3333 }
3334
3335 assert(ret == cpu->kvm_msr_buf->nmsrs);
3336 /*
3337 * MTRR masks: Each mask consists of 5 parts
3338 * a 10..0: must be zero
3339 * b 11 : valid bit
3340 * c n-1.12: actual mask bits
3341 * d 51..n: reserved must be zero
3342 * e 63.52: reserved must be zero
3343 *
3344 * 'n' is the number of physical bits supported by the CPU and is
3345 * apparently always <= 52. We know our 'n' but don't know what
3346 * the destinations 'n' is; it might be smaller, in which case
3347 * it masks (c) on loading. It might be larger, in which case
3348 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
3349 * we're migrating to.
3350 */
3351
3352 if (cpu->fill_mtrr_mask) {
3353 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
3354 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
3355 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
3356 } else {
3357 mtrr_top_bits = 0;
3358 }
3359
3360 for (i = 0; i < ret; i++) {
3361 uint32_t index = msrs[i].index;
3362 switch (index) {
3363 case MSR_IA32_SYSENTER_CS:
3364 env->sysenter_cs = msrs[i].data;
3365 break;
3366 case MSR_IA32_SYSENTER_ESP:
3367 env->sysenter_esp = msrs[i].data;
3368 break;
3369 case MSR_IA32_SYSENTER_EIP:
3370 env->sysenter_eip = msrs[i].data;
3371 break;
3372 case MSR_PAT:
3373 env->pat = msrs[i].data;
3374 break;
3375 case MSR_STAR:
3376 env->star = msrs[i].data;
3377 break;
3378 #ifdef TARGET_X86_64
3379 case MSR_CSTAR:
3380 env->cstar = msrs[i].data;
3381 break;
3382 case MSR_KERNELGSBASE:
3383 env->kernelgsbase = msrs[i].data;
3384 break;
3385 case MSR_FMASK:
3386 env->fmask = msrs[i].data;
3387 break;
3388 case MSR_LSTAR:
3389 env->lstar = msrs[i].data;
3390 break;
3391 #endif
3392 case MSR_IA32_TSC:
3393 env->tsc = msrs[i].data;
3394 break;
3395 case MSR_TSC_AUX:
3396 env->tsc_aux = msrs[i].data;
3397 break;
3398 case MSR_TSC_ADJUST:
3399 env->tsc_adjust = msrs[i].data;
3400 break;
3401 case MSR_IA32_TSCDEADLINE:
3402 env->tsc_deadline = msrs[i].data;
3403 break;
3404 case MSR_VM_HSAVE_PA:
3405 env->vm_hsave = msrs[i].data;
3406 break;
3407 case MSR_KVM_SYSTEM_TIME:
3408 env->system_time_msr = msrs[i].data;
3409 break;
3410 case MSR_KVM_WALL_CLOCK:
3411 env->wall_clock_msr = msrs[i].data;
3412 break;
3413 case MSR_MCG_STATUS:
3414 env->mcg_status = msrs[i].data;
3415 break;
3416 case MSR_MCG_CTL:
3417 env->mcg_ctl = msrs[i].data;
3418 break;
3419 case MSR_MCG_EXT_CTL:
3420 env->mcg_ext_ctl = msrs[i].data;
3421 break;
3422 case MSR_IA32_MISC_ENABLE:
3423 env->msr_ia32_misc_enable = msrs[i].data;
3424 break;
3425 case MSR_IA32_SMBASE:
3426 env->smbase = msrs[i].data;
3427 break;
3428 case MSR_SMI_COUNT:
3429 env->msr_smi_count = msrs[i].data;
3430 break;
3431 case MSR_IA32_FEATURE_CONTROL:
3432 env->msr_ia32_feature_control = msrs[i].data;
3433 break;
3434 case MSR_IA32_BNDCFGS:
3435 env->msr_bndcfgs = msrs[i].data;
3436 break;
3437 case MSR_IA32_XSS:
3438 env->xss = msrs[i].data;
3439 break;
3440 case MSR_IA32_UMWAIT_CONTROL:
3441 env->umwait = msrs[i].data;
3442 break;
3443 default:
3444 if (msrs[i].index >= MSR_MC0_CTL &&
3445 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
3446 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
3447 }
3448 break;
3449 case MSR_KVM_ASYNC_PF_EN:
3450 env->async_pf_en_msr = msrs[i].data;
3451 break;
3452 case MSR_KVM_PV_EOI_EN:
3453 env->pv_eoi_en_msr = msrs[i].data;
3454 break;
3455 case MSR_KVM_STEAL_TIME:
3456 env->steal_time_msr = msrs[i].data;
3457 break;
3458 case MSR_KVM_POLL_CONTROL: {
3459 env->poll_control_msr = msrs[i].data;
3460 break;
3461 }
3462 case MSR_CORE_PERF_FIXED_CTR_CTRL:
3463 env->msr_fixed_ctr_ctrl = msrs[i].data;
3464 break;
3465 case MSR_CORE_PERF_GLOBAL_CTRL:
3466 env->msr_global_ctrl = msrs[i].data;
3467 break;
3468 case MSR_CORE_PERF_GLOBAL_STATUS:
3469 env->msr_global_status = msrs[i].data;
3470 break;
3471 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
3472 env->msr_global_ovf_ctrl = msrs[i].data;
3473 break;
3474 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
3475 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
3476 break;
3477 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
3478 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
3479 break;
3480 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
3481 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
3482 break;
3483 case HV_X64_MSR_HYPERCALL:
3484 env->msr_hv_hypercall = msrs[i].data;
3485 break;
3486 case HV_X64_MSR_GUEST_OS_ID:
3487 env->msr_hv_guest_os_id = msrs[i].data;
3488 break;
3489 case HV_X64_MSR_APIC_ASSIST_PAGE:
3490 env->msr_hv_vapic = msrs[i].data;
3491 break;
3492 case HV_X64_MSR_REFERENCE_TSC:
3493 env->msr_hv_tsc = msrs[i].data;
3494 break;
3495 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3496 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
3497 break;
3498 case HV_X64_MSR_VP_RUNTIME:
3499 env->msr_hv_runtime = msrs[i].data;
3500 break;
3501 case HV_X64_MSR_SCONTROL:
3502 env->msr_hv_synic_control = msrs[i].data;
3503 break;
3504 case HV_X64_MSR_SIEFP:
3505 env->msr_hv_synic_evt_page = msrs[i].data;
3506 break;
3507 case HV_X64_MSR_SIMP:
3508 env->msr_hv_synic_msg_page = msrs[i].data;
3509 break;
3510 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
3511 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
3512 break;
3513 case HV_X64_MSR_STIMER0_CONFIG:
3514 case HV_X64_MSR_STIMER1_CONFIG:
3515 case HV_X64_MSR_STIMER2_CONFIG:
3516 case HV_X64_MSR_STIMER3_CONFIG:
3517 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
3518 msrs[i].data;
3519 break;
3520 case HV_X64_MSR_STIMER0_COUNT:
3521 case HV_X64_MSR_STIMER1_COUNT:
3522 case HV_X64_MSR_STIMER2_COUNT:
3523 case HV_X64_MSR_STIMER3_COUNT:
3524 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
3525 msrs[i].data;
3526 break;
3527 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3528 env->msr_hv_reenlightenment_control = msrs[i].data;
3529 break;
3530 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3531 env->msr_hv_tsc_emulation_control = msrs[i].data;
3532 break;
3533 case HV_X64_MSR_TSC_EMULATION_STATUS:
3534 env->msr_hv_tsc_emulation_status = msrs[i].data;
3535 break;
3536 case MSR_MTRRdefType:
3537 env->mtrr_deftype = msrs[i].data;
3538 break;
3539 case MSR_MTRRfix64K_00000:
3540 env->mtrr_fixed[0] = msrs[i].data;
3541 break;
3542 case MSR_MTRRfix16K_80000:
3543 env->mtrr_fixed[1] = msrs[i].data;
3544 break;
3545 case MSR_MTRRfix16K_A0000:
3546 env->mtrr_fixed[2] = msrs[i].data;
3547 break;
3548 case MSR_MTRRfix4K_C0000:
3549 env->mtrr_fixed[3] = msrs[i].data;
3550 break;
3551 case MSR_MTRRfix4K_C8000:
3552 env->mtrr_fixed[4] = msrs[i].data;
3553 break;
3554 case MSR_MTRRfix4K_D0000:
3555 env->mtrr_fixed[5] = msrs[i].data;
3556 break;
3557 case MSR_MTRRfix4K_D8000:
3558 env->mtrr_fixed[6] = msrs[i].data;
3559 break;
3560 case MSR_MTRRfix4K_E0000:
3561 env->mtrr_fixed[7] = msrs[i].data;
3562 break;
3563 case MSR_MTRRfix4K_E8000:
3564 env->mtrr_fixed[8] = msrs[i].data;
3565 break;
3566 case MSR_MTRRfix4K_F0000:
3567 env->mtrr_fixed[9] = msrs[i].data;
3568 break;
3569 case MSR_MTRRfix4K_F8000:
3570 env->mtrr_fixed[10] = msrs[i].data;
3571 break;
3572 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
3573 if (index & 1) {
3574 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
3575 mtrr_top_bits;
3576 } else {
3577 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
3578 }
3579 break;
3580 case MSR_IA32_SPEC_CTRL:
3581 env->spec_ctrl = msrs[i].data;
3582 break;
3583 case MSR_IA32_TSX_CTRL:
3584 env->tsx_ctrl = msrs[i].data;
3585 break;
3586 case MSR_VIRT_SSBD:
3587 env->virt_ssbd = msrs[i].data;
3588 break;
3589 case MSR_IA32_RTIT_CTL:
3590 env->msr_rtit_ctrl = msrs[i].data;
3591 break;
3592 case MSR_IA32_RTIT_STATUS:
3593 env->msr_rtit_status = msrs[i].data;
3594 break;
3595 case MSR_IA32_RTIT_OUTPUT_BASE:
3596 env->msr_rtit_output_base = msrs[i].data;
3597 break;
3598 case MSR_IA32_RTIT_OUTPUT_MASK:
3599 env->msr_rtit_output_mask = msrs[i].data;
3600 break;
3601 case MSR_IA32_RTIT_CR3_MATCH:
3602 env->msr_rtit_cr3_match = msrs[i].data;
3603 break;
3604 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
3605 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
3606 break;
3607 }
3608 }
3609
3610 return 0;
3611 }
3612
3613 static int kvm_put_mp_state(X86CPU *cpu)
3614 {
3615 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
3616
3617 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
3618 }
3619
3620 static int kvm_get_mp_state(X86CPU *cpu)
3621 {
3622 CPUState *cs = CPU(cpu);
3623 CPUX86State *env = &cpu->env;
3624 struct kvm_mp_state mp_state;
3625 int ret;
3626
3627 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
3628 if (ret < 0) {
3629 return ret;
3630 }
3631 env->mp_state = mp_state.mp_state;
3632 if (kvm_irqchip_in_kernel()) {
3633 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
3634 }
3635 return 0;
3636 }
3637
3638 static int kvm_get_apic(X86CPU *cpu)
3639 {
3640 DeviceState *apic = cpu->apic_state;
3641 struct kvm_lapic_state kapic;
3642 int ret;
3643
3644 if (apic && kvm_irqchip_in_kernel()) {
3645 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
3646 if (ret < 0) {
3647 return ret;
3648 }
3649
3650 kvm_get_apic_state(apic, &kapic);
3651 }
3652 return 0;
3653 }
3654
3655 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
3656 {
3657 CPUState *cs = CPU(cpu);
3658 CPUX86State *env = &cpu->env;
3659 struct kvm_vcpu_events events = {};
3660
3661 if (!kvm_has_vcpu_events()) {
3662 return 0;
3663 }
3664
3665 events.flags = 0;
3666
3667 if (has_exception_payload) {
3668 events.flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3669 events.exception.pending = env->exception_pending;
3670 events.exception_has_payload = env->exception_has_payload;
3671 events.exception_payload = env->exception_payload;
3672 }
3673 events.exception.nr = env->exception_nr;
3674 events.exception.injected = env->exception_injected;
3675 events.exception.has_error_code = env->has_error_code;
3676 events.exception.error_code = env->error_code;
3677
3678 events.interrupt.injected = (env->interrupt_injected >= 0);
3679 events.interrupt.nr = env->interrupt_injected;
3680 events.interrupt.soft = env->soft_interrupt;
3681
3682 events.nmi.injected = env->nmi_injected;
3683 events.nmi.pending = env->nmi_pending;
3684 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
3685
3686 events.sipi_vector = env->sipi_vector;
3687
3688 if (has_msr_smbase) {
3689 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
3690 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
3691 if (kvm_irqchip_in_kernel()) {
3692 /* As soon as these are moved to the kernel, remove them
3693 * from cs->interrupt_request.
3694 */
3695 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
3696 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
3697 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
3698 } else {
3699 /* Keep these in cs->interrupt_request. */
3700 events.smi.pending = 0;
3701 events.smi.latched_init = 0;
3702 }
3703 /* Stop SMI delivery on old machine types to avoid a reboot
3704 * on an inward migration of an old VM.
3705 */
3706 if (!cpu->kvm_no_smi_migration) {
3707 events.flags |= KVM_VCPUEVENT_VALID_SMM;
3708 }
3709 }
3710
3711 if (level >= KVM_PUT_RESET_STATE) {
3712 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
3713 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
3714 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
3715 }
3716 }
3717
3718 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
3719 }
3720
3721 static int kvm_get_vcpu_events(X86CPU *cpu)
3722 {
3723 CPUX86State *env = &cpu->env;
3724 struct kvm_vcpu_events events;
3725 int ret;
3726
3727 if (!kvm_has_vcpu_events()) {
3728 return 0;
3729 }
3730
3731 memset(&events, 0, sizeof(events));
3732 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
3733 if (ret < 0) {
3734 return ret;
3735 }
3736
3737 if (events.flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3738 env->exception_pending = events.exception.pending;
3739 env->exception_has_payload = events.exception_has_payload;
3740 env->exception_payload = events.exception_payload;
3741 } else {
3742 env->exception_pending = 0;
3743 env->exception_has_payload = false;
3744 }
3745 env->exception_injected = events.exception.injected;
3746 env->exception_nr =
3747 (env->exception_pending || env->exception_injected) ?
3748 events.exception.nr : -1;
3749 env->has_error_code = events.exception.has_error_code;
3750 env->error_code = events.exception.error_code;
3751
3752 env->interrupt_injected =
3753 events.interrupt.injected ? events.interrupt.nr : -1;
3754 env->soft_interrupt = events.interrupt.soft;
3755
3756 env->nmi_injected = events.nmi.injected;
3757 env->nmi_pending = events.nmi.pending;
3758 if (events.nmi.masked) {
3759 env->hflags2 |= HF2_NMI_MASK;
3760 } else {
3761 env->hflags2 &= ~HF2_NMI_MASK;
3762 }
3763
3764 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
3765 if (events.smi.smm) {
3766 env->hflags |= HF_SMM_MASK;
3767 } else {
3768 env->hflags &= ~HF_SMM_MASK;
3769 }
3770 if (events.smi.pending) {
3771 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3772 } else {
3773 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3774 }
3775 if (events.smi.smm_inside_nmi) {
3776 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
3777 } else {
3778 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
3779 }
3780 if (events.smi.latched_init) {
3781 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3782 } else {
3783 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3784 }
3785 }
3786
3787 env->sipi_vector = events.sipi_vector;
3788
3789 return 0;
3790 }
3791
3792 static int kvm_guest_debug_workarounds(X86CPU *cpu)
3793 {
3794 CPUState *cs = CPU(cpu);
3795 CPUX86State *env = &cpu->env;
3796 int ret = 0;
3797 unsigned long reinject_trap = 0;
3798
3799 if (!kvm_has_vcpu_events()) {
3800 if (env->exception_nr == EXCP01_DB) {
3801 reinject_trap = KVM_GUESTDBG_INJECT_DB;
3802 } else if (env->exception_injected == EXCP03_INT3) {
3803 reinject_trap = KVM_GUESTDBG_INJECT_BP;
3804 }
3805 kvm_reset_exception(env);
3806 }
3807
3808 /*
3809 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
3810 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
3811 * by updating the debug state once again if single-stepping is on.
3812 * Another reason to call kvm_update_guest_debug here is a pending debug
3813 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
3814 * reinject them via SET_GUEST_DEBUG.
3815 */
3816 if (reinject_trap ||
3817 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
3818 ret = kvm_update_guest_debug(cs, reinject_trap);
3819 }
3820 return ret;
3821 }
3822
3823 static int kvm_put_debugregs(X86CPU *cpu)
3824 {
3825 CPUX86State *env = &cpu->env;
3826 struct kvm_debugregs dbgregs;
3827 int i;
3828
3829 if (!kvm_has_debugregs()) {
3830 return 0;
3831 }
3832
3833 memset(&dbgregs, 0, sizeof(dbgregs));
3834 for (i = 0; i < 4; i++) {
3835 dbgregs.db[i] = env->dr[i];
3836 }
3837 dbgregs.dr6 = env->dr[6];
3838 dbgregs.dr7 = env->dr[7];
3839 dbgregs.flags = 0;
3840
3841 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
3842 }
3843
3844 static int kvm_get_debugregs(X86CPU *cpu)
3845 {
3846 CPUX86State *env = &cpu->env;
3847 struct kvm_debugregs dbgregs;
3848 int i, ret;
3849
3850 if (!kvm_has_debugregs()) {
3851 return 0;
3852 }
3853
3854 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
3855 if (ret < 0) {
3856 return ret;
3857 }
3858 for (i = 0; i < 4; i++) {
3859 env->dr[i] = dbgregs.db[i];
3860 }
3861 env->dr[4] = env->dr[6] = dbgregs.dr6;
3862 env->dr[5] = env->dr[7] = dbgregs.dr7;
3863
3864 return 0;
3865 }
3866
3867 static int kvm_put_nested_state(X86CPU *cpu)
3868 {
3869 CPUX86State *env = &cpu->env;
3870 int max_nested_state_len = kvm_max_nested_state_length();
3871
3872 if (!env->nested_state) {
3873 return 0;
3874 }
3875
3876 assert(env->nested_state->size <= max_nested_state_len);
3877 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_NESTED_STATE, env->nested_state);
3878 }
3879
3880 static int kvm_get_nested_state(X86CPU *cpu)
3881 {
3882 CPUX86State *env = &cpu->env;
3883 int max_nested_state_len = kvm_max_nested_state_length();
3884 int ret;
3885
3886 if (!env->nested_state) {
3887 return 0;
3888 }
3889
3890 /*
3891 * It is possible that migration restored a smaller size into
3892 * nested_state->hdr.size than what our kernel support.
3893 * We preserve migration origin nested_state->hdr.size for
3894 * call to KVM_SET_NESTED_STATE but wish that our next call
3895 * to KVM_GET_NESTED_STATE will use max size our kernel support.
3896 */
3897 env->nested_state->size = max_nested_state_len;
3898
3899 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_NESTED_STATE, env->nested_state);
3900 if (ret < 0) {
3901 return ret;
3902 }
3903
3904 if (env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE) {
3905 env->hflags |= HF_GUEST_MASK;
3906 } else {
3907 env->hflags &= ~HF_GUEST_MASK;
3908 }
3909
3910 return ret;
3911 }
3912
3913 int kvm_arch_put_registers(CPUState *cpu, int level)
3914 {
3915 X86CPU *x86_cpu = X86_CPU(cpu);
3916 int ret;
3917
3918 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
3919
3920 if (level >= KVM_PUT_RESET_STATE) {
3921 ret = kvm_put_nested_state(x86_cpu);
3922 if (ret < 0) {
3923 return ret;
3924 }
3925
3926 ret = kvm_put_msr_feature_control(x86_cpu);
3927 if (ret < 0) {
3928 return ret;
3929 }
3930 }
3931
3932 if (level == KVM_PUT_FULL_STATE) {
3933 /* We don't check for kvm_arch_set_tsc_khz() errors here,
3934 * because TSC frequency mismatch shouldn't abort migration,
3935 * unless the user explicitly asked for a more strict TSC
3936 * setting (e.g. using an explicit "tsc-freq" option).
3937 */
3938 kvm_arch_set_tsc_khz(cpu);
3939 }
3940
3941 ret = kvm_getput_regs(x86_cpu, 1);
3942 if (ret < 0) {
3943 return ret;
3944 }
3945 ret = kvm_put_xsave(x86_cpu);
3946 if (ret < 0) {
3947 return ret;
3948 }
3949 ret = kvm_put_xcrs(x86_cpu);
3950 if (ret < 0) {
3951 return ret;
3952 }
3953 ret = kvm_put_sregs(x86_cpu);
3954 if (ret < 0) {
3955 return ret;
3956 }
3957 /* must be before kvm_put_msrs */
3958 ret = kvm_inject_mce_oldstyle(x86_cpu);
3959 if (ret < 0) {
3960 return ret;
3961 }
3962 ret = kvm_put_msrs(x86_cpu, level);
3963 if (ret < 0) {
3964 return ret;
3965 }
3966 ret = kvm_put_vcpu_events(x86_cpu, level);
3967 if (ret < 0) {
3968 return ret;
3969 }
3970 if (level >= KVM_PUT_RESET_STATE) {
3971 ret = kvm_put_mp_state(x86_cpu);
3972 if (ret < 0) {
3973 return ret;
3974 }
3975 }
3976
3977 ret = kvm_put_tscdeadline_msr(x86_cpu);
3978 if (ret < 0) {
3979 return ret;
3980 }
3981 ret = kvm_put_debugregs(x86_cpu);
3982 if (ret < 0) {
3983 return ret;
3984 }
3985 /* must be last */
3986 ret = kvm_guest_debug_workarounds(x86_cpu);
3987 if (ret < 0) {
3988 return ret;
3989 }
3990 return 0;
3991 }
3992
3993 int kvm_arch_get_registers(CPUState *cs)
3994 {
3995 X86CPU *cpu = X86_CPU(cs);
3996 int ret;
3997
3998 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
3999
4000 ret = kvm_get_vcpu_events(cpu);
4001 if (ret < 0) {
4002 goto out;
4003 }
4004 /*
4005 * KVM_GET_MPSTATE can modify CS and RIP, call it before
4006 * KVM_GET_REGS and KVM_GET_SREGS.
4007 */
4008 ret = kvm_get_mp_state(cpu);
4009 if (ret < 0) {
4010 goto out;
4011 }
4012 ret = kvm_getput_regs(cpu, 0);
4013 if (ret < 0) {
4014 goto out;
4015 }
4016 ret = kvm_get_xsave(cpu);
4017 if (ret < 0) {
4018 goto out;
4019 }
4020 ret = kvm_get_xcrs(cpu);
4021 if (ret < 0) {
4022 goto out;
4023 }
4024 ret = kvm_get_sregs(cpu);
4025 if (ret < 0) {
4026 goto out;
4027 }
4028 ret = kvm_get_msrs(cpu);
4029 if (ret < 0) {
4030 goto out;
4031 }
4032 ret = kvm_get_apic(cpu);
4033 if (ret < 0) {
4034 goto out;
4035 }
4036 ret = kvm_get_debugregs(cpu);
4037 if (ret < 0) {
4038 goto out;
4039 }
4040 ret = kvm_get_nested_state(cpu);
4041 if (ret < 0) {
4042 goto out;
4043 }
4044 ret = 0;
4045 out:
4046 cpu_sync_bndcs_hflags(&cpu->env);
4047 return ret;
4048 }
4049
4050 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
4051 {
4052 X86CPU *x86_cpu = X86_CPU(cpu);
4053 CPUX86State *env = &x86_cpu->env;
4054 int ret;
4055
4056 /* Inject NMI */
4057 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
4058 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
4059 qemu_mutex_lock_iothread();
4060 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
4061 qemu_mutex_unlock_iothread();
4062 DPRINTF("injected NMI\n");
4063 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
4064 if (ret < 0) {
4065 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
4066 strerror(-ret));
4067 }
4068 }
4069 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
4070 qemu_mutex_lock_iothread();
4071 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
4072 qemu_mutex_unlock_iothread();
4073 DPRINTF("injected SMI\n");
4074 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
4075 if (ret < 0) {
4076 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
4077 strerror(-ret));
4078 }
4079 }
4080 }
4081
4082 if (!kvm_pic_in_kernel()) {
4083 qemu_mutex_lock_iothread();
4084 }
4085
4086 /* Force the VCPU out of its inner loop to process any INIT requests
4087 * or (for userspace APIC, but it is cheap to combine the checks here)
4088 * pending TPR access reports.
4089 */
4090 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
4091 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
4092 !(env->hflags & HF_SMM_MASK)) {
4093 cpu->exit_request = 1;
4094 }
4095 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
4096 cpu->exit_request = 1;
4097 }
4098 }
4099
4100 if (!kvm_pic_in_kernel()) {
4101 /* Try to inject an interrupt if the guest can accept it */
4102 if (run->ready_for_interrupt_injection &&
4103 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
4104 (env->eflags & IF_MASK)) {
4105 int irq;
4106
4107 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
4108 irq = cpu_get_pic_interrupt(env);
4109 if (irq >= 0) {
4110 struct kvm_interrupt intr;
4111
4112 intr.irq = irq;
4113 DPRINTF("injected interrupt %d\n", irq);
4114 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
4115 if (ret < 0) {
4116 fprintf(stderr,
4117 "KVM: injection failed, interrupt lost (%s)\n",
4118 strerror(-ret));
4119 }
4120 }
4121 }
4122
4123 /* If we have an interrupt but the guest is not ready to receive an
4124 * interrupt, request an interrupt window exit. This will
4125 * cause a return to userspace as soon as the guest is ready to
4126 * receive interrupts. */
4127 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
4128 run->request_interrupt_window = 1;
4129 } else {
4130 run->request_interrupt_window = 0;
4131 }
4132
4133 DPRINTF("setting tpr\n");
4134 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4135
4136 qemu_mutex_unlock_iothread();
4137 }
4138 }
4139
4140 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
4141 {
4142 X86CPU *x86_cpu = X86_CPU(cpu);
4143 CPUX86State *env = &x86_cpu->env;
4144
4145 if (run->flags & KVM_RUN_X86_SMM) {
4146 env->hflags |= HF_SMM_MASK;
4147 } else {
4148 env->hflags &= ~HF_SMM_MASK;
4149 }
4150 if (run->if_flag) {
4151 env->eflags |= IF_MASK;
4152 } else {
4153 env->eflags &= ~IF_MASK;
4154 }
4155
4156 /* We need to protect the apic state against concurrent accesses from
4157 * different threads in case the userspace irqchip is used. */
4158 if (!kvm_irqchip_in_kernel()) {
4159 qemu_mutex_lock_iothread();
4160 }
4161 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
4162 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4163 if (!kvm_irqchip_in_kernel()) {
4164 qemu_mutex_unlock_iothread();
4165 }
4166 return cpu_get_mem_attrs(env);
4167 }
4168
4169 int kvm_arch_process_async_events(CPUState *cs)
4170 {
4171 X86CPU *cpu = X86_CPU(cs);
4172 CPUX86State *env = &cpu->env;
4173
4174 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
4175 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
4176 assert(env->mcg_cap);
4177
4178 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
4179
4180 kvm_cpu_synchronize_state(cs);
4181
4182 if (env->exception_nr == EXCP08_DBLE) {
4183 /* this means triple fault */
4184 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
4185 cs->exit_request = 1;
4186 return 0;
4187 }
4188 kvm_queue_exception(env, EXCP12_MCHK, 0, 0);
4189 env->has_error_code = 0;
4190
4191 cs->halted = 0;
4192 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
4193 env->mp_state = KVM_MP_STATE_RUNNABLE;
4194 }
4195 }
4196
4197 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
4198 !(env->hflags & HF_SMM_MASK)) {
4199 kvm_cpu_synchronize_state(cs);
4200 do_cpu_init(cpu);
4201 }
4202
4203 if (kvm_irqchip_in_kernel()) {
4204 return 0;
4205 }
4206
4207 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
4208 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
4209 apic_poll_irq(cpu->apic_state);
4210 }
4211 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4212 (env->eflags & IF_MASK)) ||
4213 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
4214 cs->halted = 0;
4215 }
4216 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
4217 kvm_cpu_synchronize_state(cs);
4218 do_cpu_sipi(cpu);
4219 }
4220 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
4221 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
4222 kvm_cpu_synchronize_state(cs);
4223 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
4224 env->tpr_access_type);
4225 }
4226
4227 return cs->halted;
4228 }
4229
4230 static int kvm_handle_halt(X86CPU *cpu)
4231 {
4232 CPUState *cs = CPU(cpu);
4233 CPUX86State *env = &cpu->env;
4234
4235 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4236 (env->eflags & IF_MASK)) &&
4237 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
4238 cs->halted = 1;
4239 return EXCP_HLT;
4240 }
4241
4242 return 0;
4243 }
4244
4245 static int kvm_handle_tpr_access(X86CPU *cpu)
4246 {
4247 CPUState *cs = CPU(cpu);
4248 struct kvm_run *run = cs->kvm_run;
4249
4250 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
4251 run->tpr_access.is_write ? TPR_ACCESS_WRITE
4252 : TPR_ACCESS_READ);
4253 return 1;
4254 }
4255
4256 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
4257 {
4258 static const uint8_t int3 = 0xcc;
4259
4260 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
4261 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
4262 return -EINVAL;
4263 }
4264 return 0;
4265 }
4266
4267 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
4268 {
4269 uint8_t int3;
4270
4271 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
4272 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
4273 return -EINVAL;
4274 }
4275 return 0;
4276 }
4277
4278 static struct {
4279 target_ulong addr;
4280 int len;
4281 int type;
4282 } hw_breakpoint[4];
4283
4284 static int nb_hw_breakpoint;
4285
4286 static int find_hw_breakpoint(target_ulong addr, int len, int type)
4287 {
4288 int n;
4289
4290 for (n = 0; n < nb_hw_breakpoint; n++) {
4291 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
4292 (hw_breakpoint[n].len == len || len == -1)) {
4293 return n;
4294 }
4295 }
4296 return -1;
4297 }
4298
4299 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
4300 target_ulong len, int type)
4301 {
4302 switch (type) {
4303 case GDB_BREAKPOINT_HW:
4304 len = 1;
4305 break;
4306 case GDB_WATCHPOINT_WRITE:
4307 case GDB_WATCHPOINT_ACCESS:
4308 switch (len) {
4309 case 1:
4310 break;
4311 case 2:
4312 case 4:
4313 case 8:
4314 if (addr & (len - 1)) {
4315 return -EINVAL;
4316 }
4317 break;
4318 default:
4319 return -EINVAL;
4320 }
4321 break;
4322 default:
4323 return -ENOSYS;
4324 }
4325
4326 if (nb_hw_breakpoint == 4) {
4327 return -ENOBUFS;
4328 }
4329 if (find_hw_breakpoint(addr, len, type) >= 0) {
4330 return -EEXIST;
4331 }
4332 hw_breakpoint[nb_hw_breakpoint].addr = addr;
4333 hw_breakpoint[nb_hw_breakpoint].len = len;
4334 hw_breakpoint[nb_hw_breakpoint].type = type;
4335 nb_hw_breakpoint++;
4336
4337 return 0;
4338 }
4339
4340 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
4341 target_ulong len, int type)
4342 {
4343 int n;
4344
4345 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
4346 if (n < 0) {
4347 return -ENOENT;
4348 }
4349 nb_hw_breakpoint--;
4350 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
4351
4352 return 0;
4353 }
4354
4355 void kvm_arch_remove_all_hw_breakpoints(void)
4356 {
4357 nb_hw_breakpoint = 0;
4358 }
4359
4360 static CPUWatchpoint hw_watchpoint;
4361
4362 static int kvm_handle_debug(X86CPU *cpu,
4363 struct kvm_debug_exit_arch *arch_info)
4364 {
4365 CPUState *cs = CPU(cpu);
4366 CPUX86State *env = &cpu->env;
4367 int ret = 0;
4368 int n;
4369
4370 if (arch_info->exception == EXCP01_DB) {
4371 if (arch_info->dr6 & DR6_BS) {
4372 if (cs->singlestep_enabled) {
4373 ret = EXCP_DEBUG;
4374 }
4375 } else {
4376 for (n = 0; n < 4; n++) {
4377 if (arch_info->dr6 & (1 << n)) {
4378 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
4379 case 0x0:
4380 ret = EXCP_DEBUG;
4381 break;
4382 case 0x1:
4383 ret = EXCP_DEBUG;
4384 cs->watchpoint_hit = &hw_watchpoint;
4385 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
4386 hw_watchpoint.flags = BP_MEM_WRITE;
4387 break;
4388 case 0x3:
4389 ret = EXCP_DEBUG;
4390 cs->watchpoint_hit = &hw_watchpoint;
4391 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
4392 hw_watchpoint.flags = BP_MEM_ACCESS;
4393 break;
4394 }
4395 }
4396 }
4397 }
4398 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
4399 ret = EXCP_DEBUG;
4400 }
4401 if (ret == 0) {
4402 cpu_synchronize_state(cs);
4403 assert(env->exception_nr == -1);
4404
4405 /* pass to guest */
4406 kvm_queue_exception(env, arch_info->exception,
4407 arch_info->exception == EXCP01_DB,
4408 arch_info->dr6);
4409 env->has_error_code = 0;
4410 }
4411
4412 return ret;
4413 }
4414
4415 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
4416 {
4417 const uint8_t type_code[] = {
4418 [GDB_BREAKPOINT_HW] = 0x0,
4419 [GDB_WATCHPOINT_WRITE] = 0x1,
4420 [GDB_WATCHPOINT_ACCESS] = 0x3
4421 };
4422 const uint8_t len_code[] = {
4423 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
4424 };
4425 int n;
4426
4427 if (kvm_sw_breakpoints_active(cpu)) {
4428 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
4429 }
4430 if (nb_hw_breakpoint > 0) {
4431 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
4432 dbg->arch.debugreg[7] = 0x0600;
4433 for (n = 0; n < nb_hw_breakpoint; n++) {
4434 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
4435 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
4436 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
4437 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
4438 }
4439 }
4440 }
4441
4442 static bool host_supports_vmx(void)
4443 {
4444 uint32_t ecx, unused;
4445
4446 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
4447 return ecx & CPUID_EXT_VMX;
4448 }
4449
4450 #define VMX_INVALID_GUEST_STATE 0x80000021
4451
4452 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
4453 {
4454 X86CPU *cpu = X86_CPU(cs);
4455 uint64_t code;
4456 int ret;
4457
4458 switch (run->exit_reason) {
4459 case KVM_EXIT_HLT:
4460 DPRINTF("handle_hlt\n");
4461 qemu_mutex_lock_iothread();
4462 ret = kvm_handle_halt(cpu);
4463 qemu_mutex_unlock_iothread();
4464 break;
4465 case KVM_EXIT_SET_TPR:
4466 ret = 0;
4467 break;
4468 case KVM_EXIT_TPR_ACCESS:
4469 qemu_mutex_lock_iothread();
4470 ret = kvm_handle_tpr_access(cpu);
4471 qemu_mutex_unlock_iothread();
4472 break;
4473 case KVM_EXIT_FAIL_ENTRY:
4474 code = run->fail_entry.hardware_entry_failure_reason;
4475 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
4476 code);
4477 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
4478 fprintf(stderr,
4479 "\nIf you're running a guest on an Intel machine without "
4480 "unrestricted mode\n"
4481 "support, the failure can be most likely due to the guest "
4482 "entering an invalid\n"
4483 "state for Intel VT. For example, the guest maybe running "
4484 "in big real mode\n"
4485 "which is not supported on less recent Intel processors."
4486 "\n\n");
4487 }
4488 ret = -1;
4489 break;
4490 case KVM_EXIT_EXCEPTION:
4491 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
4492 run->ex.exception, run->ex.error_code);
4493 ret = -1;
4494 break;
4495 case KVM_EXIT_DEBUG:
4496 DPRINTF("kvm_exit_debug\n");
4497 qemu_mutex_lock_iothread();
4498 ret = kvm_handle_debug(cpu, &run->debug.arch);
4499 qemu_mutex_unlock_iothread();
4500 break;
4501 case KVM_EXIT_HYPERV:
4502 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
4503 break;
4504 case KVM_EXIT_IOAPIC_EOI:
4505 ioapic_eoi_broadcast(run->eoi.vector);
4506 ret = 0;
4507 break;
4508 default:
4509 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
4510 ret = -1;
4511 break;
4512 }
4513
4514 return ret;
4515 }
4516
4517 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4518 {
4519 X86CPU *cpu = X86_CPU(cs);
4520 CPUX86State *env = &cpu->env;
4521
4522 kvm_cpu_synchronize_state(cs);
4523 return !(env->cr[0] & CR0_PE_MASK) ||
4524 ((env->segs[R_CS].selector & 3) != 3);
4525 }
4526
4527 void kvm_arch_init_irq_routing(KVMState *s)
4528 {
4529 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
4530 /* If kernel can't do irq routing, interrupt source
4531 * override 0->2 cannot be set up as required by HPET.
4532 * So we have to disable it.
4533 */
4534 no_hpet = 1;
4535 }
4536 /* We know at this point that we're using the in-kernel
4537 * irqchip, so we can use irqfds, and on x86 we know
4538 * we can use msi via irqfd and GSI routing.
4539 */
4540 kvm_msi_via_irqfd_allowed = true;
4541 kvm_gsi_routing_allowed = true;
4542
4543 if (kvm_irqchip_is_split()) {
4544 int i;
4545
4546 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
4547 MSI routes for signaling interrupts to the local apics. */
4548 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
4549 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
4550 error_report("Could not enable split IRQ mode.");
4551 exit(1);
4552 }
4553 }
4554 }
4555 }
4556
4557 int kvm_arch_irqchip_create(KVMState *s)
4558 {
4559 int ret;
4560 if (kvm_kernel_irqchip_split()) {
4561 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
4562 if (ret) {
4563 error_report("Could not enable split irqchip mode: %s",
4564 strerror(-ret));
4565 exit(1);
4566 } else {
4567 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
4568 kvm_split_irqchip = true;
4569 return 1;
4570 }
4571 } else {
4572 return 0;
4573 }
4574 }
4575
4576 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
4577 uint64_t address, uint32_t data, PCIDevice *dev)
4578 {
4579 X86IOMMUState *iommu = x86_iommu_get_default();
4580
4581 if (iommu) {
4582 int ret;
4583 MSIMessage src, dst;
4584 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
4585
4586 if (!class->int_remap) {
4587 return 0;
4588 }
4589
4590 src.address = route->u.msi.address_hi;
4591 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
4592 src.address |= route->u.msi.address_lo;
4593 src.data = route->u.msi.data;
4594
4595 ret = class->int_remap(iommu, &src, &dst, dev ? \
4596 pci_requester_id(dev) : \
4597 X86_IOMMU_SID_INVALID);
4598 if (ret) {
4599 trace_kvm_x86_fixup_msi_error(route->gsi);
4600 return 1;
4601 }
4602
4603 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
4604 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
4605 route->u.msi.data = dst.data;
4606 }
4607
4608 return 0;
4609 }
4610
4611 typedef struct MSIRouteEntry MSIRouteEntry;
4612
4613 struct MSIRouteEntry {
4614 PCIDevice *dev; /* Device pointer */
4615 int vector; /* MSI/MSIX vector index */
4616 int virq; /* Virtual IRQ index */
4617 QLIST_ENTRY(MSIRouteEntry) list;
4618 };
4619
4620 /* List of used GSI routes */
4621 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
4622 QLIST_HEAD_INITIALIZER(msi_route_list);
4623
4624 static void kvm_update_msi_routes_all(void *private, bool global,
4625 uint32_t index, uint32_t mask)
4626 {
4627 int cnt = 0, vector;
4628 MSIRouteEntry *entry;
4629 MSIMessage msg;
4630 PCIDevice *dev;
4631
4632 /* TODO: explicit route update */
4633 QLIST_FOREACH(entry, &msi_route_list, list) {
4634 cnt++;
4635 vector = entry->vector;
4636 dev = entry->dev;
4637 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
4638 msg = msix_get_message(dev, vector);
4639 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
4640 msg = msi_get_message(dev, vector);
4641 } else {
4642 /*
4643 * Either MSI/MSIX is disabled for the device, or the
4644 * specific message was masked out. Skip this one.
4645 */
4646 continue;
4647 }
4648 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
4649 }
4650 kvm_irqchip_commit_routes(kvm_state);
4651 trace_kvm_x86_update_msi_routes(cnt);
4652 }
4653
4654 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
4655 int vector, PCIDevice *dev)
4656 {
4657 static bool notify_list_inited = false;
4658 MSIRouteEntry *entry;
4659
4660 if (!dev) {
4661 /* These are (possibly) IOAPIC routes only used for split
4662 * kernel irqchip mode, while what we are housekeeping are
4663 * PCI devices only. */
4664 return 0;
4665 }
4666
4667 entry = g_new0(MSIRouteEntry, 1);
4668 entry->dev = dev;
4669 entry->vector = vector;
4670 entry->virq = route->gsi;
4671 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
4672
4673 trace_kvm_x86_add_msi_route(route->gsi);
4674
4675 if (!notify_list_inited) {
4676 /* For the first time we do add route, add ourselves into
4677 * IOMMU's IEC notify list if needed. */
4678 X86IOMMUState *iommu = x86_iommu_get_default();
4679 if (iommu) {
4680 x86_iommu_iec_register_notifier(iommu,
4681 kvm_update_msi_routes_all,
4682 NULL);
4683 }
4684 notify_list_inited = true;
4685 }
4686 return 0;
4687 }
4688
4689 int kvm_arch_release_virq_post(int virq)
4690 {
4691 MSIRouteEntry *entry, *next;
4692 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
4693 if (entry->virq == virq) {
4694 trace_kvm_x86_remove_msi_route(virq);
4695 QLIST_REMOVE(entry, list);
4696 g_free(entry);
4697 break;
4698 }
4699 }
4700 return 0;
4701 }
4702
4703 int kvm_arch_msi_data_to_gsi(uint32_t data)
4704 {
4705 abort();
4706 }
AR7 emulation for QEMU