spapr: Expose the name of the interrupt controller node
[qemu/ar7.git] / include / hw / pci / pci_bus.h
blobdfb75752cbc1a2bd75654c6243d807f67657dd1d
1 #ifndef QEMU_PCI_BUS_H
2 #define QEMU_PCI_BUS_H
4 #include "hw/pci/pci.h"
6 /*
7 * PCI Bus datastructures.
9 * Do not access the following members directly;
10 * use accessor functions in pci.h
13 typedef struct PCIBusClass {
14 /*< private >*/
15 BusClass parent_class;
16 /*< public >*/
18 bool (*is_root)(PCIBus *bus);
19 int (*bus_num)(PCIBus *bus);
20 uint16_t (*numa_node)(PCIBus *bus);
21 } PCIBusClass;
23 struct PCIBus {
24 BusState qbus;
25 PCIIOMMUFunc iommu_fn;
26 void *iommu_opaque;
27 uint8_t devfn_min;
28 uint32_t slot_reserved_mask;
29 pci_set_irq_fn set_irq;
30 pci_map_irq_fn map_irq;
31 pci_route_irq_fn route_intx_to_irq;
32 void *irq_opaque;
33 PCIDevice *devices[PCI_SLOT_MAX * PCI_FUNC_MAX];
34 PCIDevice *parent_dev;
35 MemoryRegion *address_space_mem;
36 MemoryRegion *address_space_io;
38 QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
39 QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
41 /* The bus IRQ state is the logical OR of the connected devices.
42 Keep a count of the number of devices with raised IRQs. */
43 int nirq;
44 int *irq_count;
46 Notifier machine_done;
49 #endif /* QEMU_PCI_BUS_H */