hw/arm: add Allwinner H3 System-on-Chip
[qemu/ar7.git] / include / hw / arm / allwinner-h3.h
blob2aac9b78ecf07c515af0a5fd7e690c2fb4108e08
1 /*
2 * Allwinner H3 System on Chip emulation
4 * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 * The Allwinner H3 is a System on Chip containing four ARM Cortex A7
22 * processor cores. Features and specifications include DDR2/DDR3 memory,
23 * SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and
24 * various I/O modules.
26 * This implementation is based on the following datasheet:
28 * https://linux-sunxi.org/File:Allwinner_H3_Datasheet_V1.2.pdf
30 * The latest datasheet and more info can be found on the Linux Sunxi wiki:
32 * https://linux-sunxi.org/H3
35 #ifndef HW_ARM_ALLWINNER_H3_H
36 #define HW_ARM_ALLWINNER_H3_H
38 #include "qom/object.h"
39 #include "hw/arm/boot.h"
40 #include "hw/timer/allwinner-a10-pit.h"
41 #include "hw/intc/arm_gic.h"
42 #include "target/arm/cpu.h"
44 /**
45 * Allwinner H3 device list
47 * This enumeration is can be used refer to a particular device in the
48 * Allwinner H3 SoC. For example, the physical memory base address for
49 * each device can be found in the AwH3State object in the memmap member
50 * using the device enum value as index.
52 * @see AwH3State
54 enum {
55 AW_H3_SRAM_A1,
56 AW_H3_SRAM_A2,
57 AW_H3_SRAM_C,
58 AW_H3_PIT,
59 AW_H3_UART0,
60 AW_H3_UART1,
61 AW_H3_UART2,
62 AW_H3_UART3,
63 AW_H3_GIC_DIST,
64 AW_H3_GIC_CPU,
65 AW_H3_GIC_HYP,
66 AW_H3_GIC_VCPU,
67 AW_H3_SDRAM
70 /** Total number of CPU cores in the H3 SoC */
71 #define AW_H3_NUM_CPUS (4)
73 /**
74 * Allwinner H3 object model
75 * @{
78 /** Object type for the Allwinner H3 SoC */
79 #define TYPE_AW_H3 "allwinner-h3"
81 /** Convert input object to Allwinner H3 state object */
82 #define AW_H3(obj) OBJECT_CHECK(AwH3State, (obj), TYPE_AW_H3)
84 /** @} */
86 /**
87 * Allwinner H3 object
89 * This struct contains the state of all the devices
90 * which are currently emulated by the H3 SoC code.
92 typedef struct AwH3State {
93 /*< private >*/
94 DeviceState parent_obj;
95 /*< public >*/
97 ARMCPU cpus[AW_H3_NUM_CPUS];
98 const hwaddr *memmap;
99 AwA10PITState timer;
100 GICState gic;
101 MemoryRegion sram_a1;
102 MemoryRegion sram_a2;
103 MemoryRegion sram_c;
104 } AwH3State;
106 #endif /* HW_ARM_ALLWINNER_H3_H */