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hw/arm: add Allwinner H3 System-on-Chip
[qemu/ar7.git] / hw / arm / allwinner-h3.c
blob7958f3768526ab1d5a37b5707de26351432f516b
1 /*
2 * Allwinner H3 System on Chip emulation
3 *
4 * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "exec/address-spaces.h"
22 #include "qapi/error.h"
23 #include "qemu/error-report.h"
24 #include "qemu/module.h"
25 #include "qemu/units.h"
26 #include "hw/qdev-core.h"
27 #include "cpu.h"
28 #include "hw/sysbus.h"
29 #include "hw/char/serial.h"
30 #include "hw/misc/unimp.h"
31 #include "sysemu/sysemu.h"
32 #include "hw/arm/allwinner-h3.h"
33
34 /* Memory map */
35 const hwaddr allwinner_h3_memmap[] = {
36 [AW_H3_SRAM_A1] = 0x00000000,
37 [AW_H3_SRAM_A2] = 0x00044000,
38 [AW_H3_SRAM_C] = 0x00010000,
39 [AW_H3_PIT] = 0x01c20c00,
40 [AW_H3_UART0] = 0x01c28000,
41 [AW_H3_UART1] = 0x01c28400,
42 [AW_H3_UART2] = 0x01c28800,
43 [AW_H3_UART3] = 0x01c28c00,
44 [AW_H3_GIC_DIST] = 0x01c81000,
45 [AW_H3_GIC_CPU] = 0x01c82000,
46 [AW_H3_GIC_HYP] = 0x01c84000,
47 [AW_H3_GIC_VCPU] = 0x01c86000,
48 [AW_H3_SDRAM] = 0x40000000
49 };
50
51 /* List of unimplemented devices */
52 struct AwH3Unimplemented {
53 const char *device_name;
54 hwaddr base;
55 hwaddr size;
56 } unimplemented[] = {
57 { "d-engine", 0x01000000, 4 * MiB },
58 { "d-inter", 0x01400000, 128 * KiB },
59 { "syscon", 0x01c00000, 4 * KiB },
60 { "dma", 0x01c02000, 4 * KiB },
61 { "nfdc", 0x01c03000, 4 * KiB },
62 { "ts", 0x01c06000, 4 * KiB },
63 { "keymem", 0x01c0b000, 4 * KiB },
64 { "lcd0", 0x01c0c000, 4 * KiB },
65 { "lcd1", 0x01c0d000, 4 * KiB },
66 { "ve", 0x01c0e000, 4 * KiB },
67 { "mmc0", 0x01c0f000, 4 * KiB },
68 { "mmc1", 0x01c10000, 4 * KiB },
69 { "mmc2", 0x01c11000, 4 * KiB },
70 { "sid", 0x01c14000, 1 * KiB },
71 { "crypto", 0x01c15000, 4 * KiB },
72 { "msgbox", 0x01c17000, 4 * KiB },
73 { "spinlock", 0x01c18000, 4 * KiB },
74 { "usb0-otg", 0x01c19000, 4 * KiB },
75 { "usb0-phy", 0x01c1a000, 4 * KiB },
76 { "usb1-phy", 0x01c1b000, 4 * KiB },
77 { "usb2-phy", 0x01c1c000, 4 * KiB },
78 { "usb3-phy", 0x01c1d000, 4 * KiB },
79 { "smc", 0x01c1e000, 4 * KiB },
80 { "ccu", 0x01c20000, 1 * KiB },
81 { "pio", 0x01c20800, 1 * KiB },
82 { "owa", 0x01c21000, 1 * KiB },
83 { "pwm", 0x01c21400, 1 * KiB },
84 { "keyadc", 0x01c21800, 1 * KiB },
85 { "pcm0", 0x01c22000, 1 * KiB },
86 { "pcm1", 0x01c22400, 1 * KiB },
87 { "pcm2", 0x01c22800, 1 * KiB },
88 { "audio", 0x01c22c00, 2 * KiB },
89 { "smta", 0x01c23400, 1 * KiB },
90 { "ths", 0x01c25000, 1 * KiB },
91 { "uart0", 0x01c28000, 1 * KiB },
92 { "uart1", 0x01c28400, 1 * KiB },
93 { "uart2", 0x01c28800, 1 * KiB },
94 { "uart3", 0x01c28c00, 1 * KiB },
95 { "twi0", 0x01c2ac00, 1 * KiB },
96 { "twi1", 0x01c2b000, 1 * KiB },
97 { "twi2", 0x01c2b400, 1 * KiB },
98 { "scr", 0x01c2c400, 1 * KiB },
99 { "emac", 0x01c30000, 64 * KiB },
100 { "gpu", 0x01c40000, 64 * KiB },
101 { "hstmr", 0x01c60000, 4 * KiB },
102 { "dramcom", 0x01c62000, 4 * KiB },
103 { "dramctl0", 0x01c63000, 4 * KiB },
104 { "dramphy0", 0x01c65000, 4 * KiB },
105 { "spi0", 0x01c68000, 4 * KiB },
106 { "spi1", 0x01c69000, 4 * KiB },
107 { "csi", 0x01cb0000, 320 * KiB },
108 { "tve", 0x01e00000, 64 * KiB },
109 { "hdmi", 0x01ee0000, 128 * KiB },
110 { "rtc", 0x01f00000, 1 * KiB },
111 { "r_timer", 0x01f00800, 1 * KiB },
112 { "r_intc", 0x01f00c00, 1 * KiB },
113 { "r_wdog", 0x01f01000, 1 * KiB },
114 { "r_prcm", 0x01f01400, 1 * KiB },
115 { "r_twd", 0x01f01800, 1 * KiB },
116 { "r_cpucfg", 0x01f01c00, 1 * KiB },
117 { "r_cir-rx", 0x01f02000, 1 * KiB },
118 { "r_twi", 0x01f02400, 1 * KiB },
119 { "r_uart", 0x01f02800, 1 * KiB },
120 { "r_pio", 0x01f02c00, 1 * KiB },
121 { "r_pwm", 0x01f03800, 1 * KiB },
122 { "core-dbg", 0x3f500000, 128 * KiB },
123 { "tsgen-ro", 0x3f506000, 4 * KiB },
124 { "tsgen-ctl", 0x3f507000, 4 * KiB },
125 { "ddr-mem", 0x40000000, 2 * GiB },
126 { "n-brom", 0xffff0000, 32 * KiB },
127 { "s-brom", 0xffff0000, 64 * KiB }
128 };
129
130 /* Per Processor Interrupts */
131 enum {
132 AW_H3_GIC_PPI_MAINT = 9,
133 AW_H3_GIC_PPI_HYPTIMER = 10,
134 AW_H3_GIC_PPI_VIRTTIMER = 11,
135 AW_H3_GIC_PPI_SECTIMER = 13,
136 AW_H3_GIC_PPI_PHYSTIMER = 14
137 };
138
139 /* Shared Processor Interrupts */
140 enum {
141 AW_H3_GIC_SPI_UART0 = 0,
142 AW_H3_GIC_SPI_UART1 = 1,
143 AW_H3_GIC_SPI_UART2 = 2,
144 AW_H3_GIC_SPI_UART3 = 3,
145 AW_H3_GIC_SPI_TIMER0 = 18,
146 AW_H3_GIC_SPI_TIMER1 = 19,
147 };
148
149 /* Allwinner H3 general constants */
150 enum {
151 AW_H3_GIC_NUM_SPI = 128
152 };
153
154 static void allwinner_h3_init(Object *obj)
155 {
156 AwH3State *s = AW_H3(obj);
157
158 s->memmap = allwinner_h3_memmap;
159
160 for (int i = 0; i < AW_H3_NUM_CPUS; i++) {
161 object_initialize_child(obj, "cpu[*]", &s->cpus[i], sizeof(s->cpus[i]),
162 ARM_CPU_TYPE_NAME("cortex-a7"),
163 &error_abort, NULL);
164 }
165
166 sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic),
167 TYPE_ARM_GIC);
168
169 sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer),
170 TYPE_AW_A10_PIT);
171 object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer),
172 "clk0-freq", &error_abort);
173 object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
174 "clk1-freq", &error_abort);
175 }
176
177 static void allwinner_h3_realize(DeviceState *dev, Error **errp)
178 {
179 AwH3State *s = AW_H3(dev);
180 unsigned i;
181
182 /* CPUs */
183 for (i = 0; i < AW_H3_NUM_CPUS; i++) {
184
185 /* Provide Power State Coordination Interface */
186 qdev_prop_set_int32(DEVICE(&s->cpus[i]), "psci-conduit",
187 QEMU_PSCI_CONDUIT_HVC);
188
189 /* Disable secondary CPUs */
190 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off",
191 i > 0);
192
193 /* All exception levels required */
194 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true);
195 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true);
196
197 /* Mark realized */
198 qdev_init_nofail(DEVICE(&s->cpus[i]));
199 }
200
201 /* Generic Interrupt Controller */
202 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_H3_GIC_NUM_SPI +
203 GIC_INTERNAL);
204 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
205 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_H3_NUM_CPUS);
206 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false);
207 qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true);
208 qdev_init_nofail(DEVICE(&s->gic));
209
210 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_GIC_DIST]);
211 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_GIC_CPU]);
212 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_GIC_HYP]);
213 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_H3_GIC_VCPU]);
214
215 /*
216 * Wire the outputs from each CPU's generic timer and the GICv3
217 * maintenance interrupt signal to the appropriate GIC PPI inputs,
218 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
219 */
220 for (i = 0; i < AW_H3_NUM_CPUS; i++) {
221 DeviceState *cpudev = DEVICE(&s->cpus[i]);
222 int ppibase = AW_H3_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS;
223 int irq;
224 /*
225 * Mapping from the output timer irq lines from the CPU to the
226 * GIC PPI inputs used for this board.
227 */
228 const int timer_irq[] = {
229 [GTIMER_PHYS] = AW_H3_GIC_PPI_PHYSTIMER,
230 [GTIMER_VIRT] = AW_H3_GIC_PPI_VIRTTIMER,
231 [GTIMER_HYP] = AW_H3_GIC_PPI_HYPTIMER,
232 [GTIMER_SEC] = AW_H3_GIC_PPI_SECTIMER,
233 };
234
235 /* Connect CPU timer outputs to GIC PPI inputs */
236 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
237 qdev_connect_gpio_out(cpudev, irq,
238 qdev_get_gpio_in(DEVICE(&s->gic),
239 ppibase + timer_irq[irq]));
240 }
241
242 /* Connect GIC outputs to CPU interrupt inputs */
243 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
244 qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
245 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + AW_H3_NUM_CPUS,
246 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
247 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (2 * AW_H3_NUM_CPUS),
248 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
249 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (3 * AW_H3_NUM_CPUS),
250 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
251
252 /* GIC maintenance signal */
253 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * AW_H3_NUM_CPUS),
254 qdev_get_gpio_in(DEVICE(&s->gic),
255 ppibase + AW_H3_GIC_PPI_MAINT));
256 }
257
258 /* Timer */
259 qdev_init_nofail(DEVICE(&s->timer));
260 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_PIT]);
261 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,
262 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER0));
263 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1,
264 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER1));
265
266 /* SRAM */
267 memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1",
268 64 * KiB, &error_abort);
269 memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2",
270 32 * KiB, &error_abort);
271 memory_region_init_ram(&s->sram_c, OBJECT(dev), "sram C",
272 44 * KiB, &error_abort);
273 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A1],
274 &s->sram_a1);
275 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A2],
276 &s->sram_a2);
277 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C],
278 &s->sram_c);
279
280 /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
281 serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2,
282 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
283 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
284 /* UART1 */
285 serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART1], 2,
286 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART1),
287 115200, serial_hd(1), DEVICE_NATIVE_ENDIAN);
288 /* UART2 */
289 serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART2], 2,
290 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART2),
291 115200, serial_hd(2), DEVICE_NATIVE_ENDIAN);
292 /* UART3 */
293 serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART3], 2,
294 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
295 115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
296
297 /* Unimplemented devices */
298 for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
299 create_unimplemented_device(unimplemented[i].device_name,
300 unimplemented[i].base,
301 unimplemented[i].size);
302 }
303 }
304
305 static void allwinner_h3_class_init(ObjectClass *oc, void *data)
306 {
307 DeviceClass *dc = DEVICE_CLASS(oc);
308
309 dc->realize = allwinner_h3_realize;
310 /* Reason: uses serial_hd() in realize function */
311 dc->user_creatable = false;
312 }
313
314 static const TypeInfo allwinner_h3_type_info = {
315 .name = TYPE_AW_H3,
316 .parent = TYPE_DEVICE,
317 .instance_size = sizeof(AwH3State),
318 .instance_init = allwinner_h3_init,
319 .class_init = allwinner_h3_class_init,
320 };
321
322 static void allwinner_h3_register_types(void)
323 {
324 type_register_static(&allwinner_h3_type_info);
325 }
326
327 type_init(allwinner_h3_register_types)
AR7 emulation for QEMU