4 * Copyright (c) 2003 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "ui/console.h"
27 #include "hw/i386/pc.h"
28 #include "hw/pci/pci.h"
30 #include "ui/pixel_ops.h"
31 #include "qemu/timer.h"
32 #include "hw/xen/xen.h"
36 //#define DEBUG_VGA_MEM
37 //#define DEBUG_VGA_REG
39 //#define DEBUG_BOCHS_VBE
41 /* 16 state changes per vertical frame @60 Hz */
42 #define VGA_TEXT_CURSOR_PERIOD_MS (1000 * 2 * 16 / 60)
45 * Video Graphics Array (VGA)
47 * Chipset docs for original IBM VGA:
48 * http://www.mcamafia.de/pdf/ibm_vgaxga_trm2.pdf
51 * http://www.osdever.net/FreeVGA/home.htm
53 * Standard VGA features and Bochs VBE extensions are implemented.
56 /* force some bits to zero */
57 const uint8_t sr_mask
[8] = {
68 const uint8_t gr_mask
[16] = {
87 #define cbswap_32(__x) \
89 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
90 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
91 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
92 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
94 #ifdef HOST_WORDS_BIGENDIAN
95 #define PAT(x) cbswap_32(x)
100 #ifdef HOST_WORDS_BIGENDIAN
106 #ifdef HOST_WORDS_BIGENDIAN
107 #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
109 #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
112 static const uint32_t mask16
[16] = {
133 #ifdef HOST_WORDS_BIGENDIAN
136 #define PAT(x) cbswap_32(x)
139 static uint32_t expand4
[256];
140 static uint16_t expand2
[256];
141 static uint8_t expand4to8
[16];
143 static void vga_update_memory_access(VGACommonState
*s
)
145 hwaddr base
, offset
, size
;
147 if (s
->legacy_address_space
== NULL
) {
151 if (s
->has_chain4_alias
) {
152 memory_region_del_subregion(s
->legacy_address_space
, &s
->chain4_alias
);
153 object_unparent(OBJECT(&s
->chain4_alias
));
154 s
->has_chain4_alias
= false;
155 s
->plane_updated
= 0xf;
157 if ((s
->sr
[VGA_SEQ_PLANE_WRITE
] & VGA_SR02_ALL_PLANES
) ==
158 VGA_SR02_ALL_PLANES
&& s
->sr
[VGA_SEQ_MEMORY_MODE
] & VGA_SR04_CHN_4M
) {
160 switch ((s
->gr
[VGA_GFX_MISC
] >> 2) & 3) {
168 offset
= s
->bank_offset
;
180 base
+= isa_mem_base
;
181 memory_region_init_alias(&s
->chain4_alias
, memory_region_owner(&s
->vram
),
182 "vga.chain4", &s
->vram
, offset
, size
);
183 memory_region_add_subregion_overlap(s
->legacy_address_space
, base
,
184 &s
->chain4_alias
, 2);
185 s
->has_chain4_alias
= true;
189 static void vga_dumb_update_retrace_info(VGACommonState
*s
)
194 static void vga_precise_update_retrace_info(VGACommonState
*s
)
197 int hretr_start_char
;
198 int hretr_skew_chars
;
202 int vretr_start_line
;
211 const int clk_hz
[] = {25175000, 28322000, 25175000, 25175000};
212 int64_t chars_per_sec
;
213 struct vga_precise_retrace
*r
= &s
->retrace_info
.precise
;
215 htotal_chars
= s
->cr
[VGA_CRTC_H_TOTAL
] + 5;
216 hretr_start_char
= s
->cr
[VGA_CRTC_H_SYNC_START
];
217 hretr_skew_chars
= (s
->cr
[VGA_CRTC_H_SYNC_END
] >> 5) & 3;
218 hretr_end_char
= s
->cr
[VGA_CRTC_H_SYNC_END
] & 0x1f;
220 vtotal_lines
= (s
->cr
[VGA_CRTC_V_TOTAL
] |
221 (((s
->cr
[VGA_CRTC_OVERFLOW
] & 1) |
222 ((s
->cr
[VGA_CRTC_OVERFLOW
] >> 4) & 2)) << 8)) + 2;
223 vretr_start_line
= s
->cr
[VGA_CRTC_V_SYNC_START
] |
224 ((((s
->cr
[VGA_CRTC_OVERFLOW
] >> 2) & 1) |
225 ((s
->cr
[VGA_CRTC_OVERFLOW
] >> 6) & 2)) << 8);
226 vretr_end_line
= s
->cr
[VGA_CRTC_V_SYNC_END
] & 0xf;
228 clocking_mode
= (s
->sr
[VGA_SEQ_CLOCK_MODE
] >> 3) & 1;
229 clock_sel
= (s
->msr
>> 2) & 3;
230 dots
= (s
->msr
& 1) ? 8 : 9;
232 chars_per_sec
= clk_hz
[clock_sel
] / dots
;
234 htotal_chars
<<= clocking_mode
;
236 r
->total_chars
= vtotal_lines
* htotal_chars
;
238 r
->ticks_per_char
= get_ticks_per_sec() / (r
->total_chars
* r
->freq
);
240 r
->ticks_per_char
= get_ticks_per_sec() / chars_per_sec
;
243 r
->vstart
= vretr_start_line
;
244 r
->vend
= r
->vstart
+ vretr_end_line
+ 1;
246 r
->hstart
= hretr_start_char
+ hretr_skew_chars
;
247 r
->hend
= r
->hstart
+ hretr_end_char
+ 1;
248 r
->htotal
= htotal_chars
;
251 div2
= (s
->cr
[VGA_CRTC_MODE
] >> 2) & 1;
252 sldiv2
= (s
->cr
[VGA_CRTC_MODE
] >> 3) & 1;
262 "div2 = %d sldiv2 = %d\n"
263 "clocking_mode = %d\n"
264 "clock_sel = %d %d\n"
266 "ticks/char = %" PRId64
"\n"
268 (double) get_ticks_per_sec() / (r
->ticks_per_char
* r
->total_chars
),
286 static uint8_t vga_precise_retrace(VGACommonState
*s
)
288 struct vga_precise_retrace
*r
= &s
->retrace_info
.precise
;
289 uint8_t val
= s
->st01
& ~(ST01_V_RETRACE
| ST01_DISP_ENABLE
);
291 if (r
->total_chars
) {
292 int cur_line
, cur_line_char
, cur_char
;
295 cur_tick
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
297 cur_char
= (cur_tick
/ r
->ticks_per_char
) % r
->total_chars
;
298 cur_line
= cur_char
/ r
->htotal
;
300 if (cur_line
>= r
->vstart
&& cur_line
<= r
->vend
) {
301 val
|= ST01_V_RETRACE
| ST01_DISP_ENABLE
;
303 cur_line_char
= cur_char
% r
->htotal
;
304 if (cur_line_char
>= r
->hstart
&& cur_line_char
<= r
->hend
) {
305 val
|= ST01_DISP_ENABLE
;
311 return s
->st01
^ (ST01_V_RETRACE
| ST01_DISP_ENABLE
);
315 static uint8_t vga_dumb_retrace(VGACommonState
*s
)
317 return s
->st01
^ (ST01_V_RETRACE
| ST01_DISP_ENABLE
);
320 int vga_ioport_invalid(VGACommonState
*s
, uint32_t addr
)
322 if (s
->msr
& VGA_MIS_COLOR
) {
324 return (addr
>= 0x3b0 && addr
<= 0x3bf);
327 return (addr
>= 0x3d0 && addr
<= 0x3df);
331 uint32_t vga_ioport_read(void *opaque
, uint32_t addr
)
333 VGACommonState
*s
= opaque
;
336 if (vga_ioport_invalid(s
, addr
)) {
341 if (s
->ar_flip_flop
== 0) {
348 index
= s
->ar_index
& 0x1f;
349 if (index
< VGA_ATT_C
) {
362 val
= s
->sr
[s
->sr_index
];
364 printf("vga: read SR%x = 0x%02x\n", s
->sr_index
, val
);
371 val
= s
->dac_write_index
;
374 val
= s
->palette
[s
->dac_read_index
* 3 + s
->dac_sub_index
];
375 if (++s
->dac_sub_index
== 3) {
376 s
->dac_sub_index
= 0;
390 val
= s
->gr
[s
->gr_index
];
392 printf("vga: read GR%x = 0x%02x\n", s
->gr_index
, val
);
401 val
= s
->cr
[s
->cr_index
];
403 printf("vga: read CR%x = 0x%02x\n", s
->cr_index
, val
);
408 /* just toggle to fool polling */
409 val
= s
->st01
= s
->retrace(s
);
417 #if defined(DEBUG_VGA)
418 printf("VGA: read addr=0x%04x data=0x%02x\n", addr
, val
);
423 void vga_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
425 VGACommonState
*s
= opaque
;
428 /* check port range access depending on color/monochrome mode */
429 if (vga_ioport_invalid(s
, addr
)) {
433 printf("VGA: write addr=0x%04x data=0x%02x\n", addr
, val
);
438 if (s
->ar_flip_flop
== 0) {
442 index
= s
->ar_index
& 0x1f;
444 case VGA_ATC_PALETTE0
... VGA_ATC_PALETTEF
:
445 s
->ar
[index
] = val
& 0x3f;
448 s
->ar
[index
] = val
& ~0x10;
450 case VGA_ATC_OVERSCAN
:
453 case VGA_ATC_PLANE_ENABLE
:
454 s
->ar
[index
] = val
& ~0xc0;
457 s
->ar
[index
] = val
& ~0xf0;
459 case VGA_ATC_COLOR_PAGE
:
460 s
->ar
[index
] = val
& ~0xf0;
466 s
->ar_flip_flop
^= 1;
469 s
->msr
= val
& ~0x10;
470 s
->update_retrace_info(s
);
473 s
->sr_index
= val
& 7;
477 printf("vga: write SR%x = 0x%02x\n", s
->sr_index
, val
);
479 s
->sr
[s
->sr_index
] = val
& sr_mask
[s
->sr_index
];
480 if (s
->sr_index
== VGA_SEQ_CLOCK_MODE
) {
481 s
->update_retrace_info(s
);
483 vga_update_memory_access(s
);
486 s
->dac_read_index
= val
;
487 s
->dac_sub_index
= 0;
491 s
->dac_write_index
= val
;
492 s
->dac_sub_index
= 0;
496 s
->dac_cache
[s
->dac_sub_index
] = val
;
497 if (++s
->dac_sub_index
== 3) {
498 memcpy(&s
->palette
[s
->dac_write_index
* 3], s
->dac_cache
, 3);
499 s
->dac_sub_index
= 0;
500 s
->dac_write_index
++;
504 s
->gr_index
= val
& 0x0f;
508 printf("vga: write GR%x = 0x%02x\n", s
->gr_index
, val
);
510 s
->gr
[s
->gr_index
] = val
& gr_mask
[s
->gr_index
];
511 vga_update_memory_access(s
);
520 printf("vga: write CR%x = 0x%02x\n", s
->cr_index
, val
);
522 /* handle CR0-7 protection */
523 if ((s
->cr
[VGA_CRTC_V_SYNC_END
] & VGA_CR11_LOCK_CR0_CR7
) &&
524 s
->cr_index
<= VGA_CRTC_OVERFLOW
) {
525 /* can always write bit 4 of CR7 */
526 if (s
->cr_index
== VGA_CRTC_OVERFLOW
) {
527 s
->cr
[VGA_CRTC_OVERFLOW
] = (s
->cr
[VGA_CRTC_OVERFLOW
] & ~0x10) |
532 s
->cr
[s
->cr_index
] = val
;
534 switch(s
->cr_index
) {
535 case VGA_CRTC_H_TOTAL
:
536 case VGA_CRTC_H_SYNC_START
:
537 case VGA_CRTC_H_SYNC_END
:
538 case VGA_CRTC_V_TOTAL
:
539 case VGA_CRTC_OVERFLOW
:
540 case VGA_CRTC_V_SYNC_END
:
542 s
->update_retrace_info(s
);
554 * Sanity check vbe register writes.
556 * As we don't have a way to signal errors to the guest in the bochs
557 * dispi interface we'll go adjust the registers to the closest valid
560 static void vbe_fixup_regs(VGACommonState
*s
)
562 uint16_t *r
= s
->vbe_regs
;
563 uint32_t bits
, linelength
, maxy
, offset
;
565 if (!(r
[VBE_DISPI_INDEX_ENABLE
] & VBE_DISPI_ENABLED
)) {
566 /* vbe is turned off -- nothing to do */
571 switch (r
[VBE_DISPI_INDEX_BPP
]) {
577 bits
= r
[VBE_DISPI_INDEX_BPP
];
583 bits
= r
[VBE_DISPI_INDEX_BPP
] = 8;
588 r
[VBE_DISPI_INDEX_XRES
] &= ~7u;
589 if (r
[VBE_DISPI_INDEX_XRES
] == 0) {
590 r
[VBE_DISPI_INDEX_XRES
] = 8;
592 if (r
[VBE_DISPI_INDEX_XRES
] > VBE_DISPI_MAX_XRES
) {
593 r
[VBE_DISPI_INDEX_XRES
] = VBE_DISPI_MAX_XRES
;
595 r
[VBE_DISPI_INDEX_VIRT_WIDTH
] &= ~7u;
596 if (r
[VBE_DISPI_INDEX_VIRT_WIDTH
] > VBE_DISPI_MAX_XRES
) {
597 r
[VBE_DISPI_INDEX_VIRT_WIDTH
] = VBE_DISPI_MAX_XRES
;
599 if (r
[VBE_DISPI_INDEX_VIRT_WIDTH
] < r
[VBE_DISPI_INDEX_XRES
]) {
600 r
[VBE_DISPI_INDEX_VIRT_WIDTH
] = r
[VBE_DISPI_INDEX_XRES
];
604 linelength
= r
[VBE_DISPI_INDEX_VIRT_WIDTH
] * bits
/ 8;
605 maxy
= s
->vbe_size
/ linelength
;
606 if (r
[VBE_DISPI_INDEX_YRES
] == 0) {
607 r
[VBE_DISPI_INDEX_YRES
] = 1;
609 if (r
[VBE_DISPI_INDEX_YRES
] > VBE_DISPI_MAX_YRES
) {
610 r
[VBE_DISPI_INDEX_YRES
] = VBE_DISPI_MAX_YRES
;
612 if (r
[VBE_DISPI_INDEX_YRES
] > maxy
) {
613 r
[VBE_DISPI_INDEX_YRES
] = maxy
;
617 if (r
[VBE_DISPI_INDEX_X_OFFSET
] > VBE_DISPI_MAX_XRES
) {
618 r
[VBE_DISPI_INDEX_X_OFFSET
] = VBE_DISPI_MAX_XRES
;
620 if (r
[VBE_DISPI_INDEX_Y_OFFSET
] > VBE_DISPI_MAX_YRES
) {
621 r
[VBE_DISPI_INDEX_Y_OFFSET
] = VBE_DISPI_MAX_YRES
;
623 offset
= r
[VBE_DISPI_INDEX_X_OFFSET
] * bits
/ 8;
624 offset
+= r
[VBE_DISPI_INDEX_Y_OFFSET
] * linelength
;
625 if (offset
+ r
[VBE_DISPI_INDEX_YRES
] * linelength
> s
->vbe_size
) {
626 r
[VBE_DISPI_INDEX_Y_OFFSET
] = 0;
627 offset
= r
[VBE_DISPI_INDEX_X_OFFSET
] * bits
/ 8;
628 if (offset
+ r
[VBE_DISPI_INDEX_YRES
] * linelength
> s
->vbe_size
) {
629 r
[VBE_DISPI_INDEX_X_OFFSET
] = 0;
634 /* update vga state */
635 r
[VBE_DISPI_INDEX_VIRT_HEIGHT
] = maxy
;
636 s
->vbe_line_offset
= linelength
;
637 s
->vbe_start_addr
= offset
/ 4;
640 static uint32_t vbe_ioport_read_index(void *opaque
, uint32_t addr
)
642 VGACommonState
*s
= opaque
;
648 uint32_t vbe_ioport_read_data(void *opaque
, uint32_t addr
)
650 VGACommonState
*s
= opaque
;
653 if (s
->vbe_index
< VBE_DISPI_INDEX_NB
) {
654 if (s
->vbe_regs
[VBE_DISPI_INDEX_ENABLE
] & VBE_DISPI_GETCAPS
) {
655 switch(s
->vbe_index
) {
656 /* XXX: do not hardcode ? */
657 case VBE_DISPI_INDEX_XRES
:
658 val
= VBE_DISPI_MAX_XRES
;
660 case VBE_DISPI_INDEX_YRES
:
661 val
= VBE_DISPI_MAX_YRES
;
663 case VBE_DISPI_INDEX_BPP
:
664 val
= VBE_DISPI_MAX_BPP
;
667 val
= s
->vbe_regs
[s
->vbe_index
];
671 val
= s
->vbe_regs
[s
->vbe_index
];
673 } else if (s
->vbe_index
== VBE_DISPI_INDEX_VIDEO_MEMORY_64K
) {
674 val
= s
->vbe_size
/ (64 * 1024);
678 #ifdef DEBUG_BOCHS_VBE
679 printf("VBE: read index=0x%x val=0x%x\n", s
->vbe_index
, val
);
684 void vbe_ioport_write_index(void *opaque
, uint32_t addr
, uint32_t val
)
686 VGACommonState
*s
= opaque
;
690 void vbe_ioport_write_data(void *opaque
, uint32_t addr
, uint32_t val
)
692 VGACommonState
*s
= opaque
;
694 if (s
->vbe_index
<= VBE_DISPI_INDEX_NB
) {
695 #ifdef DEBUG_BOCHS_VBE
696 printf("VBE: write index=0x%x val=0x%x\n", s
->vbe_index
, val
);
698 switch(s
->vbe_index
) {
699 case VBE_DISPI_INDEX_ID
:
700 if (val
== VBE_DISPI_ID0
||
701 val
== VBE_DISPI_ID1
||
702 val
== VBE_DISPI_ID2
||
703 val
== VBE_DISPI_ID3
||
704 val
== VBE_DISPI_ID4
) {
705 s
->vbe_regs
[s
->vbe_index
] = val
;
708 case VBE_DISPI_INDEX_XRES
:
709 case VBE_DISPI_INDEX_YRES
:
710 case VBE_DISPI_INDEX_BPP
:
711 case VBE_DISPI_INDEX_VIRT_WIDTH
:
712 case VBE_DISPI_INDEX_X_OFFSET
:
713 case VBE_DISPI_INDEX_Y_OFFSET
:
714 s
->vbe_regs
[s
->vbe_index
] = val
;
717 case VBE_DISPI_INDEX_BANK
:
718 if (s
->vbe_regs
[VBE_DISPI_INDEX_BPP
] == 4) {
719 val
&= (s
->vbe_bank_mask
>> 2);
721 val
&= s
->vbe_bank_mask
;
723 s
->vbe_regs
[s
->vbe_index
] = val
;
724 s
->bank_offset
= (val
<< 16);
725 vga_update_memory_access(s
);
727 case VBE_DISPI_INDEX_ENABLE
:
728 if ((val
& VBE_DISPI_ENABLED
) &&
729 !(s
->vbe_regs
[VBE_DISPI_INDEX_ENABLE
] & VBE_DISPI_ENABLED
)) {
730 int h
, shift_control
;
732 s
->vbe_regs
[VBE_DISPI_INDEX_VIRT_WIDTH
] = 0;
733 s
->vbe_regs
[VBE_DISPI_INDEX_X_OFFSET
] = 0;
734 s
->vbe_regs
[VBE_DISPI_INDEX_Y_OFFSET
] = 0;
735 s
->vbe_regs
[VBE_DISPI_INDEX_ENABLE
] |= VBE_DISPI_ENABLED
;
738 /* clear the screen */
739 if (!(val
& VBE_DISPI_NOCLEARMEM
)) {
740 memset(s
->vram_ptr
, 0,
741 s
->vbe_regs
[VBE_DISPI_INDEX_YRES
] * s
->vbe_line_offset
);
744 /* we initialize the VGA graphic mode */
745 /* graphic mode + memory map 1 */
746 s
->gr
[VGA_GFX_MISC
] = (s
->gr
[VGA_GFX_MISC
] & ~0x0c) | 0x04 |
747 VGA_GR06_GRAPHICS_MODE
;
748 s
->cr
[VGA_CRTC_MODE
] |= 3; /* no CGA modes */
749 s
->cr
[VGA_CRTC_OFFSET
] = s
->vbe_line_offset
>> 3;
751 s
->cr
[VGA_CRTC_H_DISP
] =
752 (s
->vbe_regs
[VBE_DISPI_INDEX_XRES
] >> 3) - 1;
753 /* height (only meaningful if < 1024) */
754 h
= s
->vbe_regs
[VBE_DISPI_INDEX_YRES
] - 1;
755 s
->cr
[VGA_CRTC_V_DISP_END
] = h
;
756 s
->cr
[VGA_CRTC_OVERFLOW
] = (s
->cr
[VGA_CRTC_OVERFLOW
] & ~0x42) |
757 ((h
>> 7) & 0x02) | ((h
>> 3) & 0x40);
758 /* line compare to 1023 */
759 s
->cr
[VGA_CRTC_LINE_COMPARE
] = 0xff;
760 s
->cr
[VGA_CRTC_OVERFLOW
] |= 0x10;
761 s
->cr
[VGA_CRTC_MAX_SCAN
] |= 0x40;
763 if (s
->vbe_regs
[VBE_DISPI_INDEX_BPP
] == 4) {
765 s
->sr
[VGA_SEQ_CLOCK_MODE
] &= ~8; /* no double line */
768 /* set chain 4 mode */
769 s
->sr
[VGA_SEQ_MEMORY_MODE
] |= VGA_SR04_CHN_4M
;
770 /* activate all planes */
771 s
->sr
[VGA_SEQ_PLANE_WRITE
] |= VGA_SR02_ALL_PLANES
;
773 s
->gr
[VGA_GFX_MODE
] = (s
->gr
[VGA_GFX_MODE
] & ~0x60) |
774 (shift_control
<< 5);
775 s
->cr
[VGA_CRTC_MAX_SCAN
] &= ~0x9f; /* no double scan */
779 s
->dac_8bit
= (val
& VBE_DISPI_8BIT_DAC
) > 0;
780 s
->vbe_regs
[s
->vbe_index
] = val
;
781 vga_update_memory_access(s
);
789 /* called for accesses between 0xa0000 and 0xc0000 */
790 uint32_t vga_mem_readb(VGACommonState
*s
, hwaddr addr
)
792 int memory_map_mode
, plane
;
795 /* convert to VGA memory offset */
796 memory_map_mode
= (s
->gr
[VGA_GFX_MISC
] >> 2) & 3;
798 switch(memory_map_mode
) {
804 addr
+= s
->bank_offset
;
819 if (s
->sr
[VGA_SEQ_MEMORY_MODE
] & VGA_SR04_CHN_4M
) {
820 /* chain 4 mode : simplest access */
821 ret
= s
->vram_ptr
[addr
];
822 } else if (s
->gr
[VGA_GFX_MODE
] & 0x10) {
823 /* odd/even mode (aka text mode mapping) */
824 plane
= (s
->gr
[VGA_GFX_PLANE_READ
] & 2) | (addr
& 1);
825 ret
= s
->vram_ptr
[((addr
& ~1) << 1) | plane
];
827 /* standard VGA latched access */
828 s
->latch
= ((uint32_t *)s
->vram_ptr
)[addr
];
830 if (!(s
->gr
[VGA_GFX_MODE
] & 0x08)) {
832 plane
= s
->gr
[VGA_GFX_PLANE_READ
];
833 ret
= GET_PLANE(s
->latch
, plane
);
836 ret
= (s
->latch
^ mask16
[s
->gr
[VGA_GFX_COMPARE_VALUE
]]) &
837 mask16
[s
->gr
[VGA_GFX_COMPARE_MASK
]];
846 /* called for accesses between 0xa0000 and 0xc0000 */
847 void vga_mem_writeb(VGACommonState
*s
, hwaddr addr
, uint32_t val
)
849 int memory_map_mode
, plane
, write_mode
, b
, func_select
, mask
;
850 uint32_t write_mask
, bit_mask
, set_mask
;
853 printf("vga: [0x" TARGET_FMT_plx
"] = 0x%02x\n", addr
, val
);
855 /* convert to VGA memory offset */
856 memory_map_mode
= (s
->gr
[VGA_GFX_MISC
] >> 2) & 3;
858 switch(memory_map_mode
) {
864 addr
+= s
->bank_offset
;
879 if (s
->sr
[VGA_SEQ_MEMORY_MODE
] & VGA_SR04_CHN_4M
) {
880 /* chain 4 mode : simplest access */
883 if (s
->sr
[VGA_SEQ_PLANE_WRITE
] & mask
) {
884 s
->vram_ptr
[addr
] = val
;
886 printf("vga: chain4: [0x" TARGET_FMT_plx
"]\n", addr
);
888 s
->plane_updated
|= mask
; /* only used to detect font change */
889 memory_region_set_dirty(&s
->vram
, addr
, 1);
891 } else if (s
->gr
[VGA_GFX_MODE
] & 0x10) {
892 /* odd/even mode (aka text mode mapping) */
893 plane
= (s
->gr
[VGA_GFX_PLANE_READ
] & 2) | (addr
& 1);
895 if (s
->sr
[VGA_SEQ_PLANE_WRITE
] & mask
) {
896 addr
= ((addr
& ~1) << 1) | plane
;
897 s
->vram_ptr
[addr
] = val
;
899 printf("vga: odd/even: [0x" TARGET_FMT_plx
"]\n", addr
);
901 s
->plane_updated
|= mask
; /* only used to detect font change */
902 memory_region_set_dirty(&s
->vram
, addr
, 1);
905 /* standard VGA latched access */
906 write_mode
= s
->gr
[VGA_GFX_MODE
] & 3;
911 b
= s
->gr
[VGA_GFX_DATA_ROTATE
] & 7;
912 val
= ((val
>> b
) | (val
<< (8 - b
))) & 0xff;
916 /* apply set/reset mask */
917 set_mask
= mask16
[s
->gr
[VGA_GFX_SR_ENABLE
]];
918 val
= (val
& ~set_mask
) |
919 (mask16
[s
->gr
[VGA_GFX_SR_VALUE
]] & set_mask
);
920 bit_mask
= s
->gr
[VGA_GFX_BIT_MASK
];
926 val
= mask16
[val
& 0x0f];
927 bit_mask
= s
->gr
[VGA_GFX_BIT_MASK
];
931 b
= s
->gr
[VGA_GFX_DATA_ROTATE
] & 7;
932 val
= (val
>> b
) | (val
<< (8 - b
));
934 bit_mask
= s
->gr
[VGA_GFX_BIT_MASK
] & val
;
935 val
= mask16
[s
->gr
[VGA_GFX_SR_VALUE
]];
939 /* apply logical operation */
940 func_select
= s
->gr
[VGA_GFX_DATA_ROTATE
] >> 3;
941 switch(func_select
) {
961 bit_mask
|= bit_mask
<< 8;
962 bit_mask
|= bit_mask
<< 16;
963 val
= (val
& bit_mask
) | (s
->latch
& ~bit_mask
);
966 /* mask data according to sr[2] */
967 mask
= s
->sr
[VGA_SEQ_PLANE_WRITE
];
968 s
->plane_updated
|= mask
; /* only used to detect font change */
969 write_mask
= mask16
[mask
];
970 ((uint32_t *)s
->vram_ptr
)[addr
] =
971 (((uint32_t *)s
->vram_ptr
)[addr
] & ~write_mask
) |
974 printf("vga: latch: [0x" TARGET_FMT_plx
"] mask=0x%08x val=0x%08x\n",
975 addr
* 4, write_mask
, val
);
977 memory_region_set_dirty(&s
->vram
, addr
<< 2, sizeof(uint32_t));
981 typedef void vga_draw_line_func(VGACommonState
*s1
, uint8_t *d
,
982 const uint8_t *s
, int width
);
984 #include "vga-helpers.h"
986 /* return true if the palette was modified */
987 static int update_palette16(VGACommonState
*s
)
990 uint32_t v
, col
, *palette
;
993 palette
= s
->last_palette
;
994 for(i
= 0; i
< 16; i
++) {
996 if (s
->ar
[VGA_ATC_MODE
] & 0x80) {
997 v
= ((s
->ar
[VGA_ATC_COLOR_PAGE
] & 0xf) << 4) | (v
& 0xf);
999 v
= ((s
->ar
[VGA_ATC_COLOR_PAGE
] & 0xc) << 4) | (v
& 0x3f);
1002 col
= rgb_to_pixel32(c6_to_8(s
->palette
[v
]),
1003 c6_to_8(s
->palette
[v
+ 1]),
1004 c6_to_8(s
->palette
[v
+ 2]));
1005 if (col
!= palette
[i
]) {
1013 /* return true if the palette was modified */
1014 static int update_palette256(VGACommonState
*s
)
1017 uint32_t v
, col
, *palette
;
1020 palette
= s
->last_palette
;
1022 for(i
= 0; i
< 256; i
++) {
1024 col
= rgb_to_pixel32(s
->palette
[v
],
1028 col
= rgb_to_pixel32(c6_to_8(s
->palette
[v
]),
1029 c6_to_8(s
->palette
[v
+ 1]),
1030 c6_to_8(s
->palette
[v
+ 2]));
1032 if (col
!= palette
[i
]) {
1041 static void vga_get_offsets(VGACommonState
*s
,
1042 uint32_t *pline_offset
,
1043 uint32_t *pstart_addr
,
1044 uint32_t *pline_compare
)
1046 uint32_t start_addr
, line_offset
, line_compare
;
1048 if (s
->vbe_regs
[VBE_DISPI_INDEX_ENABLE
] & VBE_DISPI_ENABLED
) {
1049 line_offset
= s
->vbe_line_offset
;
1050 start_addr
= s
->vbe_start_addr
;
1051 line_compare
= 65535;
1053 /* compute line_offset in bytes */
1054 line_offset
= s
->cr
[VGA_CRTC_OFFSET
];
1057 /* starting address */
1058 start_addr
= s
->cr
[VGA_CRTC_START_LO
] |
1059 (s
->cr
[VGA_CRTC_START_HI
] << 8);
1062 line_compare
= s
->cr
[VGA_CRTC_LINE_COMPARE
] |
1063 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x10) << 4) |
1064 ((s
->cr
[VGA_CRTC_MAX_SCAN
] & 0x40) << 3);
1066 *pline_offset
= line_offset
;
1067 *pstart_addr
= start_addr
;
1068 *pline_compare
= line_compare
;
1071 /* update start_addr and line_offset. Return TRUE if modified */
1072 static int update_basic_params(VGACommonState
*s
)
1075 uint32_t start_addr
, line_offset
, line_compare
;
1079 s
->get_offsets(s
, &line_offset
, &start_addr
, &line_compare
);
1081 if (line_offset
!= s
->line_offset
||
1082 start_addr
!= s
->start_addr
||
1083 line_compare
!= s
->line_compare
) {
1084 s
->line_offset
= line_offset
;
1085 s
->start_addr
= start_addr
;
1086 s
->line_compare
= line_compare
;
1093 static const uint8_t cursor_glyph
[32 * 4] = {
1094 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1095 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1096 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1097 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1098 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1099 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1100 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1101 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1102 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1103 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1104 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1105 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1106 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1107 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1108 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1109 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1112 static void vga_get_text_resolution(VGACommonState
*s
, int *pwidth
, int *pheight
,
1113 int *pcwidth
, int *pcheight
)
1115 int width
, cwidth
, height
, cheight
;
1117 /* total width & height */
1118 cheight
= (s
->cr
[VGA_CRTC_MAX_SCAN
] & 0x1f) + 1;
1120 if (!(s
->sr
[VGA_SEQ_CLOCK_MODE
] & VGA_SR01_CHAR_CLK_8DOTS
)) {
1123 if (s
->sr
[VGA_SEQ_CLOCK_MODE
] & 0x08) {
1124 cwidth
= 16; /* NOTE: no 18 pixel wide */
1126 width
= (s
->cr
[VGA_CRTC_H_DISP
] + 1);
1127 if (s
->cr
[VGA_CRTC_V_TOTAL
] == 100) {
1128 /* ugly hack for CGA 160x100x16 - explain me the logic */
1131 height
= s
->cr
[VGA_CRTC_V_DISP_END
] |
1132 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x02) << 7) |
1133 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x40) << 3);
1134 height
= (height
+ 1) / cheight
;
1140 *pcheight
= cheight
;
1151 static void vga_draw_text(VGACommonState
*s
, int full_update
)
1153 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
1154 int cx
, cy
, cheight
, cw
, ch
, cattr
, height
, width
, ch_attr
;
1155 int cx_min
, cx_max
, linesize
, x_incr
, line
, line1
;
1156 uint32_t offset
, fgcol
, bgcol
, v
, cursor_offset
;
1157 uint8_t *d1
, *d
, *src
, *dest
, *cursor_ptr
;
1158 const uint8_t *font_ptr
, *font_base
[2];
1159 int dup9
, line_offset
;
1161 uint32_t *ch_attr_ptr
;
1162 int64_t now
= qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
);
1164 /* compute font data address (in plane 2) */
1165 v
= s
->sr
[VGA_SEQ_CHARACTER_MAP
];
1166 offset
= (((v
>> 4) & 1) | ((v
<< 1) & 6)) * 8192 * 4 + 2;
1167 if (offset
!= s
->font_offsets
[0]) {
1168 s
->font_offsets
[0] = offset
;
1171 font_base
[0] = s
->vram_ptr
+ offset
;
1173 offset
= (((v
>> 5) & 1) | ((v
>> 1) & 6)) * 8192 * 4 + 2;
1174 font_base
[1] = s
->vram_ptr
+ offset
;
1175 if (offset
!= s
->font_offsets
[1]) {
1176 s
->font_offsets
[1] = offset
;
1179 if (s
->plane_updated
& (1 << 2) || s
->has_chain4_alias
) {
1180 /* if the plane 2 was modified since the last display, it
1181 indicates the font may have been modified */
1182 s
->plane_updated
= 0;
1185 full_update
|= update_basic_params(s
);
1187 line_offset
= s
->line_offset
;
1189 vga_get_text_resolution(s
, &width
, &height
, &cw
, &cheight
);
1190 if ((height
* width
) <= 1) {
1191 /* better than nothing: exit if transient size is too small */
1194 if ((height
* width
) > CH_ATTR_SIZE
) {
1195 /* better than nothing: exit if transient size is too big */
1199 if (width
!= s
->last_width
|| height
!= s
->last_height
||
1200 cw
!= s
->last_cw
|| cheight
!= s
->last_ch
|| s
->last_depth
) {
1201 s
->last_scr_width
= width
* cw
;
1202 s
->last_scr_height
= height
* cheight
;
1203 qemu_console_resize(s
->con
, s
->last_scr_width
, s
->last_scr_height
);
1204 surface
= qemu_console_surface(s
->con
);
1205 dpy_text_resize(s
->con
, width
, height
);
1207 s
->last_width
= width
;
1208 s
->last_height
= height
;
1209 s
->last_ch
= cheight
;
1213 full_update
|= update_palette16(s
);
1214 palette
= s
->last_palette
;
1215 x_incr
= cw
* surface_bytes_per_pixel(surface
);
1218 s
->full_update_text
= 1;
1220 if (s
->full_update_gfx
) {
1221 s
->full_update_gfx
= 0;
1225 cursor_offset
= ((s
->cr
[VGA_CRTC_CURSOR_HI
] << 8) |
1226 s
->cr
[VGA_CRTC_CURSOR_LO
]) - s
->start_addr
;
1227 if (cursor_offset
!= s
->cursor_offset
||
1228 s
->cr
[VGA_CRTC_CURSOR_START
] != s
->cursor_start
||
1229 s
->cr
[VGA_CRTC_CURSOR_END
] != s
->cursor_end
) {
1230 /* if the cursor position changed, we update the old and new
1232 if (s
->cursor_offset
< CH_ATTR_SIZE
)
1233 s
->last_ch_attr
[s
->cursor_offset
] = -1;
1234 if (cursor_offset
< CH_ATTR_SIZE
)
1235 s
->last_ch_attr
[cursor_offset
] = -1;
1236 s
->cursor_offset
= cursor_offset
;
1237 s
->cursor_start
= s
->cr
[VGA_CRTC_CURSOR_START
];
1238 s
->cursor_end
= s
->cr
[VGA_CRTC_CURSOR_END
];
1240 cursor_ptr
= s
->vram_ptr
+ (s
->start_addr
+ cursor_offset
) * 4;
1241 if (now
>= s
->cursor_blink_time
) {
1242 s
->cursor_blink_time
= now
+ VGA_TEXT_CURSOR_PERIOD_MS
/ 2;
1243 s
->cursor_visible_phase
= !s
->cursor_visible_phase
;
1246 dest
= surface_data(surface
);
1247 linesize
= surface_stride(surface
);
1248 ch_attr_ptr
= s
->last_ch_attr
;
1250 offset
= s
->start_addr
* 4;
1251 for(cy
= 0; cy
< height
; cy
++) {
1253 src
= s
->vram_ptr
+ offset
;
1256 for(cx
= 0; cx
< width
; cx
++) {
1257 ch_attr
= *(uint16_t *)src
;
1258 if (full_update
|| ch_attr
!= *ch_attr_ptr
|| src
== cursor_ptr
) {
1263 *ch_attr_ptr
= ch_attr
;
1264 #ifdef HOST_WORDS_BIGENDIAN
1266 cattr
= ch_attr
& 0xff;
1268 ch
= ch_attr
& 0xff;
1269 cattr
= ch_attr
>> 8;
1271 font_ptr
= font_base
[(cattr
>> 3) & 1];
1272 font_ptr
+= 32 * 4 * ch
;
1273 bgcol
= palette
[cattr
>> 4];
1274 fgcol
= palette
[cattr
& 0x0f];
1276 vga_draw_glyph16(d1
, linesize
,
1277 font_ptr
, cheight
, fgcol
, bgcol
);
1278 } else if (cw
!= 9) {
1279 vga_draw_glyph8(d1
, linesize
,
1280 font_ptr
, cheight
, fgcol
, bgcol
);
1283 if (ch
>= 0xb0 && ch
<= 0xdf &&
1284 (s
->ar
[VGA_ATC_MODE
] & 0x04)) {
1287 vga_draw_glyph9(d1
, linesize
,
1288 font_ptr
, cheight
, fgcol
, bgcol
, dup9
);
1290 if (src
== cursor_ptr
&&
1291 !(s
->cr
[VGA_CRTC_CURSOR_START
] & 0x20) &&
1292 s
->cursor_visible_phase
) {
1293 int line_start
, line_last
, h
;
1294 /* draw the cursor */
1295 line_start
= s
->cr
[VGA_CRTC_CURSOR_START
] & 0x1f;
1296 line_last
= s
->cr
[VGA_CRTC_CURSOR_END
] & 0x1f;
1297 /* XXX: check that */
1298 if (line_last
> cheight
- 1)
1299 line_last
= cheight
- 1;
1300 if (line_last
>= line_start
&& line_start
< cheight
) {
1301 h
= line_last
- line_start
+ 1;
1302 d
= d1
+ linesize
* line_start
;
1304 vga_draw_glyph16(d
, linesize
,
1305 cursor_glyph
, h
, fgcol
, bgcol
);
1306 } else if (cw
!= 9) {
1307 vga_draw_glyph8(d
, linesize
,
1308 cursor_glyph
, h
, fgcol
, bgcol
);
1310 vga_draw_glyph9(d
, linesize
,
1311 cursor_glyph
, h
, fgcol
, bgcol
, 1);
1321 dpy_gfx_update(s
->con
, cx_min
* cw
, cy
* cheight
,
1322 (cx_max
- cx_min
+ 1) * cw
, cheight
);
1324 dest
+= linesize
* cheight
;
1325 line1
= line
+ cheight
;
1326 offset
+= line_offset
;
1327 if (line
< s
->line_compare
&& line1
>= s
->line_compare
) {
1352 static vga_draw_line_func
* const vga_draw_line_table
[VGA_DRAW_LINE_NB
] = {
1369 static int vga_get_bpp(VGACommonState
*s
)
1373 if (s
->vbe_regs
[VBE_DISPI_INDEX_ENABLE
] & VBE_DISPI_ENABLED
) {
1374 ret
= s
->vbe_regs
[VBE_DISPI_INDEX_BPP
];
1381 static void vga_get_resolution(VGACommonState
*s
, int *pwidth
, int *pheight
)
1385 if (s
->vbe_regs
[VBE_DISPI_INDEX_ENABLE
] & VBE_DISPI_ENABLED
) {
1386 width
= s
->vbe_regs
[VBE_DISPI_INDEX_XRES
];
1387 height
= s
->vbe_regs
[VBE_DISPI_INDEX_YRES
];
1389 width
= (s
->cr
[VGA_CRTC_H_DISP
] + 1) * 8;
1390 height
= s
->cr
[VGA_CRTC_V_DISP_END
] |
1391 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x02) << 7) |
1392 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x40) << 3);
1393 height
= (height
+ 1);
1399 void vga_invalidate_scanlines(VGACommonState
*s
, int y1
, int y2
)
1402 if (y1
>= VGA_MAX_HEIGHT
)
1404 if (y2
>= VGA_MAX_HEIGHT
)
1405 y2
= VGA_MAX_HEIGHT
;
1406 for(y
= y1
; y
< y2
; y
++) {
1407 s
->invalidated_y_table
[y
>> 5] |= 1 << (y
& 0x1f);
1411 void vga_sync_dirty_bitmap(VGACommonState
*s
)
1413 memory_region_sync_dirty_bitmap(&s
->vram
);
1416 void vga_dirty_log_start(VGACommonState
*s
)
1418 memory_region_set_log(&s
->vram
, true, DIRTY_MEMORY_VGA
);
1421 void vga_dirty_log_stop(VGACommonState
*s
)
1423 memory_region_set_log(&s
->vram
, false, DIRTY_MEMORY_VGA
);
1429 static void vga_draw_graphic(VGACommonState
*s
, int full_update
)
1431 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
1432 int y1
, y
, update
, linesize
, y_start
, double_scan
, mask
, depth
;
1433 int width
, height
, shift_control
, line_offset
, bwidth
, bits
;
1434 ram_addr_t page0
, page1
, page_min
, page_max
;
1435 int disp_width
, multi_scan
, multi_run
;
1437 uint32_t v
, addr1
, addr
;
1438 vga_draw_line_func
*vga_draw_line
= NULL
;
1440 pixman_format_code_t format
;
1441 #ifdef HOST_WORDS_BIGENDIAN
1442 bool byteswap
= !s
->big_endian_fb
;
1444 bool byteswap
= s
->big_endian_fb
;
1447 full_update
|= update_basic_params(s
);
1450 vga_sync_dirty_bitmap(s
);
1452 s
->get_resolution(s
, &width
, &height
);
1455 shift_control
= (s
->gr
[VGA_GFX_MODE
] >> 5) & 3;
1456 double_scan
= (s
->cr
[VGA_CRTC_MAX_SCAN
] >> 7);
1457 if (shift_control
!= 1) {
1458 multi_scan
= (((s
->cr
[VGA_CRTC_MAX_SCAN
] & 0x1f) + 1) << double_scan
)
1461 /* in CGA modes, multi_scan is ignored */
1462 /* XXX: is it correct ? */
1463 multi_scan
= double_scan
;
1465 multi_run
= multi_scan
;
1466 if (shift_control
!= s
->shift_control
||
1467 double_scan
!= s
->double_scan
) {
1469 s
->shift_control
= shift_control
;
1470 s
->double_scan
= double_scan
;
1473 if (shift_control
== 0) {
1474 if (s
->sr
[VGA_SEQ_CLOCK_MODE
] & 8) {
1477 } else if (shift_control
== 1) {
1478 if (s
->sr
[VGA_SEQ_CLOCK_MODE
] & 8) {
1483 depth
= s
->get_bpp(s
);
1486 * Check whether we can share the surface with the backend
1487 * or whether we need a shadow surface. We share native
1488 * endian surfaces for 15bpp and above and byteswapped
1489 * surfaces for 24bpp and above.
1491 format
= qemu_default_pixman_format(depth
, !byteswap
);
1493 share_surface
= dpy_gfx_check_format(s
->con
, format
)
1494 && !s
->force_shadow
;
1496 share_surface
= false;
1498 if (s
->line_offset
!= s
->last_line_offset
||
1499 disp_width
!= s
->last_width
||
1500 height
!= s
->last_height
||
1501 s
->last_depth
!= depth
||
1502 s
->last_byteswap
!= byteswap
||
1503 share_surface
!= is_buffer_shared(surface
)) {
1504 if (share_surface
) {
1505 surface
= qemu_create_displaysurface_from(disp_width
,
1506 height
, format
, s
->line_offset
,
1507 s
->vram_ptr
+ (s
->start_addr
* 4));
1508 dpy_gfx_replace_surface(s
->con
, surface
);
1510 printf("VGA: Using shared surface for depth=%d swap=%d\n",
1514 qemu_console_resize(s
->con
, disp_width
, height
);
1515 surface
= qemu_console_surface(s
->con
);
1517 printf("VGA: Using shadow surface for depth=%d swap=%d\n",
1521 s
->last_scr_width
= disp_width
;
1522 s
->last_scr_height
= height
;
1523 s
->last_width
= disp_width
;
1524 s
->last_height
= height
;
1525 s
->last_line_offset
= s
->line_offset
;
1526 s
->last_depth
= depth
;
1527 s
->last_byteswap
= byteswap
;
1529 } else if (is_buffer_shared(surface
) &&
1530 (full_update
|| surface_data(surface
) != s
->vram_ptr
1531 + (s
->start_addr
* 4))) {
1532 pixman_format_code_t format
=
1533 qemu_default_pixman_format(depth
, !byteswap
);
1534 surface
= qemu_create_displaysurface_from(disp_width
,
1535 height
, format
, s
->line_offset
,
1536 s
->vram_ptr
+ (s
->start_addr
* 4));
1537 dpy_gfx_replace_surface(s
->con
, surface
);
1540 if (shift_control
== 0) {
1541 full_update
|= update_palette16(s
);
1542 if (s
->sr
[VGA_SEQ_CLOCK_MODE
] & 8) {
1543 v
= VGA_DRAW_LINE4D2
;
1548 } else if (shift_control
== 1) {
1549 full_update
|= update_palette16(s
);
1550 if (s
->sr
[VGA_SEQ_CLOCK_MODE
] & 8) {
1551 v
= VGA_DRAW_LINE2D2
;
1557 switch(s
->get_bpp(s
)) {
1560 full_update
|= update_palette256(s
);
1561 v
= VGA_DRAW_LINE8D2
;
1565 full_update
|= update_palette256(s
);
1570 v
= s
->big_endian_fb
? VGA_DRAW_LINE15_BE
: VGA_DRAW_LINE15_LE
;
1574 v
= s
->big_endian_fb
? VGA_DRAW_LINE16_BE
: VGA_DRAW_LINE16_LE
;
1578 v
= s
->big_endian_fb
? VGA_DRAW_LINE24_BE
: VGA_DRAW_LINE24_LE
;
1582 v
= s
->big_endian_fb
? VGA_DRAW_LINE32_BE
: VGA_DRAW_LINE32_LE
;
1587 vga_draw_line
= vga_draw_line_table
[v
];
1589 if (!is_buffer_shared(surface
) && s
->cursor_invalidate
) {
1590 s
->cursor_invalidate(s
);
1593 line_offset
= s
->line_offset
;
1595 printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
1596 width
, height
, v
, line_offset
, s
->cr
[9], s
->cr
[VGA_CRTC_MODE
],
1597 s
->line_compare
, s
->sr
[VGA_SEQ_CLOCK_MODE
]);
1599 addr1
= (s
->start_addr
* 4);
1600 bwidth
= (width
* bits
+ 7) / 8;
1604 d
= surface_data(surface
);
1605 linesize
= surface_stride(surface
);
1607 for(y
= 0; y
< height
; y
++) {
1609 if (!(s
->cr
[VGA_CRTC_MODE
] & 1)) {
1611 /* CGA compatibility handling */
1612 shift
= 14 + ((s
->cr
[VGA_CRTC_MODE
] >> 6) & 1);
1613 addr
= (addr
& ~(1 << shift
)) | ((y1
& 1) << shift
);
1615 if (!(s
->cr
[VGA_CRTC_MODE
] & 2)) {
1616 addr
= (addr
& ~0x8000) | ((y1
& 2) << 14);
1618 update
= full_update
;
1620 page1
= addr
+ bwidth
- 1;
1621 update
|= memory_region_get_dirty(&s
->vram
, page0
, page1
- page0
,
1623 /* explicit invalidation for the hardware cursor */
1624 update
|= (s
->invalidated_y_table
[y
>> 5] >> (y
& 0x1f)) & 1;
1628 if (page0
< page_min
)
1630 if (page1
> page_max
)
1632 if (!(is_buffer_shared(surface
))) {
1633 vga_draw_line(s
, d
, s
->vram_ptr
+ addr
, width
);
1634 if (s
->cursor_draw_line
)
1635 s
->cursor_draw_line(s
, d
, y
);
1639 /* flush to display */
1640 dpy_gfx_update(s
->con
, 0, y_start
,
1641 disp_width
, y
- y_start
);
1646 mask
= (s
->cr
[VGA_CRTC_MODE
] & 3) ^ 3;
1647 if ((y1
& mask
) == mask
)
1648 addr1
+= line_offset
;
1650 multi_run
= multi_scan
;
1654 /* line compare acts on the displayed lines */
1655 if (y
== s
->line_compare
)
1660 /* flush to display */
1661 dpy_gfx_update(s
->con
, 0, y_start
,
1662 disp_width
, y
- y_start
);
1664 /* reset modified pages */
1665 if (page_max
>= page_min
) {
1666 memory_region_reset_dirty(&s
->vram
,
1668 page_max
- page_min
,
1671 memset(s
->invalidated_y_table
, 0, ((height
+ 31) >> 5) * 4);
1674 static void vga_draw_blank(VGACommonState
*s
, int full_update
)
1676 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
1682 if (s
->last_scr_width
<= 0 || s
->last_scr_height
<= 0)
1685 w
= s
->last_scr_width
* surface_bytes_per_pixel(surface
);
1686 d
= surface_data(surface
);
1687 for(i
= 0; i
< s
->last_scr_height
; i
++) {
1689 d
+= surface_stride(surface
);
1691 dpy_gfx_update(s
->con
, 0, 0,
1692 s
->last_scr_width
, s
->last_scr_height
);
1695 #define GMODE_TEXT 0
1696 #define GMODE_GRAPH 1
1697 #define GMODE_BLANK 2
1699 static void vga_update_display(void *opaque
)
1701 VGACommonState
*s
= opaque
;
1702 DisplaySurface
*surface
= qemu_console_surface(s
->con
);
1703 int full_update
, graphic_mode
;
1705 qemu_flush_coalesced_mmio_buffer();
1707 if (surface_bits_per_pixel(surface
) == 0) {
1711 if (!(s
->ar_index
& 0x20)) {
1712 graphic_mode
= GMODE_BLANK
;
1714 graphic_mode
= s
->gr
[VGA_GFX_MISC
] & VGA_GR06_GRAPHICS_MODE
;
1716 if (graphic_mode
!= s
->graphic_mode
) {
1717 s
->graphic_mode
= graphic_mode
;
1718 s
->cursor_blink_time
= qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
);
1721 switch(graphic_mode
) {
1723 vga_draw_text(s
, full_update
);
1726 vga_draw_graphic(s
, full_update
);
1730 vga_draw_blank(s
, full_update
);
1736 /* force a full display refresh */
1737 static void vga_invalidate_display(void *opaque
)
1739 VGACommonState
*s
= opaque
;
1742 s
->last_height
= -1;
1745 void vga_common_reset(VGACommonState
*s
)
1748 memset(s
->sr
, '\0', sizeof(s
->sr
));
1750 memset(s
->gr
, '\0', sizeof(s
->gr
));
1752 memset(s
->ar
, '\0', sizeof(s
->ar
));
1753 s
->ar_flip_flop
= 0;
1755 memset(s
->cr
, '\0', sizeof(s
->cr
));
1761 s
->dac_sub_index
= 0;
1762 s
->dac_read_index
= 0;
1763 s
->dac_write_index
= 0;
1764 memset(s
->dac_cache
, '\0', sizeof(s
->dac_cache
));
1766 memset(s
->palette
, '\0', sizeof(s
->palette
));
1769 memset(s
->vbe_regs
, '\0', sizeof(s
->vbe_regs
));
1770 s
->vbe_regs
[VBE_DISPI_INDEX_ID
] = VBE_DISPI_ID5
;
1771 s
->vbe_start_addr
= 0;
1772 s
->vbe_line_offset
= 0;
1773 s
->vbe_bank_mask
= (s
->vram_size
>> 16) - 1;
1774 memset(s
->font_offsets
, '\0', sizeof(s
->font_offsets
));
1775 s
->graphic_mode
= -1; /* force full update */
1776 s
->shift_control
= 0;
1779 s
->line_compare
= 0;
1781 s
->plane_updated
= 0;
1786 s
->last_scr_width
= 0;
1787 s
->last_scr_height
= 0;
1788 s
->cursor_start
= 0;
1790 s
->cursor_offset
= 0;
1791 s
->big_endian_fb
= s
->default_endian_fb
;
1792 memset(s
->invalidated_y_table
, '\0', sizeof(s
->invalidated_y_table
));
1793 memset(s
->last_palette
, '\0', sizeof(s
->last_palette
));
1794 memset(s
->last_ch_attr
, '\0', sizeof(s
->last_ch_attr
));
1795 switch (vga_retrace_method
) {
1796 case VGA_RETRACE_DUMB
:
1798 case VGA_RETRACE_PRECISE
:
1799 memset(&s
->retrace_info
, 0, sizeof (s
->retrace_info
));
1802 vga_update_memory_access(s
);
1805 static void vga_reset(void *opaque
)
1807 VGACommonState
*s
= opaque
;
1808 vga_common_reset(s
);
1811 #define TEXTMODE_X(x) ((x) % width)
1812 #define TEXTMODE_Y(x) ((x) / width)
1813 #define VMEM2CHTYPE(v) ((v & 0xff0007ff) | \
1814 ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
1815 /* relay text rendering to the display driver
1816 * instead of doing a full vga_update_display() */
1817 static void vga_update_text(void *opaque
, console_ch_t
*chardata
)
1819 VGACommonState
*s
= opaque
;
1820 int graphic_mode
, i
, cursor_offset
, cursor_visible
;
1821 int cw
, cheight
, width
, height
, size
, c_min
, c_max
;
1823 console_ch_t
*dst
, val
;
1824 char msg_buffer
[80];
1825 int full_update
= 0;
1827 qemu_flush_coalesced_mmio_buffer();
1829 if (!(s
->ar_index
& 0x20)) {
1830 graphic_mode
= GMODE_BLANK
;
1832 graphic_mode
= s
->gr
[VGA_GFX_MISC
] & VGA_GR06_GRAPHICS_MODE
;
1834 if (graphic_mode
!= s
->graphic_mode
) {
1835 s
->graphic_mode
= graphic_mode
;
1838 if (s
->last_width
== -1) {
1843 switch (graphic_mode
) {
1845 /* TODO: update palette */
1846 full_update
|= update_basic_params(s
);
1848 /* total width & height */
1849 cheight
= (s
->cr
[VGA_CRTC_MAX_SCAN
] & 0x1f) + 1;
1851 if (!(s
->sr
[VGA_SEQ_CLOCK_MODE
] & VGA_SR01_CHAR_CLK_8DOTS
)) {
1854 if (s
->sr
[VGA_SEQ_CLOCK_MODE
] & 0x08) {
1855 cw
= 16; /* NOTE: no 18 pixel wide */
1857 width
= (s
->cr
[VGA_CRTC_H_DISP
] + 1);
1858 if (s
->cr
[VGA_CRTC_V_TOTAL
] == 100) {
1859 /* ugly hack for CGA 160x100x16 - explain me the logic */
1862 height
= s
->cr
[VGA_CRTC_V_DISP_END
] |
1863 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x02) << 7) |
1864 ((s
->cr
[VGA_CRTC_OVERFLOW
] & 0x40) << 3);
1865 height
= (height
+ 1) / cheight
;
1868 size
= (height
* width
);
1869 if (size
> CH_ATTR_SIZE
) {
1873 snprintf(msg_buffer
, sizeof(msg_buffer
), "%i x %i Text mode",
1878 if (width
!= s
->last_width
|| height
!= s
->last_height
||
1879 cw
!= s
->last_cw
|| cheight
!= s
->last_ch
) {
1880 s
->last_scr_width
= width
* cw
;
1881 s
->last_scr_height
= height
* cheight
;
1882 qemu_console_resize(s
->con
, s
->last_scr_width
, s
->last_scr_height
);
1883 dpy_text_resize(s
->con
, width
, height
);
1885 s
->last_width
= width
;
1886 s
->last_height
= height
;
1887 s
->last_ch
= cheight
;
1893 s
->full_update_gfx
= 1;
1895 if (s
->full_update_text
) {
1896 s
->full_update_text
= 0;
1900 /* Update "hardware" cursor */
1901 cursor_offset
= ((s
->cr
[VGA_CRTC_CURSOR_HI
] << 8) |
1902 s
->cr
[VGA_CRTC_CURSOR_LO
]) - s
->start_addr
;
1903 if (cursor_offset
!= s
->cursor_offset
||
1904 s
->cr
[VGA_CRTC_CURSOR_START
] != s
->cursor_start
||
1905 s
->cr
[VGA_CRTC_CURSOR_END
] != s
->cursor_end
|| full_update
) {
1906 cursor_visible
= !(s
->cr
[VGA_CRTC_CURSOR_START
] & 0x20);
1907 if (cursor_visible
&& cursor_offset
< size
&& cursor_offset
>= 0)
1908 dpy_text_cursor(s
->con
,
1909 TEXTMODE_X(cursor_offset
),
1910 TEXTMODE_Y(cursor_offset
));
1912 dpy_text_cursor(s
->con
, -1, -1);
1913 s
->cursor_offset
= cursor_offset
;
1914 s
->cursor_start
= s
->cr
[VGA_CRTC_CURSOR_START
];
1915 s
->cursor_end
= s
->cr
[VGA_CRTC_CURSOR_END
];
1918 src
= (uint32_t *) s
->vram_ptr
+ s
->start_addr
;
1922 for (i
= 0; i
< size
; src
++, dst
++, i
++)
1923 console_write_ch(dst
, VMEM2CHTYPE(le32_to_cpu(*src
)));
1925 dpy_text_update(s
->con
, 0, 0, width
, height
);
1929 for (i
= 0; i
< size
; src
++, dst
++, i
++) {
1930 console_write_ch(&val
, VMEM2CHTYPE(le32_to_cpu(*src
)));
1938 for (; i
< size
; src
++, dst
++, i
++) {
1939 console_write_ch(&val
, VMEM2CHTYPE(le32_to_cpu(*src
)));
1946 if (c_min
<= c_max
) {
1947 i
= TEXTMODE_Y(c_min
);
1948 dpy_text_update(s
->con
, 0, i
, width
, TEXTMODE_Y(c_max
) - i
+ 1);
1957 s
->get_resolution(s
, &width
, &height
);
1958 snprintf(msg_buffer
, sizeof(msg_buffer
), "%i x %i Graphic mode",
1966 snprintf(msg_buffer
, sizeof(msg_buffer
), "VGA Blank mode");
1970 /* Display a message */
1972 s
->last_height
= height
= 3;
1973 dpy_text_cursor(s
->con
, -1, -1);
1974 dpy_text_resize(s
->con
, s
->last_width
, height
);
1976 for (dst
= chardata
, i
= 0; i
< s
->last_width
* height
; i
++)
1977 console_write_ch(dst
++, ' ');
1979 size
= strlen(msg_buffer
);
1980 width
= (s
->last_width
- size
) / 2;
1981 dst
= chardata
+ s
->last_width
+ width
;
1982 for (i
= 0; i
< size
; i
++)
1983 console_write_ch(dst
++, 0x00200100 | msg_buffer
[i
]);
1985 dpy_text_update(s
->con
, 0, 0, s
->last_width
, height
);
1988 static uint64_t vga_mem_read(void *opaque
, hwaddr addr
,
1991 VGACommonState
*s
= opaque
;
1993 return vga_mem_readb(s
, addr
);
1996 static void vga_mem_write(void *opaque
, hwaddr addr
,
1997 uint64_t data
, unsigned size
)
1999 VGACommonState
*s
= opaque
;
2001 return vga_mem_writeb(s
, addr
, data
);
2004 const MemoryRegionOps vga_mem_ops
= {
2005 .read
= vga_mem_read
,
2006 .write
= vga_mem_write
,
2007 .endianness
= DEVICE_LITTLE_ENDIAN
,
2009 .min_access_size
= 1,
2010 .max_access_size
= 1,
2014 static int vga_common_post_load(void *opaque
, int version_id
)
2016 VGACommonState
*s
= opaque
;
2019 s
->graphic_mode
= -1;
2023 static bool vga_endian_state_needed(void *opaque
)
2025 VGACommonState
*s
= opaque
;
2028 * Only send the endian state if it's different from the
2029 * default one, thus ensuring backward compatibility for
2030 * migration of the common case
2032 return s
->default_endian_fb
!= s
->big_endian_fb
;
2035 static const VMStateDescription vmstate_vga_endian
= {
2036 .name
= "vga.endian",
2038 .minimum_version_id
= 1,
2039 .fields
= (VMStateField
[]) {
2040 VMSTATE_BOOL(big_endian_fb
, VGACommonState
),
2041 VMSTATE_END_OF_LIST()
2045 const VMStateDescription vmstate_vga_common
= {
2048 .minimum_version_id
= 2,
2049 .post_load
= vga_common_post_load
,
2050 .fields
= (VMStateField
[]) {
2051 VMSTATE_UINT32(latch
, VGACommonState
),
2052 VMSTATE_UINT8(sr_index
, VGACommonState
),
2053 VMSTATE_PARTIAL_BUFFER(sr
, VGACommonState
, 8),
2054 VMSTATE_UINT8(gr_index
, VGACommonState
),
2055 VMSTATE_PARTIAL_BUFFER(gr
, VGACommonState
, 16),
2056 VMSTATE_UINT8(ar_index
, VGACommonState
),
2057 VMSTATE_BUFFER(ar
, VGACommonState
),
2058 VMSTATE_INT32(ar_flip_flop
, VGACommonState
),
2059 VMSTATE_UINT8(cr_index
, VGACommonState
),
2060 VMSTATE_BUFFER(cr
, VGACommonState
),
2061 VMSTATE_UINT8(msr
, VGACommonState
),
2062 VMSTATE_UINT8(fcr
, VGACommonState
),
2063 VMSTATE_UINT8(st00
, VGACommonState
),
2064 VMSTATE_UINT8(st01
, VGACommonState
),
2066 VMSTATE_UINT8(dac_state
, VGACommonState
),
2067 VMSTATE_UINT8(dac_sub_index
, VGACommonState
),
2068 VMSTATE_UINT8(dac_read_index
, VGACommonState
),
2069 VMSTATE_UINT8(dac_write_index
, VGACommonState
),
2070 VMSTATE_BUFFER(dac_cache
, VGACommonState
),
2071 VMSTATE_BUFFER(palette
, VGACommonState
),
2073 VMSTATE_INT32(bank_offset
, VGACommonState
),
2074 VMSTATE_UINT8_EQUAL(is_vbe_vmstate
, VGACommonState
),
2075 VMSTATE_UINT16(vbe_index
, VGACommonState
),
2076 VMSTATE_UINT16_ARRAY(vbe_regs
, VGACommonState
, VBE_DISPI_INDEX_NB
),
2077 VMSTATE_UINT32(vbe_start_addr
, VGACommonState
),
2078 VMSTATE_UINT32(vbe_line_offset
, VGACommonState
),
2079 VMSTATE_UINT32(vbe_bank_mask
, VGACommonState
),
2080 VMSTATE_END_OF_LIST()
2082 .subsections
= (VMStateSubsection
[]) {
2084 .vmsd
= &vmstate_vga_endian
,
2085 .needed
= vga_endian_state_needed
,
2092 static const GraphicHwOps vga_ops
= {
2093 .invalidate
= vga_invalidate_display
,
2094 .gfx_update
= vga_update_display
,
2095 .text_update
= vga_update_text
,
2098 void vga_common_init(VGACommonState
*s
, Object
*obj
, bool global_vmstate
)
2102 for(i
= 0;i
< 256; i
++) {
2104 for(j
= 0; j
< 8; j
++) {
2105 v
|= ((i
>> j
) & 1) << (j
* 4);
2110 for(j
= 0; j
< 4; j
++) {
2111 v
|= ((i
>> (2 * j
)) & 3) << (j
* 4);
2115 for(i
= 0; i
< 16; i
++) {
2117 for(j
= 0; j
< 4; j
++) {
2120 v
|= b
<< (2 * j
+ 1);
2125 /* valid range: 1 MB -> 256 MB */
2126 s
->vram_size
= 1024 * 1024;
2127 while (s
->vram_size
< (s
->vram_size_mb
<< 20) &&
2128 s
->vram_size
< (256 << 20)) {
2131 s
->vram_size_mb
= s
->vram_size
>> 20;
2133 s
->vbe_size
= s
->vram_size
;
2136 s
->is_vbe_vmstate
= 1;
2137 memory_region_init_ram(&s
->vram
, obj
, "vga.vram", s
->vram_size
,
2139 vmstate_register_ram(&s
->vram
, global_vmstate
? NULL
: DEVICE(obj
));
2140 xen_register_framebuffer(&s
->vram
);
2141 s
->vram_ptr
= memory_region_get_ram_ptr(&s
->vram
);
2142 s
->get_bpp
= vga_get_bpp
;
2143 s
->get_offsets
= vga_get_offsets
;
2144 s
->get_resolution
= vga_get_resolution
;
2145 s
->hw_ops
= &vga_ops
;
2146 switch (vga_retrace_method
) {
2147 case VGA_RETRACE_DUMB
:
2148 s
->retrace
= vga_dumb_retrace
;
2149 s
->update_retrace_info
= vga_dumb_update_retrace_info
;
2152 case VGA_RETRACE_PRECISE
:
2153 s
->retrace
= vga_precise_retrace
;
2154 s
->update_retrace_info
= vga_precise_update_retrace_info
;
2159 * Set default fb endian based on target, could probably be turned
2160 * into a device attribute set by the machine/platform to remove
2161 * all target endian dependencies from this file.
2163 #ifdef TARGET_WORDS_BIGENDIAN
2164 s
->default_endian_fb
= true;
2166 s
->default_endian_fb
= false;
2168 vga_dirty_log_start(s
);
2171 static const MemoryRegionPortio vga_portio_list
[] = {
2172 { 0x04, 2, 1, .read
= vga_ioport_read
, .write
= vga_ioport_write
}, /* 3b4 */
2173 { 0x0a, 1, 1, .read
= vga_ioport_read
, .write
= vga_ioport_write
}, /* 3ba */
2174 { 0x10, 16, 1, .read
= vga_ioport_read
, .write
= vga_ioport_write
}, /* 3c0 */
2175 { 0x24, 2, 1, .read
= vga_ioport_read
, .write
= vga_ioport_write
}, /* 3d4 */
2176 { 0x2a, 1, 1, .read
= vga_ioport_read
, .write
= vga_ioport_write
}, /* 3da */
2177 PORTIO_END_OF_LIST(),
2180 static const MemoryRegionPortio vbe_portio_list
[] = {
2181 { 0, 1, 2, .read
= vbe_ioport_read_index
, .write
= vbe_ioport_write_index
},
2183 { 1, 1, 2, .read
= vbe_ioport_read_data
, .write
= vbe_ioport_write_data
},
2185 { 2, 1, 2, .read
= vbe_ioport_read_data
, .write
= vbe_ioport_write_data
},
2186 PORTIO_END_OF_LIST(),
2189 /* Used by both ISA and PCI */
2190 MemoryRegion
*vga_init_io(VGACommonState
*s
, Object
*obj
,
2191 const MemoryRegionPortio
**vga_ports
,
2192 const MemoryRegionPortio
**vbe_ports
)
2194 MemoryRegion
*vga_mem
;
2196 *vga_ports
= vga_portio_list
;
2197 *vbe_ports
= vbe_portio_list
;
2199 vga_mem
= g_malloc(sizeof(*vga_mem
));
2200 memory_region_init_io(vga_mem
, obj
, &vga_mem_ops
, s
,
2201 "vga-lowmem", 0x20000);
2202 memory_region_set_flush_coalesced(vga_mem
);
2207 void vga_init(VGACommonState
*s
, Object
*obj
, MemoryRegion
*address_space
,
2208 MemoryRegion
*address_space_io
, bool init_vga_ports
)
2210 MemoryRegion
*vga_io_memory
;
2211 const MemoryRegionPortio
*vga_ports
, *vbe_ports
;
2213 qemu_register_reset(vga_reset
, s
);
2217 s
->legacy_address_space
= address_space
;
2219 vga_io_memory
= vga_init_io(s
, obj
, &vga_ports
, &vbe_ports
);
2220 memory_region_add_subregion_overlap(address_space
,
2221 isa_mem_base
+ 0x000a0000,
2224 memory_region_set_coalescing(vga_io_memory
);
2225 if (init_vga_ports
) {
2226 portio_list_init(&s
->vga_port_list
, obj
, vga_ports
, s
, "vga");
2227 portio_list_set_flush_coalesced(&s
->vga_port_list
);
2228 portio_list_add(&s
->vga_port_list
, address_space_io
, 0x3b0);
2231 portio_list_init(&s
->vbe_port_list
, obj
, vbe_ports
, s
, "vbe");
2232 portio_list_add(&s
->vbe_port_list
, address_space_io
, 0x1ce);
2236 void vga_init_vbe(VGACommonState
*s
, Object
*obj
, MemoryRegion
*system_memory
)
2238 /* With pc-0.12 and below we map both the PCI BAR and the fixed VBE region,
2239 * so use an alias to avoid double-mapping the same region.
2241 memory_region_init_alias(&s
->vram_vbe
, obj
, "vram.vbe",
2242 &s
->vram
, 0, memory_region_size(&s
->vram
));
2243 /* XXX: use optimized standard vga accesses */
2244 memory_region_add_subregion(system_memory
,
2245 VBE_DISPI_LFB_PHYSICAL_ADDRESS
,