target-sparc/fop_helper.c

   1 /*
   2  * FPU op helpers
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "cpu.h"
  22 #include "exec/helper-proto.h"
  23
  24 #define QT0 (env->qt0)
  25 #define QT1 (env->qt1)
  26
  27 target_ulong helper_check_ieee_exceptions(CPUSPARCState *env)
  28 {
  29     target_ulong status = get_float_exception_flags(&env->fp_status);
  30     target_ulong fsr = env->fsr;
  31
  32     if (unlikely(status)) {
  33         /* Keep exception flags clear for next time.  */
  34         set_float_exception_flags(0, &env->fp_status);
  35
  36         /* Copy IEEE 754 flags into FSR */
  37         if (status & float_flag_invalid) {
  38             fsr |= FSR_NVC;
  39         }
  40         if (status & float_flag_overflow) {
  41             fsr |= FSR_OFC;
  42         }
  43         if (status & float_flag_underflow) {
  44             fsr |= FSR_UFC;
  45         }
  46         if (status & float_flag_divbyzero) {
  47             fsr |= FSR_DZC;
  48         }
  49         if (status & float_flag_inexact) {
  50             fsr |= FSR_NXC;
  51         }
  52
  53         if ((fsr & FSR_CEXC_MASK) & ((fsr & FSR_TEM_MASK) >> 23)) {
  54             /* Unmasked exception, generate a trap.  Note that while
  55                the helper is marked as NO_WG, we can get away with
  56                writing to cpu state along the exception path, since
  57                TCG generated code will never see the write.  */
  58             env->fsr = fsr | FSR_FTT_IEEE_EXCP;
  59             helper_raise_exception(env, TT_FP_EXCP);
  60         } else {
  61             /* Accumulate exceptions */
  62             fsr |= (fsr & FSR_CEXC_MASK) << 5;
  63         }
  64     }
  65
  66     return fsr;
  67 }
  68
  69 #define F_HELPER(name, p) void helper_f##name##p(CPUSPARCState *env)
  70
  71 #define F_BINOP(name)                                           \
  72     float32 helper_f ## name ## s (CPUSPARCState *env, float32 src1, \
  73                                    float32 src2)                \
  74     {                                                           \
  75         return float32_ ## name (src1, src2, &env->fp_status);  \
  76     }                                                           \
  77     float64 helper_f ## name ## d (CPUSPARCState * env, float64 src1,\
  78                                    float64 src2)                \
  79     {                                                           \
  80         return float64_ ## name (src1, src2, &env->fp_status);  \
  81     }                                                           \
  82     F_HELPER(name, q)                                           \
  83     {                                                           \
  84         QT0 = float128_ ## name (QT0, QT1, &env->fp_status);    \
  85     }
  86
  87 F_BINOP(add);
  88 F_BINOP(sub);
  89 F_BINOP(mul);
  90 F_BINOP(div);
  91 #undef F_BINOP
  92
  93 float64 helper_fsmuld(CPUSPARCState *env, float32 src1, float32 src2)
  94 {
  95     return float64_mul(float32_to_float64(src1, &env->fp_status),
  96                        float32_to_float64(src2, &env->fp_status),
  97                        &env->fp_status);
  98 }
  99
 100 void helper_fdmulq(CPUSPARCState *env, float64 src1, float64 src2)
 101 {
 102     QT0 = float128_mul(float64_to_float128(src1, &env->fp_status),
 103                        float64_to_float128(src2, &env->fp_status),
 104                        &env->fp_status);
 105 }
 106
 107 float32 helper_fnegs(float32 src)
 108 {
 109     return float32_chs(src);
 110 }
 111
 112 #ifdef TARGET_SPARC64
 113 float64 helper_fnegd(float64 src)
 114 {
 115     return float64_chs(src);
 116 }
 117
 118 F_HELPER(neg, q)
 119 {
 120     QT0 = float128_chs(QT1);
 121 }
 122 #endif
 123
 124 /* Integer to float conversion.  */
 125 float32 helper_fitos(CPUSPARCState *env, int32_t src)
 126 {
 127     return int32_to_float32(src, &env->fp_status);
 128 }
 129
 130 float64 helper_fitod(CPUSPARCState *env, int32_t src)
 131 {
 132     return int32_to_float64(src, &env->fp_status);
 133 }
 134
 135 void helper_fitoq(CPUSPARCState *env, int32_t src)
 136 {
 137     QT0 = int32_to_float128(src, &env->fp_status);
 138 }
 139
 140 #ifdef TARGET_SPARC64
 141 float32 helper_fxtos(CPUSPARCState *env, int64_t src)
 142 {
 143     return int64_to_float32(src, &env->fp_status);
 144 }
 145
 146 float64 helper_fxtod(CPUSPARCState *env, int64_t src)
 147 {
 148     return int64_to_float64(src, &env->fp_status);
 149 }
 150
 151 void helper_fxtoq(CPUSPARCState *env, int64_t src)
 152 {
 153     QT0 = int64_to_float128(src, &env->fp_status);
 154 }
 155 #endif
 156 #undef F_HELPER
 157
 158 /* floating point conversion */
 159 float32 helper_fdtos(CPUSPARCState *env, float64 src)
 160 {
 161     return float64_to_float32(src, &env->fp_status);
 162 }
 163
 164 float64 helper_fstod(CPUSPARCState *env, float32 src)
 165 {
 166     return float32_to_float64(src, &env->fp_status);
 167 }
 168
 169 float32 helper_fqtos(CPUSPARCState *env)
 170 {
 171     return float128_to_float32(QT1, &env->fp_status);
 172 }
 173
 174 void helper_fstoq(CPUSPARCState *env, float32 src)
 175 {
 176     QT0 = float32_to_float128(src, &env->fp_status);
 177 }
 178
 179 float64 helper_fqtod(CPUSPARCState *env)
 180 {
 181     return float128_to_float64(QT1, &env->fp_status);
 182 }
 183
 184 void helper_fdtoq(CPUSPARCState *env, float64 src)
 185 {
 186     QT0 = float64_to_float128(src, &env->fp_status);
 187 }
 188
 189 /* Float to integer conversion.  */
 190 int32_t helper_fstoi(CPUSPARCState *env, float32 src)
 191 {
 192     return float32_to_int32_round_to_zero(src, &env->fp_status);
 193 }
 194
 195 int32_t helper_fdtoi(CPUSPARCState *env, float64 src)
 196 {
 197     return float64_to_int32_round_to_zero(src, &env->fp_status);
 198 }
 199
 200 int32_t helper_fqtoi(CPUSPARCState *env)
 201 {
 202     return float128_to_int32_round_to_zero(QT1, &env->fp_status);
 203 }
 204
 205 #ifdef TARGET_SPARC64
 206 int64_t helper_fstox(CPUSPARCState *env, float32 src)
 207 {
 208     return float32_to_int64_round_to_zero(src, &env->fp_status);
 209 }
 210
 211 int64_t helper_fdtox(CPUSPARCState *env, float64 src)
 212 {
 213     return float64_to_int64_round_to_zero(src, &env->fp_status);
 214 }
 215
 216 int64_t helper_fqtox(CPUSPARCState *env)
 217 {
 218     return float128_to_int64_round_to_zero(QT1, &env->fp_status);
 219 }
 220 #endif
 221
 222 float32 helper_fabss(float32 src)
 223 {
 224     return float32_abs(src);
 225 }
 226
 227 #ifdef TARGET_SPARC64
 228 float64 helper_fabsd(float64 src)
 229 {
 230     return float64_abs(src);
 231 }
 232
 233 void helper_fabsq(CPUSPARCState *env)
 234 {
 235     QT0 = float128_abs(QT1);
 236 }
 237 #endif
 238
 239 float32 helper_fsqrts(CPUSPARCState *env, float32 src)
 240 {
 241     return float32_sqrt(src, &env->fp_status);
 242 }
 243
 244 float64 helper_fsqrtd(CPUSPARCState *env, float64 src)
 245 {
 246     return float64_sqrt(src, &env->fp_status);
 247 }
 248
 249 void helper_fsqrtq(CPUSPARCState *env)
 250 {
 251     QT0 = float128_sqrt(QT1, &env->fp_status);
 252 }
 253
 254 #define GEN_FCMP(name, size, reg1, reg2, FS, E)                         \
 255     target_ulong glue(helper_, name) (CPUSPARCState *env)               \
 256     {                                                                   \
 257         int ret;                                                        \
 258         target_ulong fsr;                                               \
 259         if (E) {                                                        \
 260             ret = glue(size, _compare)(reg1, reg2, &env->fp_status);    \
 261         } else {                                                        \
 262             ret = glue(size, _compare_quiet)(reg1, reg2,                \
 263                                              &env->fp_status);          \
 264         }                                                               \
 265         fsr = helper_check_ieee_exceptions(env);                        \
 266         switch (ret) {                                                  \
 267         case float_relation_unordered:                                  \
 268             fsr |= (FSR_FCC1 | FSR_FCC0) << FS;                         \
 269             fsr |= FSR_NVA;                                             \
 270             break;                                                      \
 271         case float_relation_less:                                       \
 272             fsr &= ~(FSR_FCC1) << FS;                                   \
 273             fsr |= FSR_FCC0 << FS;                                      \
 274             break;                                                      \
 275         case float_relation_greater:                                    \
 276             fsr &= ~(FSR_FCC0) << FS;                                   \
 277             fsr |= FSR_FCC1 << FS;                                      \
 278             break;                                                      \
 279         default:                                                        \
 280             fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                      \
 281             break;                                                      \
 282         }                                                               \
 283         return fsr;                                                     \
 284     }
 285 #define GEN_FCMP_T(name, size, FS, E)                                   \
 286     target_ulong glue(helper_, name)(CPUSPARCState *env, size src1, size src2)\
 287     {                                                                   \
 288         int ret;                                                        \
 289         target_ulong fsr;                                               \
 290         if (E) {                                                        \
 291             ret = glue(size, _compare)(src1, src2, &env->fp_status);    \
 292         } else {                                                        \
 293             ret = glue(size, _compare_quiet)(src1, src2,                \
 294                                              &env->fp_status);          \
 295         }                                                               \
 296         fsr = helper_check_ieee_exceptions(env);                        \
 297         switch (ret) {                                                  \
 298         case float_relation_unordered:                                  \
 299             fsr |= (FSR_FCC1 | FSR_FCC0) << FS;                         \
 300             break;                                                      \
 301         case float_relation_less:                                       \
 302             fsr &= ~(FSR_FCC1 << FS);                                   \
 303             fsr |= FSR_FCC0 << FS;                                      \
 304             break;                                                      \
 305         case float_relation_greater:                                    \
 306             fsr &= ~(FSR_FCC0 << FS);                                   \
 307             fsr |= FSR_FCC1 << FS;                                      \
 308             break;                                                      \
 309         default:                                                        \
 310             fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                      \
 311             break;                                                      \
 312         }                                                               \
 313         return fsr;                                                     \
 314     }
 315
 316 GEN_FCMP_T(fcmps, float32, 0, 0);
 317 GEN_FCMP_T(fcmpd, float64, 0, 0);
 318
 319 GEN_FCMP_T(fcmpes, float32, 0, 1);
 320 GEN_FCMP_T(fcmped, float64, 0, 1);
 321
 322 GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
 323 GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
 324
 325 #ifdef TARGET_SPARC64
 326 GEN_FCMP_T(fcmps_fcc1, float32, 22, 0);
 327 GEN_FCMP_T(fcmpd_fcc1, float64, 22, 0);
 328 GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);
 329
 330 GEN_FCMP_T(fcmps_fcc2, float32, 24, 0);
 331 GEN_FCMP_T(fcmpd_fcc2, float64, 24, 0);
 332 GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);
 333
 334 GEN_FCMP_T(fcmps_fcc3, float32, 26, 0);
 335 GEN_FCMP_T(fcmpd_fcc3, float64, 26, 0);
 336 GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);
 337
 338 GEN_FCMP_T(fcmpes_fcc1, float32, 22, 1);
 339 GEN_FCMP_T(fcmped_fcc1, float64, 22, 1);
 340 GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);
 341
 342 GEN_FCMP_T(fcmpes_fcc2, float32, 24, 1);
 343 GEN_FCMP_T(fcmped_fcc2, float64, 24, 1);
 344 GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);
 345
 346 GEN_FCMP_T(fcmpes_fcc3, float32, 26, 1);
 347 GEN_FCMP_T(fcmped_fcc3, float64, 26, 1);
 348 GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
 349 #endif
 350 #undef GEN_FCMP_T
 351 #undef GEN_FCMP
 352
 353 static void set_fsr(CPUSPARCState *env, target_ulong fsr)
 354 {
 355     int rnd_mode;
 356
 357     switch (fsr & FSR_RD_MASK) {
 358     case FSR_RD_NEAREST:
 359         rnd_mode = float_round_nearest_even;
 360         break;
 361     default:
 362     case FSR_RD_ZERO:
 363         rnd_mode = float_round_to_zero;
 364         break;
 365     case FSR_RD_POS:
 366         rnd_mode = float_round_up;
 367         break;
 368     case FSR_RD_NEG:
 369         rnd_mode = float_round_down;
 370         break;
 371     }
 372     set_float_rounding_mode(rnd_mode, &env->fp_status);
 373 }
 374
 375 target_ulong helper_ldfsr(CPUSPARCState *env, target_ulong old_fsr,
 376                           uint32_t new_fsr)
 377 {
 378     old_fsr = (new_fsr & FSR_LDFSR_MASK) | (old_fsr & FSR_LDFSR_OLDMASK);
 379     set_fsr(env, old_fsr);
 380     return old_fsr;
 381 }
 382
 383 #ifdef TARGET_SPARC64
 384 target_ulong helper_ldxfsr(CPUSPARCState *env, target_ulong old_fsr,
 385                            uint64_t new_fsr)
 386 {
 387     old_fsr = (new_fsr & FSR_LDXFSR_MASK) | (old_fsr & FSR_LDXFSR_OLDMASK);
 388     set_fsr(env, old_fsr);
 389     return old_fsr;
 390 }
 391 #endif