hw/intc/slavio_intctl.c

   1 /*
   2  * QEMU Sparc SLAVIO interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "monitor/monitor.h"
  27 #include "hw/sysbus.h"
  28 #include "hw/intc/intc.h"
  29 #include "trace.h"
  30
  31 //#define DEBUG_IRQ_COUNT
  32
  33 /*
  34  * Registers of interrupt controller in sun4m.
  35  *
  36  * This is the interrupt controller part of chip STP2001 (Slave I/O), also
  37  * produced as NCR89C105. See
  38  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
  39  *
  40  * There is a system master controller and one for each cpu.
  41  *
  42  */
  43
  44 #define MAX_CPUS 16
  45 #define MAX_PILS 16
  46
  47 struct SLAVIO_INTCTLState;
  48
  49 typedef struct SLAVIO_CPUINTCTLState {
  50     MemoryRegion iomem;
  51     struct SLAVIO_INTCTLState *master;
  52     uint32_t intreg_pending;
  53     uint32_t cpu;
  54     uint32_t irl_out;
  55 } SLAVIO_CPUINTCTLState;
  56
  57 #define TYPE_SLAVIO_INTCTL "slavio_intctl"
  58 #define SLAVIO_INTCTL(obj) \
  59     OBJECT_CHECK(SLAVIO_INTCTLState, (obj), TYPE_SLAVIO_INTCTL)
  60
  61 typedef struct SLAVIO_INTCTLState {
  62     SysBusDevice parent_obj;
  63
  64     MemoryRegion iomem;
  65 #ifdef DEBUG_IRQ_COUNT
  66     uint64_t irq_count[32];
  67 #endif
  68     qemu_irq cpu_irqs[MAX_CPUS][MAX_PILS];
  69     SLAVIO_CPUINTCTLState slaves[MAX_CPUS];
  70     uint32_t intregm_pending;
  71     uint32_t intregm_disabled;
  72     uint32_t target_cpu;
  73 } SLAVIO_INTCTLState;
  74
  75 #define INTCTL_MAXADDR 0xf
  76 #define INTCTL_SIZE (INTCTL_MAXADDR + 1)
  77 #define INTCTLM_SIZE 0x14
  78 #define MASTER_IRQ_MASK ~0x0fa2007f
  79 #define MASTER_DISABLE 0x80000000
  80 #define CPU_SOFTIRQ_MASK 0xfffe0000
  81 #define CPU_IRQ_INT15_IN (1 << 15)
  82 #define CPU_IRQ_TIMER_IN (1 << 14)
  83
  84 static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs);
  85
  86 // per-cpu interrupt controller
  87 static uint64_t slavio_intctl_mem_readl(void *opaque, hwaddr addr,
  88                                         unsigned size)
  89 {
  90     SLAVIO_CPUINTCTLState *s = opaque;
  91     uint32_t saddr, ret;
  92
  93     saddr = addr >> 2;
  94     switch (saddr) {
  95     case 0:
  96         ret = s->intreg_pending;
  97         break;
  98     default:
  99         ret = 0;
 100         break;
 101     }
 102     trace_slavio_intctl_mem_readl(s->cpu, addr, ret);
 103
 104     return ret;
 105 }
 106
 107 static void slavio_intctl_mem_writel(void *opaque, hwaddr addr,
 108                                      uint64_t val, unsigned size)
 109 {
 110     SLAVIO_CPUINTCTLState *s = opaque;
 111     uint32_t saddr;
 112
 113     saddr = addr >> 2;
 114     trace_slavio_intctl_mem_writel(s->cpu, addr, val);
 115     switch (saddr) {
 116     case 1: // clear pending softints
 117         val &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN;
 118         s->intreg_pending &= ~val;
 119         slavio_check_interrupts(s->master, 1);
 120         trace_slavio_intctl_mem_writel_clear(s->cpu, val, s->intreg_pending);
 121         break;
 122     case 2: // set softint
 123         val &= CPU_SOFTIRQ_MASK;
 124         s->intreg_pending |= val;
 125         slavio_check_interrupts(s->master, 1);
 126         trace_slavio_intctl_mem_writel_set(s->cpu, val, s->intreg_pending);
 127         break;
 128     default:
 129         break;
 130     }
 131 }
 132
 133 static const MemoryRegionOps slavio_intctl_mem_ops = {
 134     .read = slavio_intctl_mem_readl,
 135     .write = slavio_intctl_mem_writel,
 136     .endianness = DEVICE_NATIVE_ENDIAN,
 137     .valid = {
 138         .min_access_size = 4,
 139         .max_access_size = 4,
 140     },
 141 };
 142
 143 // master system interrupt controller
 144 static uint64_t slavio_intctlm_mem_readl(void *opaque, hwaddr addr,
 145                                          unsigned size)
 146 {
 147     SLAVIO_INTCTLState *s = opaque;
 148     uint32_t saddr, ret;
 149
 150     saddr = addr >> 2;
 151     switch (saddr) {
 152     case 0:
 153         ret = s->intregm_pending & ~MASTER_DISABLE;
 154         break;
 155     case 1:
 156         ret = s->intregm_disabled & MASTER_IRQ_MASK;
 157         break;
 158     case 4:
 159         ret = s->target_cpu;
 160         break;
 161     default:
 162         ret = 0;
 163         break;
 164     }
 165     trace_slavio_intctlm_mem_readl(addr, ret);
 166
 167     return ret;
 168 }
 169
 170 static void slavio_intctlm_mem_writel(void *opaque, hwaddr addr,
 171                                       uint64_t val, unsigned size)
 172 {
 173     SLAVIO_INTCTLState *s = opaque;
 174     uint32_t saddr;
 175
 176     saddr = addr >> 2;
 177     trace_slavio_intctlm_mem_writel(addr, val);
 178     switch (saddr) {
 179     case 2: // clear (enable)
 180         // Force clear unused bits
 181         val &= MASTER_IRQ_MASK;
 182         s->intregm_disabled &= ~val;
 183         trace_slavio_intctlm_mem_writel_enable(val, s->intregm_disabled);
 184         slavio_check_interrupts(s, 1);
 185         break;
 186     case 3: // set (disable; doesn't affect pending)
 187         // Force clear unused bits
 188         val &= MASTER_IRQ_MASK;
 189         s->intregm_disabled |= val;
 190         slavio_check_interrupts(s, 1);
 191         trace_slavio_intctlm_mem_writel_disable(val, s->intregm_disabled);
 192         break;
 193     case 4:
 194         s->target_cpu = val & (MAX_CPUS - 1);
 195         slavio_check_interrupts(s, 1);
 196         trace_slavio_intctlm_mem_writel_target(s->target_cpu);
 197         break;
 198     default:
 199         break;
 200     }
 201 }
 202
 203 static const MemoryRegionOps slavio_intctlm_mem_ops = {
 204     .read = slavio_intctlm_mem_readl,
 205     .write = slavio_intctlm_mem_writel,
 206     .endianness = DEVICE_NATIVE_ENDIAN,
 207     .valid = {
 208         .min_access_size = 4,
 209         .max_access_size = 4,
 210     },
 211 };
 212
 213 static const uint32_t intbit_to_level[] = {
 214     2, 3, 5, 7, 9, 11, 13, 2,   3, 5, 7, 9, 11, 13, 12, 12,
 215     6, 13, 4, 10, 8, 9, 11, 0,  0, 0, 0, 15, 15, 15, 15, 0,
 216 };
 217
 218 static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs)
 219 {
 220     uint32_t pending = s->intregm_pending, pil_pending;
 221     unsigned int i, j;
 222
 223     pending &= ~s->intregm_disabled;
 224
 225     trace_slavio_check_interrupts(pending, s->intregm_disabled);
 226     for (i = 0; i < MAX_CPUS; i++) {
 227         pil_pending = 0;
 228
 229         /* If we are the current interrupt target, get hard interrupts */
 230         if (pending && !(s->intregm_disabled & MASTER_DISABLE) &&
 231             (i == s->target_cpu)) {
 232             for (j = 0; j < 32; j++) {
 233                 if ((pending & (1 << j)) && intbit_to_level[j]) {
 234                     pil_pending |= 1 << intbit_to_level[j];
 235                 }
 236             }
 237         }
 238
 239         /* Calculate current pending hard interrupts for display */
 240         s->slaves[i].intreg_pending &= CPU_SOFTIRQ_MASK | CPU_IRQ_INT15_IN |
 241             CPU_IRQ_TIMER_IN;
 242         if (i == s->target_cpu) {
 243             for (j = 0; j < 32; j++) {
 244                 if ((s->intregm_pending & (1U << j)) && intbit_to_level[j]) {
 245                     s->slaves[i].intreg_pending |= 1 << intbit_to_level[j];
 246                 }
 247             }
 248         }
 249
 250         /* Level 15 and CPU timer interrupts are only masked when
 251            the MASTER_DISABLE bit is set */
 252         if (!(s->intregm_disabled & MASTER_DISABLE)) {
 253             pil_pending |= s->slaves[i].intreg_pending &
 254                 (CPU_IRQ_INT15_IN | CPU_IRQ_TIMER_IN);
 255         }
 256
 257         /* Add soft interrupts */
 258         pil_pending |= (s->slaves[i].intreg_pending & CPU_SOFTIRQ_MASK) >> 16;
 259
 260         if (set_irqs) {
 261             /* Since there is not really an interrupt 0 (and pil_pending
 262              * and irl_out bit zero are thus always zero) there is no need
 263              * to do anything with cpu_irqs[i][0] and it is OK not to do
 264              * the j=0 iteration of this loop.
 265              */
 266             for (j = MAX_PILS-1; j > 0; j--) {
 267                 if (pil_pending & (1 << j)) {
 268                     if (!(s->slaves[i].irl_out & (1 << j))) {
 269                         qemu_irq_raise(s->cpu_irqs[i][j]);
 270                     }
 271                 } else {
 272                     if (s->slaves[i].irl_out & (1 << j)) {
 273                         qemu_irq_lower(s->cpu_irqs[i][j]);
 274                     }
 275                 }
 276             }
 277         }
 278         s->slaves[i].irl_out = pil_pending;
 279     }
 280 }
 281
 282 /*
 283  * "irq" here is the bit number in the system interrupt register to
 284  * separate serial and keyboard interrupts sharing a level.
 285  */
 286 static void slavio_set_irq(void *opaque, int irq, int level)
 287 {
 288     SLAVIO_INTCTLState *s = opaque;
 289     uint32_t mask = 1 << irq;
 290     uint32_t pil = intbit_to_level[irq];
 291     unsigned int i;
 292
 293     trace_slavio_set_irq(s->target_cpu, irq, pil, level);
 294     if (pil > 0) {
 295         if (level) {
 296 #ifdef DEBUG_IRQ_COUNT
 297             s->irq_count[pil]++;
 298 #endif
 299             s->intregm_pending |= mask;
 300             if (pil == 15) {
 301                 for (i = 0; i < MAX_CPUS; i++) {
 302                     s->slaves[i].intreg_pending |= 1 << pil;
 303                 }
 304             }
 305         } else {
 306             s->intregm_pending &= ~mask;
 307             if (pil == 15) {
 308                 for (i = 0; i < MAX_CPUS; i++) {
 309                     s->slaves[i].intreg_pending &= ~(1 << pil);
 310                 }
 311             }
 312         }
 313         slavio_check_interrupts(s, 1);
 314     }
 315 }
 316
 317 static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
 318 {
 319     SLAVIO_INTCTLState *s = opaque;
 320
 321     trace_slavio_set_timer_irq_cpu(cpu, level);
 322
 323     if (level) {
 324         s->slaves[cpu].intreg_pending |= CPU_IRQ_TIMER_IN;
 325     } else {
 326         s->slaves[cpu].intreg_pending &= ~CPU_IRQ_TIMER_IN;
 327     }
 328
 329     slavio_check_interrupts(s, 1);
 330 }
 331
 332 static void slavio_set_irq_all(void *opaque, int irq, int level)
 333 {
 334     if (irq < 32) {
 335         slavio_set_irq(opaque, irq, level);
 336     } else {
 337         slavio_set_timer_irq_cpu(opaque, irq - 32, level);
 338     }
 339 }
 340
 341 static int vmstate_intctl_post_load(void *opaque, int version_id)
 342 {
 343     SLAVIO_INTCTLState *s = opaque;
 344
 345     slavio_check_interrupts(s, 0);
 346     return 0;
 347 }
 348
 349 static const VMStateDescription vmstate_intctl_cpu = {
 350     .name ="slavio_intctl_cpu",
 351     .version_id = 1,
 352     .minimum_version_id = 1,
 353     .fields = (VMStateField[]) {
 354         VMSTATE_UINT32(intreg_pending, SLAVIO_CPUINTCTLState),
 355         VMSTATE_END_OF_LIST()
 356     }
 357 };
 358
 359 static const VMStateDescription vmstate_intctl = {
 360     .name ="slavio_intctl",
 361     .version_id = 1,
 362     .minimum_version_id = 1,
 363     .post_load = vmstate_intctl_post_load,
 364     .fields = (VMStateField[]) {
 365         VMSTATE_STRUCT_ARRAY(slaves, SLAVIO_INTCTLState, MAX_CPUS, 1,
 366                              vmstate_intctl_cpu, SLAVIO_CPUINTCTLState),
 367         VMSTATE_UINT32(intregm_pending, SLAVIO_INTCTLState),
 368         VMSTATE_UINT32(intregm_disabled, SLAVIO_INTCTLState),
 369         VMSTATE_UINT32(target_cpu, SLAVIO_INTCTLState),
 370         VMSTATE_END_OF_LIST()
 371     }
 372 };
 373
 374 static void slavio_intctl_reset(DeviceState *d)
 375 {
 376     SLAVIO_INTCTLState *s = SLAVIO_INTCTL(d);
 377     int i;
 378
 379     for (i = 0; i < MAX_CPUS; i++) {
 380         s->slaves[i].intreg_pending = 0;
 381         s->slaves[i].irl_out = 0;
 382     }
 383     s->intregm_disabled = ~MASTER_IRQ_MASK;
 384     s->intregm_pending = 0;
 385     s->target_cpu = 0;
 386     slavio_check_interrupts(s, 0);
 387 }
 388
 389 #ifdef DEBUG_IRQ_COUNT
 390 static bool slavio_intctl_get_statistics(InterruptStatsProvider *obj,
 391                                          uint64_t **irq_counts,
 392                                          unsigned int *nb_irqs)
 393 {
 394     SLAVIO_INTCTLState *s = SLAVIO_INTCTL(obj);
 395     *irq_counts = s->irq_count;
 396     *nb_irqs = ARRAY_SIZE(s->irq_count);
 397     return true;
 398 }
 399 #endif
 400
 401 static void slavio_intctl_print_info(InterruptStatsProvider *obj, Monitor *mon)
 402 {
 403     SLAVIO_INTCTLState *s = SLAVIO_INTCTL(obj);
 404     int i;
 405
 406     for (i = 0; i < MAX_CPUS; i++) {
 407         monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i,
 408                        s->slaves[i].intreg_pending);
 409     }
 410     monitor_printf(mon, "master: pending 0x%08x, disabled 0x%08x\n",
 411                    s->intregm_pending, s->intregm_disabled);
 412 }
 413
 414 static void slavio_intctl_init(Object *obj)
 415 {
 416     DeviceState *dev = DEVICE(obj);
 417     SLAVIO_INTCTLState *s = SLAVIO_INTCTL(obj);
 418     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 419     unsigned int i, j;
 420     char slave_name[45];
 421
 422     qdev_init_gpio_in(dev, slavio_set_irq_all, 32 + MAX_CPUS);
 423     memory_region_init_io(&s->iomem, obj, &slavio_intctlm_mem_ops, s,
 424                           "master-interrupt-controller", INTCTLM_SIZE);
 425     sysbus_init_mmio(sbd, &s->iomem);
 426
 427     for (i = 0; i < MAX_CPUS; i++) {
 428         snprintf(slave_name, sizeof(slave_name),
 429                  "slave-interrupt-controller-%i", i);
 430         for (j = 0; j < MAX_PILS; j++) {
 431             sysbus_init_irq(sbd, &s->cpu_irqs[i][j]);
 432         }
 433         memory_region_init_io(&s->slaves[i].iomem, OBJECT(s),
 434                               &slavio_intctl_mem_ops,
 435                               &s->slaves[i], slave_name, INTCTL_SIZE);
 436         sysbus_init_mmio(sbd, &s->slaves[i].iomem);
 437         s->slaves[i].cpu = i;
 438         s->slaves[i].master = s;
 439     }
 440 }
 441
 442 static void slavio_intctl_class_init(ObjectClass *klass, void *data)
 443 {
 444     DeviceClass *dc = DEVICE_CLASS(klass);
 445     InterruptStatsProviderClass *ic = INTERRUPT_STATS_PROVIDER_CLASS(klass);
 446
 447     dc->reset = slavio_intctl_reset;
 448     dc->vmsd = &vmstate_intctl;
 449 #ifdef DEBUG_IRQ_COUNT
 450     ic->get_statistics = slavio_intctl_get_statistics;
 451 #endif
 452     ic->print_info = slavio_intctl_print_info;
 453 }
 454
 455 static const TypeInfo slavio_intctl_info = {
 456     .name          = TYPE_SLAVIO_INTCTL,
 457     .parent        = TYPE_SYS_BUS_DEVICE,
 458     .instance_size = sizeof(SLAVIO_INTCTLState),
 459     .instance_init = slavio_intctl_init,
 460     .class_init    = slavio_intctl_class_init,
 461     .interfaces = (InterfaceInfo[]) {
 462         { TYPE_INTERRUPT_STATS_PROVIDER },
 463         { }
 464     },
 465 };
 466
 467 static void slavio_intctl_register_types(void)
 468 {
 469     type_register_static(&slavio_intctl_info);
 470 }
 471
 472 type_init(slavio_intctl_register_types)