2 * QEMU IDE Emulation: PCI VIA82C686B support.
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
6 * Copyright (c) 2010 Huacai Chen <zltjiangshi@gmail.com>
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu/osdep.h"
28 #include "hw/pci/pci.h"
29 #include "sysemu/sysemu.h"
30 #include "sysemu/dma.h"
32 #include "hw/ide/pci.h"
35 static uint64_t bmdma_read(void *opaque
, hwaddr addr
,
38 BMDMAState
*bm
= opaque
;
42 return ((uint64_t)1 << (size
* 8)) - 1;
57 trace_bmdma_read_via(addr
, val
);
61 static void bmdma_write(void *opaque
, hwaddr addr
,
62 uint64_t val
, unsigned size
)
64 BMDMAState
*bm
= opaque
;
70 trace_bmdma_write_via(addr
, val
);
73 bmdma_cmd_writeb(bm
, val
);
76 bm
->status
= (val
& 0x60) | (bm
->status
& 1) | (bm
->status
& ~val
& 0x06);
82 static const MemoryRegionOps via_bmdma_ops
= {
87 static void bmdma_setup_bar(PCIIDEState
*d
)
91 memory_region_init(&d
->bmdma_bar
, OBJECT(d
), "via-bmdma-container", 16);
92 for(i
= 0;i
< 2; i
++) {
93 BMDMAState
*bm
= &d
->bmdma
[i
];
95 memory_region_init_io(&bm
->extra_io
, OBJECT(d
), &via_bmdma_ops
, bm
,
97 memory_region_add_subregion(&d
->bmdma_bar
, i
* 8, &bm
->extra_io
);
98 memory_region_init_io(&bm
->addr_ioport
, OBJECT(d
),
99 &bmdma_addr_ioport_ops
, bm
, "bmdma", 4);
100 memory_region_add_subregion(&d
->bmdma_bar
, i
* 8 + 4, &bm
->addr_ioport
);
104 static void via_reset(void *opaque
)
106 PCIIDEState
*d
= opaque
;
107 PCIDevice
*pd
= PCI_DEVICE(d
);
108 uint8_t *pci_conf
= pd
->config
;
111 for (i
= 0; i
< 2; i
++) {
112 ide_bus_reset(&d
->bus
[i
]);
115 pci_set_word(pci_conf
+ PCI_COMMAND
, PCI_COMMAND_WAIT
);
116 pci_set_word(pci_conf
+ PCI_STATUS
, PCI_STATUS_FAST_BACK
|
117 PCI_STATUS_DEVSEL_MEDIUM
);
119 pci_set_long(pci_conf
+ PCI_BASE_ADDRESS_0
, 0x000001f0);
120 pci_set_long(pci_conf
+ PCI_BASE_ADDRESS_1
, 0x000003f4);
121 pci_set_long(pci_conf
+ PCI_BASE_ADDRESS_2
, 0x00000170);
122 pci_set_long(pci_conf
+ PCI_BASE_ADDRESS_3
, 0x00000374);
123 pci_set_long(pci_conf
+ PCI_BASE_ADDRESS_4
, 0x0000cc01); /* BMIBA: 20-23h */
124 pci_set_long(pci_conf
+ PCI_INTERRUPT_LINE
, 0x0000010e);
126 /* IDE chip enable, IDE configuration 1/2, IDE FIFO Configuration*/
127 pci_set_long(pci_conf
+ 0x40, 0x0a090600);
128 /* IDE misc configuration 1/2/3 */
129 pci_set_long(pci_conf
+ 0x44, 0x00c00068);
130 /* IDE Timing control */
131 pci_set_long(pci_conf
+ 0x48, 0xa8a8a8a8);
132 /* IDE Address Setup Time */
133 pci_set_long(pci_conf
+ 0x4c, 0x000000ff);
134 /* UltraDMA Extended Timing Control*/
135 pci_set_long(pci_conf
+ 0x50, 0x07070707);
136 /* UltraDMA FIFO Control */
137 pci_set_long(pci_conf
+ 0x54, 0x00000004);
138 /* IDE primary sector size */
139 pci_set_long(pci_conf
+ 0x60, 0x00000200);
140 /* IDE secondary sector size */
141 pci_set_long(pci_conf
+ 0x68, 0x00000200);
143 pci_set_long(pci_conf
+ 0xc0, 0x00020001);
146 static void vt82c686b_init_ports(PCIIDEState
*d
) {
147 static const struct {
157 for (i
= 0; i
< 2; i
++) {
158 ide_bus_new(&d
->bus
[i
], sizeof(d
->bus
[i
]), DEVICE(d
), i
, 2);
159 ide_init_ioport(&d
->bus
[i
], NULL
, port_info
[i
].iobase
,
160 port_info
[i
].iobase2
);
161 ide_init2(&d
->bus
[i
], isa_get_irq(NULL
, port_info
[i
].isairq
));
163 bmdma_init(&d
->bus
[i
], &d
->bmdma
[i
], d
);
164 d
->bmdma
[i
].bus
= &d
->bus
[i
];
165 ide_register_restart_cb(&d
->bus
[i
]);
170 static void vt82c686b_ide_realize(PCIDevice
*dev
, Error
**errp
)
172 PCIIDEState
*d
= PCI_IDE(dev
);
173 uint8_t *pci_conf
= dev
->config
;
175 pci_config_set_prog_interface(pci_conf
, 0x8a); /* legacy ATA mode */
176 pci_set_long(pci_conf
+ PCI_CAPABILITY_LIST
, 0x000000c0);
178 qemu_register_reset(via_reset
, d
);
180 pci_register_bar(dev
, 4, PCI_BASE_ADDRESS_SPACE_IO
, &d
->bmdma_bar
);
182 vmstate_register(DEVICE(dev
), 0, &vmstate_ide_pci
, d
);
184 vt82c686b_init_ports(d
);
187 static void vt82c686b_ide_exitfn(PCIDevice
*dev
)
189 PCIIDEState
*d
= PCI_IDE(dev
);
192 for (i
= 0; i
< 2; ++i
) {
193 memory_region_del_subregion(&d
->bmdma_bar
, &d
->bmdma
[i
].extra_io
);
194 memory_region_del_subregion(&d
->bmdma_bar
, &d
->bmdma
[i
].addr_ioport
);
198 void vt82c686b_ide_init(PCIBus
*bus
, DriveInfo
**hd_table
, int devfn
)
202 dev
= pci_create_simple(bus
, devfn
, "via-ide");
203 pci_ide_create_devs(dev
, hd_table
);
206 static void via_ide_class_init(ObjectClass
*klass
, void *data
)
208 DeviceClass
*dc
= DEVICE_CLASS(klass
);
209 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
211 k
->realize
= vt82c686b_ide_realize
;
212 k
->exit
= vt82c686b_ide_exitfn
;
213 k
->vendor_id
= PCI_VENDOR_ID_VIA
;
214 k
->device_id
= PCI_DEVICE_ID_VIA_IDE
;
216 k
->class_id
= PCI_CLASS_STORAGE_IDE
;
217 set_bit(DEVICE_CATEGORY_STORAGE
, dc
->categories
);
220 static const TypeInfo via_ide_info
= {
222 .parent
= TYPE_PCI_IDE
,
223 .class_init
= via_ide_class_init
,
226 static void via_ide_register_types(void)
228 type_register_static(&via_ide_info
);
231 type_init(via_ide_register_types
)