spapr: register dummy ICPs later
[qemu/ar7.git] / hw / ppc / spapr.c
blob3f1c5c5133cb85c2528a32dcfaec53f18950642c
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
27 #include "qemu/osdep.h"
28 #include "qapi/error.h"
29 #include "qapi/visitor.h"
30 #include "sysemu/sysemu.h"
31 #include "sysemu/numa.h"
32 #include "hw/hw.h"
33 #include "qemu/log.h"
34 #include "hw/fw-path-provider.h"
35 #include "elf.h"
36 #include "net/net.h"
37 #include "sysemu/device_tree.h"
38 #include "sysemu/block-backend.h"
39 #include "sysemu/cpus.h"
40 #include "sysemu/hw_accel.h"
41 #include "kvm_ppc.h"
42 #include "migration/misc.h"
43 #include "migration/global_state.h"
44 #include "migration/register.h"
45 #include "mmu-hash64.h"
46 #include "mmu-book3s-v3.h"
47 #include "cpu-models.h"
48 #include "qom/cpu.h"
50 #include "hw/boards.h"
51 #include "hw/ppc/ppc.h"
52 #include "hw/loader.h"
54 #include "hw/ppc/fdt.h"
55 #include "hw/ppc/spapr.h"
56 #include "hw/ppc/spapr_vio.h"
57 #include "hw/pci-host/spapr.h"
58 #include "hw/ppc/xics.h"
59 #include "hw/pci/msi.h"
61 #include "hw/pci/pci.h"
62 #include "hw/scsi/scsi.h"
63 #include "hw/virtio/virtio-scsi.h"
64 #include "hw/virtio/vhost-scsi-common.h"
66 #include "exec/address-spaces.h"
67 #include "hw/usb.h"
68 #include "qemu/config-file.h"
69 #include "qemu/error-report.h"
70 #include "trace.h"
71 #include "hw/nmi.h"
72 #include "hw/intc/intc.h"
74 #include "hw/compat.h"
75 #include "qemu/cutils.h"
76 #include "hw/ppc/spapr_cpu_core.h"
78 #include <libfdt.h>
80 /* SLOF memory layout:
82 * SLOF raw image loaded at 0, copies its romfs right below the flat
83 * device-tree, then position SLOF itself 31M below that
85 * So we set FW_OVERHEAD to 40MB which should account for all of that
86 * and more
88 * We load our kernel at 4M, leaving space for SLOF initial image
90 #define FDT_MAX_SIZE 0x100000
91 #define RTAS_MAX_SIZE 0x10000
92 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */
93 #define FW_MAX_SIZE 0x400000
94 #define FW_FILE_NAME "slof.bin"
95 #define FW_OVERHEAD 0x2800000
96 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
98 #define MIN_RMA_SLOF 128UL
100 #define PHANDLE_XICP 0x00001111
102 /* These two functions implement the VCPU id numbering: one to compute them
103 * all and one to identify thread 0 of a VCORE. Any change to the first one
104 * is likely to have an impact on the second one, so let's keep them close.
106 static int spapr_vcpu_id(sPAPRMachineState *spapr, int cpu_index)
108 return
109 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads;
111 static bool spapr_is_thread0_in_vcore(sPAPRMachineState *spapr,
112 PowerPCCPU *cpu)
114 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0;
117 static ICSState *spapr_ics_create(sPAPRMachineState *spapr,
118 const char *type_ics,
119 int nr_irqs, Error **errp)
121 Error *local_err = NULL;
122 Object *obj;
124 obj = object_new(type_ics);
125 object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort);
126 object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr),
127 &error_abort);
128 object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err);
129 if (local_err) {
130 goto error;
132 object_property_set_bool(obj, true, "realized", &local_err);
133 if (local_err) {
134 goto error;
137 return ICS_SIMPLE(obj);
139 error:
140 error_propagate(errp, local_err);
141 return NULL;
144 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque)
146 /* Dummy entries correspond to unused ICPState objects in older QEMUs,
147 * and newer QEMUs don't even have them. In both cases, we don't want
148 * to send anything on the wire.
150 return false;
153 static const VMStateDescription pre_2_10_vmstate_dummy_icp = {
154 .name = "icp/server",
155 .version_id = 1,
156 .minimum_version_id = 1,
157 .needed = pre_2_10_vmstate_dummy_icp_needed,
158 .fields = (VMStateField[]) {
159 VMSTATE_UNUSED(4), /* uint32_t xirr */
160 VMSTATE_UNUSED(1), /* uint8_t pending_priority */
161 VMSTATE_UNUSED(1), /* uint8_t mfrr */
162 VMSTATE_END_OF_LIST()
166 static void pre_2_10_vmstate_register_dummy_icp(int i)
168 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp,
169 (void *)(uintptr_t) i);
172 static void pre_2_10_vmstate_unregister_dummy_icp(int i)
174 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp,
175 (void *)(uintptr_t) i);
178 static int xics_max_server_number(sPAPRMachineState *spapr)
180 return DIV_ROUND_UP(max_cpus * spapr->vsmt, smp_threads);
183 static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp)
185 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
187 if (kvm_enabled()) {
188 if (machine_kernel_irqchip_allowed(machine) &&
189 !xics_kvm_init(spapr, errp)) {
190 spapr->icp_type = TYPE_KVM_ICP;
191 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, errp);
193 if (machine_kernel_irqchip_required(machine) && !spapr->ics) {
194 error_prepend(errp, "kernel_irqchip requested but unavailable: ");
195 return;
199 if (!spapr->ics) {
200 xics_spapr_init(spapr);
201 spapr->icp_type = TYPE_ICP;
202 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp);
203 if (!spapr->ics) {
204 return;
209 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
210 int smt_threads)
212 int i, ret = 0;
213 uint32_t servers_prop[smt_threads];
214 uint32_t gservers_prop[smt_threads * 2];
215 int index = spapr_get_vcpu_id(cpu);
217 if (cpu->compat_pvr) {
218 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
219 if (ret < 0) {
220 return ret;
224 /* Build interrupt servers and gservers properties */
225 for (i = 0; i < smt_threads; i++) {
226 servers_prop[i] = cpu_to_be32(index + i);
227 /* Hack, direct the group queues back to cpu 0 */
228 gservers_prop[i*2] = cpu_to_be32(index + i);
229 gservers_prop[i*2 + 1] = 0;
231 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
232 servers_prop, sizeof(servers_prop));
233 if (ret < 0) {
234 return ret;
236 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
237 gservers_prop, sizeof(gservers_prop));
239 return ret;
242 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu)
244 int index = spapr_get_vcpu_id(cpu);
245 uint32_t associativity[] = {cpu_to_be32(0x5),
246 cpu_to_be32(0x0),
247 cpu_to_be32(0x0),
248 cpu_to_be32(0x0),
249 cpu_to_be32(cpu->node_id),
250 cpu_to_be32(index)};
252 /* Advertise NUMA via ibm,associativity */
253 return fdt_setprop(fdt, offset, "ibm,associativity", associativity,
254 sizeof(associativity));
257 /* Populate the "ibm,pa-features" property */
258 static void spapr_populate_pa_features(sPAPRMachineState *spapr,
259 PowerPCCPU *cpu,
260 void *fdt, int offset,
261 bool legacy_guest)
263 CPUPPCState *env = &cpu->env;
264 uint8_t pa_features_206[] = { 6, 0,
265 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
266 uint8_t pa_features_207[] = { 24, 0,
267 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
268 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
269 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
270 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
271 uint8_t pa_features_300[] = { 66, 0,
272 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */
273 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */
274 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */
275 /* 6: DS207 */
276 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */
277 /* 16: Vector */
278 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
279 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */
280 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
281 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */
282 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */
283 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */
284 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */
285 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */
286 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */
287 /* 42: PM, 44: PC RA, 46: SC vec'd */
288 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */
289 /* 48: SIMD, 50: QP BFP, 52: String */
290 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */
291 /* 54: DecFP, 56: DecI, 58: SHA */
292 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */
293 /* 60: NM atomic, 62: RNG */
294 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */
296 uint8_t *pa_features = NULL;
297 size_t pa_size;
299 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) {
300 pa_features = pa_features_206;
301 pa_size = sizeof(pa_features_206);
303 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) {
304 pa_features = pa_features_207;
305 pa_size = sizeof(pa_features_207);
307 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) {
308 pa_features = pa_features_300;
309 pa_size = sizeof(pa_features_300);
311 if (!pa_features) {
312 return;
315 if (env->ci_large_pages) {
317 * Note: we keep CI large pages off by default because a 64K capable
318 * guest provisioned with large pages might otherwise try to map a qemu
319 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages
320 * even if that qemu runs on a 4k host.
321 * We dd this bit back here if we are confident this is not an issue
323 pa_features[3] |= 0x20;
325 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) {
326 pa_features[24] |= 0x80; /* Transactional memory support */
328 if (legacy_guest && pa_size > 40) {
329 /* Workaround for broken kernels that attempt (guest) radix
330 * mode when they can't handle it, if they see the radix bit set
331 * in pa-features. So hide it from them. */
332 pa_features[40 + 2] &= ~0x80; /* Radix MMU */
335 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
338 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
340 int ret = 0, offset, cpus_offset;
341 CPUState *cs;
342 char cpu_model[32];
343 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
345 CPU_FOREACH(cs) {
346 PowerPCCPU *cpu = POWERPC_CPU(cs);
347 DeviceClass *dc = DEVICE_GET_CLASS(cs);
348 int index = spapr_get_vcpu_id(cpu);
349 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
351 if (!spapr_is_thread0_in_vcore(spapr, cpu)) {
352 continue;
355 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
357 cpus_offset = fdt_path_offset(fdt, "/cpus");
358 if (cpus_offset < 0) {
359 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
360 if (cpus_offset < 0) {
361 return cpus_offset;
364 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
365 if (offset < 0) {
366 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
367 if (offset < 0) {
368 return offset;
372 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
373 pft_size_prop, sizeof(pft_size_prop));
374 if (ret < 0) {
375 return ret;
378 if (nb_numa_nodes > 1) {
379 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu);
380 if (ret < 0) {
381 return ret;
385 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt);
386 if (ret < 0) {
387 return ret;
390 spapr_populate_pa_features(spapr, cpu, fdt, offset,
391 spapr->cas_legacy_guest_workaround);
393 return ret;
396 static hwaddr spapr_node0_size(MachineState *machine)
398 if (nb_numa_nodes) {
399 int i;
400 for (i = 0; i < nb_numa_nodes; ++i) {
401 if (numa_info[i].node_mem) {
402 return MIN(pow2floor(numa_info[i].node_mem),
403 machine->ram_size);
407 return machine->ram_size;
410 static void add_str(GString *s, const gchar *s1)
412 g_string_append_len(s, s1, strlen(s1) + 1);
415 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
416 hwaddr size)
418 uint32_t associativity[] = {
419 cpu_to_be32(0x4), /* length */
420 cpu_to_be32(0x0), cpu_to_be32(0x0),
421 cpu_to_be32(0x0), cpu_to_be32(nodeid)
423 char mem_name[32];
424 uint64_t mem_reg_property[2];
425 int off;
427 mem_reg_property[0] = cpu_to_be64(start);
428 mem_reg_property[1] = cpu_to_be64(size);
430 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
431 off = fdt_add_subnode(fdt, 0, mem_name);
432 _FDT(off);
433 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
434 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
435 sizeof(mem_reg_property))));
436 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
437 sizeof(associativity))));
438 return off;
441 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
443 MachineState *machine = MACHINE(spapr);
444 hwaddr mem_start, node_size;
445 int i, nb_nodes = nb_numa_nodes;
446 NodeInfo *nodes = numa_info;
447 NodeInfo ramnode;
449 /* No NUMA nodes, assume there is just one node with whole RAM */
450 if (!nb_numa_nodes) {
451 nb_nodes = 1;
452 ramnode.node_mem = machine->ram_size;
453 nodes = &ramnode;
456 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
457 if (!nodes[i].node_mem) {
458 continue;
460 if (mem_start >= machine->ram_size) {
461 node_size = 0;
462 } else {
463 node_size = nodes[i].node_mem;
464 if (node_size > machine->ram_size - mem_start) {
465 node_size = machine->ram_size - mem_start;
468 if (!mem_start) {
469 /* spapr_machine_init() checks for rma_size <= node0_size
470 * already */
471 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
472 mem_start += spapr->rma_size;
473 node_size -= spapr->rma_size;
475 for ( ; node_size; ) {
476 hwaddr sizetmp = pow2floor(node_size);
478 /* mem_start != 0 here */
479 if (ctzl(mem_start) < ctzl(sizetmp)) {
480 sizetmp = 1ULL << ctzl(mem_start);
483 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
484 node_size -= sizetmp;
485 mem_start += sizetmp;
489 return 0;
492 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
493 sPAPRMachineState *spapr)
495 PowerPCCPU *cpu = POWERPC_CPU(cs);
496 CPUPPCState *env = &cpu->env;
497 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
498 int index = spapr_get_vcpu_id(cpu);
499 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
500 0xffffffff, 0xffffffff};
501 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq()
502 : SPAPR_TIMEBASE_FREQ;
503 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
504 uint32_t page_sizes_prop[64];
505 size_t page_sizes_prop_size;
506 uint32_t vcpus_per_socket = smp_threads * smp_cores;
507 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
508 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu));
509 sPAPRDRConnector *drc;
510 int drc_index;
511 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ];
512 int i;
514 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index);
515 if (drc) {
516 drc_index = spapr_drc_index(drc);
517 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)));
520 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
521 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
523 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
524 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
525 env->dcache_line_size)));
526 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
527 env->dcache_line_size)));
528 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
529 env->icache_line_size)));
530 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
531 env->icache_line_size)));
533 if (pcc->l1_dcache_size) {
534 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
535 pcc->l1_dcache_size)));
536 } else {
537 warn_report("Unknown L1 dcache size for cpu");
539 if (pcc->l1_icache_size) {
540 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
541 pcc->l1_icache_size)));
542 } else {
543 warn_report("Unknown L1 icache size for cpu");
546 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
547 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
548 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
549 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
550 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
551 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
553 if (env->spr_cb[SPR_PURR].oea_read) {
554 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
557 if (env->mmu_model & POWERPC_MMU_1TSEG) {
558 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
559 segs, sizeof(segs))));
562 /* Advertise VSX (vector extensions) if available
563 * 1 == VMX / Altivec available
564 * 2 == VSX available
566 * Only CPUs for which we create core types in spapr_cpu_core.c
567 * are possible, and all of those have VMX */
568 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) {
569 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2)));
570 } else {
571 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1)));
574 /* Advertise DFP (Decimal Floating Point) if available
575 * 0 / no property == no DFP
576 * 1 == DFP available */
577 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) {
578 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
581 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
582 sizeof(page_sizes_prop));
583 if (page_sizes_prop_size) {
584 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
585 page_sizes_prop, page_sizes_prop_size)));
588 spapr_populate_pa_features(spapr, cpu, fdt, offset, false);
590 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
591 cs->cpu_index / vcpus_per_socket)));
593 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
594 pft_size_prop, sizeof(pft_size_prop))));
596 if (nb_numa_nodes > 1) {
597 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu));
600 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
602 if (pcc->radix_page_info) {
603 for (i = 0; i < pcc->radix_page_info->count; i++) {
604 radix_AP_encodings[i] =
605 cpu_to_be32(pcc->radix_page_info->entries[i]);
607 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings",
608 radix_AP_encodings,
609 pcc->radix_page_info->count *
610 sizeof(radix_AP_encodings[0]))));
614 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
616 CPUState *cs;
617 int cpus_offset;
618 char *nodename;
620 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
621 _FDT(cpus_offset);
622 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
623 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
626 * We walk the CPUs in reverse order to ensure that CPU DT nodes
627 * created by fdt_add_subnode() end up in the right order in FDT
628 * for the guest kernel the enumerate the CPUs correctly.
630 CPU_FOREACH_REVERSE(cs) {
631 PowerPCCPU *cpu = POWERPC_CPU(cs);
632 int index = spapr_get_vcpu_id(cpu);
633 DeviceClass *dc = DEVICE_GET_CLASS(cs);
634 int offset;
636 if (!spapr_is_thread0_in_vcore(spapr, cpu)) {
637 continue;
640 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
641 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
642 g_free(nodename);
643 _FDT(offset);
644 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
649 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr)
651 MemoryDeviceInfoList *info;
653 for (info = list; info; info = info->next) {
654 MemoryDeviceInfo *value = info->value;
656 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) {
657 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data;
659 if (pcdimm_info->addr >= addr &&
660 addr < (pcdimm_info->addr + pcdimm_info->size)) {
661 return pcdimm_info->node;
666 return -1;
670 * Adds ibm,dynamic-reconfiguration-memory node.
671 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation
672 * of this device tree node.
674 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
676 MachineState *machine = MACHINE(spapr);
677 int ret, i, offset;
678 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
679 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
680 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size;
681 uint32_t nr_lmbs = (spapr->hotplug_memory.base +
682 memory_region_size(&spapr->hotplug_memory.mr)) /
683 lmb_size;
684 uint32_t *int_buf, *cur_index, buf_len;
685 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
686 MemoryDeviceInfoList *dimms = NULL;
689 * Don't create the node if there is no hotpluggable memory
691 if (machine->ram_size == machine->maxram_size) {
692 return 0;
696 * Allocate enough buffer size to fit in ibm,dynamic-memory
697 * or ibm,associativity-lookup-arrays
699 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
700 * sizeof(uint32_t);
701 cur_index = int_buf = g_malloc0(buf_len);
703 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
705 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
706 sizeof(prop_lmb_size));
707 if (ret < 0) {
708 goto out;
711 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
712 if (ret < 0) {
713 goto out;
716 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
717 if (ret < 0) {
718 goto out;
721 if (hotplug_lmb_start) {
722 MemoryDeviceInfoList **prev = &dimms;
723 qmp_pc_dimm_device_list(qdev_get_machine(), &prev);
726 /* ibm,dynamic-memory */
727 int_buf[0] = cpu_to_be32(nr_lmbs);
728 cur_index++;
729 for (i = 0; i < nr_lmbs; i++) {
730 uint64_t addr = i * lmb_size;
731 uint32_t *dynamic_memory = cur_index;
733 if (i >= hotplug_lmb_start) {
734 sPAPRDRConnector *drc;
736 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i);
737 g_assert(drc);
739 dynamic_memory[0] = cpu_to_be32(addr >> 32);
740 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
741 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc));
742 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
743 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr));
744 if (memory_region_present(get_system_memory(), addr)) {
745 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
746 } else {
747 dynamic_memory[5] = cpu_to_be32(0);
749 } else {
751 * LMB information for RMA, boot time RAM and gap b/n RAM and
752 * hotplug memory region -- all these are marked as reserved
753 * and as having no valid DRC.
755 dynamic_memory[0] = cpu_to_be32(addr >> 32);
756 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
757 dynamic_memory[2] = cpu_to_be32(0);
758 dynamic_memory[3] = cpu_to_be32(0); /* reserved */
759 dynamic_memory[4] = cpu_to_be32(-1);
760 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED |
761 SPAPR_LMB_FLAGS_DRC_INVALID);
764 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
766 qapi_free_MemoryDeviceInfoList(dimms);
767 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
768 if (ret < 0) {
769 goto out;
772 /* ibm,associativity-lookup-arrays */
773 cur_index = int_buf;
774 int_buf[0] = cpu_to_be32(nr_nodes);
775 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */
776 cur_index += 2;
777 for (i = 0; i < nr_nodes; i++) {
778 uint32_t associativity[] = {
779 cpu_to_be32(0x0),
780 cpu_to_be32(0x0),
781 cpu_to_be32(0x0),
782 cpu_to_be32(i)
784 memcpy(cur_index, associativity, sizeof(associativity));
785 cur_index += 4;
787 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
788 (cur_index - int_buf) * sizeof(uint32_t));
789 out:
790 g_free(int_buf);
791 return ret;
794 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt,
795 sPAPROptionVector *ov5_updates)
797 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
798 int ret = 0, offset;
800 /* Generate ibm,dynamic-reconfiguration-memory node if required */
801 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) {
802 g_assert(smc->dr_lmb_enabled);
803 ret = spapr_populate_drconf_memory(spapr, fdt);
804 if (ret) {
805 goto out;
809 offset = fdt_path_offset(fdt, "/chosen");
810 if (offset < 0) {
811 offset = fdt_add_subnode(fdt, 0, "chosen");
812 if (offset < 0) {
813 return offset;
816 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas,
817 "ibm,architecture-vec-5");
819 out:
820 return ret;
823 static bool spapr_hotplugged_dev_before_cas(void)
825 Object *drc_container, *obj;
826 ObjectProperty *prop;
827 ObjectPropertyIterator iter;
829 drc_container = container_get(object_get_root(), "/dr-connector");
830 object_property_iter_init(&iter, drc_container);
831 while ((prop = object_property_iter_next(&iter))) {
832 if (!strstart(prop->type, "link<", NULL)) {
833 continue;
835 obj = object_property_get_link(drc_container, prop->name, NULL);
836 if (spapr_drc_needed(obj)) {
837 return true;
840 return false;
843 int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
844 target_ulong addr, target_ulong size,
845 sPAPROptionVector *ov5_updates)
847 void *fdt, *fdt_skel;
848 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
850 if (spapr_hotplugged_dev_before_cas()) {
851 return 1;
854 if (size < sizeof(hdr) || size > FW_MAX_SIZE) {
855 error_report("SLOF provided an unexpected CAS buffer size "
856 TARGET_FMT_lu " (min: %zu, max: %u)",
857 size, sizeof(hdr), FW_MAX_SIZE);
858 exit(EXIT_FAILURE);
861 size -= sizeof(hdr);
863 /* Create skeleton */
864 fdt_skel = g_malloc0(size);
865 _FDT((fdt_create(fdt_skel, size)));
866 _FDT((fdt_begin_node(fdt_skel, "")));
867 _FDT((fdt_end_node(fdt_skel)));
868 _FDT((fdt_finish(fdt_skel)));
869 fdt = g_malloc0(size);
870 _FDT((fdt_open_into(fdt_skel, fdt, size)));
871 g_free(fdt_skel);
873 /* Fixup cpu nodes */
874 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
876 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) {
877 return -1;
880 /* Pack resulting tree */
881 _FDT((fdt_pack(fdt)));
883 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
884 trace_spapr_cas_failed(size);
885 return -1;
888 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
889 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
890 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
891 g_free(fdt);
893 return 0;
896 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt)
898 int rtas;
899 GString *hypertas = g_string_sized_new(256);
900 GString *qemu_hypertas = g_string_sized_new(256);
901 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) };
902 uint64_t max_hotplug_addr = spapr->hotplug_memory.base +
903 memory_region_size(&spapr->hotplug_memory.mr);
904 uint32_t lrdr_capacity[] = {
905 cpu_to_be32(max_hotplug_addr >> 32),
906 cpu_to_be32(max_hotplug_addr & 0xffffffff),
907 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE),
908 cpu_to_be32(max_cpus / smp_threads),
911 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas"));
913 /* hypertas */
914 add_str(hypertas, "hcall-pft");
915 add_str(hypertas, "hcall-term");
916 add_str(hypertas, "hcall-dabr");
917 add_str(hypertas, "hcall-interrupt");
918 add_str(hypertas, "hcall-tce");
919 add_str(hypertas, "hcall-vio");
920 add_str(hypertas, "hcall-splpar");
921 add_str(hypertas, "hcall-bulk");
922 add_str(hypertas, "hcall-set-mode");
923 add_str(hypertas, "hcall-sprg0");
924 add_str(hypertas, "hcall-copy");
925 add_str(hypertas, "hcall-debug");
926 add_str(qemu_hypertas, "hcall-memop1");
928 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
929 add_str(hypertas, "hcall-multi-tce");
932 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
933 add_str(hypertas, "hcall-hpt-resize");
936 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions",
937 hypertas->str, hypertas->len));
938 g_string_free(hypertas, TRUE);
939 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions",
940 qemu_hypertas->str, qemu_hypertas->len));
941 g_string_free(qemu_hypertas, TRUE);
943 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points",
944 refpoints, sizeof(refpoints)));
946 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max",
947 RTAS_ERROR_LOG_MAX));
948 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate",
949 RTAS_EVENT_SCAN_RATE));
951 g_assert(msi_nonbroken);
952 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0));
955 * According to PAPR, rtas ibm,os-term does not guarantee a return
956 * back to the guest cpu.
958 * While an additional ibm,extended-os-term property indicates
959 * that rtas call return will always occur. Set this property.
961 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0));
963 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity",
964 lrdr_capacity, sizeof(lrdr_capacity)));
966 spapr_dt_rtas_tokens(fdt, rtas);
969 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features
970 * that the guest may request and thus the valid values for bytes 24..26 of
971 * option vector 5: */
972 static void spapr_dt_ov5_platform_support(void *fdt, int chosen)
974 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu);
976 char val[2 * 4] = {
977 23, 0x00, /* Xive mode, filled in below. */
978 24, 0x00, /* Hash/Radix, filled in below. */
979 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */
980 26, 0x40, /* Radix options: GTSE == yes. */
983 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0,
984 first_ppc_cpu->compat_pvr)) {
985 /* If we're in a pre POWER9 compat mode then the guest should do hash */
986 val[3] = 0x00; /* Hash */
987 } else if (kvm_enabled()) {
988 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) {
989 val[3] = 0x80; /* OV5_MMU_BOTH */
990 } else if (kvmppc_has_cap_mmu_radix()) {
991 val[3] = 0x40; /* OV5_MMU_RADIX_300 */
992 } else {
993 val[3] = 0x00; /* Hash */
995 } else {
996 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */
997 val[3] = 0xC0;
999 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support",
1000 val, sizeof(val)));
1003 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt)
1005 MachineState *machine = MACHINE(spapr);
1006 int chosen;
1007 const char *boot_device = machine->boot_order;
1008 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
1009 size_t cb = 0;
1010 char *bootlist = get_boot_devices_list(&cb, true);
1012 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen"));
1014 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline));
1015 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start",
1016 spapr->initrd_base));
1017 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end",
1018 spapr->initrd_base + spapr->initrd_size));
1020 if (spapr->kernel_size) {
1021 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
1022 cpu_to_be64(spapr->kernel_size) };
1024 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel",
1025 &kprop, sizeof(kprop)));
1026 if (spapr->kernel_le) {
1027 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0));
1030 if (boot_menu) {
1031 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu)));
1033 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width));
1034 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height));
1035 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth));
1037 if (cb && bootlist) {
1038 int i;
1040 for (i = 0; i < cb; i++) {
1041 if (bootlist[i] == '\n') {
1042 bootlist[i] = ' ';
1045 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist));
1048 if (boot_device && strlen(boot_device)) {
1049 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device));
1052 if (!spapr->has_graphics && stdout_path) {
1053 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path));
1056 spapr_dt_ov5_platform_support(fdt, chosen);
1058 g_free(stdout_path);
1059 g_free(bootlist);
1062 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt)
1064 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR
1065 * KVM to work under pHyp with some guest co-operation */
1066 int hypervisor;
1067 uint8_t hypercall[16];
1069 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor"));
1070 /* indicate KVM hypercall interface */
1071 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm"));
1072 if (kvmppc_has_cap_fixup_hcalls()) {
1074 * Older KVM versions with older guest kernels were broken
1075 * with the magic page, don't allow the guest to map it.
1077 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
1078 sizeof(hypercall))) {
1079 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions",
1080 hypercall, sizeof(hypercall)));
1085 static void *spapr_build_fdt(sPAPRMachineState *spapr,
1086 hwaddr rtas_addr,
1087 hwaddr rtas_size)
1089 MachineState *machine = MACHINE(spapr);
1090 MachineClass *mc = MACHINE_GET_CLASS(machine);
1091 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1092 int ret;
1093 void *fdt;
1094 sPAPRPHBState *phb;
1095 char *buf;
1097 fdt = g_malloc0(FDT_MAX_SIZE);
1098 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
1100 /* Root node */
1101 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp"));
1102 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)"));
1103 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries"));
1106 * Add info to guest to indentify which host is it being run on
1107 * and what is the uuid of the guest
1109 if (kvmppc_get_host_model(&buf)) {
1110 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf));
1111 g_free(buf);
1113 if (kvmppc_get_host_serial(&buf)) {
1114 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf));
1115 g_free(buf);
1118 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
1120 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf));
1121 if (qemu_uuid_set) {
1122 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf));
1124 g_free(buf);
1126 if (qemu_get_vm_name()) {
1127 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name",
1128 qemu_get_vm_name()));
1131 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2));
1132 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2));
1134 /* /interrupt controller */
1135 spapr_dt_xics(xics_max_server_number(spapr), fdt, PHANDLE_XICP);
1137 ret = spapr_populate_memory(spapr, fdt);
1138 if (ret < 0) {
1139 error_report("couldn't setup memory nodes in fdt");
1140 exit(1);
1143 /* /vdevice */
1144 spapr_dt_vdevice(spapr->vio_bus, fdt);
1146 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
1147 ret = spapr_rng_populate_dt(fdt);
1148 if (ret < 0) {
1149 error_report("could not set up rng device in the fdt");
1150 exit(1);
1154 QLIST_FOREACH(phb, &spapr->phbs, list) {
1155 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
1156 if (ret < 0) {
1157 error_report("couldn't setup PCI devices in fdt");
1158 exit(1);
1162 /* cpus */
1163 spapr_populate_cpus_dt_node(fdt, spapr);
1165 if (smc->dr_lmb_enabled) {
1166 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
1169 if (mc->has_hotpluggable_cpus) {
1170 int offset = fdt_path_offset(fdt, "/cpus");
1171 ret = spapr_drc_populate_dt(fdt, offset, NULL,
1172 SPAPR_DR_CONNECTOR_TYPE_CPU);
1173 if (ret < 0) {
1174 error_report("Couldn't set up CPU DR device tree properties");
1175 exit(1);
1179 /* /event-sources */
1180 spapr_dt_events(spapr, fdt);
1182 /* /rtas */
1183 spapr_dt_rtas(spapr, fdt);
1185 /* /chosen */
1186 spapr_dt_chosen(spapr, fdt);
1188 /* /hypervisor */
1189 if (kvm_enabled()) {
1190 spapr_dt_hypervisor(spapr, fdt);
1193 /* Build memory reserve map */
1194 if (spapr->kernel_size) {
1195 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size)));
1197 if (spapr->initrd_size) {
1198 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size)));
1201 /* ibm,client-architecture-support updates */
1202 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas);
1203 if (ret < 0) {
1204 error_report("couldn't setup CAS properties fdt");
1205 exit(1);
1208 return fdt;
1211 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1213 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1216 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
1217 PowerPCCPU *cpu)
1219 CPUPPCState *env = &cpu->env;
1221 /* The TCG path should also be holding the BQL at this point */
1222 g_assert(qemu_mutex_iothread_locked());
1224 if (msr_pr) {
1225 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1226 env->gpr[3] = H_PRIVILEGE;
1227 } else {
1228 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1232 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp)
1234 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1236 return spapr->patb_entry;
1239 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1240 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1241 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1242 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1243 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1246 * Get the fd to access the kernel htab, re-opening it if necessary
1248 static int get_htab_fd(sPAPRMachineState *spapr)
1250 Error *local_err = NULL;
1252 if (spapr->htab_fd >= 0) {
1253 return spapr->htab_fd;
1256 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err);
1257 if (spapr->htab_fd < 0) {
1258 error_report_err(local_err);
1261 return spapr->htab_fd;
1264 void close_htab_fd(sPAPRMachineState *spapr)
1266 if (spapr->htab_fd >= 0) {
1267 close(spapr->htab_fd);
1269 spapr->htab_fd = -1;
1272 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp)
1274 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1276 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1;
1279 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp)
1281 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1283 assert(kvm_enabled());
1285 if (!spapr->htab) {
1286 return 0;
1289 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18);
1292 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp,
1293 hwaddr ptex, int n)
1295 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1296 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
1298 if (!spapr->htab) {
1300 * HTAB is controlled by KVM. Fetch into temporary buffer
1302 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64);
1303 kvmppc_read_hptes(hptes, ptex, n);
1304 return hptes;
1308 * HTAB is controlled by QEMU. Just point to the internally
1309 * accessible PTEG.
1311 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset);
1314 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp,
1315 const ppc_hash_pte64_t *hptes,
1316 hwaddr ptex, int n)
1318 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1320 if (!spapr->htab) {
1321 g_free((void *)hptes);
1324 /* Nothing to do for qemu managed HPT */
1327 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex,
1328 uint64_t pte0, uint64_t pte1)
1330 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
1331 hwaddr offset = ptex * HASH_PTE_SIZE_64;
1333 if (!spapr->htab) {
1334 kvmppc_write_hpte(ptex, pte0, pte1);
1335 } else {
1336 stq_p(spapr->htab + offset, pte0);
1337 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1);
1341 int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1343 int shift;
1345 /* We aim for a hash table of size 1/128 the size of RAM (rounded
1346 * up). The PAPR recommendation is actually 1/64 of RAM size, but
1347 * that's much more than is needed for Linux guests */
1348 shift = ctz64(pow2ceil(ramsize)) - 7;
1349 shift = MAX(shift, 18); /* Minimum architected size */
1350 shift = MIN(shift, 46); /* Maximum architected size */
1351 return shift;
1354 void spapr_free_hpt(sPAPRMachineState *spapr)
1356 g_free(spapr->htab);
1357 spapr->htab = NULL;
1358 spapr->htab_shift = 0;
1359 close_htab_fd(spapr);
1362 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1363 Error **errp)
1365 long rc;
1367 /* Clean up any HPT info from a previous boot */
1368 spapr_free_hpt(spapr);
1370 rc = kvmppc_reset_htab(shift);
1371 if (rc < 0) {
1372 /* kernel-side HPT needed, but couldn't allocate one */
1373 error_setg_errno(errp, errno,
1374 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1375 shift);
1376 /* This is almost certainly fatal, but if the caller really
1377 * wants to carry on with shift == 0, it's welcome to try */
1378 } else if (rc > 0) {
1379 /* kernel-side HPT allocated */
1380 if (rc != shift) {
1381 error_setg(errp,
1382 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1383 shift, rc);
1386 spapr->htab_shift = shift;
1387 spapr->htab = NULL;
1388 } else {
1389 /* kernel-side HPT not needed, allocate in userspace instead */
1390 size_t size = 1ULL << shift;
1391 int i;
1393 spapr->htab = qemu_memalign(size, size);
1394 if (!spapr->htab) {
1395 error_setg_errno(errp, errno,
1396 "Could not allocate HPT of order %d", shift);
1397 return;
1400 memset(spapr->htab, 0, size);
1401 spapr->htab_shift = shift;
1403 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1404 DIRTY_HPTE(HPTE(spapr->htab, i));
1407 /* We're setting up a hash table, so that means we're not radix */
1408 spapr->patb_entry = 0;
1411 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr)
1413 int hpt_shift;
1415 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED)
1416 || (spapr->cas_reboot
1417 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) {
1418 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);
1419 } else {
1420 uint64_t current_ram_size;
1422 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size();
1423 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size);
1425 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal);
1427 if (spapr->vrma_adjust) {
1428 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)),
1429 spapr->htab_shift);
1433 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1435 bool matched = false;
1437 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1438 matched = true;
1441 if (!matched) {
1442 error_report("Device %s is not supported by this machine yet.",
1443 qdev_fw_name(DEVICE(sbdev)));
1444 exit(1);
1448 static int spapr_reset_drcs(Object *child, void *opaque)
1450 sPAPRDRConnector *drc =
1451 (sPAPRDRConnector *) object_dynamic_cast(child,
1452 TYPE_SPAPR_DR_CONNECTOR);
1454 if (drc) {
1455 spapr_drc_reset(drc);
1458 return 0;
1461 static void spapr_machine_reset(void)
1463 MachineState *machine = MACHINE(qdev_get_machine());
1464 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1465 PowerPCCPU *first_ppc_cpu;
1466 uint32_t rtas_limit;
1467 hwaddr rtas_addr, fdt_addr;
1468 void *fdt;
1469 int rc;
1471 /* Check for unknown sysbus devices */
1472 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1474 spapr_caps_reset(spapr);
1476 first_ppc_cpu = POWERPC_CPU(first_cpu);
1477 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() &&
1478 ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0,
1479 spapr->max_compat_pvr)) {
1480 /* If using KVM with radix mode available, VCPUs can be started
1481 * without a HPT because KVM will start them in radix mode.
1482 * Set the GR bit in PATB so that we know there is no HPT. */
1483 spapr->patb_entry = PATBE1_GR;
1484 } else {
1485 spapr_setup_hpt_and_vrma(spapr);
1488 /* if this reset wasn't generated by CAS, we should reset our
1489 * negotiated options and start from scratch */
1490 if (!spapr->cas_reboot) {
1491 spapr_ovec_cleanup(spapr->ov5_cas);
1492 spapr->ov5_cas = spapr_ovec_new();
1494 ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, &error_fatal);
1497 qemu_devices_reset();
1499 /* DRC reset may cause a device to be unplugged. This will cause troubles
1500 * if this device is used by another device (eg, a running vhost backend
1501 * will crash QEMU if the DIMM holding the vring goes away). To avoid such
1502 * situations, we reset DRCs after all devices have been reset.
1504 object_child_foreach_recursive(object_get_root(), spapr_reset_drcs, NULL);
1506 spapr_clear_pending_events(spapr);
1509 * We place the device tree and RTAS just below either the top of the RMA,
1510 * or just below 2GB, whichever is lowere, so that it can be
1511 * processed with 32-bit real mode code if necessary
1513 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1514 rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1515 fdt_addr = rtas_addr - FDT_MAX_SIZE;
1517 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size);
1519 spapr_load_rtas(spapr, fdt, rtas_addr);
1521 rc = fdt_pack(fdt);
1523 /* Should only fail if we've built a corrupted tree */
1524 assert(rc == 0);
1526 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
1527 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
1528 fdt_totalsize(fdt), FDT_MAX_SIZE);
1529 exit(1);
1532 /* Load the fdt */
1533 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
1534 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1535 g_free(fdt);
1537 /* Set up the entry state */
1538 first_ppc_cpu->env.gpr[3] = fdt_addr;
1539 first_ppc_cpu->env.gpr[5] = 0;
1540 first_cpu->halted = 0;
1541 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
1543 spapr->cas_reboot = false;
1546 static void spapr_create_nvram(sPAPRMachineState *spapr)
1548 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1549 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1551 if (dinfo) {
1552 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1553 &error_fatal);
1556 qdev_init_nofail(dev);
1558 spapr->nvram = (struct sPAPRNVRAM *)dev;
1561 static void spapr_rtc_create(sPAPRMachineState *spapr)
1563 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC);
1564 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc),
1565 &error_fatal);
1566 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized",
1567 &error_fatal);
1568 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc),
1569 "date", &error_fatal);
1572 /* Returns whether we want to use VGA or not */
1573 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1575 switch (vga_interface_type) {
1576 case VGA_NONE:
1577 return false;
1578 case VGA_DEVICE:
1579 return true;
1580 case VGA_STD:
1581 case VGA_VIRTIO:
1582 return pci_vga_init(pci_bus) != NULL;
1583 default:
1584 error_setg(errp,
1585 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1586 return false;
1590 static int spapr_pre_load(void *opaque)
1592 int rc;
1594 rc = spapr_caps_pre_load(opaque);
1595 if (rc) {
1596 return rc;
1599 return 0;
1602 static int spapr_post_load(void *opaque, int version_id)
1604 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1605 int err = 0;
1607 err = spapr_caps_post_migration(spapr);
1608 if (err) {
1609 return err;
1612 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) {
1613 CPUState *cs;
1614 CPU_FOREACH(cs) {
1615 PowerPCCPU *cpu = POWERPC_CPU(cs);
1616 icp_resend(ICP(cpu->intc));
1620 /* In earlier versions, there was no separate qdev for the PAPR
1621 * RTC, so the RTC offset was stored directly in sPAPREnvironment.
1622 * So when migrating from those versions, poke the incoming offset
1623 * value into the RTC device */
1624 if (version_id < 3) {
1625 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset);
1628 if (kvm_enabled() && spapr->patb_entry) {
1629 PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
1630 bool radix = !!(spapr->patb_entry & PATBE1_GR);
1631 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE);
1633 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry);
1634 if (err) {
1635 error_report("Process table config unsupported by the host");
1636 return -EINVAL;
1640 return err;
1643 static int spapr_pre_save(void *opaque)
1645 int rc;
1647 rc = spapr_caps_pre_save(opaque);
1648 if (rc) {
1649 return rc;
1652 return 0;
1655 static bool version_before_3(void *opaque, int version_id)
1657 return version_id < 3;
1660 static bool spapr_pending_events_needed(void *opaque)
1662 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1663 return !QTAILQ_EMPTY(&spapr->pending_events);
1666 static const VMStateDescription vmstate_spapr_event_entry = {
1667 .name = "spapr_event_log_entry",
1668 .version_id = 1,
1669 .minimum_version_id = 1,
1670 .fields = (VMStateField[]) {
1671 VMSTATE_UINT32(summary, sPAPREventLogEntry),
1672 VMSTATE_UINT32(extended_length, sPAPREventLogEntry),
1673 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0,
1674 NULL, extended_length),
1675 VMSTATE_END_OF_LIST()
1679 static const VMStateDescription vmstate_spapr_pending_events = {
1680 .name = "spapr_pending_events",
1681 .version_id = 1,
1682 .minimum_version_id = 1,
1683 .needed = spapr_pending_events_needed,
1684 .fields = (VMStateField[]) {
1685 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1,
1686 vmstate_spapr_event_entry, sPAPREventLogEntry, next),
1687 VMSTATE_END_OF_LIST()
1691 static bool spapr_ov5_cas_needed(void *opaque)
1693 sPAPRMachineState *spapr = opaque;
1694 sPAPROptionVector *ov5_mask = spapr_ovec_new();
1695 sPAPROptionVector *ov5_legacy = spapr_ovec_new();
1696 sPAPROptionVector *ov5_removed = spapr_ovec_new();
1697 bool cas_needed;
1699 /* Prior to the introduction of sPAPROptionVector, we had two option
1700 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY.
1701 * Both of these options encode machine topology into the device-tree
1702 * in such a way that the now-booted OS should still be able to interact
1703 * appropriately with QEMU regardless of what options were actually
1704 * negotiatied on the source side.
1706 * As such, we can avoid migrating the CAS-negotiated options if these
1707 * are the only options available on the current machine/platform.
1708 * Since these are the only options available for pseries-2.7 and
1709 * earlier, this allows us to maintain old->new/new->old migration
1710 * compatibility.
1712 * For QEMU 2.8+, there are additional CAS-negotiatable options available
1713 * via default pseries-2.8 machines and explicit command-line parameters.
1714 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware
1715 * of the actual CAS-negotiated values to continue working properly. For
1716 * example, availability of memory unplug depends on knowing whether
1717 * OV5_HP_EVT was negotiated via CAS.
1719 * Thus, for any cases where the set of available CAS-negotiatable
1720 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we
1721 * include the CAS-negotiated options in the migration stream.
1723 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY);
1724 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY);
1726 /* spapr_ovec_diff returns true if bits were removed. we avoid using
1727 * the mask itself since in the future it's possible "legacy" bits may be
1728 * removed via machine options, which could generate a false positive
1729 * that breaks migration.
1731 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask);
1732 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy);
1734 spapr_ovec_cleanup(ov5_mask);
1735 spapr_ovec_cleanup(ov5_legacy);
1736 spapr_ovec_cleanup(ov5_removed);
1738 return cas_needed;
1741 static const VMStateDescription vmstate_spapr_ov5_cas = {
1742 .name = "spapr_option_vector_ov5_cas",
1743 .version_id = 1,
1744 .minimum_version_id = 1,
1745 .needed = spapr_ov5_cas_needed,
1746 .fields = (VMStateField[]) {
1747 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1,
1748 vmstate_spapr_ovec, sPAPROptionVector),
1749 VMSTATE_END_OF_LIST()
1753 static bool spapr_patb_entry_needed(void *opaque)
1755 sPAPRMachineState *spapr = opaque;
1757 return !!spapr->patb_entry;
1760 static const VMStateDescription vmstate_spapr_patb_entry = {
1761 .name = "spapr_patb_entry",
1762 .version_id = 1,
1763 .minimum_version_id = 1,
1764 .needed = spapr_patb_entry_needed,
1765 .fields = (VMStateField[]) {
1766 VMSTATE_UINT64(patb_entry, sPAPRMachineState),
1767 VMSTATE_END_OF_LIST()
1771 static const VMStateDescription vmstate_spapr = {
1772 .name = "spapr",
1773 .version_id = 3,
1774 .minimum_version_id = 1,
1775 .pre_load = spapr_pre_load,
1776 .post_load = spapr_post_load,
1777 .pre_save = spapr_pre_save,
1778 .fields = (VMStateField[]) {
1779 /* used to be @next_irq */
1780 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1782 /* RTC offset */
1783 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
1785 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
1786 VMSTATE_END_OF_LIST()
1788 .subsections = (const VMStateDescription*[]) {
1789 &vmstate_spapr_ov5_cas,
1790 &vmstate_spapr_patb_entry,
1791 &vmstate_spapr_pending_events,
1792 &vmstate_spapr_cap_htm,
1793 &vmstate_spapr_cap_vsx,
1794 &vmstate_spapr_cap_dfp,
1795 &vmstate_spapr_cap_cfpc,
1796 &vmstate_spapr_cap_sbbc,
1797 &vmstate_spapr_cap_ibs,
1798 NULL
1802 static int htab_save_setup(QEMUFile *f, void *opaque)
1804 sPAPRMachineState *spapr = opaque;
1806 /* "Iteration" header */
1807 if (!spapr->htab_shift) {
1808 qemu_put_be32(f, -1);
1809 } else {
1810 qemu_put_be32(f, spapr->htab_shift);
1813 if (spapr->htab) {
1814 spapr->htab_save_index = 0;
1815 spapr->htab_first_pass = true;
1816 } else {
1817 if (spapr->htab_shift) {
1818 assert(kvm_enabled());
1823 return 0;
1826 static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr,
1827 int chunkstart, int n_valid, int n_invalid)
1829 qemu_put_be32(f, chunkstart);
1830 qemu_put_be16(f, n_valid);
1831 qemu_put_be16(f, n_invalid);
1832 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1833 HASH_PTE_SIZE_64 * n_valid);
1836 static void htab_save_end_marker(QEMUFile *f)
1838 qemu_put_be32(f, 0);
1839 qemu_put_be16(f, 0);
1840 qemu_put_be16(f, 0);
1843 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
1844 int64_t max_ns)
1846 bool has_timeout = max_ns != -1;
1847 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1848 int index = spapr->htab_save_index;
1849 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1851 assert(spapr->htab_first_pass);
1853 do {
1854 int chunkstart;
1856 /* Consume invalid HPTEs */
1857 while ((index < htabslots)
1858 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1859 CLEAN_HPTE(HPTE(spapr->htab, index));
1860 index++;
1863 /* Consume valid HPTEs */
1864 chunkstart = index;
1865 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1866 && HPTE_VALID(HPTE(spapr->htab, index))) {
1867 CLEAN_HPTE(HPTE(spapr->htab, index));
1868 index++;
1871 if (index > chunkstart) {
1872 int n_valid = index - chunkstart;
1874 htab_save_chunk(f, spapr, chunkstart, n_valid, 0);
1876 if (has_timeout &&
1877 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1878 break;
1881 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1883 if (index >= htabslots) {
1884 assert(index == htabslots);
1885 index = 0;
1886 spapr->htab_first_pass = false;
1888 spapr->htab_save_index = index;
1891 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
1892 int64_t max_ns)
1894 bool final = max_ns < 0;
1895 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1896 int examined = 0, sent = 0;
1897 int index = spapr->htab_save_index;
1898 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1900 assert(!spapr->htab_first_pass);
1902 do {
1903 int chunkstart, invalidstart;
1905 /* Consume non-dirty HPTEs */
1906 while ((index < htabslots)
1907 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1908 index++;
1909 examined++;
1912 chunkstart = index;
1913 /* Consume valid dirty HPTEs */
1914 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1915 && HPTE_DIRTY(HPTE(spapr->htab, index))
1916 && HPTE_VALID(HPTE(spapr->htab, index))) {
1917 CLEAN_HPTE(HPTE(spapr->htab, index));
1918 index++;
1919 examined++;
1922 invalidstart = index;
1923 /* Consume invalid dirty HPTEs */
1924 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
1925 && HPTE_DIRTY(HPTE(spapr->htab, index))
1926 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1927 CLEAN_HPTE(HPTE(spapr->htab, index));
1928 index++;
1929 examined++;
1932 if (index > chunkstart) {
1933 int n_valid = invalidstart - chunkstart;
1934 int n_invalid = index - invalidstart;
1936 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid);
1937 sent += index - chunkstart;
1939 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1940 break;
1944 if (examined >= htabslots) {
1945 break;
1948 if (index >= htabslots) {
1949 assert(index == htabslots);
1950 index = 0;
1952 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1954 if (index >= htabslots) {
1955 assert(index == htabslots);
1956 index = 0;
1959 spapr->htab_save_index = index;
1961 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
1964 #define MAX_ITERATION_NS 5000000 /* 5 ms */
1965 #define MAX_KVM_BUF_SIZE 2048
1967 static int htab_save_iterate(QEMUFile *f, void *opaque)
1969 sPAPRMachineState *spapr = opaque;
1970 int fd;
1971 int rc = 0;
1973 /* Iteration header */
1974 if (!spapr->htab_shift) {
1975 qemu_put_be32(f, -1);
1976 return 1;
1977 } else {
1978 qemu_put_be32(f, 0);
1981 if (!spapr->htab) {
1982 assert(kvm_enabled());
1984 fd = get_htab_fd(spapr);
1985 if (fd < 0) {
1986 return fd;
1989 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
1990 if (rc < 0) {
1991 return rc;
1993 } else if (spapr->htab_first_pass) {
1994 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1995 } else {
1996 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
1999 htab_save_end_marker(f);
2001 return rc;
2004 static int htab_save_complete(QEMUFile *f, void *opaque)
2006 sPAPRMachineState *spapr = opaque;
2007 int fd;
2009 /* Iteration header */
2010 if (!spapr->htab_shift) {
2011 qemu_put_be32(f, -1);
2012 return 0;
2013 } else {
2014 qemu_put_be32(f, 0);
2017 if (!spapr->htab) {
2018 int rc;
2020 assert(kvm_enabled());
2022 fd = get_htab_fd(spapr);
2023 if (fd < 0) {
2024 return fd;
2027 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
2028 if (rc < 0) {
2029 return rc;
2031 } else {
2032 if (spapr->htab_first_pass) {
2033 htab_save_first_pass(f, spapr, -1);
2035 htab_save_later_pass(f, spapr, -1);
2038 /* End marker */
2039 htab_save_end_marker(f);
2041 return 0;
2044 static int htab_load(QEMUFile *f, void *opaque, int version_id)
2046 sPAPRMachineState *spapr = opaque;
2047 uint32_t section_hdr;
2048 int fd = -1;
2049 Error *local_err = NULL;
2051 if (version_id < 1 || version_id > 1) {
2052 error_report("htab_load() bad version");
2053 return -EINVAL;
2056 section_hdr = qemu_get_be32(f);
2058 if (section_hdr == -1) {
2059 spapr_free_hpt(spapr);
2060 return 0;
2063 if (section_hdr) {
2064 /* First section gives the htab size */
2065 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
2066 if (local_err) {
2067 error_report_err(local_err);
2068 return -EINVAL;
2070 return 0;
2073 if (!spapr->htab) {
2074 assert(kvm_enabled());
2076 fd = kvmppc_get_htab_fd(true, 0, &local_err);
2077 if (fd < 0) {
2078 error_report_err(local_err);
2079 return fd;
2083 while (true) {
2084 uint32_t index;
2085 uint16_t n_valid, n_invalid;
2087 index = qemu_get_be32(f);
2088 n_valid = qemu_get_be16(f);
2089 n_invalid = qemu_get_be16(f);
2091 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
2092 /* End of Stream */
2093 break;
2096 if ((index + n_valid + n_invalid) >
2097 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
2098 /* Bad index in stream */
2099 error_report(
2100 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
2101 index, n_valid, n_invalid, spapr->htab_shift);
2102 return -EINVAL;
2105 if (spapr->htab) {
2106 if (n_valid) {
2107 qemu_get_buffer(f, HPTE(spapr->htab, index),
2108 HASH_PTE_SIZE_64 * n_valid);
2110 if (n_invalid) {
2111 memset(HPTE(spapr->htab, index + n_valid), 0,
2112 HASH_PTE_SIZE_64 * n_invalid);
2114 } else {
2115 int rc;
2117 assert(fd >= 0);
2119 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
2120 if (rc < 0) {
2121 return rc;
2126 if (!spapr->htab) {
2127 assert(fd >= 0);
2128 close(fd);
2131 return 0;
2134 static void htab_save_cleanup(void *opaque)
2136 sPAPRMachineState *spapr = opaque;
2138 close_htab_fd(spapr);
2141 static SaveVMHandlers savevm_htab_handlers = {
2142 .save_setup = htab_save_setup,
2143 .save_live_iterate = htab_save_iterate,
2144 .save_live_complete_precopy = htab_save_complete,
2145 .save_cleanup = htab_save_cleanup,
2146 .load_state = htab_load,
2149 static void spapr_boot_set(void *opaque, const char *boot_device,
2150 Error **errp)
2152 MachineState *machine = MACHINE(opaque);
2153 machine->boot_order = g_strdup(boot_device);
2156 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
2158 MachineState *machine = MACHINE(spapr);
2159 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
2160 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
2161 int i;
2163 for (i = 0; i < nr_lmbs; i++) {
2164 uint64_t addr;
2166 addr = i * lmb_size + spapr->hotplug_memory.base;
2167 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB,
2168 addr / lmb_size);
2173 * If RAM size, maxmem size and individual node mem sizes aren't aligned
2174 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest
2175 * since we can't support such unaligned sizes with DRCONF_MEMORY.
2177 static void spapr_validate_node_memory(MachineState *machine, Error **errp)
2179 int i;
2181 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2182 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
2183 " is not aligned to %llu MiB",
2184 machine->ram_size,
2185 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2186 return;
2189 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
2190 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
2191 " is not aligned to %llu MiB",
2192 machine->ram_size,
2193 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2194 return;
2197 for (i = 0; i < nb_numa_nodes; i++) {
2198 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
2199 error_setg(errp,
2200 "Node %d memory size 0x%" PRIx64
2201 " is not aligned to %llu MiB",
2202 i, numa_info[i].node_mem,
2203 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
2204 return;
2209 /* find cpu slot in machine->possible_cpus by core_id */
2210 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx)
2212 int index = id / smp_threads;
2214 if (index >= ms->possible_cpus->len) {
2215 return NULL;
2217 if (idx) {
2218 *idx = index;
2220 return &ms->possible_cpus->cpus[index];
2223 static void spapr_init_cpus(sPAPRMachineState *spapr)
2225 MachineState *machine = MACHINE(spapr);
2226 MachineClass *mc = MACHINE_GET_CLASS(machine);
2227 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2228 const char *type = spapr_get_cpu_core_type(machine->cpu_type);
2229 const CPUArchIdList *possible_cpus;
2230 int boot_cores_nr = smp_cpus / smp_threads;
2231 int i;
2233 possible_cpus = mc->possible_cpu_arch_ids(machine);
2234 if (mc->has_hotpluggable_cpus) {
2235 if (smp_cpus % smp_threads) {
2236 error_report("smp_cpus (%u) must be multiple of threads (%u)",
2237 smp_cpus, smp_threads);
2238 exit(1);
2240 if (max_cpus % smp_threads) {
2241 error_report("max_cpus (%u) must be multiple of threads (%u)",
2242 max_cpus, smp_threads);
2243 exit(1);
2245 } else {
2246 if (max_cpus != smp_cpus) {
2247 error_report("This machine version does not support CPU hotplug");
2248 exit(1);
2250 boot_cores_nr = possible_cpus->len;
2253 if (smc->pre_2_10_has_unused_icps) {
2254 int i;
2256 for (i = 0; i < xics_max_server_number(spapr); i++) {
2257 /* Dummy entries get deregistered when real ICPState objects
2258 * are registered during CPU core hotplug.
2260 pre_2_10_vmstate_register_dummy_icp(i);
2264 for (i = 0; i < possible_cpus->len; i++) {
2265 int core_id = i * smp_threads;
2267 if (mc->has_hotpluggable_cpus) {
2268 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU,
2269 spapr_vcpu_id(spapr, core_id));
2272 if (i < boot_cores_nr) {
2273 Object *core = object_new(type);
2274 int nr_threads = smp_threads;
2276 /* Handle the partially filled core for older machine types */
2277 if ((i + 1) * smp_threads >= smp_cpus) {
2278 nr_threads = smp_cpus - i * smp_threads;
2281 object_property_set_int(core, nr_threads, "nr-threads",
2282 &error_fatal);
2283 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
2284 &error_fatal);
2285 object_property_set_bool(core, true, "realized", &error_fatal);
2290 static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp)
2292 Error *local_err = NULL;
2293 bool vsmt_user = !!spapr->vsmt;
2294 int kvm_smt = kvmppc_smt_threads();
2295 int ret;
2297 if (!kvm_enabled() && (smp_threads > 1)) {
2298 error_setg(&local_err, "TCG cannot support more than 1 thread/core "
2299 "on a pseries machine");
2300 goto out;
2302 if (!is_power_of_2(smp_threads)) {
2303 error_setg(&local_err, "Cannot support %d threads/core on a pseries "
2304 "machine because it must be a power of 2", smp_threads);
2305 goto out;
2308 /* Detemine the VSMT mode to use: */
2309 if (vsmt_user) {
2310 if (spapr->vsmt < smp_threads) {
2311 error_setg(&local_err, "Cannot support VSMT mode %d"
2312 " because it must be >= threads/core (%d)",
2313 spapr->vsmt, smp_threads);
2314 goto out;
2316 /* In this case, spapr->vsmt has been set by the command line */
2317 } else {
2319 * Default VSMT value is tricky, because we need it to be as
2320 * consistent as possible (for migration), but this requires
2321 * changing it for at least some existing cases. We pick 8 as
2322 * the value that we'd get with KVM on POWER8, the
2323 * overwhelmingly common case in production systems.
2325 spapr->vsmt = MAX(8, smp_threads);
2328 /* KVM: If necessary, set the SMT mode: */
2329 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) {
2330 ret = kvmppc_set_smt_threads(spapr->vsmt);
2331 if (ret) {
2332 /* Looks like KVM isn't able to change VSMT mode */
2333 error_setg(&local_err,
2334 "Failed to set KVM's VSMT mode to %d (errno %d)",
2335 spapr->vsmt, ret);
2336 /* We can live with that if the default one is big enough
2337 * for the number of threads, and a submultiple of the one
2338 * we want. In this case we'll waste some vcpu ids, but
2339 * behaviour will be correct */
2340 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) {
2341 warn_report_err(local_err);
2342 local_err = NULL;
2343 goto out;
2344 } else {
2345 if (!vsmt_user) {
2346 error_append_hint(&local_err,
2347 "On PPC, a VM with %d threads/core"
2348 " on a host with %d threads/core"
2349 " requires the use of VSMT mode %d.\n",
2350 smp_threads, kvm_smt, spapr->vsmt);
2352 kvmppc_hint_smt_possible(&local_err);
2353 goto out;
2357 /* else TCG: nothing to do currently */
2358 out:
2359 error_propagate(errp, local_err);
2362 /* pSeries LPAR / sPAPR hardware init */
2363 static void spapr_machine_init(MachineState *machine)
2365 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
2366 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
2367 const char *kernel_filename = machine->kernel_filename;
2368 const char *initrd_filename = machine->initrd_filename;
2369 PCIHostState *phb;
2370 int i;
2371 MemoryRegion *sysmem = get_system_memory();
2372 MemoryRegion *ram = g_new(MemoryRegion, 1);
2373 MemoryRegion *rma_region;
2374 void *rma = NULL;
2375 hwaddr rma_alloc_size;
2376 hwaddr node0_size = spapr_node0_size(machine);
2377 long load_limit, fw_size;
2378 char *filename;
2379 Error *resize_hpt_err = NULL;
2381 msi_nonbroken = true;
2383 QLIST_INIT(&spapr->phbs);
2384 QTAILQ_INIT(&spapr->pending_dimm_unplugs);
2386 /* Check HPT resizing availability */
2387 kvmppc_check_papr_resize_hpt(&resize_hpt_err);
2388 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) {
2390 * If the user explicitly requested a mode we should either
2391 * supply it, or fail completely (which we do below). But if
2392 * it's not set explicitly, we reset our mode to something
2393 * that works
2395 if (resize_hpt_err) {
2396 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2397 error_free(resize_hpt_err);
2398 resize_hpt_err = NULL;
2399 } else {
2400 spapr->resize_hpt = smc->resize_hpt_default;
2404 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT);
2406 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) {
2408 * User requested HPT resize, but this host can't supply it. Bail out
2410 error_report_err(resize_hpt_err);
2411 exit(1);
2414 /* Allocate RMA if necessary */
2415 rma_alloc_size = kvmppc_alloc_rma(&rma);
2417 if (rma_alloc_size == -1) {
2418 error_report("Unable to create RMA");
2419 exit(1);
2422 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
2423 spapr->rma_size = rma_alloc_size;
2424 } else {
2425 spapr->rma_size = node0_size;
2427 /* With KVM, we don't actually know whether KVM supports an
2428 * unbounded RMA (PR KVM) or is limited by the hash table size
2429 * (HV KVM using VRMA), so we always assume the latter
2431 * In that case, we also limit the initial allocations for RTAS
2432 * etc... to 256M since we have no way to know what the VRMA size
2433 * is going to be as it depends on the size of the hash table
2434 * isn't determined yet.
2436 if (kvm_enabled()) {
2437 spapr->vrma_adjust = 1;
2438 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
2441 /* Actually we don't support unbounded RMA anymore since we
2442 * added proper emulation of HV mode. The max we can get is
2443 * 16G which also happens to be what we configure for PAPR
2444 * mode so make sure we don't do anything bigger than that
2446 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull);
2449 if (spapr->rma_size > node0_size) {
2450 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
2451 spapr->rma_size);
2452 exit(1);
2455 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */
2456 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
2458 /* Set up Interrupt Controller before we create the VCPUs */
2459 xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal);
2461 /* Set up containers for ibm,client-architecture-support negotiated options
2463 spapr->ov5 = spapr_ovec_new();
2464 spapr->ov5_cas = spapr_ovec_new();
2466 if (smc->dr_lmb_enabled) {
2467 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY);
2468 spapr_validate_node_memory(machine, &error_fatal);
2471 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY);
2472 if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) {
2473 /* KVM and TCG always allow GTSE with radix... */
2474 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE);
2476 /* ... but not with hash (currently). */
2478 /* advertise support for dedicated HP event source to guests */
2479 if (spapr->use_hotplug_event_source) {
2480 spapr_ovec_set(spapr->ov5, OV5_HP_EVT);
2483 /* advertise support for HPT resizing */
2484 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) {
2485 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE);
2488 /* init CPUs */
2489 spapr_set_vsmt_mode(spapr, &error_fatal);
2491 spapr_init_cpus(spapr);
2493 if (kvm_enabled()) {
2494 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
2495 kvmppc_enable_logical_ci_hcalls();
2496 kvmppc_enable_set_mode_hcall();
2498 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */
2499 kvmppc_enable_clear_ref_mod_hcalls();
2502 /* allocate RAM */
2503 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
2504 machine->ram_size);
2505 memory_region_add_subregion(sysmem, 0, ram);
2507 if (rma_alloc_size && rma) {
2508 rma_region = g_new(MemoryRegion, 1);
2509 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
2510 rma_alloc_size, rma);
2511 vmstate_register_ram_global(rma_region);
2512 memory_region_add_subregion(sysmem, 0, rma_region);
2515 /* initialize hotplug memory address space */
2516 if (machine->ram_size < machine->maxram_size) {
2517 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
2519 * Limit the number of hotpluggable memory slots to half the number
2520 * slots that KVM supports, leaving the other half for PCI and other
2521 * devices. However ensure that number of slots doesn't drop below 32.
2523 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 :
2524 SPAPR_MAX_RAM_SLOTS;
2526 if (max_memslots < SPAPR_MAX_RAM_SLOTS) {
2527 max_memslots = SPAPR_MAX_RAM_SLOTS;
2529 if (machine->ram_slots > max_memslots) {
2530 error_report("Specified number of memory slots %"
2531 PRIu64" exceeds max supported %d",
2532 machine->ram_slots, max_memslots);
2533 exit(1);
2536 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
2537 SPAPR_HOTPLUG_MEM_ALIGN);
2538 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
2539 "hotplug-memory", hotplug_mem_size);
2540 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
2541 &spapr->hotplug_memory.mr);
2544 if (smc->dr_lmb_enabled) {
2545 spapr_create_lmb_dr_connectors(spapr);
2548 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
2549 if (!filename) {
2550 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
2551 exit(1);
2553 spapr->rtas_size = get_image_size(filename);
2554 if (spapr->rtas_size < 0) {
2555 error_report("Could not get size of LPAR rtas '%s'", filename);
2556 exit(1);
2558 spapr->rtas_blob = g_malloc(spapr->rtas_size);
2559 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
2560 error_report("Could not load LPAR rtas '%s'", filename);
2561 exit(1);
2563 if (spapr->rtas_size > RTAS_MAX_SIZE) {
2564 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
2565 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
2566 exit(1);
2568 g_free(filename);
2570 /* Set up RTAS event infrastructure */
2571 spapr_events_init(spapr);
2573 /* Set up the RTC RTAS interfaces */
2574 spapr_rtc_create(spapr);
2576 /* Set up VIO bus */
2577 spapr->vio_bus = spapr_vio_bus_init();
2579 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
2580 if (serial_hds[i]) {
2581 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
2585 /* We always have at least the nvram device on VIO */
2586 spapr_create_nvram(spapr);
2588 /* Set up PCI */
2589 spapr_pci_rtas_init();
2591 phb = spapr_create_phb(spapr, 0);
2593 for (i = 0; i < nb_nics; i++) {
2594 NICInfo *nd = &nd_table[i];
2596 if (!nd->model) {
2597 nd->model = g_strdup("ibmveth");
2600 if (strcmp(nd->model, "ibmveth") == 0) {
2601 spapr_vlan_create(spapr->vio_bus, nd);
2602 } else {
2603 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
2607 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
2608 spapr_vscsi_create(spapr->vio_bus);
2611 /* Graphics */
2612 if (spapr_vga_init(phb->bus, &error_fatal)) {
2613 spapr->has_graphics = true;
2614 machine->usb |= defaults_enabled() && !machine->usb_disabled;
2617 if (machine->usb) {
2618 if (smc->use_ohci_by_default) {
2619 pci_create_simple(phb->bus, -1, "pci-ohci");
2620 } else {
2621 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
2624 if (spapr->has_graphics) {
2625 USBBus *usb_bus = usb_bus_find(-1);
2627 usb_create_simple(usb_bus, "usb-kbd");
2628 usb_create_simple(usb_bus, "usb-mouse");
2632 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
2633 error_report(
2634 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
2635 MIN_RMA_SLOF);
2636 exit(1);
2639 if (kernel_filename) {
2640 uint64_t lowaddr = 0;
2642 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address,
2643 NULL, NULL, &lowaddr, NULL, 1,
2644 PPC_ELF_MACHINE, 0, 0);
2645 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) {
2646 spapr->kernel_size = load_elf(kernel_filename,
2647 translate_kernel_address, NULL, NULL,
2648 &lowaddr, NULL, 0, PPC_ELF_MACHINE,
2649 0, 0);
2650 spapr->kernel_le = spapr->kernel_size > 0;
2652 if (spapr->kernel_size < 0) {
2653 error_report("error loading %s: %s", kernel_filename,
2654 load_elf_strerror(spapr->kernel_size));
2655 exit(1);
2658 /* load initrd */
2659 if (initrd_filename) {
2660 /* Try to locate the initrd in the gap between the kernel
2661 * and the firmware. Add a bit of space just in case
2663 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size
2664 + 0x1ffff) & ~0xffff;
2665 spapr->initrd_size = load_image_targphys(initrd_filename,
2666 spapr->initrd_base,
2667 load_limit
2668 - spapr->initrd_base);
2669 if (spapr->initrd_size < 0) {
2670 error_report("could not load initial ram disk '%s'",
2671 initrd_filename);
2672 exit(1);
2677 if (bios_name == NULL) {
2678 bios_name = FW_FILE_NAME;
2680 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
2681 if (!filename) {
2682 error_report("Could not find LPAR firmware '%s'", bios_name);
2683 exit(1);
2685 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
2686 if (fw_size <= 0) {
2687 error_report("Could not load LPAR firmware '%s'", filename);
2688 exit(1);
2690 g_free(filename);
2692 /* FIXME: Should register things through the MachineState's qdev
2693 * interface, this is a legacy from the sPAPREnvironment structure
2694 * which predated MachineState but had a similar function */
2695 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
2696 register_savevm_live(NULL, "spapr/htab", -1, 1,
2697 &savevm_htab_handlers, spapr);
2699 qemu_register_boot_set(spapr_boot_set, spapr);
2701 if (kvm_enabled()) {
2702 /* to stop and start vmclock */
2703 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change,
2704 &spapr->tb);
2706 kvmppc_spapr_enable_inkernel_multitce();
2710 static int spapr_kvm_type(const char *vm_type)
2712 if (!vm_type) {
2713 return 0;
2716 if (!strcmp(vm_type, "HV")) {
2717 return 1;
2720 if (!strcmp(vm_type, "PR")) {
2721 return 2;
2724 error_report("Unknown kvm-type specified '%s'", vm_type);
2725 exit(1);
2729 * Implementation of an interface to adjust firmware path
2730 * for the bootindex property handling.
2732 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2733 DeviceState *dev)
2735 #define CAST(type, obj, name) \
2736 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2737 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2738 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2739 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON);
2741 if (d) {
2742 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2743 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2744 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2746 if (spapr) {
2748 * Replace "channel@0/disk@0,0" with "disk@8000000000000000":
2749 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun
2750 * in the top 16 bits of the 64-bit LUN
2752 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2753 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2754 (uint64_t)id << 48);
2755 } else if (virtio) {
2757 * We use SRP luns of the form 01000000 | (target << 8) | lun
2758 * in the top 32 bits of the 64-bit LUN
2759 * Note: the quote above is from SLOF and it is wrong,
2760 * the actual binding is:
2761 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun )
2763 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2764 if (d->lun >= 256) {
2765 /* Use the LUN "flat space addressing method" */
2766 id |= 0x4000;
2768 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2769 (uint64_t)id << 32);
2770 } else if (usb) {
2772 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun
2773 * in the top 32 bits of the 64-bit LUN
2775 unsigned usb_port = atoi(usb->port->path);
2776 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2777 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2778 (uint64_t)id << 32);
2783 * SLOF probes the USB devices, and if it recognizes that the device is a
2784 * storage device, it changes its name to "storage" instead of "usb-host",
2785 * and additionally adds a child node for the SCSI LUN, so the correct
2786 * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
2788 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
2789 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
2790 if (usb_host_dev_is_scsi_storage(usbdev)) {
2791 return g_strdup_printf("storage@%s/disk", usbdev->port->path);
2795 if (phb) {
2796 /* Replace "pci" with "pci@800000020000000" */
2797 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2800 if (vsc) {
2801 /* Same logic as virtio above */
2802 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun;
2803 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32);
2806 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) {
2807 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */
2808 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE);
2809 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn));
2812 return NULL;
2815 static char *spapr_get_kvm_type(Object *obj, Error **errp)
2817 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2819 return g_strdup(spapr->kvm_type);
2822 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2824 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2826 g_free(spapr->kvm_type);
2827 spapr->kvm_type = g_strdup(value);
2830 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp)
2832 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2834 return spapr->use_hotplug_event_source;
2837 static void spapr_set_modern_hotplug_events(Object *obj, bool value,
2838 Error **errp)
2840 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2842 spapr->use_hotplug_event_source = value;
2845 static char *spapr_get_resize_hpt(Object *obj, Error **errp)
2847 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2849 switch (spapr->resize_hpt) {
2850 case SPAPR_RESIZE_HPT_DEFAULT:
2851 return g_strdup("default");
2852 case SPAPR_RESIZE_HPT_DISABLED:
2853 return g_strdup("disabled");
2854 case SPAPR_RESIZE_HPT_ENABLED:
2855 return g_strdup("enabled");
2856 case SPAPR_RESIZE_HPT_REQUIRED:
2857 return g_strdup("required");
2859 g_assert_not_reached();
2862 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp)
2864 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2866 if (strcmp(value, "default") == 0) {
2867 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT;
2868 } else if (strcmp(value, "disabled") == 0) {
2869 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED;
2870 } else if (strcmp(value, "enabled") == 0) {
2871 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED;
2872 } else if (strcmp(value, "required") == 0) {
2873 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED;
2874 } else {
2875 error_setg(errp, "Bad value for \"resize-hpt\" property");
2879 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name,
2880 void *opaque, Error **errp)
2882 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
2885 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name,
2886 void *opaque, Error **errp)
2888 visit_type_uint32(v, name, (uint32_t *)opaque, errp);
2891 static void spapr_instance_init(Object *obj)
2893 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2895 spapr->htab_fd = -1;
2896 spapr->use_hotplug_event_source = true;
2897 object_property_add_str(obj, "kvm-type",
2898 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
2899 object_property_set_description(obj, "kvm-type",
2900 "Specifies the KVM virtualization mode (HV, PR)",
2901 NULL);
2902 object_property_add_bool(obj, "modern-hotplug-events",
2903 spapr_get_modern_hotplug_events,
2904 spapr_set_modern_hotplug_events,
2905 NULL);
2906 object_property_set_description(obj, "modern-hotplug-events",
2907 "Use dedicated hotplug event mechanism in"
2908 " place of standard EPOW events when possible"
2909 " (required for memory hot-unplug support)",
2910 NULL);
2912 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr,
2913 "Maximum permitted CPU compatibility mode",
2914 &error_fatal);
2916 object_property_add_str(obj, "resize-hpt",
2917 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL);
2918 object_property_set_description(obj, "resize-hpt",
2919 "Resizing of the Hash Page Table (enabled, disabled, required)",
2920 NULL);
2921 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt,
2922 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort);
2923 object_property_set_description(obj, "vsmt",
2924 "Virtual SMT: KVM behaves as if this were"
2925 " the host's SMT mode", &error_abort);
2928 static void spapr_machine_finalizefn(Object *obj)
2930 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2932 g_free(spapr->kvm_type);
2935 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
2937 cpu_synchronize_state(cs);
2938 ppc_cpu_do_system_reset(cs);
2941 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2943 CPUState *cs;
2945 CPU_FOREACH(cs) {
2946 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
2950 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size,
2951 uint32_t node, bool dedicated_hp_event_source,
2952 Error **errp)
2954 sPAPRDRConnector *drc;
2955 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2956 int i, fdt_offset, fdt_size;
2957 void *fdt;
2958 uint64_t addr = addr_start;
2959 bool hotplugged = spapr_drc_hotplugged(dev);
2960 Error *local_err = NULL;
2962 for (i = 0; i < nr_lmbs; i++) {
2963 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
2964 addr / SPAPR_MEMORY_BLOCK_SIZE);
2965 g_assert(drc);
2967 fdt = create_device_tree(&fdt_size);
2968 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2969 SPAPR_MEMORY_BLOCK_SIZE);
2971 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err);
2972 if (local_err) {
2973 while (addr > addr_start) {
2974 addr -= SPAPR_MEMORY_BLOCK_SIZE;
2975 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
2976 addr / SPAPR_MEMORY_BLOCK_SIZE);
2977 spapr_drc_detach(drc);
2979 g_free(fdt);
2980 error_propagate(errp, local_err);
2981 return;
2983 if (!hotplugged) {
2984 spapr_drc_reset(drc);
2986 addr += SPAPR_MEMORY_BLOCK_SIZE;
2988 /* send hotplug notification to the
2989 * guest only in case of hotplugged memory
2991 if (hotplugged) {
2992 if (dedicated_hp_event_source) {
2993 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
2994 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
2995 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
2996 nr_lmbs,
2997 spapr_drc_index(drc));
2998 } else {
2999 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB,
3000 nr_lmbs);
3005 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3006 uint32_t node, Error **errp)
3008 Error *local_err = NULL;
3009 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
3010 PCDIMMDevice *dimm = PC_DIMM(dev);
3011 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3012 MemoryRegion *mr;
3013 uint64_t align, size, addr;
3015 mr = ddc->get_memory_region(dimm, &local_err);
3016 if (local_err) {
3017 goto out;
3019 align = memory_region_get_alignment(mr);
3020 size = memory_region_size(mr);
3022 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
3023 if (local_err) {
3024 goto out;
3027 addr = object_property_get_uint(OBJECT(dimm),
3028 PC_DIMM_ADDR_PROP, &local_err);
3029 if (local_err) {
3030 goto out_unplug;
3033 spapr_add_lmbs(dev, addr, size, node,
3034 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT),
3035 &local_err);
3036 if (local_err) {
3037 goto out_unplug;
3040 return;
3042 out_unplug:
3043 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
3044 out:
3045 error_propagate(errp, local_err);
3048 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3049 Error **errp)
3051 PCDIMMDevice *dimm = PC_DIMM(dev);
3052 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3053 MemoryRegion *mr;
3054 uint64_t size;
3055 char *mem_dev;
3057 mr = ddc->get_memory_region(dimm, errp);
3058 if (!mr) {
3059 return;
3061 size = memory_region_size(mr);
3063 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
3064 error_setg(errp, "Hotplugged memory size must be a multiple of "
3065 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
3066 return;
3069 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL);
3070 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) {
3071 error_setg(errp, "Memory backend has bad page size. "
3072 "Use 'memory-backend-file' with correct mem-path.");
3073 goto out;
3076 out:
3077 g_free(mem_dev);
3080 struct sPAPRDIMMState {
3081 PCDIMMDevice *dimm;
3082 uint32_t nr_lmbs;
3083 QTAILQ_ENTRY(sPAPRDIMMState) next;
3086 static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s,
3087 PCDIMMDevice *dimm)
3089 sPAPRDIMMState *dimm_state = NULL;
3091 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) {
3092 if (dimm_state->dimm == dimm) {
3093 break;
3096 return dimm_state;
3099 static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr,
3100 uint32_t nr_lmbs,
3101 PCDIMMDevice *dimm)
3103 sPAPRDIMMState *ds = NULL;
3106 * If this request is for a DIMM whose removal had failed earlier
3107 * (due to guest's refusal to remove the LMBs), we would have this
3108 * dimm already in the pending_dimm_unplugs list. In that
3109 * case don't add again.
3111 ds = spapr_pending_dimm_unplugs_find(spapr, dimm);
3112 if (!ds) {
3113 ds = g_malloc0(sizeof(sPAPRDIMMState));
3114 ds->nr_lmbs = nr_lmbs;
3115 ds->dimm = dimm;
3116 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next);
3118 return ds;
3121 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr,
3122 sPAPRDIMMState *dimm_state)
3124 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next);
3125 g_free(dimm_state);
3128 static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms,
3129 PCDIMMDevice *dimm)
3131 sPAPRDRConnector *drc;
3132 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3133 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort);
3134 uint64_t size = memory_region_size(mr);
3135 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3136 uint32_t avail_lmbs = 0;
3137 uint64_t addr_start, addr;
3138 int i;
3140 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3141 &error_abort);
3143 addr = addr_start;
3144 for (i = 0; i < nr_lmbs; i++) {
3145 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3146 addr / SPAPR_MEMORY_BLOCK_SIZE);
3147 g_assert(drc);
3148 if (drc->dev) {
3149 avail_lmbs++;
3151 addr += SPAPR_MEMORY_BLOCK_SIZE;
3154 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm);
3157 /* Callback to be called during DRC release. */
3158 void spapr_lmb_release(DeviceState *dev)
3160 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_hotplug_handler(dev));
3161 PCDIMMDevice *dimm = PC_DIMM(dev);
3162 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3163 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort);
3164 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev));
3166 /* This information will get lost if a migration occurs
3167 * during the unplug process. In this case recover it. */
3168 if (ds == NULL) {
3169 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev));
3170 g_assert(ds);
3171 /* The DRC being examined by the caller at least must be counted */
3172 g_assert(ds->nr_lmbs);
3175 if (--ds->nr_lmbs) {
3176 return;
3180 * Now that all the LMBs have been removed by the guest, call the
3181 * pc-dimm unplug handler to cleanup up the pc-dimm device.
3183 pc_dimm_memory_unplug(dev, &spapr->hotplug_memory, mr);
3184 object_unparent(OBJECT(dev));
3185 spapr_pending_dimm_unplugs_remove(spapr, ds);
3188 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev,
3189 DeviceState *dev, Error **errp)
3191 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev);
3192 Error *local_err = NULL;
3193 PCDIMMDevice *dimm = PC_DIMM(dev);
3194 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
3195 MemoryRegion *mr;
3196 uint32_t nr_lmbs;
3197 uint64_t size, addr_start, addr;
3198 int i;
3199 sPAPRDRConnector *drc;
3201 mr = ddc->get_memory_region(dimm, &local_err);
3202 if (local_err) {
3203 goto out;
3205 size = memory_region_size(mr);
3206 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE;
3208 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP,
3209 &local_err);
3210 if (local_err) {
3211 goto out;
3215 * An existing pending dimm state for this DIMM means that there is an
3216 * unplug operation in progress, waiting for the spapr_lmb_release
3217 * callback to complete the job (BQL can't cover that far). In this case,
3218 * bail out to avoid detaching DRCs that were already released.
3220 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) {
3221 error_setg(&local_err,
3222 "Memory unplug already in progress for device %s",
3223 dev->id);
3224 goto out;
3227 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm);
3229 addr = addr_start;
3230 for (i = 0; i < nr_lmbs; i++) {
3231 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3232 addr / SPAPR_MEMORY_BLOCK_SIZE);
3233 g_assert(drc);
3235 spapr_drc_detach(drc);
3236 addr += SPAPR_MEMORY_BLOCK_SIZE;
3239 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB,
3240 addr_start / SPAPR_MEMORY_BLOCK_SIZE);
3241 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB,
3242 nr_lmbs, spapr_drc_index(drc));
3243 out:
3244 error_propagate(errp, local_err);
3247 static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
3248 sPAPRMachineState *spapr)
3250 PowerPCCPU *cpu = POWERPC_CPU(cs);
3251 DeviceClass *dc = DEVICE_GET_CLASS(cs);
3252 int id = spapr_get_vcpu_id(cpu);
3253 void *fdt;
3254 int offset, fdt_size;
3255 char *nodename;
3257 fdt = create_device_tree(&fdt_size);
3258 nodename = g_strdup_printf("%s@%x", dc->fw_name, id);
3259 offset = fdt_add_subnode(fdt, 0, nodename);
3261 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
3262 g_free(nodename);
3264 *fdt_offset = offset;
3265 return fdt;
3268 /* Callback to be called during DRC release. */
3269 void spapr_core_release(DeviceState *dev)
3271 MachineState *ms = MACHINE(qdev_get_hotplug_handler(dev));
3272 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);
3273 CPUCore *cc = CPU_CORE(dev);
3274 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL);
3276 if (smc->pre_2_10_has_unused_icps) {
3277 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
3278 int i;
3280 for (i = 0; i < cc->nr_threads; i++) {
3281 CPUState *cs = CPU(sc->threads[i]);
3283 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index);
3287 assert(core_slot);
3288 core_slot->cpu = NULL;
3289 object_unparent(OBJECT(dev));
3292 static
3293 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev,
3294 Error **errp)
3296 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3297 int index;
3298 sPAPRDRConnector *drc;
3299 CPUCore *cc = CPU_CORE(dev);
3301 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) {
3302 error_setg(errp, "Unable to find CPU core with core-id: %d",
3303 cc->core_id);
3304 return;
3306 if (index == 0) {
3307 error_setg(errp, "Boot CPU core may not be unplugged");
3308 return;
3311 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU,
3312 spapr_vcpu_id(spapr, cc->core_id));
3313 g_assert(drc);
3315 spapr_drc_detach(drc);
3317 spapr_hotplug_req_remove_by_index(drc);
3320 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3321 Error **errp)
3323 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
3324 MachineClass *mc = MACHINE_GET_CLASS(spapr);
3325 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3326 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
3327 CPUCore *cc = CPU_CORE(dev);
3328 CPUState *cs = CPU(core->threads[0]);
3329 sPAPRDRConnector *drc;
3330 Error *local_err = NULL;
3331 CPUArchId *core_slot;
3332 int index;
3333 bool hotplugged = spapr_drc_hotplugged(dev);
3335 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3336 if (!core_slot) {
3337 error_setg(errp, "Unable to find CPU core with core-id: %d",
3338 cc->core_id);
3339 return;
3341 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU,
3342 spapr_vcpu_id(spapr, cc->core_id));
3344 g_assert(drc || !mc->has_hotpluggable_cpus);
3346 if (drc) {
3347 void *fdt;
3348 int fdt_offset;
3350 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr);
3352 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err);
3353 if (local_err) {
3354 g_free(fdt);
3355 error_propagate(errp, local_err);
3356 return;
3359 if (hotplugged) {
3361 * Send hotplug notification interrupt to the guest only
3362 * in case of hotplugged CPUs.
3364 spapr_hotplug_req_add_by_index(drc);
3365 } else {
3366 spapr_drc_reset(drc);
3370 core_slot->cpu = OBJECT(dev);
3372 if (smc->pre_2_10_has_unused_icps) {
3373 int i;
3375 for (i = 0; i < cc->nr_threads; i++) {
3376 cs = CPU(core->threads[i]);
3377 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index);
3382 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
3383 Error **errp)
3385 MachineState *machine = MACHINE(OBJECT(hotplug_dev));
3386 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
3387 Error *local_err = NULL;
3388 CPUCore *cc = CPU_CORE(dev);
3389 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type);
3390 const char *type = object_get_typename(OBJECT(dev));
3391 CPUArchId *core_slot;
3392 int index;
3394 if (dev->hotplugged && !mc->has_hotpluggable_cpus) {
3395 error_setg(&local_err, "CPU hotplug not supported for this machine");
3396 goto out;
3399 if (strcmp(base_core_type, type)) {
3400 error_setg(&local_err, "CPU core type should be %s", base_core_type);
3401 goto out;
3404 if (cc->core_id % smp_threads) {
3405 error_setg(&local_err, "invalid core id %d", cc->core_id);
3406 goto out;
3410 * In general we should have homogeneous threads-per-core, but old
3411 * (pre hotplug support) machine types allow the last core to have
3412 * reduced threads as a compatibility hack for when we allowed
3413 * total vcpus not a multiple of threads-per-core.
3415 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) {
3416 error_setg(&local_err, "invalid nr-threads %d, must be %d",
3417 cc->nr_threads, smp_threads);
3418 goto out;
3421 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index);
3422 if (!core_slot) {
3423 error_setg(&local_err, "core id %d out of range", cc->core_id);
3424 goto out;
3427 if (core_slot->cpu) {
3428 error_setg(&local_err, "core %d already populated", cc->core_id);
3429 goto out;
3432 numa_cpu_pre_plug(core_slot, dev, &local_err);
3434 out:
3435 error_propagate(errp, local_err);
3438 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
3439 DeviceState *dev, Error **errp)
3441 MachineState *ms = MACHINE(hotplug_dev);
3442 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms);
3444 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3445 int node;
3447 if (!smc->dr_lmb_enabled) {
3448 error_setg(errp, "Memory hotplug not supported for this machine");
3449 return;
3451 node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
3452 if (*errp) {
3453 return;
3455 if (node < 0 || node >= MAX_NODES) {
3456 error_setg(errp, "Invaild node %d", node);
3457 return;
3461 * Currently PowerPC kernel doesn't allow hot-adding memory to
3462 * memory-less node, but instead will silently add the memory
3463 * to the first node that has some memory. This causes two
3464 * unexpected behaviours for the user.
3466 * - Memory gets hotplugged to a different node than what the user
3467 * specified.
3468 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs
3469 * to memory-less node, a reboot will set things accordingly
3470 * and the previously hotplugged memory now ends in the right node.
3471 * This appears as if some memory moved from one node to another.
3473 * So until kernel starts supporting memory hotplug to memory-less
3474 * nodes, just prevent such attempts upfront in QEMU.
3476 if (nb_numa_nodes && !numa_info[node].node_mem) {
3477 error_setg(errp, "Can't hotplug memory to memory-less node %d",
3478 node);
3479 return;
3482 spapr_memory_plug(hotplug_dev, dev, node, errp);
3483 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3484 spapr_core_plug(hotplug_dev, dev, errp);
3488 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev,
3489 DeviceState *dev, Error **errp)
3491 sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev));
3492 MachineClass *mc = MACHINE_GET_CLASS(sms);
3494 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3495 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) {
3496 spapr_memory_unplug_request(hotplug_dev, dev, errp);
3497 } else {
3498 /* NOTE: this means there is a window after guest reset, prior to
3499 * CAS negotiation, where unplug requests will fail due to the
3500 * capability not being detected yet. This is a bit different than
3501 * the case with PCI unplug, where the events will be queued and
3502 * eventually handled by the guest after boot
3504 error_setg(errp, "Memory hot unplug not supported for this guest");
3506 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3507 if (!mc->has_hotpluggable_cpus) {
3508 error_setg(errp, "CPU hot unplug not supported on this machine");
3509 return;
3511 spapr_core_unplug_request(hotplug_dev, dev, errp);
3515 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev,
3516 DeviceState *dev, Error **errp)
3518 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3519 spapr_memory_pre_plug(hotplug_dev, dev, errp);
3520 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3521 spapr_core_pre_plug(hotplug_dev, dev, errp);
3525 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine,
3526 DeviceState *dev)
3528 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
3529 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) {
3530 return HOTPLUG_HANDLER(machine);
3532 return NULL;
3535 static CpuInstanceProperties
3536 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index)
3538 CPUArchId *core_slot;
3539 MachineClass *mc = MACHINE_GET_CLASS(machine);
3541 /* make sure possible_cpu are intialized */
3542 mc->possible_cpu_arch_ids(machine);
3543 /* get CPU core slot containing thread that matches cpu_index */
3544 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL);
3545 assert(core_slot);
3546 return core_slot->props;
3549 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx)
3551 return idx / smp_cores % nb_numa_nodes;
3554 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine)
3556 int i;
3557 const char *core_type;
3558 int spapr_max_cores = max_cpus / smp_threads;
3559 MachineClass *mc = MACHINE_GET_CLASS(machine);
3561 if (!mc->has_hotpluggable_cpus) {
3562 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
3564 if (machine->possible_cpus) {
3565 assert(machine->possible_cpus->len == spapr_max_cores);
3566 return machine->possible_cpus;
3569 core_type = spapr_get_cpu_core_type(machine->cpu_type);
3570 if (!core_type) {
3571 error_report("Unable to find sPAPR CPU Core definition");
3572 exit(1);
3575 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
3576 sizeof(CPUArchId) * spapr_max_cores);
3577 machine->possible_cpus->len = spapr_max_cores;
3578 for (i = 0; i < machine->possible_cpus->len; i++) {
3579 int core_id = i * smp_threads;
3581 machine->possible_cpus->cpus[i].type = core_type;
3582 machine->possible_cpus->cpus[i].vcpus_count = smp_threads;
3583 machine->possible_cpus->cpus[i].arch_id = core_id;
3584 machine->possible_cpus->cpus[i].props.has_core_id = true;
3585 machine->possible_cpus->cpus[i].props.core_id = core_id;
3587 return machine->possible_cpus;
3590 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index,
3591 uint64_t *buid, hwaddr *pio,
3592 hwaddr *mmio32, hwaddr *mmio64,
3593 unsigned n_dma, uint32_t *liobns, Error **errp)
3596 * New-style PHB window placement.
3598 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window
3599 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO
3600 * windows.
3602 * Some guest kernels can't work with MMIO windows above 1<<46
3603 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB
3605 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each
3606 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the
3607 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the
3608 * 1TiB 64-bit MMIO windows for each PHB.
3610 const uint64_t base_buid = 0x800000020000000ULL;
3611 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
3612 SPAPR_PCI_MEM64_WIN_SIZE - 1)
3613 int i;
3615 /* Sanity check natural alignments */
3616 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
3617 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0);
3618 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0);
3619 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0);
3620 /* Sanity check bounds */
3621 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) >
3622 SPAPR_PCI_MEM32_WIN_SIZE);
3623 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) >
3624 SPAPR_PCI_MEM64_WIN_SIZE);
3626 if (index >= SPAPR_MAX_PHBS) {
3627 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)",
3628 SPAPR_MAX_PHBS - 1);
3629 return;
3632 *buid = base_buid + index;
3633 for (i = 0; i < n_dma; ++i) {
3634 liobns[i] = SPAPR_PCI_LIOBN(index, i);
3637 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE;
3638 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE;
3639 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE;
3642 static ICSState *spapr_ics_get(XICSFabric *dev, int irq)
3644 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3646 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL;
3649 static void spapr_ics_resend(XICSFabric *dev)
3651 sPAPRMachineState *spapr = SPAPR_MACHINE(dev);
3653 ics_resend(spapr->ics);
3656 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id)
3658 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id);
3660 return cpu ? ICP(cpu->intc) : NULL;
3663 #define ICS_IRQ_FREE(ics, srcno) \
3664 (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
3666 static int ics_find_free_block(ICSState *ics, int num, int alignnum)
3668 int first, i;
3670 for (first = 0; first < ics->nr_irqs; first += alignnum) {
3671 if (num > (ics->nr_irqs - first)) {
3672 return -1;
3674 for (i = first; i < first + num; ++i) {
3675 if (!ICS_IRQ_FREE(ics, i)) {
3676 break;
3679 if (i == (first + num)) {
3680 return first;
3684 return -1;
3688 * Allocate the IRQ number and set the IRQ type, LSI or MSI
3690 static void spapr_irq_set_lsi(sPAPRMachineState *spapr, int irq, bool lsi)
3692 ics_set_irq_type(spapr->ics, irq - spapr->ics->offset, lsi);
3695 int spapr_irq_alloc(sPAPRMachineState *spapr, int irq_hint, bool lsi,
3696 Error **errp)
3698 ICSState *ics = spapr->ics;
3699 int irq;
3701 if (!ics) {
3702 return -1;
3704 if (irq_hint) {
3705 if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) {
3706 error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint);
3707 return -1;
3709 irq = irq_hint;
3710 } else {
3711 irq = ics_find_free_block(ics, 1, 1);
3712 if (irq < 0) {
3713 error_setg(errp, "can't allocate IRQ: no IRQ left");
3714 return -1;
3716 irq += ics->offset;
3719 spapr_irq_set_lsi(spapr, irq, lsi);
3720 trace_spapr_irq_alloc(irq);
3722 return irq;
3726 * Allocate block of consecutive IRQs, and return the number of the first IRQ in
3727 * the block. If align==true, aligns the first IRQ number to num.
3729 int spapr_irq_alloc_block(sPAPRMachineState *spapr, int num, bool lsi,
3730 bool align, Error **errp)
3732 ICSState *ics = spapr->ics;
3733 int i, first = -1;
3735 if (!ics) {
3736 return -1;
3740 * MSIMesage::data is used for storing VIRQ so
3741 * it has to be aligned to num to support multiple
3742 * MSI vectors. MSI-X is not affected by this.
3743 * The hint is used for the first IRQ, the rest should
3744 * be allocated continuously.
3746 if (align) {
3747 assert((num == 1) || (num == 2) || (num == 4) ||
3748 (num == 8) || (num == 16) || (num == 32));
3749 first = ics_find_free_block(ics, num, num);
3750 } else {
3751 first = ics_find_free_block(ics, num, 1);
3753 if (first < 0) {
3754 error_setg(errp, "can't find a free %d-IRQ block", num);
3755 return -1;
3758 first += ics->offset;
3759 for (i = first; i < first + num; ++i) {
3760 spapr_irq_set_lsi(spapr, i, lsi);
3763 trace_spapr_irq_alloc_block(first, num, lsi, align);
3765 return first;
3768 void spapr_irq_free(sPAPRMachineState *spapr, int irq, int num)
3770 ICSState *ics = spapr->ics;
3771 int srcno = irq - ics->offset;
3772 int i;
3774 if (ics_valid_irq(ics, irq)) {
3775 trace_spapr_irq_free(0, irq, num);
3776 for (i = srcno; i < srcno + num; ++i) {
3777 if (ICS_IRQ_FREE(ics, i)) {
3778 trace_spapr_irq_free_warn(0, i + ics->offset);
3780 memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
3785 qemu_irq spapr_qirq(sPAPRMachineState *spapr, int irq)
3787 ICSState *ics = spapr->ics;
3789 if (ics_valid_irq(ics, irq)) {
3790 return ics->qirqs[irq - ics->offset];
3793 return NULL;
3796 static void spapr_pic_print_info(InterruptStatsProvider *obj,
3797 Monitor *mon)
3799 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
3800 CPUState *cs;
3802 CPU_FOREACH(cs) {
3803 PowerPCCPU *cpu = POWERPC_CPU(cs);
3805 icp_pic_print_info(ICP(cpu->intc), mon);
3808 ics_pic_print_info(spapr->ics, mon);
3811 int spapr_get_vcpu_id(PowerPCCPU *cpu)
3813 return cpu->vcpu_id;
3816 void spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp)
3818 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
3819 int vcpu_id;
3821 vcpu_id = spapr_vcpu_id(spapr, cpu_index);
3823 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) {
3824 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id);
3825 error_append_hint(errp, "Adjust the number of cpus to %d "
3826 "or try to raise the number of threads per core\n",
3827 vcpu_id * smp_threads / spapr->vsmt);
3828 return;
3831 cpu->vcpu_id = vcpu_id;
3834 PowerPCCPU *spapr_find_cpu(int vcpu_id)
3836 CPUState *cs;
3838 CPU_FOREACH(cs) {
3839 PowerPCCPU *cpu = POWERPC_CPU(cs);
3841 if (spapr_get_vcpu_id(cpu) == vcpu_id) {
3842 return cpu;
3846 return NULL;
3849 static void spapr_machine_class_init(ObjectClass *oc, void *data)
3851 MachineClass *mc = MACHINE_CLASS(oc);
3852 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
3853 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
3854 NMIClass *nc = NMI_CLASS(oc);
3855 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
3856 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
3857 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
3858 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
3860 mc->desc = "pSeries Logical Partition (PAPR compliant)";
3863 * We set up the default / latest behaviour here. The class_init
3864 * functions for the specific versioned machine types can override
3865 * these details for backwards compatibility
3867 mc->init = spapr_machine_init;
3868 mc->reset = spapr_machine_reset;
3869 mc->block_default_type = IF_SCSI;
3870 mc->max_cpus = 1024;
3871 mc->no_parallel = 1;
3872 mc->default_boot_order = "";
3873 mc->default_ram_size = 512 * M_BYTE;
3874 mc->kvm_type = spapr_kvm_type;
3875 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE);
3876 mc->pci_allow_0_address = true;
3877 mc->get_hotplug_handler = spapr_get_hotplug_handler;
3878 hc->pre_plug = spapr_machine_device_pre_plug;
3879 hc->plug = spapr_machine_device_plug;
3880 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props;
3881 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id;
3882 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids;
3883 hc->unplug_request = spapr_machine_device_unplug_request;
3885 smc->dr_lmb_enabled = true;
3886 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
3887 mc->has_hotpluggable_cpus = true;
3888 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED;
3889 fwc->get_dev_path = spapr_get_fw_dev_path;
3890 nc->nmi_monitor_handler = spapr_nmi;
3891 smc->phb_placement = spapr_phb_placement;
3892 vhc->hypercall = emulate_spapr_hypercall;
3893 vhc->hpt_mask = spapr_hpt_mask;
3894 vhc->map_hptes = spapr_map_hptes;
3895 vhc->unmap_hptes = spapr_unmap_hptes;
3896 vhc->store_hpte = spapr_store_hpte;
3897 vhc->get_patbe = spapr_get_patbe;
3898 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr;
3899 xic->ics_get = spapr_ics_get;
3900 xic->ics_resend = spapr_ics_resend;
3901 xic->icp_get = spapr_icp_get;
3902 ispc->print_info = spapr_pic_print_info;
3903 /* Force NUMA node memory size to be a multiple of
3904 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity
3905 * in which LMBs are represented and hot-added
3907 mc->numa_mem_align_shift = 28;
3909 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF;
3910 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON;
3911 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON;
3912 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN;
3913 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN;
3914 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN;
3915 spapr_caps_add_properties(smc, &error_abort);
3918 static const TypeInfo spapr_machine_info = {
3919 .name = TYPE_SPAPR_MACHINE,
3920 .parent = TYPE_MACHINE,
3921 .abstract = true,
3922 .instance_size = sizeof(sPAPRMachineState),
3923 .instance_init = spapr_instance_init,
3924 .instance_finalize = spapr_machine_finalizefn,
3925 .class_size = sizeof(sPAPRMachineClass),
3926 .class_init = spapr_machine_class_init,
3927 .interfaces = (InterfaceInfo[]) {
3928 { TYPE_FW_PATH_PROVIDER },
3929 { TYPE_NMI },
3930 { TYPE_HOTPLUG_HANDLER },
3931 { TYPE_PPC_VIRTUAL_HYPERVISOR },
3932 { TYPE_XICS_FABRIC },
3933 { TYPE_INTERRUPT_STATS_PROVIDER },
3938 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
3939 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
3940 void *data) \
3942 MachineClass *mc = MACHINE_CLASS(oc); \
3943 spapr_machine_##suffix##_class_options(mc); \
3944 if (latest) { \
3945 mc->alias = "pseries"; \
3946 mc->is_default = 1; \
3949 static void spapr_machine_##suffix##_instance_init(Object *obj) \
3951 MachineState *machine = MACHINE(obj); \
3952 spapr_machine_##suffix##_instance_options(machine); \
3954 static const TypeInfo spapr_machine_##suffix##_info = { \
3955 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
3956 .parent = TYPE_SPAPR_MACHINE, \
3957 .class_init = spapr_machine_##suffix##_class_init, \
3958 .instance_init = spapr_machine_##suffix##_instance_init, \
3959 }; \
3960 static void spapr_machine_register_##suffix(void) \
3962 type_register(&spapr_machine_##suffix##_info); \
3964 type_init(spapr_machine_register_##suffix)
3967 * pseries-2.12
3969 static void spapr_machine_2_12_instance_options(MachineState *machine)
3973 static void spapr_machine_2_12_class_options(MachineClass *mc)
3975 /* Defaults for the latest behaviour inherited from the base class */
3978 DEFINE_SPAPR_MACHINE(2_12, "2.12", true);
3981 * pseries-2.11
3983 #define SPAPR_COMPAT_2_11 \
3984 HW_COMPAT_2_11
3986 static void spapr_machine_2_11_instance_options(MachineState *machine)
3988 spapr_machine_2_12_instance_options(machine);
3991 static void spapr_machine_2_11_class_options(MachineClass *mc)
3993 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
3995 spapr_machine_2_12_class_options(mc);
3996 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON;
3997 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_11);
4000 DEFINE_SPAPR_MACHINE(2_11, "2.11", false);
4003 * pseries-2.10
4005 #define SPAPR_COMPAT_2_10 \
4006 HW_COMPAT_2_10
4008 static void spapr_machine_2_10_instance_options(MachineState *machine)
4010 spapr_machine_2_11_instance_options(machine);
4013 static void spapr_machine_2_10_class_options(MachineClass *mc)
4015 spapr_machine_2_11_class_options(mc);
4016 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_10);
4019 DEFINE_SPAPR_MACHINE(2_10, "2.10", false);
4022 * pseries-2.9
4024 #define SPAPR_COMPAT_2_9 \
4025 HW_COMPAT_2_9 \
4027 .driver = TYPE_POWERPC_CPU, \
4028 .property = "pre-2.10-migration", \
4029 .value = "on", \
4030 }, \
4032 static void spapr_machine_2_9_instance_options(MachineState *machine)
4034 spapr_machine_2_10_instance_options(machine);
4037 static void spapr_machine_2_9_class_options(MachineClass *mc)
4039 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4041 spapr_machine_2_10_class_options(mc);
4042 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9);
4043 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram;
4044 smc->pre_2_10_has_unused_icps = true;
4045 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED;
4048 DEFINE_SPAPR_MACHINE(2_9, "2.9", false);
4051 * pseries-2.8
4053 #define SPAPR_COMPAT_2_8 \
4054 HW_COMPAT_2_8 \
4056 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4057 .property = "pcie-extended-configuration-space", \
4058 .value = "off", \
4061 static void spapr_machine_2_8_instance_options(MachineState *machine)
4063 spapr_machine_2_9_instance_options(machine);
4066 static void spapr_machine_2_8_class_options(MachineClass *mc)
4068 spapr_machine_2_9_class_options(mc);
4069 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8);
4070 mc->numa_mem_align_shift = 23;
4073 DEFINE_SPAPR_MACHINE(2_8, "2.8", false);
4076 * pseries-2.7
4078 #define SPAPR_COMPAT_2_7 \
4079 HW_COMPAT_2_7 \
4081 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4082 .property = "mem_win_size", \
4083 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\
4084 }, \
4086 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4087 .property = "mem64_win_size", \
4088 .value = "0", \
4089 }, \
4091 .driver = TYPE_POWERPC_CPU, \
4092 .property = "pre-2.8-migration", \
4093 .value = "on", \
4094 }, \
4096 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \
4097 .property = "pre-2.8-migration", \
4098 .value = "on", \
4101 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index,
4102 uint64_t *buid, hwaddr *pio,
4103 hwaddr *mmio32, hwaddr *mmio64,
4104 unsigned n_dma, uint32_t *liobns, Error **errp)
4106 /* Legacy PHB placement for pseries-2.7 and earlier machine types */
4107 const uint64_t base_buid = 0x800000020000000ULL;
4108 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */
4109 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */
4110 const hwaddr pio_offset = 0x80000000; /* 2 GiB */
4111 const uint32_t max_index = 255;
4112 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */
4114 uint64_t ram_top = MACHINE(spapr)->ram_size;
4115 hwaddr phb0_base, phb_base;
4116 int i;
4118 /* Do we have hotpluggable memory? */
4119 if (MACHINE(spapr)->maxram_size > ram_top) {
4120 /* Can't just use maxram_size, because there may be an
4121 * alignment gap between normal and hotpluggable memory
4122 * regions */
4123 ram_top = spapr->hotplug_memory.base +
4124 memory_region_size(&spapr->hotplug_memory.mr);
4127 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment);
4129 if (index > max_index) {
4130 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
4131 max_index);
4132 return;
4135 *buid = base_buid + index;
4136 for (i = 0; i < n_dma; ++i) {
4137 liobns[i] = SPAPR_PCI_LIOBN(index, i);
4140 phb_base = phb0_base + index * phb_spacing;
4141 *pio = phb_base + pio_offset;
4142 *mmio32 = phb_base + mmio_offset;
4144 * We don't set the 64-bit MMIO window, relying on the PHB's
4145 * fallback behaviour of automatically splitting a large "32-bit"
4146 * window into contiguous 32-bit and 64-bit windows
4150 static void spapr_machine_2_7_instance_options(MachineState *machine)
4152 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
4154 spapr_machine_2_8_instance_options(machine);
4155 spapr->use_hotplug_event_source = false;
4158 static void spapr_machine_2_7_class_options(MachineClass *mc)
4160 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4162 spapr_machine_2_8_class_options(mc);
4163 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3");
4164 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7);
4165 smc->phb_placement = phb_placement_2_7;
4168 DEFINE_SPAPR_MACHINE(2_7, "2.7", false);
4171 * pseries-2.6
4173 #define SPAPR_COMPAT_2_6 \
4174 HW_COMPAT_2_6 \
4176 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
4177 .property = "ddw",\
4178 .value = stringify(off),\
4181 static void spapr_machine_2_6_instance_options(MachineState *machine)
4183 spapr_machine_2_7_instance_options(machine);
4186 static void spapr_machine_2_6_class_options(MachineClass *mc)
4188 spapr_machine_2_7_class_options(mc);
4189 mc->has_hotpluggable_cpus = false;
4190 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6);
4193 DEFINE_SPAPR_MACHINE(2_6, "2.6", false);
4196 * pseries-2.5
4198 #define SPAPR_COMPAT_2_5 \
4199 HW_COMPAT_2_5 \
4201 .driver = "spapr-vlan", \
4202 .property = "use-rx-buffer-pools", \
4203 .value = "off", \
4206 static void spapr_machine_2_5_instance_options(MachineState *machine)
4208 spapr_machine_2_6_instance_options(machine);
4211 static void spapr_machine_2_5_class_options(MachineClass *mc)
4213 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4215 spapr_machine_2_6_class_options(mc);
4216 smc->use_ohci_by_default = true;
4217 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
4220 DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
4223 * pseries-2.4
4225 #define SPAPR_COMPAT_2_4 \
4226 HW_COMPAT_2_4
4228 static void spapr_machine_2_4_instance_options(MachineState *machine)
4230 spapr_machine_2_5_instance_options(machine);
4233 static void spapr_machine_2_4_class_options(MachineClass *mc)
4235 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
4237 spapr_machine_2_5_class_options(mc);
4238 smc->dr_lmb_enabled = false;
4239 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
4242 DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
4245 * pseries-2.3
4247 #define SPAPR_COMPAT_2_3 \
4248 HW_COMPAT_2_3 \
4250 .driver = "spapr-pci-host-bridge",\
4251 .property = "dynamic-reconfiguration",\
4252 .value = "off",\
4255 static void spapr_machine_2_3_instance_options(MachineState *machine)
4257 spapr_machine_2_4_instance_options(machine);
4260 static void spapr_machine_2_3_class_options(MachineClass *mc)
4262 spapr_machine_2_4_class_options(mc);
4263 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
4265 DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
4268 * pseries-2.2
4271 #define SPAPR_COMPAT_2_2 \
4272 HW_COMPAT_2_2 \
4274 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
4275 .property = "mem_win_size",\
4276 .value = "0x20000000",\
4279 static void spapr_machine_2_2_instance_options(MachineState *machine)
4281 spapr_machine_2_3_instance_options(machine);
4282 machine->suppress_vmdesc = true;
4285 static void spapr_machine_2_2_class_options(MachineClass *mc)
4287 spapr_machine_2_3_class_options(mc);
4288 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
4290 DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
4293 * pseries-2.1
4295 #define SPAPR_COMPAT_2_1 \
4296 HW_COMPAT_2_1
4298 static void spapr_machine_2_1_instance_options(MachineState *machine)
4300 spapr_machine_2_2_instance_options(machine);
4303 static void spapr_machine_2_1_class_options(MachineClass *mc)
4305 spapr_machine_2_2_class_options(mc);
4306 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
4308 DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
4310 static void spapr_machine_register_types(void)
4312 type_register_static(&spapr_machine_info);
4315 type_init(spapr_machine_register_types)