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Merge tag 'v2.4.0-rc3'
[qemu/ar7.git] / target-mips / translate_init.c
blob9304e746b4ef963f7d4f1a4e1d73dfc7a5134e21
1 /*
2 * MIPS emulation for qemu: CPU initialisation routines.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2007 Herve Poussineau
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* CPU / CPU family specific config register values. */
22
23 /* Have config1, uncached coherency */
24 #define MIPS_CONFIG0 \
25 ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
26
27 /* Have config2, no coprocessor2 attached, no MDMX support attached,
28 no performance counters, watch registers present,
29 no code compression, EJTAG present, no FPU */
30 #define MIPS_CONFIG1 \
31 ((1U << CP0C1_M) | \
32 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
33 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
34 (0 << CP0C1_FP))
35
36 /* Have config3, no tertiary/secondary caches implemented */
37 #define MIPS_CONFIG2 \
38 ((1U << CP0C2_M))
39
40 /* No config4, no DSP ASE, no large physaddr (PABITS),
41 no external interrupt controller, no vectored interrupts,
42 no 1kb pages, no SmartMIPS ASE, no trace logic */
43 #define MIPS_CONFIG3 \
44 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
45 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
46 (0 << CP0C3_SM) | (0 << CP0C3_TL))
47
48 #define MIPS_CONFIG4 \
49 ((0 << CP0C4_M))
50
51 #define MIPS_CONFIG5 \
52 ((0 << CP0C5_M))
53
54 /* MMU types, the first four entries have the same layout as the
55 CP0C0_MT field. */
56 enum mips_mmu_types {
57 MMU_TYPE_NONE,
58 MMU_TYPE_R4000,
59 MMU_TYPE_RESERVED,
60 MMU_TYPE_FMT,
61 MMU_TYPE_R3000,
62 MMU_TYPE_R6000,
63 MMU_TYPE_R8000
64 };
65
66 struct mips_def_t {
67 const char *name;
68 int32_t CP0_PRid;
69 int32_t CP0_Config0;
70 int32_t CP0_Config1;
71 int32_t CP0_Config2;
72 int32_t CP0_Config3;
73 int32_t CP0_Config4;
74 int32_t CP0_Config4_rw_bitmask;
75 int32_t CP0_Config5;
76 int32_t CP0_Config5_rw_bitmask;
77 int32_t CP0_Config6;
78 int32_t CP0_Config7;
79 target_ulong CP0_LLAddr_rw_bitmask;
80 int CP0_LLAddr_shift;
81 int32_t SYNCI_Step;
82 int32_t CCRes;
83 int32_t CP0_Status_rw_bitmask;
84 int32_t CP0_TCStatus_rw_bitmask;
85 int32_t CP0_SRSCtl;
86 int32_t CP1_fcr0;
87 int32_t MSAIR;
88 int32_t SEGBITS;
89 int32_t PABITS;
90 int32_t CP0_SRSConf0_rw_bitmask;
91 int32_t CP0_SRSConf0;
92 int32_t CP0_SRSConf1_rw_bitmask;
93 int32_t CP0_SRSConf1;
94 int32_t CP0_SRSConf2_rw_bitmask;
95 int32_t CP0_SRSConf2;
96 int32_t CP0_SRSConf3_rw_bitmask;
97 int32_t CP0_SRSConf3;
98 int32_t CP0_SRSConf4_rw_bitmask;
99 int32_t CP0_SRSConf4;
100 int32_t CP0_PageGrain_rw_bitmask;
101 int32_t CP0_PageGrain;
102 int insn_flags;
103 enum mips_mmu_types mmu_type;
104 };
105
106 /*****************************************************************************/
107 /* MIPS CPU definitions */
108 static const mips_def_t mips_defs[] =
109 {
110 {
111 .name = "4Kc",
112 .CP0_PRid = 0x00018000,
113 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
114 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
115 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
116 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
117 (0 << CP0C1_CA),
118 .CP0_Config2 = MIPS_CONFIG2,
119 .CP0_Config3 = MIPS_CONFIG3,
120 .CP0_LLAddr_rw_bitmask = 0,
121 .CP0_LLAddr_shift = 4,
122 .SYNCI_Step = 32,
123 .CCRes = 2,
124 .CP0_Status_rw_bitmask = 0x1278FF17,
125 .SEGBITS = 32,
126 .PABITS = 32,
127 .insn_flags = CPU_MIPS32,
128 .mmu_type = MMU_TYPE_R4000,
129 },
130 {
131 .name = "4Km",
132 .CP0_PRid = 0x00018300,
133 /* Config1 implemented, fixed mapping MMU,
134 no virtual icache, uncached coherency. */
135 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
136 .CP0_Config1 = MIPS_CONFIG1 |
137 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
138 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
139 (1 << CP0C1_CA),
140 .CP0_Config2 = MIPS_CONFIG2,
141 .CP0_Config3 = MIPS_CONFIG3,
142 .CP0_LLAddr_rw_bitmask = 0,
143 .CP0_LLAddr_shift = 4,
144 .SYNCI_Step = 32,
145 .CCRes = 2,
146 .CP0_Status_rw_bitmask = 0x1258FF17,
147 .SEGBITS = 32,
148 .PABITS = 32,
149 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
150 .mmu_type = MMU_TYPE_FMT,
151 },
152 {
153 .name = "4KEcR1",
154 .CP0_PRid = 0x00018400,
155 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
156 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
157 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
158 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
159 (0 << CP0C1_CA),
160 .CP0_Config2 = MIPS_CONFIG2,
161 .CP0_Config3 = MIPS_CONFIG3,
162 .CP0_LLAddr_rw_bitmask = 0,
163 .CP0_LLAddr_shift = 4,
164 .SYNCI_Step = 32,
165 .CCRes = 2,
166 .CP0_Status_rw_bitmask = 0x1278FF17,
167 .SEGBITS = 32,
168 .PABITS = 32,
169 .insn_flags = CPU_MIPS32,
170 .mmu_type = MMU_TYPE_R4000,
171 },
172 {
173 .name = "4KEmR1",
174 .CP0_PRid = 0x00018500,
175 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
176 .CP0_Config1 = MIPS_CONFIG1 |
177 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
178 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
179 (1 << CP0C1_CA),
180 .CP0_Config2 = MIPS_CONFIG2,
181 .CP0_Config3 = MIPS_CONFIG3,
182 .CP0_LLAddr_rw_bitmask = 0,
183 .CP0_LLAddr_shift = 4,
184 .SYNCI_Step = 32,
185 .CCRes = 2,
186 .CP0_Status_rw_bitmask = 0x1258FF17,
187 .SEGBITS = 32,
188 .PABITS = 32,
189 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
190 .mmu_type = MMU_TYPE_FMT,
191 },
192 {
193 .name = "4KEc",
194 .CP0_PRid = 0x00019000,
195 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
196 (MMU_TYPE_R4000 << CP0C0_MT),
197 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
198 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
199 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
200 (0 << CP0C1_CA),
201 .CP0_Config2 = MIPS_CONFIG2,
202 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
203 .CP0_LLAddr_rw_bitmask = 0,
204 .CP0_LLAddr_shift = 4,
205 .SYNCI_Step = 32,
206 .CCRes = 2,
207 .CP0_Status_rw_bitmask = 0x1278FF17,
208 .SEGBITS = 32,
209 .PABITS = 32,
210 .insn_flags = CPU_MIPS32R2,
211 .mmu_type = MMU_TYPE_R4000,
212 },
213 {
214 .name = "4KEm",
215 .CP0_PRid = 0x00019100,
216 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
217 (MMU_TYPE_FMT << CP0C0_MT),
218 .CP0_Config1 = MIPS_CONFIG1 |
219 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
220 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
221 (1 << CP0C1_CA),
222 .CP0_Config2 = MIPS_CONFIG2,
223 .CP0_Config3 = MIPS_CONFIG3,
224 .CP0_LLAddr_rw_bitmask = 0,
225 .CP0_LLAddr_shift = 4,
226 .SYNCI_Step = 32,
227 .CCRes = 2,
228 .CP0_Status_rw_bitmask = 0x1258FF17,
229 .SEGBITS = 32,
230 .PABITS = 32,
231 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
232 .mmu_type = MMU_TYPE_FMT,
233 },
234 {
235 .name = "24Kc",
236 .CP0_PRid = 0x00019300,
237 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
238 (MMU_TYPE_R4000 << CP0C0_MT),
239 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
240 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
241 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
242 (1 << CP0C1_CA),
243 .CP0_Config2 = MIPS_CONFIG2,
244 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
245 .CP0_LLAddr_rw_bitmask = 0,
246 .CP0_LLAddr_shift = 4,
247 .SYNCI_Step = 32,
248 .CCRes = 2,
249 /* No DSP implemented. */
250 .CP0_Status_rw_bitmask = 0x1278FF1F,
251 .SEGBITS = 32,
252 .PABITS = 32,
253 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
254 .mmu_type = MMU_TYPE_R4000,
255 },
256 {
257 .name = "24Kf",
258 .CP0_PRid = 0x00019300,
259 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
260 (MMU_TYPE_R4000 << CP0C0_MT),
261 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
262 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
263 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
264 (1 << CP0C1_CA),
265 .CP0_Config2 = MIPS_CONFIG2,
266 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
267 .CP0_LLAddr_rw_bitmask = 0,
268 .CP0_LLAddr_shift = 4,
269 .SYNCI_Step = 32,
270 .CCRes = 2,
271 /* No DSP implemented. */
272 .CP0_Status_rw_bitmask = 0x3678FF1F,
273 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
274 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
275 .SEGBITS = 32,
276 .PABITS = 32,
277 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
278 .mmu_type = MMU_TYPE_R4000,
279 },
280 {
281 .name = "34Kf",
282 .CP0_PRid = 0x00019500,
283 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
284 (MMU_TYPE_R4000 << CP0C0_MT),
285 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
286 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
287 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
288 (1 << CP0C1_CA),
289 .CP0_Config2 = MIPS_CONFIG2,
290 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) |
291 (1 << CP0C3_DSPP),
292 .CP0_LLAddr_rw_bitmask = 0,
293 .CP0_LLAddr_shift = 0,
294 .SYNCI_Step = 32,
295 .CCRes = 2,
296 .CP0_Status_rw_bitmask = 0x3778FF1F,
297 .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
298 (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
299 (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
300 (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
301 (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
302 (0xff << CP0TCSt_TASID),
303 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
304 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
305 .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
306 .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
307 .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
308 (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
309 .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
310 .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
311 (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
312 .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
313 .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
314 (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
315 .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
316 .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
317 (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
318 .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
319 .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
320 (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
321 .SEGBITS = 32,
322 .PABITS = 32,
323 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
324 .mmu_type = MMU_TYPE_R4000,
325 },
326 {
327 .name = "74Kf",
328 .CP0_PRid = 0x00019700,
329 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
330 (MMU_TYPE_R4000 << CP0C0_MT),
331 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
332 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
333 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
334 (1 << CP0C1_CA),
335 .CP0_Config2 = MIPS_CONFIG2,
336 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
337 (1 << CP0C3_VInt),
338 .CP0_LLAddr_rw_bitmask = 0,
339 .CP0_LLAddr_shift = 4,
340 .SYNCI_Step = 32,
341 .CCRes = 2,
342 .CP0_Status_rw_bitmask = 0x3778FF1F,
343 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
344 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
345 .SEGBITS = 32,
346 .PABITS = 32,
347 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
348 .mmu_type = MMU_TYPE_R4000,
349 },
350 {
351 .name = "M14K",
352 .CP0_PRid = 0x00019b00,
353 /* Config1 implemented, fixed mapping MMU,
354 no virtual icache, uncached coherency. */
355 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_KU) | (0x2 << CP0C0_K23) |
356 (0x1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT),
357 .CP0_Config1 = MIPS_CONFIG1,
358 .CP0_Config2 = MIPS_CONFIG2,
359 .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt),
360 .CP0_LLAddr_rw_bitmask = 0,
361 .CP0_LLAddr_shift = 4,
362 .SYNCI_Step = 32,
363 .CCRes = 2,
364 .CP0_Status_rw_bitmask = 0x1258FF17,
365 .SEGBITS = 32,
366 .PABITS = 32,
367 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
368 .mmu_type = MMU_TYPE_FMT,
369 },
370 {
371 .name = "M14Kc",
372 /* This is the TLB-based MMU core. */
373 .CP0_PRid = 0x00019c00,
374 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
375 (MMU_TYPE_R4000 << CP0C0_MT),
376 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
377 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
378 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
379 .CP0_Config2 = MIPS_CONFIG2,
380 .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt),
381 .CP0_LLAddr_rw_bitmask = 0,
382 .CP0_LLAddr_shift = 4,
383 .SYNCI_Step = 32,
384 .CCRes = 2,
385 .CP0_Status_rw_bitmask = 0x1278FF17,
386 .SEGBITS = 32,
387 .PABITS = 32,
388 .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS,
389 .mmu_type = MMU_TYPE_R4000,
390 },
391 {
392 /* A generic CPU providing MIPS32 Release 5 features.
393 FIXME: Eventually this should be replaced by a real CPU model. */
394 .name = "mips32r5-generic",
395 .CP0_PRid = 0x00019700,
396 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
397 (MMU_TYPE_R4000 << CP0C0_MT),
398 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
399 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
400 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
401 (1 << CP0C1_CA),
402 .CP0_Config2 = MIPS_CONFIG2,
403 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
404 (1 << CP0C3_LPA),
405 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M),
406 .CP0_Config4_rw_bitmask = 0,
407 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR) | (1 << CP0C5_LLB) |
408 (1 << CP0C5_MVH),
409 .CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) |
410 (1 << CP0C5_CV) | (0 << CP0C5_EVA) |
411 (1 << CP0C5_MSAEn) | (1 << CP0C5_UFR) |
412 (0 << CP0C5_NFExists),
413 .CP0_LLAddr_rw_bitmask = 0,
414 .CP0_LLAddr_shift = 4,
415 .SYNCI_Step = 32,
416 .CCRes = 2,
417 .CP0_Status_rw_bitmask = 0x3778FF1F,
418 .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
419 .CP1_fcr0 = (1 << FCR0_UFRP) | (1 << FCR0_F64) | (1 << FCR0_L) |
420 (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
421 (0x93 << FCR0_PRID),
422 .SEGBITS = 32,
423 .PABITS = 40,
424 .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_MSA,
425 .mmu_type = MMU_TYPE_R4000,
426 },
427 {
428 /* A generic CPU supporting MIPS32 Release 6 ISA.
429 FIXME: Support IEEE 754-2008 FP.
430 Eventually this should be replaced by a real CPU model. */
431 .name = "mips32r6-generic",
432 .CP0_PRid = 0x00010000,
433 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) |
434 (MMU_TYPE_R4000 << CP0C0_MT),
435 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
436 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
437 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
438 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
439 .CP0_Config2 = MIPS_CONFIG2,
440 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_BP) | (1 << CP0C3_BI) |
441 (2 << CP0C3_ISA) | (1 << CP0C3_ULRI) |
442 (1 << CP0C3_RXI) | (1U << CP0C3_M),
443 .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
444 (3 << CP0C4_IE) | (1U << CP0C4_M),
445 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_LLB),
446 .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
447 (1 << CP0C5_UFE),
448 .CP0_LLAddr_rw_bitmask = 0,
449 .CP0_LLAddr_shift = 0,
450 .SYNCI_Step = 32,
451 .CCRes = 2,
452 .CP0_Status_rw_bitmask = 0x3058FF1F,
453 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
454 (1U << CP0PG_RIE),
455 .CP0_PageGrain_rw_bitmask = 0,
456 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_F64) | (1 << FCR0_L) |
457 (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
458 (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
459 .SEGBITS = 32,
460 .PABITS = 32,
461 .insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS,
462 .mmu_type = MMU_TYPE_R4000,
463 },
464 #if defined(TARGET_MIPS64)
465 {
466 .name = "R4000",
467 .CP0_PRid = 0x00000400,
468 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
469 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
470 /* Note: Config1 is only used internally, the R4000 has only Config0. */
471 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
472 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
473 .CP0_LLAddr_shift = 4,
474 .SYNCI_Step = 16,
475 .CCRes = 2,
476 .CP0_Status_rw_bitmask = 0x3678FFFF,
477 /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
478 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
479 .SEGBITS = 40,
480 .PABITS = 36,
481 .insn_flags = CPU_MIPS3,
482 .mmu_type = MMU_TYPE_R4000,
483 },
484 {
485 .name = "VR5432",
486 .CP0_PRid = 0x00005400,
487 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
488 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
489 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
490 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL,
491 .CP0_LLAddr_shift = 4,
492 .SYNCI_Step = 16,
493 .CCRes = 2,
494 .CP0_Status_rw_bitmask = 0x3678FFFF,
495 /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
496 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
497 .SEGBITS = 40,
498 .PABITS = 32,
499 .insn_flags = CPU_VR54XX,
500 .mmu_type = MMU_TYPE_R4000,
501 },
502 {
503 .name = "5Kc",
504 .CP0_PRid = 0x00018100,
505 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
506 (MMU_TYPE_R4000 << CP0C0_MT),
507 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
508 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
509 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
510 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
511 .CP0_Config2 = MIPS_CONFIG2,
512 .CP0_Config3 = MIPS_CONFIG3,
513 .CP0_LLAddr_rw_bitmask = 0,
514 .CP0_LLAddr_shift = 4,
515 .SYNCI_Step = 32,
516 .CCRes = 2,
517 .CP0_Status_rw_bitmask = 0x12F8FFFF,
518 .SEGBITS = 42,
519 .PABITS = 36,
520 .insn_flags = CPU_MIPS64,
521 .mmu_type = MMU_TYPE_R4000,
522 },
523 {
524 .name = "5Kf",
525 .CP0_PRid = 0x00018100,
526 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
527 (MMU_TYPE_R4000 << CP0C0_MT),
528 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
529 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
530 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
531 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
532 .CP0_Config2 = MIPS_CONFIG2,
533 .CP0_Config3 = MIPS_CONFIG3,
534 .CP0_LLAddr_rw_bitmask = 0,
535 .CP0_LLAddr_shift = 4,
536 .SYNCI_Step = 32,
537 .CCRes = 2,
538 .CP0_Status_rw_bitmask = 0x36F8FFFF,
539 /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
540 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
541 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
542 .SEGBITS = 42,
543 .PABITS = 36,
544 .insn_flags = CPU_MIPS64,
545 .mmu_type = MMU_TYPE_R4000,
546 },
547 {
548 .name = "20Kc",
549 /* We emulate a later version of the 20Kc, earlier ones had a broken
550 WAIT instruction. */
551 .CP0_PRid = 0x000182a0,
552 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
553 (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
554 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
555 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
556 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
557 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
558 .CP0_Config2 = MIPS_CONFIG2,
559 .CP0_Config3 = MIPS_CONFIG3,
560 .CP0_LLAddr_rw_bitmask = 0,
561 .CP0_LLAddr_shift = 0,
562 .SYNCI_Step = 32,
563 .CCRes = 1,
564 .CP0_Status_rw_bitmask = 0x36FBFFFF,
565 /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
566 .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
567 (1 << FCR0_D) | (1 << FCR0_S) |
568 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
569 .SEGBITS = 40,
570 .PABITS = 36,
571 .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
572 .mmu_type = MMU_TYPE_R4000,
573 },
574 {
575 /* A generic CPU providing MIPS64 Release 2 features.
576 FIXME: Eventually this should be replaced by a real CPU model. */
577 .name = "MIPS64R2-generic",
578 .CP0_PRid = 0x00010000,
579 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
580 (MMU_TYPE_R4000 << CP0C0_MT),
581 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
582 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
583 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
584 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
585 .CP0_Config2 = MIPS_CONFIG2,
586 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
587 .CP0_LLAddr_rw_bitmask = 0,
588 .CP0_LLAddr_shift = 0,
589 .SYNCI_Step = 32,
590 .CCRes = 2,
591 .CP0_Status_rw_bitmask = 0x36FBFFFF,
592 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
593 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
594 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
595 .SEGBITS = 42,
596 .PABITS = 36,
597 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
598 .mmu_type = MMU_TYPE_R4000,
599 },
600 {
601 .name = "5KEc",
602 .CP0_PRid = 0x00018900,
603 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
604 (MMU_TYPE_R4000 << CP0C0_MT),
605 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
606 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
607 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
608 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
609 .CP0_Config2 = MIPS_CONFIG2,
610 .CP0_Config3 = MIPS_CONFIG3,
611 .CP0_LLAddr_rw_bitmask = 0,
612 .CP0_LLAddr_shift = 4,
613 .SYNCI_Step = 32,
614 .CCRes = 2,
615 .CP0_Status_rw_bitmask = 0x12F8FFFF,
616 .SEGBITS = 42,
617 .PABITS = 36,
618 .insn_flags = CPU_MIPS64R2,
619 .mmu_type = MMU_TYPE_R4000,
620 },
621 {
622 .name = "5KEf",
623 .CP0_PRid = 0x00018900,
624 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
625 (MMU_TYPE_R4000 << CP0C0_MT),
626 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
627 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
628 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
629 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
630 .CP0_Config2 = MIPS_CONFIG2,
631 .CP0_Config3 = MIPS_CONFIG3,
632 .CP0_LLAddr_rw_bitmask = 0,
633 .CP0_LLAddr_shift = 4,
634 .SYNCI_Step = 32,
635 .CCRes = 2,
636 .CP0_Status_rw_bitmask = 0x36F8FFFF,
637 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
638 (1 << FCR0_D) | (1 << FCR0_S) |
639 (0x89 << FCR0_PRID) | (0x0 << FCR0_REV),
640 .SEGBITS = 42,
641 .PABITS = 36,
642 .insn_flags = CPU_MIPS64R2,
643 .mmu_type = MMU_TYPE_R4000,
644 },
645 {
646 /* A generic CPU supporting MIPS64 Release 6 ISA.
647 FIXME: Support IEEE 754-2008 FP.
648 Eventually this should be replaced by a real CPU model. */
649 .name = "MIPS64R6-generic",
650 .CP0_PRid = 0x00010000,
651 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
652 (MMU_TYPE_R4000 << CP0C0_MT),
653 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
654 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
655 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
656 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
657 .CP0_Config2 = MIPS_CONFIG2,
658 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
659 (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
660 (1 << CP0C3_RXI) | (1 << CP0C3_LPA),
661 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
662 (0xfc << CP0C4_KScrExist),
663 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_LLB),
664 .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
665 (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
666 .CP0_LLAddr_rw_bitmask = 0,
667 .CP0_LLAddr_shift = 0,
668 .SYNCI_Step = 32,
669 .CCRes = 2,
670 .CP0_Status_rw_bitmask = 0x30D8FFFF,
671 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
672 (1U << CP0PG_RIE),
673 .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
674 .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_F64) | (1 << FCR0_L) |
675 (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
676 (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
677 .SEGBITS = 48,
678 .PABITS = 48,
679 .insn_flags = CPU_MIPS64R6 | ASE_MSA,
680 .mmu_type = MMU_TYPE_R4000,
681 },
682 {
683 .name = "Loongson-2E",
684 .CP0_PRid = 0x6302,
685 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
686 .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
687 (0x1<<5) | (0x1<<4) | (0x1<<1),
688 /* Note: Config1 is only used internally,
689 Loongson-2E has only Config0. */
690 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
691 .SYNCI_Step = 16,
692 .CCRes = 2,
693 .CP0_Status_rw_bitmask = 0x35D0FFFF,
694 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
695 .SEGBITS = 40,
696 .PABITS = 40,
697 .insn_flags = CPU_LOONGSON2E,
698 .mmu_type = MMU_TYPE_R4000,
699 },
700 {
701 .name = "Loongson-2F",
702 .CP0_PRid = 0x6303,
703 /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */
704 .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) |
705 (0x1<<5) | (0x1<<4) | (0x1<<1),
706 /* Note: Config1 is only used internally,
707 Loongson-2F has only Config0. */
708 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
709 .SYNCI_Step = 16,
710 .CCRes = 2,
711 .CP0_Status_rw_bitmask = 0xF5D0FF1F, /* Bits 7:5 not writable. */
712 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
713 .SEGBITS = 40,
714 .PABITS = 40,
715 .insn_flags = CPU_LOONGSON2F,
716 .mmu_type = MMU_TYPE_R4000,
717 },
718 {
719 /* A generic CPU providing MIPS64 ASE DSP 2 features.
720 FIXME: Eventually this should be replaced by a real CPU model. */
721 .name = "mips64dspr2",
722 .CP0_PRid = 0x00010000,
723 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
724 (MMU_TYPE_R4000 << CP0C0_MT),
725 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
726 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
727 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
728 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
729 .CP0_Config2 = MIPS_CONFIG2,
730 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) |
731 (1 << CP0C3_DSPP) | (1 << CP0C3_LPA),
732 .CP0_LLAddr_rw_bitmask = 0,
733 .CP0_LLAddr_shift = 0,
734 .SYNCI_Step = 32,
735 .CCRes = 2,
736 .CP0_Status_rw_bitmask = 0x37FBFFFF,
737 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
738 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
739 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
740 .SEGBITS = 42,
741 .PABITS = 36,
742 .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
743 .mmu_type = MMU_TYPE_R4000,
744 },
745
746 #endif
747 };
748
749 static const mips_def_t *cpu_mips_find_by_name (const char *name)
750 {
751 int i;
752
753 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
754 if (strcasecmp(name, mips_defs[i].name) == 0) {
755 return &mips_defs[i];
756 }
757 }
758 return NULL;
759 }
760
761 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf)
762 {
763 int i;
764
765 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
766 (*cpu_fprintf)(f, "MIPS '%s'\n",
767 mips_defs[i].name);
768 }
769 }
770
771 #ifndef CONFIG_USER_ONLY
772 static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
773 {
774 env->tlb->nb_tlb = 1;
775 env->tlb->map_address = &no_mmu_map_address;
776 }
777
778 static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
779 {
780 env->tlb->nb_tlb = 1;
781 env->tlb->map_address = &fixed_mmu_map_address;
782 }
783
784 static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
785 {
786 env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
787 env->tlb->map_address = &r4k_map_address;
788 env->tlb->helper_tlbwi = r4k_helper_tlbwi;
789 env->tlb->helper_tlbwr = r4k_helper_tlbwr;
790 env->tlb->helper_tlbp = r4k_helper_tlbp;
791 env->tlb->helper_tlbr = r4k_helper_tlbr;
792 env->tlb->helper_tlbinv = r4k_helper_tlbinv;
793 env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
794 }
795
796 static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
797 {
798 MIPSCPU *cpu = mips_env_get_cpu(env);
799
800 env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
801
802 switch (def->mmu_type) {
803 case MMU_TYPE_NONE:
804 no_mmu_init(env, def);
805 break;
806 case MMU_TYPE_R4000:
807 r4k_mmu_init(env, def);
808 break;
809 case MMU_TYPE_FMT:
810 fixed_mmu_init(env, def);
811 break;
812 case MMU_TYPE_R3000:
813 case MMU_TYPE_R6000:
814 case MMU_TYPE_R8000:
815 default:
816 cpu_abort(CPU(cpu), "MMU type not supported\n");
817 }
818 }
819 #endif /* CONFIG_USER_ONLY */
820
821 static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
822 {
823 int i;
824
825 for (i = 0; i < MIPS_FPU_MAX; i++)
826 env->fpus[i].fcr0 = def->CP1_fcr0;
827
828 memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
829 }
830
831 static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
832 {
833 env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
834
835 /* MVPConf1 implemented, TLB sharable, no gating storage support,
836 programmable cache partitioning implemented, number of allocatable
837 and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
838 implemented, 5 TCs implemented. */
839 env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
840 (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
841 // TODO: actually do 2 VPEs.
842 // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
843 // (0x04 << CP0MVPC0_PTC);
844 (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
845 (0x00 << CP0MVPC0_PTC);
846 #if !defined(CONFIG_USER_ONLY)
847 /* Usermode has no TLB support */
848 env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
849 #endif
850
851 /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
852 no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
853 env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
854 (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
855 (0x1 << CP0MVPC1_PCP1);
856 }
857
858 static void msa_reset(CPUMIPSState *env)
859 {
860 #ifdef CONFIG_USER_ONLY
861 /* MSA access enabled */
862 env->CP0_Config5 |= 1 << CP0C5_MSAEn;
863 env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
864 #endif
865
866 /* MSA CSR:
867 - non-signaling floating point exception mode off (NX bit is 0)
868 - Cause, Enables, and Flags are all 0
869 - round to nearest / ties to even (RM bits are 0) */
870 env->active_tc.msacsr = 0;
871
872 restore_msa_fp_status(env);
873
874 /* tininess detected after rounding.*/
875 set_float_detect_tininess(float_tininess_after_rounding,
876 &env->active_tc.msa_fp_status);
877
878 /* clear float_status exception flags */
879 set_float_exception_flags(0, &env->active_tc.msa_fp_status);
880
881 /* clear float_status nan mode */
882 set_default_nan_mode(0, &env->active_tc.msa_fp_status);
883 }
AR7 emulation for QEMU