2 * MIPS emulation helpers for qemu.
4 * Copyright (c) 2004-2005 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/host-utils.h"
22 #include "exec/helper-proto.h"
23 #include "exec/cpu_ldst.h"
24 #include "sysemu/kvm.h"
26 #ifndef CONFIG_USER_ONLY
27 static inline void cpu_mips_tlb_flush (CPUMIPSState
*env
, int flush_global
);
30 /*****************************************************************************/
31 /* Exceptions processing helpers */
33 static inline void QEMU_NORETURN
do_raise_exception_err(CPUMIPSState
*env
,
38 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
40 if (exception
< EXCP_SC
) {
41 qemu_log("%s: %d %d\n", __func__
, exception
, error_code
);
43 cs
->exception_index
= exception
;
44 env
->error_code
= error_code
;
47 /* now we have a real cpu fault */
48 cpu_restore_state(cs
, pc
);
54 static inline void QEMU_NORETURN
do_raise_exception(CPUMIPSState
*env
,
58 do_raise_exception_err(env
, exception
, 0, pc
);
61 void helper_raise_exception_err(CPUMIPSState
*env
, uint32_t exception
,
64 do_raise_exception_err(env
, exception
, error_code
, 0);
67 void helper_raise_exception(CPUMIPSState
*env
, uint32_t exception
)
69 do_raise_exception(env
, exception
, 0);
72 #if defined(CONFIG_USER_ONLY)
73 #define HELPER_LD(name, insn, type) \
74 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
77 return (type) cpu_##insn##_data(env, addr); \
80 #define HELPER_LD(name, insn, type) \
81 static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
86 case 0: return (type) cpu_##insn##_kernel(env, addr); break; \
87 case 1: return (type) cpu_##insn##_super(env, addr); break; \
89 case 2: return (type) cpu_##insn##_user(env, addr); break; \
93 HELPER_LD(lw
, ldl
, int32_t)
94 #if defined(TARGET_MIPS64)
95 HELPER_LD(ld
, ldq
, int64_t)
99 #if defined(CONFIG_USER_ONLY)
100 #define HELPER_ST(name, insn, type) \
101 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
102 type val, int mem_idx) \
104 cpu_##insn##_data(env, addr, val); \
107 #define HELPER_ST(name, insn, type) \
108 static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
109 type val, int mem_idx) \
113 case 0: cpu_##insn##_kernel(env, addr, val); break; \
114 case 1: cpu_##insn##_super(env, addr, val); break; \
116 case 2: cpu_##insn##_user(env, addr, val); break; \
120 HELPER_ST(sb
, stb
, uint8_t)
121 HELPER_ST(sw
, stl
, uint32_t)
122 #if defined(TARGET_MIPS64)
123 HELPER_ST(sd
, stq
, uint64_t)
127 target_ulong
helper_clo (target_ulong arg1
)
132 target_ulong
helper_clz (target_ulong arg1
)
137 #if defined(TARGET_MIPS64)
138 target_ulong
helper_dclo (target_ulong arg1
)
143 target_ulong
helper_dclz (target_ulong arg1
)
147 #endif /* TARGET_MIPS64 */
149 /* 64 bits arithmetic for 32 bits hosts */
150 static inline uint64_t get_HILO(CPUMIPSState
*env
)
152 return ((uint64_t)(env
->active_tc
.HI
[0]) << 32) | (uint32_t)env
->active_tc
.LO
[0];
155 static inline target_ulong
set_HIT0_LO(CPUMIPSState
*env
, uint64_t HILO
)
158 env
->active_tc
.LO
[0] = (int32_t)(HILO
& 0xFFFFFFFF);
159 tmp
= env
->active_tc
.HI
[0] = (int32_t)(HILO
>> 32);
163 static inline target_ulong
set_HI_LOT0(CPUMIPSState
*env
, uint64_t HILO
)
165 target_ulong tmp
= env
->active_tc
.LO
[0] = (int32_t)(HILO
& 0xFFFFFFFF);
166 env
->active_tc
.HI
[0] = (int32_t)(HILO
>> 32);
170 /* Multiplication variants of the vr54xx. */
171 target_ulong
helper_muls(CPUMIPSState
*env
, target_ulong arg1
,
174 return set_HI_LOT0(env
, 0 - ((int64_t)(int32_t)arg1
*
175 (int64_t)(int32_t)arg2
));
178 target_ulong
helper_mulsu(CPUMIPSState
*env
, target_ulong arg1
,
181 return set_HI_LOT0(env
, 0 - (uint64_t)(uint32_t)arg1
*
182 (uint64_t)(uint32_t)arg2
);
185 target_ulong
helper_macc(CPUMIPSState
*env
, target_ulong arg1
,
188 return set_HI_LOT0(env
, (int64_t)get_HILO(env
) + (int64_t)(int32_t)arg1
*
189 (int64_t)(int32_t)arg2
);
192 target_ulong
helper_macchi(CPUMIPSState
*env
, target_ulong arg1
,
195 return set_HIT0_LO(env
, (int64_t)get_HILO(env
) + (int64_t)(int32_t)arg1
*
196 (int64_t)(int32_t)arg2
);
199 target_ulong
helper_maccu(CPUMIPSState
*env
, target_ulong arg1
,
202 return set_HI_LOT0(env
, (uint64_t)get_HILO(env
) +
203 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
206 target_ulong
helper_macchiu(CPUMIPSState
*env
, target_ulong arg1
,
209 return set_HIT0_LO(env
, (uint64_t)get_HILO(env
) +
210 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
213 target_ulong
helper_msac(CPUMIPSState
*env
, target_ulong arg1
,
216 return set_HI_LOT0(env
, (int64_t)get_HILO(env
) - (int64_t)(int32_t)arg1
*
217 (int64_t)(int32_t)arg2
);
220 target_ulong
helper_msachi(CPUMIPSState
*env
, target_ulong arg1
,
223 return set_HIT0_LO(env
, (int64_t)get_HILO(env
) - (int64_t)(int32_t)arg1
*
224 (int64_t)(int32_t)arg2
);
227 target_ulong
helper_msacu(CPUMIPSState
*env
, target_ulong arg1
,
230 return set_HI_LOT0(env
, (uint64_t)get_HILO(env
) -
231 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
234 target_ulong
helper_msachiu(CPUMIPSState
*env
, target_ulong arg1
,
237 return set_HIT0_LO(env
, (uint64_t)get_HILO(env
) -
238 (uint64_t)(uint32_t)arg1
* (uint64_t)(uint32_t)arg2
);
241 target_ulong
helper_mulhi(CPUMIPSState
*env
, target_ulong arg1
,
244 return set_HIT0_LO(env
, (int64_t)(int32_t)arg1
* (int64_t)(int32_t)arg2
);
247 target_ulong
helper_mulhiu(CPUMIPSState
*env
, target_ulong arg1
,
250 return set_HIT0_LO(env
, (uint64_t)(uint32_t)arg1
*
251 (uint64_t)(uint32_t)arg2
);
254 target_ulong
helper_mulshi(CPUMIPSState
*env
, target_ulong arg1
,
257 return set_HIT0_LO(env
, 0 - (int64_t)(int32_t)arg1
*
258 (int64_t)(int32_t)arg2
);
261 target_ulong
helper_mulshiu(CPUMIPSState
*env
, target_ulong arg1
,
264 return set_HIT0_LO(env
, 0 - (uint64_t)(uint32_t)arg1
*
265 (uint64_t)(uint32_t)arg2
);
268 static inline target_ulong
bitswap(target_ulong v
)
270 v
= ((v
>> 1) & (target_ulong
)0x5555555555555555ULL
) |
271 ((v
& (target_ulong
)0x5555555555555555ULL
) << 1);
272 v
= ((v
>> 2) & (target_ulong
)0x3333333333333333ULL
) |
273 ((v
& (target_ulong
)0x3333333333333333ULL
) << 2);
274 v
= ((v
>> 4) & (target_ulong
)0x0F0F0F0F0F0F0F0FULL
) |
275 ((v
& (target_ulong
)0x0F0F0F0F0F0F0F0FULL
) << 4);
280 target_ulong
helper_dbitswap(target_ulong rt
)
286 target_ulong
helper_bitswap(target_ulong rt
)
288 return (int32_t)bitswap(rt
);
291 #ifndef CONFIG_USER_ONLY
293 static inline hwaddr
do_translate_address(CPUMIPSState
*env
,
294 target_ulong address
,
299 lladdr
= cpu_mips_translate_address(env
, address
, rw
);
301 if (lladdr
== -1LL) {
302 cpu_loop_exit(CPU(mips_env_get_cpu(env
)));
308 #define HELPER_LD_ATOMIC(name, insn, almask) \
309 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
311 if (arg & almask) { \
312 env->CP0_BadVAddr = arg; \
313 helper_raise_exception(env, EXCP_AdEL); \
315 env->lladdr = do_translate_address(env, arg, 0); \
316 env->llval = do_##insn(env, arg, mem_idx); \
319 HELPER_LD_ATOMIC(ll
, lw
, 0x3)
321 HELPER_LD_ATOMIC(lld
, ld
, 0x7)
323 #undef HELPER_LD_ATOMIC
325 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask) \
326 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \
327 target_ulong arg2, int mem_idx) \
331 if (arg2 & almask) { \
332 env->CP0_BadVAddr = arg2; \
333 helper_raise_exception(env, EXCP_AdES); \
335 if (do_translate_address(env, arg2, 1) == env->lladdr) { \
336 tmp = do_##ld_insn(env, arg2, mem_idx); \
337 if (tmp == env->llval) { \
338 do_##st_insn(env, arg2, arg1, mem_idx); \
344 HELPER_ST_ATOMIC(sc
, lw
, sw
, 0x3)
346 HELPER_ST_ATOMIC(scd
, ld
, sd
, 0x7)
348 #undef HELPER_ST_ATOMIC
351 #ifdef TARGET_WORDS_BIGENDIAN
352 #define GET_LMASK(v) ((v) & 3)
353 #define GET_OFFSET(addr, offset) (addr + (offset))
355 #define GET_LMASK(v) (((v) & 3) ^ 3)
356 #define GET_OFFSET(addr, offset) (addr - (offset))
359 void helper_swl(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
362 do_sb(env
, arg2
, (uint8_t)(arg1
>> 24), mem_idx
);
364 if (GET_LMASK(arg2
) <= 2)
365 do_sb(env
, GET_OFFSET(arg2
, 1), (uint8_t)(arg1
>> 16), mem_idx
);
367 if (GET_LMASK(arg2
) <= 1)
368 do_sb(env
, GET_OFFSET(arg2
, 2), (uint8_t)(arg1
>> 8), mem_idx
);
370 if (GET_LMASK(arg2
) == 0)
371 do_sb(env
, GET_OFFSET(arg2
, 3), (uint8_t)arg1
, mem_idx
);
374 void helper_swr(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
377 do_sb(env
, arg2
, (uint8_t)arg1
, mem_idx
);
379 if (GET_LMASK(arg2
) >= 1)
380 do_sb(env
, GET_OFFSET(arg2
, -1), (uint8_t)(arg1
>> 8), mem_idx
);
382 if (GET_LMASK(arg2
) >= 2)
383 do_sb(env
, GET_OFFSET(arg2
, -2), (uint8_t)(arg1
>> 16), mem_idx
);
385 if (GET_LMASK(arg2
) == 3)
386 do_sb(env
, GET_OFFSET(arg2
, -3), (uint8_t)(arg1
>> 24), mem_idx
);
389 #if defined(TARGET_MIPS64)
390 /* "half" load and stores. We must do the memory access inline,
391 or fault handling won't work. */
393 #ifdef TARGET_WORDS_BIGENDIAN
394 #define GET_LMASK64(v) ((v) & 7)
396 #define GET_LMASK64(v) (((v) & 7) ^ 7)
399 void helper_sdl(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
402 do_sb(env
, arg2
, (uint8_t)(arg1
>> 56), mem_idx
);
404 if (GET_LMASK64(arg2
) <= 6)
405 do_sb(env
, GET_OFFSET(arg2
, 1), (uint8_t)(arg1
>> 48), mem_idx
);
407 if (GET_LMASK64(arg2
) <= 5)
408 do_sb(env
, GET_OFFSET(arg2
, 2), (uint8_t)(arg1
>> 40), mem_idx
);
410 if (GET_LMASK64(arg2
) <= 4)
411 do_sb(env
, GET_OFFSET(arg2
, 3), (uint8_t)(arg1
>> 32), mem_idx
);
413 if (GET_LMASK64(arg2
) <= 3)
414 do_sb(env
, GET_OFFSET(arg2
, 4), (uint8_t)(arg1
>> 24), mem_idx
);
416 if (GET_LMASK64(arg2
) <= 2)
417 do_sb(env
, GET_OFFSET(arg2
, 5), (uint8_t)(arg1
>> 16), mem_idx
);
419 if (GET_LMASK64(arg2
) <= 1)
420 do_sb(env
, GET_OFFSET(arg2
, 6), (uint8_t)(arg1
>> 8), mem_idx
);
422 if (GET_LMASK64(arg2
) <= 0)
423 do_sb(env
, GET_OFFSET(arg2
, 7), (uint8_t)arg1
, mem_idx
);
426 void helper_sdr(CPUMIPSState
*env
, target_ulong arg1
, target_ulong arg2
,
429 do_sb(env
, arg2
, (uint8_t)arg1
, mem_idx
);
431 if (GET_LMASK64(arg2
) >= 1)
432 do_sb(env
, GET_OFFSET(arg2
, -1), (uint8_t)(arg1
>> 8), mem_idx
);
434 if (GET_LMASK64(arg2
) >= 2)
435 do_sb(env
, GET_OFFSET(arg2
, -2), (uint8_t)(arg1
>> 16), mem_idx
);
437 if (GET_LMASK64(arg2
) >= 3)
438 do_sb(env
, GET_OFFSET(arg2
, -3), (uint8_t)(arg1
>> 24), mem_idx
);
440 if (GET_LMASK64(arg2
) >= 4)
441 do_sb(env
, GET_OFFSET(arg2
, -4), (uint8_t)(arg1
>> 32), mem_idx
);
443 if (GET_LMASK64(arg2
) >= 5)
444 do_sb(env
, GET_OFFSET(arg2
, -5), (uint8_t)(arg1
>> 40), mem_idx
);
446 if (GET_LMASK64(arg2
) >= 6)
447 do_sb(env
, GET_OFFSET(arg2
, -6), (uint8_t)(arg1
>> 48), mem_idx
);
449 if (GET_LMASK64(arg2
) == 7)
450 do_sb(env
, GET_OFFSET(arg2
, -7), (uint8_t)(arg1
>> 56), mem_idx
);
452 #endif /* TARGET_MIPS64 */
454 static const int multiple_regs
[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
456 void helper_lwm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
459 target_ulong base_reglist
= reglist
& 0xf;
460 target_ulong do_r31
= reglist
& 0x10;
462 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
465 for (i
= 0; i
< base_reglist
; i
++) {
466 env
->active_tc
.gpr
[multiple_regs
[i
]] =
467 (target_long
)do_lw(env
, addr
, mem_idx
);
473 env
->active_tc
.gpr
[31] = (target_long
)do_lw(env
, addr
, mem_idx
);
477 void helper_swm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
480 target_ulong base_reglist
= reglist
& 0xf;
481 target_ulong do_r31
= reglist
& 0x10;
483 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
486 for (i
= 0; i
< base_reglist
; i
++) {
487 do_sw(env
, addr
, env
->active_tc
.gpr
[multiple_regs
[i
]], mem_idx
);
493 do_sw(env
, addr
, env
->active_tc
.gpr
[31], mem_idx
);
497 #if defined(TARGET_MIPS64)
498 void helper_ldm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
501 target_ulong base_reglist
= reglist
& 0xf;
502 target_ulong do_r31
= reglist
& 0x10;
504 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
507 for (i
= 0; i
< base_reglist
; i
++) {
508 env
->active_tc
.gpr
[multiple_regs
[i
]] = do_ld(env
, addr
, mem_idx
);
514 env
->active_tc
.gpr
[31] = do_ld(env
, addr
, mem_idx
);
518 void helper_sdm(CPUMIPSState
*env
, target_ulong addr
, target_ulong reglist
,
521 target_ulong base_reglist
= reglist
& 0xf;
522 target_ulong do_r31
= reglist
& 0x10;
524 if (base_reglist
> 0 && base_reglist
<= ARRAY_SIZE (multiple_regs
)) {
527 for (i
= 0; i
< base_reglist
; i
++) {
528 do_sd(env
, addr
, env
->active_tc
.gpr
[multiple_regs
[i
]], mem_idx
);
534 do_sd(env
, addr
, env
->active_tc
.gpr
[31], mem_idx
);
539 #ifndef CONFIG_USER_ONLY
541 static bool mips_vpe_is_wfi(MIPSCPU
*c
)
543 CPUState
*cpu
= CPU(c
);
544 CPUMIPSState
*env
= &c
->env
;
546 /* If the VPE is halted but otherwise active, it means it's waiting for
548 return cpu
->halted
&& mips_vpe_active(env
);
551 static inline void mips_vpe_wake(MIPSCPU
*c
)
553 /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
554 because there might be other conditions that state that c should
556 cpu_interrupt(CPU(c
), CPU_INTERRUPT_WAKE
);
559 static inline void mips_vpe_sleep(MIPSCPU
*cpu
)
561 CPUState
*cs
= CPU(cpu
);
563 /* The VPE was shut off, really go to bed.
564 Reset any old _WAKE requests. */
566 cpu_reset_interrupt(cs
, CPU_INTERRUPT_WAKE
);
569 static inline void mips_tc_wake(MIPSCPU
*cpu
, int tc
)
571 CPUMIPSState
*c
= &cpu
->env
;
573 /* FIXME: TC reschedule. */
574 if (mips_vpe_active(c
) && !mips_vpe_is_wfi(cpu
)) {
579 static inline void mips_tc_sleep(MIPSCPU
*cpu
, int tc
)
581 CPUMIPSState
*c
= &cpu
->env
;
583 /* FIXME: TC reschedule. */
584 if (!mips_vpe_active(c
)) {
591 * @env: CPU from which mapping is performed.
592 * @tc: Should point to an int with the value of the global TC index.
594 * This function will transform @tc into a local index within the
595 * returned #CPUMIPSState.
597 /* FIXME: This code assumes that all VPEs have the same number of TCs,
598 which depends on runtime setup. Can probably be fixed by
599 walking the list of CPUMIPSStates. */
600 static CPUMIPSState
*mips_cpu_map_tc(CPUMIPSState
*env
, int *tc
)
608 if (!(env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
))) {
609 /* Not allowed to address other CPUs. */
610 *tc
= env
->current_tc
;
614 cs
= CPU(mips_env_get_cpu(env
));
615 vpe_idx
= tc_idx
/ cs
->nr_threads
;
616 *tc
= tc_idx
% cs
->nr_threads
;
617 other_cs
= qemu_get_cpu(vpe_idx
);
618 if (other_cs
== NULL
) {
621 cpu
= MIPS_CPU(other_cs
);
625 /* The per VPE CP0_Status register shares some fields with the per TC
626 CP0_TCStatus registers. These fields are wired to the same registers,
627 so changes to either of them should be reflected on both registers.
629 Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
631 These helper call synchronizes the regs for a given cpu. */
633 /* Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. */
634 /* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
637 /* Called for updates to CP0_TCStatus. */
638 static void sync_c0_tcstatus(CPUMIPSState
*cpu
, int tc
,
642 uint32_t tcu
, tmx
, tasid
, tksu
;
643 uint32_t mask
= ((1U << CP0St_CU3
)
650 tcu
= (v
>> CP0TCSt_TCU0
) & 0xf;
651 tmx
= (v
>> CP0TCSt_TMX
) & 0x1;
653 tksu
= (v
>> CP0TCSt_TKSU
) & 0x3;
655 status
= tcu
<< CP0St_CU0
;
656 status
|= tmx
<< CP0St_MX
;
657 status
|= tksu
<< CP0St_KSU
;
659 cpu
->CP0_Status
&= ~mask
;
660 cpu
->CP0_Status
|= status
;
662 /* Sync the TASID with EntryHi. */
663 cpu
->CP0_EntryHi
&= ~0xff;
664 cpu
->CP0_EntryHi
|= tasid
;
669 /* Called for updates to CP0_EntryHi. */
670 static void sync_c0_entryhi(CPUMIPSState
*cpu
, int tc
)
673 uint32_t asid
, v
= cpu
->CP0_EntryHi
;
677 if (tc
== cpu
->current_tc
) {
678 tcst
= &cpu
->active_tc
.CP0_TCStatus
;
680 tcst
= &cpu
->tcs
[tc
].CP0_TCStatus
;
688 target_ulong
helper_mfc0_mvpcontrol(CPUMIPSState
*env
)
690 return env
->mvp
->CP0_MVPControl
;
693 target_ulong
helper_mfc0_mvpconf0(CPUMIPSState
*env
)
695 return env
->mvp
->CP0_MVPConf0
;
698 target_ulong
helper_mfc0_mvpconf1(CPUMIPSState
*env
)
700 return env
->mvp
->CP0_MVPConf1
;
703 target_ulong
helper_mfc0_random(CPUMIPSState
*env
)
705 return (int32_t)cpu_mips_get_random(env
);
708 target_ulong
helper_mfc0_tcstatus(CPUMIPSState
*env
)
710 return env
->active_tc
.CP0_TCStatus
;
713 target_ulong
helper_mftc0_tcstatus(CPUMIPSState
*env
)
715 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
716 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
718 if (other_tc
== other
->current_tc
)
719 return other
->active_tc
.CP0_TCStatus
;
721 return other
->tcs
[other_tc
].CP0_TCStatus
;
724 target_ulong
helper_mfc0_tcbind(CPUMIPSState
*env
)
726 return env
->active_tc
.CP0_TCBind
;
729 target_ulong
helper_mftc0_tcbind(CPUMIPSState
*env
)
731 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
732 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
734 if (other_tc
== other
->current_tc
)
735 return other
->active_tc
.CP0_TCBind
;
737 return other
->tcs
[other_tc
].CP0_TCBind
;
740 target_ulong
helper_mfc0_tcrestart(CPUMIPSState
*env
)
742 return env
->active_tc
.PC
;
745 target_ulong
helper_mftc0_tcrestart(CPUMIPSState
*env
)
747 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
748 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
750 if (other_tc
== other
->current_tc
)
751 return other
->active_tc
.PC
;
753 return other
->tcs
[other_tc
].PC
;
756 target_ulong
helper_mfc0_tchalt(CPUMIPSState
*env
)
758 return env
->active_tc
.CP0_TCHalt
;
761 target_ulong
helper_mftc0_tchalt(CPUMIPSState
*env
)
763 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
764 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
766 if (other_tc
== other
->current_tc
)
767 return other
->active_tc
.CP0_TCHalt
;
769 return other
->tcs
[other_tc
].CP0_TCHalt
;
772 target_ulong
helper_mfc0_tccontext(CPUMIPSState
*env
)
774 return env
->active_tc
.CP0_TCContext
;
777 target_ulong
helper_mftc0_tccontext(CPUMIPSState
*env
)
779 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
780 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
782 if (other_tc
== other
->current_tc
)
783 return other
->active_tc
.CP0_TCContext
;
785 return other
->tcs
[other_tc
].CP0_TCContext
;
788 target_ulong
helper_mfc0_tcschedule(CPUMIPSState
*env
)
790 return env
->active_tc
.CP0_TCSchedule
;
793 target_ulong
helper_mftc0_tcschedule(CPUMIPSState
*env
)
795 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
796 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
798 if (other_tc
== other
->current_tc
)
799 return other
->active_tc
.CP0_TCSchedule
;
801 return other
->tcs
[other_tc
].CP0_TCSchedule
;
804 target_ulong
helper_mfc0_tcschefback(CPUMIPSState
*env
)
806 return env
->active_tc
.CP0_TCScheFBack
;
809 target_ulong
helper_mftc0_tcschefback(CPUMIPSState
*env
)
811 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
812 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
814 if (other_tc
== other
->current_tc
)
815 return other
->active_tc
.CP0_TCScheFBack
;
817 return other
->tcs
[other_tc
].CP0_TCScheFBack
;
820 target_ulong
helper_mfc0_count(CPUMIPSState
*env
)
822 return (int32_t)cpu_mips_get_count(env
);
825 target_ulong
helper_mftc0_entryhi(CPUMIPSState
*env
)
827 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
828 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
830 return other
->CP0_EntryHi
;
833 target_ulong
helper_mftc0_cause(CPUMIPSState
*env
)
835 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
837 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
839 if (other_tc
== other
->current_tc
) {
840 tccause
= other
->CP0_Cause
;
842 tccause
= other
->CP0_Cause
;
848 target_ulong
helper_mftc0_status(CPUMIPSState
*env
)
850 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
851 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
853 return other
->CP0_Status
;
856 target_ulong
helper_mfc0_lladdr(CPUMIPSState
*env
)
858 return (int32_t)(env
->lladdr
>> env
->CP0_LLAddr_shift
);
861 target_ulong
helper_mfc0_watchlo(CPUMIPSState
*env
, uint32_t sel
)
863 return (int32_t)env
->CP0_WatchLo
[sel
];
866 target_ulong
helper_mfc0_watchhi(CPUMIPSState
*env
, uint32_t sel
)
868 return env
->CP0_WatchHi
[sel
];
871 target_ulong
helper_mfc0_debug(CPUMIPSState
*env
)
873 target_ulong t0
= env
->CP0_Debug
;
874 if (env
->hflags
& MIPS_HFLAG_DM
)
880 target_ulong
helper_mftc0_debug(CPUMIPSState
*env
)
882 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
884 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
886 if (other_tc
== other
->current_tc
)
887 tcstatus
= other
->active_tc
.CP0_Debug_tcstatus
;
889 tcstatus
= other
->tcs
[other_tc
].CP0_Debug_tcstatus
;
891 /* XXX: Might be wrong, check with EJTAG spec. */
892 return (other
->CP0_Debug
& ~((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
))) |
893 (tcstatus
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
)));
896 #if defined(TARGET_MIPS64)
897 target_ulong
helper_dmfc0_tcrestart(CPUMIPSState
*env
)
899 return env
->active_tc
.PC
;
902 target_ulong
helper_dmfc0_tchalt(CPUMIPSState
*env
)
904 return env
->active_tc
.CP0_TCHalt
;
907 target_ulong
helper_dmfc0_tccontext(CPUMIPSState
*env
)
909 return env
->active_tc
.CP0_TCContext
;
912 target_ulong
helper_dmfc0_tcschedule(CPUMIPSState
*env
)
914 return env
->active_tc
.CP0_TCSchedule
;
917 target_ulong
helper_dmfc0_tcschefback(CPUMIPSState
*env
)
919 return env
->active_tc
.CP0_TCScheFBack
;
922 target_ulong
helper_dmfc0_lladdr(CPUMIPSState
*env
)
924 return env
->lladdr
>> env
->CP0_LLAddr_shift
;
927 target_ulong
helper_dmfc0_watchlo(CPUMIPSState
*env
, uint32_t sel
)
929 return env
->CP0_WatchLo
[sel
];
931 #endif /* TARGET_MIPS64 */
933 void helper_mtc0_index(CPUMIPSState
*env
, target_ulong arg1
)
935 uint32_t index_p
= env
->CP0_Index
& 0x80000000;
936 uint32_t tlb_index
= arg1
& 0x7fffffff;
937 if (tlb_index
< env
->tlb
->nb_tlb
) {
938 if (env
->insn_flags
& ISA_MIPS32R6
) {
939 index_p
|= arg1
& 0x80000000;
941 env
->CP0_Index
= index_p
| tlb_index
;
945 void helper_mtc0_mvpcontrol(CPUMIPSState
*env
, target_ulong arg1
)
950 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
))
951 mask
|= (1 << CP0MVPCo_CPA
) | (1 << CP0MVPCo_VPC
) |
953 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
954 mask
|= (1 << CP0MVPCo_STLB
);
955 newval
= (env
->mvp
->CP0_MVPControl
& ~mask
) | (arg1
& mask
);
957 // TODO: Enable/disable shared TLB, enable/disable VPEs.
959 env
->mvp
->CP0_MVPControl
= newval
;
962 void helper_mtc0_vpecontrol(CPUMIPSState
*env
, target_ulong arg1
)
967 mask
= (1 << CP0VPECo_YSI
) | (1 << CP0VPECo_GSI
) |
968 (1 << CP0VPECo_TE
) | (0xff << CP0VPECo_TargTC
);
969 newval
= (env
->CP0_VPEControl
& ~mask
) | (arg1
& mask
);
971 /* Yield scheduler intercept not implemented. */
972 /* Gating storage scheduler intercept not implemented. */
974 // TODO: Enable/disable TCs.
976 env
->CP0_VPEControl
= newval
;
979 void helper_mttc0_vpecontrol(CPUMIPSState
*env
, target_ulong arg1
)
981 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
982 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
986 mask
= (1 << CP0VPECo_YSI
) | (1 << CP0VPECo_GSI
) |
987 (1 << CP0VPECo_TE
) | (0xff << CP0VPECo_TargTC
);
988 newval
= (other
->CP0_VPEControl
& ~mask
) | (arg1
& mask
);
990 /* TODO: Enable/disable TCs. */
992 other
->CP0_VPEControl
= newval
;
995 target_ulong
helper_mftc0_vpecontrol(CPUMIPSState
*env
)
997 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
998 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
999 /* FIXME: Mask away return zero on read bits. */
1000 return other
->CP0_VPEControl
;
1003 target_ulong
helper_mftc0_vpeconf0(CPUMIPSState
*env
)
1005 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1006 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1008 return other
->CP0_VPEConf0
;
1011 void helper_mtc0_vpeconf0(CPUMIPSState
*env
, target_ulong arg1
)
1016 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_MVP
)) {
1017 if (env
->CP0_VPEConf0
& (1 << CP0VPEC0_VPA
))
1018 mask
|= (0xff << CP0VPEC0_XTC
);
1019 mask
|= (1 << CP0VPEC0_MVP
) | (1 << CP0VPEC0_VPA
);
1021 newval
= (env
->CP0_VPEConf0
& ~mask
) | (arg1
& mask
);
1023 // TODO: TC exclusive handling due to ERL/EXL.
1025 env
->CP0_VPEConf0
= newval
;
1028 void helper_mttc0_vpeconf0(CPUMIPSState
*env
, target_ulong arg1
)
1030 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1031 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1035 mask
|= (1 << CP0VPEC0_MVP
) | (1 << CP0VPEC0_VPA
);
1036 newval
= (other
->CP0_VPEConf0
& ~mask
) | (arg1
& mask
);
1038 /* TODO: TC exclusive handling due to ERL/EXL. */
1039 other
->CP0_VPEConf0
= newval
;
1042 void helper_mtc0_vpeconf1(CPUMIPSState
*env
, target_ulong arg1
)
1047 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1048 mask
|= (0xff << CP0VPEC1_NCX
) | (0xff << CP0VPEC1_NCP2
) |
1049 (0xff << CP0VPEC1_NCP1
);
1050 newval
= (env
->CP0_VPEConf1
& ~mask
) | (arg1
& mask
);
1052 /* UDI not implemented. */
1053 /* CP2 not implemented. */
1055 // TODO: Handle FPU (CP1) binding.
1057 env
->CP0_VPEConf1
= newval
;
1060 void helper_mtc0_yqmask(CPUMIPSState
*env
, target_ulong arg1
)
1062 /* Yield qualifier inputs not implemented. */
1063 env
->CP0_YQMask
= 0x00000000;
1066 void helper_mtc0_vpeopt(CPUMIPSState
*env
, target_ulong arg1
)
1068 env
->CP0_VPEOpt
= arg1
& 0x0000ffff;
1071 #define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
1073 void helper_mtc0_entrylo0(CPUMIPSState
*env
, target_ulong arg1
)
1075 /* 1k pages not implemented */
1076 target_ulong rxi
= arg1
& (env
->CP0_PageGrain
& (3u << CP0PG_XIE
));
1077 env
->CP0_EntryLo0
= (arg1
& MTC0_ENTRYLO_MASK(env
))
1078 | (rxi
<< (CP0EnLo_XI
- 30));
1081 #if defined(TARGET_MIPS64)
1082 #define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
1084 void helper_dmtc0_entrylo0(CPUMIPSState
*env
, uint64_t arg1
)
1086 uint64_t rxi
= arg1
& ((env
->CP0_PageGrain
& (3ull << CP0PG_XIE
)) << 32);
1087 env
->CP0_EntryLo0
= (arg1
& DMTC0_ENTRYLO_MASK(env
)) | rxi
;
1091 void helper_mtc0_tcstatus(CPUMIPSState
*env
, target_ulong arg1
)
1093 uint32_t mask
= env
->CP0_TCStatus_rw_bitmask
;
1096 newval
= (env
->active_tc
.CP0_TCStatus
& ~mask
) | (arg1
& mask
);
1098 env
->active_tc
.CP0_TCStatus
= newval
;
1099 sync_c0_tcstatus(env
, env
->current_tc
, newval
);
1102 void helper_mttc0_tcstatus(CPUMIPSState
*env
, target_ulong arg1
)
1104 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1105 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1107 if (other_tc
== other
->current_tc
)
1108 other
->active_tc
.CP0_TCStatus
= arg1
;
1110 other
->tcs
[other_tc
].CP0_TCStatus
= arg1
;
1111 sync_c0_tcstatus(other
, other_tc
, arg1
);
1114 void helper_mtc0_tcbind(CPUMIPSState
*env
, target_ulong arg1
)
1116 uint32_t mask
= (1 << CP0TCBd_TBE
);
1119 if (env
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1120 mask
|= (1 << CP0TCBd_CurVPE
);
1121 newval
= (env
->active_tc
.CP0_TCBind
& ~mask
) | (arg1
& mask
);
1122 env
->active_tc
.CP0_TCBind
= newval
;
1125 void helper_mttc0_tcbind(CPUMIPSState
*env
, target_ulong arg1
)
1127 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1128 uint32_t mask
= (1 << CP0TCBd_TBE
);
1130 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1132 if (other
->mvp
->CP0_MVPControl
& (1 << CP0MVPCo_VPC
))
1133 mask
|= (1 << CP0TCBd_CurVPE
);
1134 if (other_tc
== other
->current_tc
) {
1135 newval
= (other
->active_tc
.CP0_TCBind
& ~mask
) | (arg1
& mask
);
1136 other
->active_tc
.CP0_TCBind
= newval
;
1138 newval
= (other
->tcs
[other_tc
].CP0_TCBind
& ~mask
) | (arg1
& mask
);
1139 other
->tcs
[other_tc
].CP0_TCBind
= newval
;
1143 void helper_mtc0_tcrestart(CPUMIPSState
*env
, target_ulong arg1
)
1145 env
->active_tc
.PC
= arg1
;
1146 env
->active_tc
.CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1148 /* MIPS16 not implemented. */
1151 void helper_mttc0_tcrestart(CPUMIPSState
*env
, target_ulong arg1
)
1153 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1154 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1156 if (other_tc
== other
->current_tc
) {
1157 other
->active_tc
.PC
= arg1
;
1158 other
->active_tc
.CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1159 other
->lladdr
= 0ULL;
1160 /* MIPS16 not implemented. */
1162 other
->tcs
[other_tc
].PC
= arg1
;
1163 other
->tcs
[other_tc
].CP0_TCStatus
&= ~(1 << CP0TCSt_TDS
);
1164 other
->lladdr
= 0ULL;
1165 /* MIPS16 not implemented. */
1169 void helper_mtc0_tchalt(CPUMIPSState
*env
, target_ulong arg1
)
1171 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
1173 env
->active_tc
.CP0_TCHalt
= arg1
& 0x1;
1175 // TODO: Halt TC / Restart (if allocated+active) TC.
1176 if (env
->active_tc
.CP0_TCHalt
& 1) {
1177 mips_tc_sleep(cpu
, env
->current_tc
);
1179 mips_tc_wake(cpu
, env
->current_tc
);
1183 void helper_mttc0_tchalt(CPUMIPSState
*env
, target_ulong arg1
)
1185 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1186 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1187 MIPSCPU
*other_cpu
= mips_env_get_cpu(other
);
1189 // TODO: Halt TC / Restart (if allocated+active) TC.
1191 if (other_tc
== other
->current_tc
)
1192 other
->active_tc
.CP0_TCHalt
= arg1
;
1194 other
->tcs
[other_tc
].CP0_TCHalt
= arg1
;
1197 mips_tc_sleep(other_cpu
, other_tc
);
1199 mips_tc_wake(other_cpu
, other_tc
);
1203 void helper_mtc0_tccontext(CPUMIPSState
*env
, target_ulong arg1
)
1205 env
->active_tc
.CP0_TCContext
= arg1
;
1208 void helper_mttc0_tccontext(CPUMIPSState
*env
, target_ulong arg1
)
1210 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1211 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1213 if (other_tc
== other
->current_tc
)
1214 other
->active_tc
.CP0_TCContext
= arg1
;
1216 other
->tcs
[other_tc
].CP0_TCContext
= arg1
;
1219 void helper_mtc0_tcschedule(CPUMIPSState
*env
, target_ulong arg1
)
1221 env
->active_tc
.CP0_TCSchedule
= arg1
;
1224 void helper_mttc0_tcschedule(CPUMIPSState
*env
, target_ulong arg1
)
1226 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1227 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1229 if (other_tc
== other
->current_tc
)
1230 other
->active_tc
.CP0_TCSchedule
= arg1
;
1232 other
->tcs
[other_tc
].CP0_TCSchedule
= arg1
;
1235 void helper_mtc0_tcschefback(CPUMIPSState
*env
, target_ulong arg1
)
1237 env
->active_tc
.CP0_TCScheFBack
= arg1
;
1240 void helper_mttc0_tcschefback(CPUMIPSState
*env
, target_ulong arg1
)
1242 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1243 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1245 if (other_tc
== other
->current_tc
)
1246 other
->active_tc
.CP0_TCScheFBack
= arg1
;
1248 other
->tcs
[other_tc
].CP0_TCScheFBack
= arg1
;
1251 void helper_mtc0_entrylo1(CPUMIPSState
*env
, target_ulong arg1
)
1253 /* 1k pages not implemented */
1254 target_ulong rxi
= arg1
& (env
->CP0_PageGrain
& (3u << CP0PG_XIE
));
1255 env
->CP0_EntryLo1
= (arg1
& MTC0_ENTRYLO_MASK(env
))
1256 | (rxi
<< (CP0EnLo_XI
- 30));
1259 #if defined(TARGET_MIPS64)
1260 void helper_dmtc0_entrylo1(CPUMIPSState
*env
, uint64_t arg1
)
1262 uint64_t rxi
= arg1
& ((env
->CP0_PageGrain
& (3ull << CP0PG_XIE
)) << 32);
1263 env
->CP0_EntryLo1
= (arg1
& DMTC0_ENTRYLO_MASK(env
)) | rxi
;
1267 void helper_mtc0_context(CPUMIPSState
*env
, target_ulong arg1
)
1269 env
->CP0_Context
= (env
->CP0_Context
& 0x007FFFFF) | (arg1
& ~0x007FFFFF);
1272 void helper_mtc0_pagemask(CPUMIPSState
*env
, target_ulong arg1
)
1274 uint64_t mask
= arg1
>> (TARGET_PAGE_BITS
+ 1);
1275 if (!(env
->insn_flags
& ISA_MIPS32R6
) || (arg1
== ~0) ||
1276 (mask
== 0x0000 || mask
== 0x0003 || mask
== 0x000F ||
1277 mask
== 0x003F || mask
== 0x00FF || mask
== 0x03FF ||
1278 mask
== 0x0FFF || mask
== 0x3FFF || mask
== 0xFFFF)) {
1279 env
->CP0_PageMask
= arg1
& (0x1FFFFFFF & (TARGET_PAGE_MASK
<< 1));
1283 void helper_mtc0_pagegrain(CPUMIPSState
*env
, target_ulong arg1
)
1285 /* SmartMIPS not implemented */
1286 /* 1k pages not implemented */
1287 env
->CP0_PageGrain
= (arg1
& env
->CP0_PageGrain_rw_bitmask
) |
1288 (env
->CP0_PageGrain
& ~env
->CP0_PageGrain_rw_bitmask
);
1289 compute_hflags(env
);
1290 restore_pamask(env
);
1293 void helper_mtc0_wired(CPUMIPSState
*env
, target_ulong arg1
)
1295 if (env
->insn_flags
& ISA_MIPS32R6
) {
1296 if (arg1
< env
->tlb
->nb_tlb
) {
1297 env
->CP0_Wired
= arg1
;
1300 env
->CP0_Wired
= arg1
% env
->tlb
->nb_tlb
;
1304 void helper_mtc0_srsconf0(CPUMIPSState
*env
, target_ulong arg1
)
1306 env
->CP0_SRSConf0
|= arg1
& env
->CP0_SRSConf0_rw_bitmask
;
1309 void helper_mtc0_srsconf1(CPUMIPSState
*env
, target_ulong arg1
)
1311 env
->CP0_SRSConf1
|= arg1
& env
->CP0_SRSConf1_rw_bitmask
;
1314 void helper_mtc0_srsconf2(CPUMIPSState
*env
, target_ulong arg1
)
1316 env
->CP0_SRSConf2
|= arg1
& env
->CP0_SRSConf2_rw_bitmask
;
1319 void helper_mtc0_srsconf3(CPUMIPSState
*env
, target_ulong arg1
)
1321 env
->CP0_SRSConf3
|= arg1
& env
->CP0_SRSConf3_rw_bitmask
;
1324 void helper_mtc0_srsconf4(CPUMIPSState
*env
, target_ulong arg1
)
1326 env
->CP0_SRSConf4
|= arg1
& env
->CP0_SRSConf4_rw_bitmask
;
1329 void helper_mtc0_hwrena(CPUMIPSState
*env
, target_ulong arg1
)
1331 uint32_t mask
= 0x0000000F;
1333 if (env
->CP0_Config3
& (1 << CP0C3_ULRI
)) {
1336 if (arg1
& (1 << 29)) {
1337 env
->hflags
|= MIPS_HFLAG_HWRENA_ULR
;
1339 env
->hflags
&= ~MIPS_HFLAG_HWRENA_ULR
;
1343 env
->CP0_HWREna
= arg1
& mask
;
1346 void helper_mtc0_count(CPUMIPSState
*env
, target_ulong arg1
)
1348 cpu_mips_store_count(env
, arg1
);
1351 void helper_mtc0_entryhi(CPUMIPSState
*env
, target_ulong arg1
)
1353 target_ulong old
, val
, mask
;
1354 mask
= (TARGET_PAGE_MASK
<< 1) | 0xFF;
1355 if (((env
->CP0_Config4
>> CP0C4_IE
) & 0x3) >= 2) {
1356 mask
|= 1 << CP0EnHi_EHINV
;
1359 /* 1k pages not implemented */
1360 #if defined(TARGET_MIPS64)
1361 if (env
->insn_flags
& ISA_MIPS32R6
) {
1362 int entryhi_r
= extract64(arg1
, 62, 2);
1363 int config0_at
= extract32(env
->CP0_Config0
, 13, 2);
1364 bool no_supervisor
= (env
->CP0_Status_rw_bitmask
& 0x8) == 0;
1365 if ((entryhi_r
== 2) ||
1366 (entryhi_r
== 1 && (no_supervisor
|| config0_at
== 1))) {
1367 /* skip EntryHi.R field if new value is reserved */
1368 mask
&= ~(0x3ull
<< 62);
1371 mask
&= env
->SEGMask
;
1373 old
= env
->CP0_EntryHi
;
1374 val
= (arg1
& mask
) | (old
& ~mask
);
1375 env
->CP0_EntryHi
= val
;
1376 if (env
->CP0_Config3
& (1 << CP0C3_MT
)) {
1377 sync_c0_entryhi(env
, env
->current_tc
);
1379 /* If the ASID changes, flush qemu's TLB. */
1380 if ((old
& 0xFF) != (val
& 0xFF))
1381 cpu_mips_tlb_flush(env
, 1);
1384 void helper_mttc0_entryhi(CPUMIPSState
*env
, target_ulong arg1
)
1386 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1387 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1389 other
->CP0_EntryHi
= arg1
;
1390 sync_c0_entryhi(other
, other_tc
);
1393 void helper_mtc0_compare(CPUMIPSState
*env
, target_ulong arg1
)
1395 cpu_mips_store_compare(env
, arg1
);
1398 void helper_mtc0_status(CPUMIPSState
*env
, target_ulong arg1
)
1400 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
1403 old
= env
->CP0_Status
;
1404 cpu_mips_store_status(env
, arg1
);
1405 val
= env
->CP0_Status
;
1407 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
1408 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1409 old
, old
& env
->CP0_Cause
& CP0Ca_IP_mask
,
1410 val
, val
& env
->CP0_Cause
& CP0Ca_IP_mask
,
1412 switch (env
->hflags
& MIPS_HFLAG_KSU
) {
1413 case MIPS_HFLAG_UM
: qemu_log(", UM\n"); break;
1414 case MIPS_HFLAG_SM
: qemu_log(", SM\n"); break;
1415 case MIPS_HFLAG_KM
: qemu_log("\n"); break;
1417 cpu_abort(CPU(cpu
), "Invalid MMU mode!\n");
1423 void helper_mttc0_status(CPUMIPSState
*env
, target_ulong arg1
)
1425 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1426 uint32_t mask
= env
->CP0_Status_rw_bitmask
& ~0xf1000018;
1427 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1429 other
->CP0_Status
= (other
->CP0_Status
& ~mask
) | (arg1
& mask
);
1430 sync_c0_status(env
, other
, other_tc
);
1433 void helper_mtc0_intctl(CPUMIPSState
*env
, target_ulong arg1
)
1435 env
->CP0_IntCtl
= (env
->CP0_IntCtl
& ~0x000003e0) | (arg1
& 0x000003e0);
1438 void helper_mtc0_srsctl(CPUMIPSState
*env
, target_ulong arg1
)
1440 uint32_t mask
= (0xf << CP0SRSCtl_ESS
) | (0xf << CP0SRSCtl_PSS
);
1441 env
->CP0_SRSCtl
= (env
->CP0_SRSCtl
& ~mask
) | (arg1
& mask
);
1444 void helper_mtc0_cause(CPUMIPSState
*env
, target_ulong arg1
)
1446 cpu_mips_store_cause(env
, arg1
);
1449 void helper_mttc0_cause(CPUMIPSState
*env
, target_ulong arg1
)
1451 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1452 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1454 cpu_mips_store_cause(other
, arg1
);
1457 target_ulong
helper_mftc0_epc(CPUMIPSState
*env
)
1459 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1460 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1462 return other
->CP0_EPC
;
1465 target_ulong
helper_mftc0_ebase(CPUMIPSState
*env
)
1467 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1468 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1470 return other
->CP0_EBase
;
1473 void helper_mtc0_ebase(CPUMIPSState
*env
, target_ulong arg1
)
1475 env
->CP0_EBase
= (env
->CP0_EBase
& ~0x3FFFF000) | (arg1
& 0x3FFFF000);
1478 void helper_mttc0_ebase(CPUMIPSState
*env
, target_ulong arg1
)
1480 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1481 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1482 other
->CP0_EBase
= (other
->CP0_EBase
& ~0x3FFFF000) | (arg1
& 0x3FFFF000);
1485 target_ulong
helper_mftc0_configx(CPUMIPSState
*env
, target_ulong idx
)
1487 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1488 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1491 case 0: return other
->CP0_Config0
;
1492 case 1: return other
->CP0_Config1
;
1493 case 2: return other
->CP0_Config2
;
1494 case 3: return other
->CP0_Config3
;
1495 /* 4 and 5 are reserved. */
1496 case 6: return other
->CP0_Config6
;
1497 case 7: return other
->CP0_Config7
;
1504 void helper_mtc0_config0(CPUMIPSState
*env
, target_ulong arg1
)
1506 env
->CP0_Config0
= (env
->CP0_Config0
& 0x81FFFFF8) | (arg1
& 0x00000007);
1509 void helper_mtc0_config2(CPUMIPSState
*env
, target_ulong arg1
)
1511 /* tertiary/secondary caches not implemented */
1512 env
->CP0_Config2
= (env
->CP0_Config2
& 0x8FFF0FFF);
1515 void helper_mtc0_config3(CPUMIPSState
*env
, target_ulong arg1
)
1517 if (env
->insn_flags
& ASE_MICROMIPS
) {
1518 env
->CP0_Config3
= (env
->CP0_Config3
& ~(1 << CP0C3_ISA_ON_EXC
)) |
1519 (arg1
& (1 << CP0C3_ISA_ON_EXC
));
1523 void helper_mtc0_config4(CPUMIPSState
*env
, target_ulong arg1
)
1525 env
->CP0_Config4
= (env
->CP0_Config4
& (~env
->CP0_Config4_rw_bitmask
)) |
1526 (arg1
& env
->CP0_Config4_rw_bitmask
);
1529 void helper_mtc0_config5(CPUMIPSState
*env
, target_ulong arg1
)
1531 env
->CP0_Config5
= (env
->CP0_Config5
& (~env
->CP0_Config5_rw_bitmask
)) |
1532 (arg1
& env
->CP0_Config5_rw_bitmask
);
1533 compute_hflags(env
);
1536 void helper_mtc0_lladdr(CPUMIPSState
*env
, target_ulong arg1
)
1538 target_long mask
= env
->CP0_LLAddr_rw_bitmask
;
1539 arg1
= arg1
<< env
->CP0_LLAddr_shift
;
1540 env
->lladdr
= (env
->lladdr
& ~mask
) | (arg1
& mask
);
1543 void helper_mtc0_watchlo(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1545 /* Watch exceptions for instructions, data loads, data stores
1547 env
->CP0_WatchLo
[sel
] = (arg1
& ~0x7);
1550 void helper_mtc0_watchhi(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1552 env
->CP0_WatchHi
[sel
] = (arg1
& 0x40FF0FF8);
1553 env
->CP0_WatchHi
[sel
] &= ~(env
->CP0_WatchHi
[sel
] & arg1
& 0x7);
1556 void helper_mtc0_xcontext(CPUMIPSState
*env
, target_ulong arg1
)
1558 target_ulong mask
= (1ULL << (env
->SEGBITS
- 7)) - 1;
1559 env
->CP0_XContext
= (env
->CP0_XContext
& mask
) | (arg1
& ~mask
);
1562 void helper_mtc0_framemask(CPUMIPSState
*env
, target_ulong arg1
)
1564 env
->CP0_Framemask
= arg1
; /* XXX */
1567 void helper_mtc0_debug(CPUMIPSState
*env
, target_ulong arg1
)
1569 env
->CP0_Debug
= (env
->CP0_Debug
& 0x8C03FC1F) | (arg1
& 0x13300120);
1570 if (arg1
& (1 << CP0DB_DM
))
1571 env
->hflags
|= MIPS_HFLAG_DM
;
1573 env
->hflags
&= ~MIPS_HFLAG_DM
;
1576 void helper_mttc0_debug(CPUMIPSState
*env
, target_ulong arg1
)
1578 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1579 uint32_t val
= arg1
& ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
));
1580 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1582 /* XXX: Might be wrong, check with EJTAG spec. */
1583 if (other_tc
== other
->current_tc
)
1584 other
->active_tc
.CP0_Debug_tcstatus
= val
;
1586 other
->tcs
[other_tc
].CP0_Debug_tcstatus
= val
;
1587 other
->CP0_Debug
= (other
->CP0_Debug
&
1588 ((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
))) |
1589 (arg1
& ~((1 << CP0DB_SSt
) | (1 << CP0DB_Halt
)));
1592 void helper_mtc0_performance0(CPUMIPSState
*env
, target_ulong arg1
)
1594 env
->CP0_Performance0
= arg1
& 0x000007ff;
1597 void helper_mtc0_taglo(CPUMIPSState
*env
, target_ulong arg1
)
1599 env
->CP0_TagLo
= arg1
& 0xFFFFFCF6;
1602 void helper_mtc0_datalo(CPUMIPSState
*env
, target_ulong arg1
)
1604 env
->CP0_DataLo
= arg1
; /* XXX */
1607 void helper_mtc0_taghi(CPUMIPSState
*env
, target_ulong arg1
)
1609 env
->CP0_TagHi
= arg1
; /* XXX */
1612 void helper_mtc0_datahi(CPUMIPSState
*env
, target_ulong arg1
)
1614 env
->CP0_DataHi
= arg1
; /* XXX */
1617 /* MIPS MT functions */
1618 target_ulong
helper_mftgpr(CPUMIPSState
*env
, uint32_t sel
)
1620 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1621 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1623 if (other_tc
== other
->current_tc
)
1624 return other
->active_tc
.gpr
[sel
];
1626 return other
->tcs
[other_tc
].gpr
[sel
];
1629 target_ulong
helper_mftlo(CPUMIPSState
*env
, uint32_t sel
)
1631 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1632 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1634 if (other_tc
== other
->current_tc
)
1635 return other
->active_tc
.LO
[sel
];
1637 return other
->tcs
[other_tc
].LO
[sel
];
1640 target_ulong
helper_mfthi(CPUMIPSState
*env
, uint32_t sel
)
1642 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1643 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1645 if (other_tc
== other
->current_tc
)
1646 return other
->active_tc
.HI
[sel
];
1648 return other
->tcs
[other_tc
].HI
[sel
];
1651 target_ulong
helper_mftacx(CPUMIPSState
*env
, uint32_t sel
)
1653 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1654 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1656 if (other_tc
== other
->current_tc
)
1657 return other
->active_tc
.ACX
[sel
];
1659 return other
->tcs
[other_tc
].ACX
[sel
];
1662 target_ulong
helper_mftdsp(CPUMIPSState
*env
)
1664 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1665 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1667 if (other_tc
== other
->current_tc
)
1668 return other
->active_tc
.DSPControl
;
1670 return other
->tcs
[other_tc
].DSPControl
;
1673 void helper_mttgpr(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1675 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1676 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1678 if (other_tc
== other
->current_tc
)
1679 other
->active_tc
.gpr
[sel
] = arg1
;
1681 other
->tcs
[other_tc
].gpr
[sel
] = arg1
;
1684 void helper_mttlo(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1686 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1687 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1689 if (other_tc
== other
->current_tc
)
1690 other
->active_tc
.LO
[sel
] = arg1
;
1692 other
->tcs
[other_tc
].LO
[sel
] = arg1
;
1695 void helper_mtthi(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1697 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1698 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1700 if (other_tc
== other
->current_tc
)
1701 other
->active_tc
.HI
[sel
] = arg1
;
1703 other
->tcs
[other_tc
].HI
[sel
] = arg1
;
1706 void helper_mttacx(CPUMIPSState
*env
, target_ulong arg1
, uint32_t sel
)
1708 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1709 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1711 if (other_tc
== other
->current_tc
)
1712 other
->active_tc
.ACX
[sel
] = arg1
;
1714 other
->tcs
[other_tc
].ACX
[sel
] = arg1
;
1717 void helper_mttdsp(CPUMIPSState
*env
, target_ulong arg1
)
1719 int other_tc
= env
->CP0_VPEControl
& (0xff << CP0VPECo_TargTC
);
1720 CPUMIPSState
*other
= mips_cpu_map_tc(env
, &other_tc
);
1722 if (other_tc
== other
->current_tc
)
1723 other
->active_tc
.DSPControl
= arg1
;
1725 other
->tcs
[other_tc
].DSPControl
= arg1
;
1728 /* MIPS MT functions */
1729 target_ulong
helper_dmt(void)
1735 target_ulong
helper_emt(void)
1741 target_ulong
helper_dvpe(CPUMIPSState
*env
)
1743 CPUState
*other_cs
= first_cpu
;
1744 target_ulong prev
= env
->mvp
->CP0_MVPControl
;
1746 CPU_FOREACH(other_cs
) {
1747 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
1748 /* Turn off all VPEs except the one executing the dvpe. */
1749 if (&other_cpu
->env
!= env
) {
1750 other_cpu
->env
.mvp
->CP0_MVPControl
&= ~(1 << CP0MVPCo_EVP
);
1751 mips_vpe_sleep(other_cpu
);
1757 target_ulong
helper_evpe(CPUMIPSState
*env
)
1759 CPUState
*other_cs
= first_cpu
;
1760 target_ulong prev
= env
->mvp
->CP0_MVPControl
;
1762 CPU_FOREACH(other_cs
) {
1763 MIPSCPU
*other_cpu
= MIPS_CPU(other_cs
);
1765 if (&other_cpu
->env
!= env
1766 /* If the VPE is WFI, don't disturb its sleep. */
1767 && !mips_vpe_is_wfi(other_cpu
)) {
1768 /* Enable the VPE. */
1769 other_cpu
->env
.mvp
->CP0_MVPControl
|= (1 << CP0MVPCo_EVP
);
1770 mips_vpe_wake(other_cpu
); /* And wake it up. */
1775 #endif /* !CONFIG_USER_ONLY */
1777 void helper_fork(target_ulong arg1
, target_ulong arg2
)
1779 fprintf(stderr
, "%s:%u - %s\n", __FILE__
, __LINE__
, __func__
);
1780 // arg1 = rt, arg2 = rs
1781 // TODO: store to TC register, assert to detect test cases.
1782 g_assert_not_reached();
1785 target_ulong
helper_yield(CPUMIPSState
*env
, target_ulong arg
)
1787 target_long arg1
= arg
;
1790 /* No scheduling policy implemented. */
1792 if (env
->CP0_VPEControl
& (1 << CP0VPECo_YSI
) &&
1793 env
->active_tc
.CP0_TCStatus
& (1 << CP0TCSt_DT
)) {
1794 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
1795 env
->CP0_VPEControl
|= 4 << CP0VPECo_EXCPT
;
1796 helper_raise_exception(env
, EXCP_THREAD
);
1799 } else if (arg1
== 0) {
1800 if (0 /* TODO: TC underflow */) {
1801 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
1802 helper_raise_exception(env
, EXCP_THREAD
);
1804 // TODO: Deallocate TC
1806 } else if (arg1
> 0) {
1807 /* Yield qualifier inputs not implemented. */
1808 env
->CP0_VPEControl
&= ~(0x7 << CP0VPECo_EXCPT
);
1809 env
->CP0_VPEControl
|= 2 << CP0VPECo_EXCPT
;
1810 helper_raise_exception(env
, EXCP_THREAD
);
1812 return env
->CP0_YQMask
;
1815 #ifndef CONFIG_USER_ONLY
1816 /* TLB management */
1817 static void cpu_mips_tlb_flush (CPUMIPSState
*env
, int flush_global
)
1819 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
1821 /* Flush qemu's TLB and discard all shadowed entries. */
1822 tlb_flush(CPU(cpu
), flush_global
);
1823 env
->tlb
->tlb_in_use
= env
->tlb
->nb_tlb
;
1826 static void r4k_mips_tlb_flush_extra (CPUMIPSState
*env
, int first
)
1828 /* Discard entries from env->tlb[first] onwards. */
1829 while (env
->tlb
->tlb_in_use
> first
) {
1830 r4k_invalidate_tlb(env
, --env
->tlb
->tlb_in_use
, 0);
1834 static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo
)
1836 #if defined(TARGET_MIPS64)
1837 return extract64(entrylo
, 6, 54);
1839 return extract64(entrylo
, 6, 24) | /* PFN */
1840 (extract64(entrylo
, 32, 32) << 24); /* PFNX */
1844 static void r4k_fill_tlb(CPUMIPSState
*env
, int idx
)
1848 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1849 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
1850 if (env
->CP0_EntryHi
& (1 << CP0EnHi_EHINV
)) {
1855 tlb
->VPN
= env
->CP0_EntryHi
& (TARGET_PAGE_MASK
<< 1);
1856 #if defined(TARGET_MIPS64)
1857 tlb
->VPN
&= env
->SEGMask
;
1859 tlb
->ASID
= env
->CP0_EntryHi
& 0xFF;
1860 tlb
->PageMask
= env
->CP0_PageMask
;
1861 tlb
->G
= env
->CP0_EntryLo0
& env
->CP0_EntryLo1
& 1;
1862 tlb
->V0
= (env
->CP0_EntryLo0
& 2) != 0;
1863 tlb
->D0
= (env
->CP0_EntryLo0
& 4) != 0;
1864 tlb
->C0
= (env
->CP0_EntryLo0
>> 3) & 0x7;
1865 tlb
->XI0
= (env
->CP0_EntryLo0
>> CP0EnLo_XI
) & 1;
1866 tlb
->RI0
= (env
->CP0_EntryLo0
>> CP0EnLo_RI
) & 1;
1867 tlb
->PFN
[0] = get_tlb_pfn_from_entrylo(env
->CP0_EntryLo0
) << 12;
1868 tlb
->V1
= (env
->CP0_EntryLo1
& 2) != 0;
1869 tlb
->D1
= (env
->CP0_EntryLo1
& 4) != 0;
1870 tlb
->C1
= (env
->CP0_EntryLo1
>> 3) & 0x7;
1871 tlb
->XI1
= (env
->CP0_EntryLo1
>> CP0EnLo_XI
) & 1;
1872 tlb
->RI1
= (env
->CP0_EntryLo1
>> CP0EnLo_RI
) & 1;
1873 tlb
->PFN
[1] = get_tlb_pfn_from_entrylo(env
->CP0_EntryLo1
) << 12;
1876 void r4k_helper_tlbinv(CPUMIPSState
*env
)
1880 uint8_t ASID
= env
->CP0_EntryHi
& 0xFF;
1882 for (idx
= 0; idx
< env
->tlb
->nb_tlb
; idx
++) {
1883 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
1884 if (!tlb
->G
&& tlb
->ASID
== ASID
) {
1888 cpu_mips_tlb_flush(env
, 1);
1891 void r4k_helper_tlbinvf(CPUMIPSState
*env
)
1895 for (idx
= 0; idx
< env
->tlb
->nb_tlb
; idx
++) {
1896 env
->tlb
->mmu
.r4k
.tlb
[idx
].EHINV
= 1;
1898 cpu_mips_tlb_flush(env
, 1);
1901 void r4k_helper_tlbwi(CPUMIPSState
*env
)
1907 bool G
, V0
, D0
, V1
, D1
;
1909 idx
= (env
->CP0_Index
& ~0x80000000) % env
->tlb
->nb_tlb
;
1910 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
1911 VPN
= env
->CP0_EntryHi
& (TARGET_PAGE_MASK
<< 1);
1912 #if defined(TARGET_MIPS64)
1913 VPN
&= env
->SEGMask
;
1915 ASID
= env
->CP0_EntryHi
& 0xff;
1916 G
= env
->CP0_EntryLo0
& env
->CP0_EntryLo1
& 1;
1917 V0
= (env
->CP0_EntryLo0
& 2) != 0;
1918 D0
= (env
->CP0_EntryLo0
& 4) != 0;
1919 V1
= (env
->CP0_EntryLo1
& 2) != 0;
1920 D1
= (env
->CP0_EntryLo1
& 4) != 0;
1922 /* Discard cached TLB entries, unless tlbwi is just upgrading access
1923 permissions on the current entry. */
1924 if (tlb
->VPN
!= VPN
|| tlb
->ASID
!= ASID
|| tlb
->G
!= G
||
1925 (tlb
->V0
&& !V0
) || (tlb
->D0
&& !D0
) ||
1926 (tlb
->V1
&& !V1
) || (tlb
->D1
&& !D1
)) {
1927 r4k_mips_tlb_flush_extra(env
, env
->tlb
->nb_tlb
);
1930 r4k_invalidate_tlb(env
, idx
, 0);
1931 r4k_fill_tlb(env
, idx
);
1934 void r4k_helper_tlbwr(CPUMIPSState
*env
)
1936 int r
= cpu_mips_get_random(env
);
1938 r4k_invalidate_tlb(env
, r
, 1);
1939 r4k_fill_tlb(env
, r
);
1942 void r4k_helper_tlbp(CPUMIPSState
*env
)
1951 ASID
= env
->CP0_EntryHi
& 0xFF;
1952 for (i
= 0; i
< env
->tlb
->nb_tlb
; i
++) {
1953 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
1954 /* 1k pages are not supported. */
1955 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
1956 tag
= env
->CP0_EntryHi
& ~mask
;
1957 VPN
= tlb
->VPN
& ~mask
;
1958 #if defined(TARGET_MIPS64)
1959 tag
&= env
->SEGMask
;
1961 /* Check ASID, virtual page number & size */
1962 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && VPN
== tag
&& !tlb
->EHINV
) {
1968 if (i
== env
->tlb
->nb_tlb
) {
1969 /* No match. Discard any shadow entries, if any of them match. */
1970 for (i
= env
->tlb
->nb_tlb
; i
< env
->tlb
->tlb_in_use
; i
++) {
1971 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[i
];
1972 /* 1k pages are not supported. */
1973 mask
= tlb
->PageMask
| ~(TARGET_PAGE_MASK
<< 1);
1974 tag
= env
->CP0_EntryHi
& ~mask
;
1975 VPN
= tlb
->VPN
& ~mask
;
1976 #if defined(TARGET_MIPS64)
1977 tag
&= env
->SEGMask
;
1979 /* Check ASID, virtual page number & size */
1980 if ((tlb
->G
== 1 || tlb
->ASID
== ASID
) && VPN
== tag
) {
1981 r4k_mips_tlb_flush_extra (env
, i
);
1986 env
->CP0_Index
|= 0x80000000;
1990 static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn
)
1992 #if defined(TARGET_MIPS64)
1993 return tlb_pfn
<< 6;
1995 return (extract64(tlb_pfn
, 0, 24) << 6) | /* PFN */
1996 (extract64(tlb_pfn
, 24, 32) << 32); /* PFNX */
2000 void r4k_helper_tlbr(CPUMIPSState
*env
)
2006 ASID
= env
->CP0_EntryHi
& 0xFF;
2007 idx
= (env
->CP0_Index
& ~0x80000000) % env
->tlb
->nb_tlb
;
2008 tlb
= &env
->tlb
->mmu
.r4k
.tlb
[idx
];
2010 /* If this will change the current ASID, flush qemu's TLB. */
2011 if (ASID
!= tlb
->ASID
)
2012 cpu_mips_tlb_flush (env
, 1);
2014 r4k_mips_tlb_flush_extra(env
, env
->tlb
->nb_tlb
);
2017 env
->CP0_EntryHi
= 1 << CP0EnHi_EHINV
;
2018 env
->CP0_PageMask
= 0;
2019 env
->CP0_EntryLo0
= 0;
2020 env
->CP0_EntryLo1
= 0;
2022 env
->CP0_EntryHi
= tlb
->VPN
| tlb
->ASID
;
2023 env
->CP0_PageMask
= tlb
->PageMask
;
2024 env
->CP0_EntryLo0
= tlb
->G
| (tlb
->V0
<< 1) | (tlb
->D0
<< 2) |
2025 ((uint64_t)tlb
->RI0
<< CP0EnLo_RI
) |
2026 ((uint64_t)tlb
->XI0
<< CP0EnLo_XI
) | (tlb
->C0
<< 3) |
2027 get_entrylo_pfn_from_tlb(tlb
->PFN
[0] >> 12);
2028 env
->CP0_EntryLo1
= tlb
->G
| (tlb
->V1
<< 1) | (tlb
->D1
<< 2) |
2029 ((uint64_t)tlb
->RI1
<< CP0EnLo_RI
) |
2030 ((uint64_t)tlb
->XI1
<< CP0EnLo_XI
) | (tlb
->C1
<< 3) |
2031 get_entrylo_pfn_from_tlb(tlb
->PFN
[1] >> 12);
2035 void helper_tlbwi(CPUMIPSState
*env
)
2037 env
->tlb
->helper_tlbwi(env
);
2040 void helper_tlbwr(CPUMIPSState
*env
)
2042 env
->tlb
->helper_tlbwr(env
);
2045 void helper_tlbp(CPUMIPSState
*env
)
2047 env
->tlb
->helper_tlbp(env
);
2050 void helper_tlbr(CPUMIPSState
*env
)
2052 env
->tlb
->helper_tlbr(env
);
2055 void helper_tlbinv(CPUMIPSState
*env
)
2057 env
->tlb
->helper_tlbinv(env
);
2060 void helper_tlbinvf(CPUMIPSState
*env
)
2062 env
->tlb
->helper_tlbinvf(env
);
2066 target_ulong
helper_di(CPUMIPSState
*env
)
2068 target_ulong t0
= env
->CP0_Status
;
2070 env
->CP0_Status
= t0
& ~(1 << CP0St_IE
);
2074 target_ulong
helper_ei(CPUMIPSState
*env
)
2076 target_ulong t0
= env
->CP0_Status
;
2078 env
->CP0_Status
= t0
| (1 << CP0St_IE
);
2082 static void debug_pre_eret(CPUMIPSState
*env
)
2084 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
2085 qemu_log("ERET: PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
,
2086 env
->active_tc
.PC
, env
->CP0_EPC
);
2087 if (env
->CP0_Status
& (1 << CP0St_ERL
))
2088 qemu_log(" ErrorEPC " TARGET_FMT_lx
, env
->CP0_ErrorEPC
);
2089 if (env
->hflags
& MIPS_HFLAG_DM
)
2090 qemu_log(" DEPC " TARGET_FMT_lx
, env
->CP0_DEPC
);
2095 static void debug_post_eret(CPUMIPSState
*env
)
2097 MIPSCPU
*cpu
= mips_env_get_cpu(env
);
2099 if (qemu_loglevel_mask(CPU_LOG_EXEC
)) {
2100 qemu_log(" => PC " TARGET_FMT_lx
" EPC " TARGET_FMT_lx
,
2101 env
->active_tc
.PC
, env
->CP0_EPC
);
2102 if (env
->CP0_Status
& (1 << CP0St_ERL
))
2103 qemu_log(" ErrorEPC " TARGET_FMT_lx
, env
->CP0_ErrorEPC
);
2104 if (env
->hflags
& MIPS_HFLAG_DM
)
2105 qemu_log(" DEPC " TARGET_FMT_lx
, env
->CP0_DEPC
);
2106 switch (env
->hflags
& MIPS_HFLAG_KSU
) {
2107 case MIPS_HFLAG_UM
: qemu_log(", UM\n"); break;
2108 case MIPS_HFLAG_SM
: qemu_log(", SM\n"); break;
2109 case MIPS_HFLAG_KM
: qemu_log("\n"); break;
2111 cpu_abort(CPU(cpu
), "Invalid MMU mode!\n");
2117 static void set_pc(CPUMIPSState
*env
, target_ulong error_pc
)
2119 env
->active_tc
.PC
= error_pc
& ~(target_ulong
)1;
2121 env
->hflags
|= MIPS_HFLAG_M16
;
2123 env
->hflags
&= ~(MIPS_HFLAG_M16
);
2127 static inline void exception_return(CPUMIPSState
*env
)
2129 debug_pre_eret(env
);
2130 if (env
->CP0_Status
& (1 << CP0St_ERL
)) {
2131 set_pc(env
, env
->CP0_ErrorEPC
);
2132 env
->CP0_Status
&= ~(1 << CP0St_ERL
);
2134 set_pc(env
, env
->CP0_EPC
);
2135 env
->CP0_Status
&= ~(1 << CP0St_EXL
);
2137 compute_hflags(env
);
2138 debug_post_eret(env
);
2141 void helper_eret(CPUMIPSState
*env
)
2143 exception_return(env
);
2147 void helper_eretnc(CPUMIPSState
*env
)
2149 exception_return(env
);
2152 void helper_deret(CPUMIPSState
*env
)
2154 debug_pre_eret(env
);
2155 set_pc(env
, env
->CP0_DEPC
);
2157 env
->hflags
&= ~MIPS_HFLAG_DM
;
2158 compute_hflags(env
);
2159 debug_post_eret(env
);
2161 #endif /* !CONFIG_USER_ONLY */
2163 target_ulong
helper_rdhwr_cpunum(CPUMIPSState
*env
)
2165 if ((env
->hflags
& MIPS_HFLAG_CP0
) ||
2166 (env
->CP0_HWREna
& (1 << 0)))
2167 return env
->CP0_EBase
& 0x3ff;
2169 helper_raise_exception(env
, EXCP_RI
);
2174 target_ulong
helper_rdhwr_synci_step(CPUMIPSState
*env
)
2176 if ((env
->hflags
& MIPS_HFLAG_CP0
) ||
2177 (env
->CP0_HWREna
& (1 << 1)))
2178 return env
->SYNCI_Step
;
2180 helper_raise_exception(env
, EXCP_RI
);
2185 target_ulong
helper_rdhwr_cc(CPUMIPSState
*env
)
2187 if ((env
->hflags
& MIPS_HFLAG_CP0
) ||
2188 (env
->CP0_HWREna
& (1 << 2)))
2189 return env
->CP0_Count
;
2191 helper_raise_exception(env
, EXCP_RI
);
2196 target_ulong
helper_rdhwr_ccres(CPUMIPSState
*env
)
2198 if ((env
->hflags
& MIPS_HFLAG_CP0
) ||
2199 (env
->CP0_HWREna
& (1 << 3)))
2202 helper_raise_exception(env
, EXCP_RI
);
2207 void helper_pmon(CPUMIPSState
*env
, int function
)
2211 case 2: /* TODO: char inbyte(int waitflag); */
2212 if (env
->active_tc
.gpr
[4] == 0)
2213 env
->active_tc
.gpr
[2] = -1;
2215 case 11: /* TODO: char inbyte (void); */
2216 env
->active_tc
.gpr
[2] = -1;
2220 printf("%c", (char)(env
->active_tc
.gpr
[4] & 0xFF));
2224 #ifndef CONFIG_USER_ONLY
2227 unsigned char *fmt
= (void *)(uintptr_t)env
->active_tc
.gpr
[4];
2235 void QEMU_NORETURN
helper_wait(CPUMIPSState
*env
)
2237 CPUState
*cs
= CPU(mips_env_get_cpu(env
));
2240 cpu_reset_interrupt(cs
, CPU_INTERRUPT_WAKE
);
2241 helper_raise_exception(env
, EXCP_HLT
);
2244 #if !defined(CONFIG_USER_ONLY)
2246 void QEMU_NORETURN
mips_cpu_do_unaligned_access(CPUState
*cs
, vaddr addr
,
2247 int access_type
, int is_user
,
2250 MIPSCPU
*cpu
= MIPS_CPU(cs
);
2251 CPUMIPSState
*env
= &cpu
->env
;
2255 env
->CP0_BadVAddr
= addr
;
2257 if (access_type
== MMU_DATA_STORE
) {
2261 if (access_type
== MMU_INST_FETCH
) {
2262 error_code
|= EXCP_INST_NOTAVAIL
;
2266 do_raise_exception_err(env
, excp
, error_code
, retaddr
);
2269 void tlb_fill(CPUState
*cs
, target_ulong addr
, int is_write
, int mmu_idx
,
2274 ret
= mips_cpu_handle_mmu_fault(cs
, addr
, is_write
, mmu_idx
);
2276 MIPSCPU
*cpu
= MIPS_CPU(cs
);
2277 CPUMIPSState
*env
= &cpu
->env
;
2279 do_raise_exception_err(env
, cs
->exception_index
,
2280 env
->error_code
, retaddr
);
2284 void mips_cpu_unassigned_access(CPUState
*cs
, hwaddr addr
,
2285 bool is_write
, bool is_exec
, int unused
,
2288 MIPSCPU
*cpu
= MIPS_CPU(cs
);
2289 CPUMIPSState
*env
= &cpu
->env
;
2292 * Raising an exception with KVM enabled will crash because it won't be from
2293 * the main execution loop so the longjmp won't have a matching setjmp.
2294 * Until we can trigger a bus error exception through KVM lets just ignore
2297 if (kvm_enabled()) {
2298 /* TODO: here a return was replaced by an assertion. */
2299 g_assert_not_reached();
2303 helper_raise_exception(env
, EXCP_IBE
);
2305 helper_raise_exception(env
, EXCP_DBE
);
2308 #endif /* !CONFIG_USER_ONLY */
2310 /* Complex FPU operations which may need stack space. */
2312 #define FLOAT_TWO32 make_float32(1 << 30)
2313 #define FLOAT_TWO64 make_float64(1ULL << 62)
2314 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2315 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2317 /* convert MIPS rounding mode in FCR31 to IEEE library */
2318 unsigned int ieee_rm
[] = {
2319 float_round_nearest_even
,
2320 float_round_to_zero
,
2325 target_ulong
helper_cfc1(CPUMIPSState
*env
, uint32_t reg
)
2327 target_ulong arg1
= 0;
2331 arg1
= (int32_t)env
->active_fpu
.fcr0
;
2334 /* UFR Support - Read Status FR */
2335 if (env
->active_fpu
.fcr0
& (1 << FCR0_UFRP
)) {
2336 if (env
->CP0_Config5
& (1 << CP0C5_UFR
)) {
2338 ((env
->CP0_Status
& (1 << CP0St_FR
)) >> CP0St_FR
);
2340 helper_raise_exception(env
, EXCP_RI
);
2345 /* FRE Support - read Config5.FRE bit */
2346 if (env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) {
2347 if (env
->CP0_Config5
& (1 << CP0C5_UFE
)) {
2348 arg1
= (env
->CP0_Config5
>> CP0C5_FRE
) & 1;
2350 helper_raise_exception(env
, EXCP_RI
);
2355 arg1
= ((env
->active_fpu
.fcr31
>> 24) & 0xfe) | ((env
->active_fpu
.fcr31
>> 23) & 0x1);
2358 arg1
= env
->active_fpu
.fcr31
& 0x0003f07c;
2361 arg1
= (env
->active_fpu
.fcr31
& 0x00000f83) | ((env
->active_fpu
.fcr31
>> 22) & 0x4);
2364 arg1
= (int32_t)env
->active_fpu
.fcr31
;
2371 void helper_ctc1(CPUMIPSState
*env
, target_ulong arg1
, uint32_t fs
, uint32_t rt
)
2375 /* UFR Alias - Reset Status FR */
2376 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_UFRP
)) && (rt
== 0))) {
2379 if (env
->CP0_Config5
& (1 << CP0C5_UFR
)) {
2380 env
->CP0_Status
&= ~(1 << CP0St_FR
);
2381 compute_hflags(env
);
2383 helper_raise_exception(env
, EXCP_RI
);
2387 /* UNFR Alias - Set Status FR */
2388 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_UFRP
)) && (rt
== 0))) {
2391 if (env
->CP0_Config5
& (1 << CP0C5_UFR
)) {
2392 env
->CP0_Status
|= (1 << CP0St_FR
);
2393 compute_hflags(env
);
2395 helper_raise_exception(env
, EXCP_RI
);
2399 /* FRE Support - clear Config5.FRE bit */
2400 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) && (rt
== 0))) {
2403 if (env
->CP0_Config5
& (1 << CP0C5_UFE
)) {
2404 env
->CP0_Config5
&= ~(1 << CP0C5_FRE
);
2405 compute_hflags(env
);
2407 helper_raise_exception(env
, EXCP_RI
);
2411 /* FRE Support - set Config5.FRE bit */
2412 if (!((env
->active_fpu
.fcr0
& (1 << FCR0_FREP
)) && (rt
== 0))) {
2415 if (env
->CP0_Config5
& (1 << CP0C5_UFE
)) {
2416 env
->CP0_Config5
|= (1 << CP0C5_FRE
);
2417 compute_hflags(env
);
2419 helper_raise_exception(env
, EXCP_RI
);
2423 if ((env
->insn_flags
& ISA_MIPS32R6
) || (arg1
& 0xffffff00)) {
2426 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0x017fffff) | ((arg1
& 0xfe) << 24) |
2427 ((arg1
& 0x1) << 23);
2430 if (arg1
& 0x007c0000)
2432 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0xfffc0f83) | (arg1
& 0x0003f07c);
2435 if (arg1
& 0x007c0000)
2437 env
->active_fpu
.fcr31
= (env
->active_fpu
.fcr31
& 0xfefff07c) | (arg1
& 0x00000f83) |
2438 ((arg1
& 0x4) << 22);
2441 if (env
->insn_flags
& ISA_MIPS32R6
) {
2442 uint32_t mask
= 0xfefc0000;
2443 env
->active_fpu
.fcr31
= (arg1
& ~mask
) |
2444 (env
->active_fpu
.fcr31
& mask
);
2445 } else if (!(arg1
& 0x007c0000)) {
2446 env
->active_fpu
.fcr31
= arg1
;
2452 /* set rounding mode */
2453 restore_rounding_mode(env
);
2454 /* set flush-to-zero mode */
2455 restore_flush_mode(env
);
2456 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2457 if ((GET_FP_ENABLE(env
->active_fpu
.fcr31
) | 0x20) & GET_FP_CAUSE(env
->active_fpu
.fcr31
)) {
2458 do_raise_exception(env
, EXCP_FPE
, GETPC());
2462 int ieee_ex_to_mips(int xcpt
)
2466 if (xcpt
& float_flag_invalid
) {
2469 if (xcpt
& float_flag_overflow
) {
2472 if (xcpt
& float_flag_underflow
) {
2473 ret
|= FP_UNDERFLOW
;
2475 if (xcpt
& float_flag_divbyzero
) {
2478 if (xcpt
& float_flag_inexact
) {
2485 static inline void update_fcr31(CPUMIPSState
*env
, uintptr_t pc
)
2487 int tmp
= ieee_ex_to_mips(get_float_exception_flags(&env
->active_fpu
.fp_status
));
2489 SET_FP_CAUSE(env
->active_fpu
.fcr31
, tmp
);
2492 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2494 if (GET_FP_ENABLE(env
->active_fpu
.fcr31
) & tmp
) {
2495 do_raise_exception(env
, EXCP_FPE
, pc
);
2497 UPDATE_FP_FLAGS(env
->active_fpu
.fcr31
, tmp
);
2503 Single precition routines have a "s" suffix, double precision a
2504 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2505 paired single lower "pl", paired single upper "pu". */
2507 /* unary operations, modifying fp status */
2508 uint64_t helper_float_sqrt_d(CPUMIPSState
*env
, uint64_t fdt0
)
2510 fdt0
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
2511 update_fcr31(env
, GETPC());
2515 uint32_t helper_float_sqrt_s(CPUMIPSState
*env
, uint32_t fst0
)
2517 fst0
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
2518 update_fcr31(env
, GETPC());
2522 uint64_t helper_float_cvtd_s(CPUMIPSState
*env
, uint32_t fst0
)
2526 fdt2
= float32_to_float64(fst0
, &env
->active_fpu
.fp_status
);
2527 update_fcr31(env
, GETPC());
2531 uint64_t helper_float_cvtd_w(CPUMIPSState
*env
, uint32_t wt0
)
2535 fdt2
= int32_to_float64(wt0
, &env
->active_fpu
.fp_status
);
2536 update_fcr31(env
, GETPC());
2540 uint64_t helper_float_cvtd_l(CPUMIPSState
*env
, uint64_t dt0
)
2544 fdt2
= int64_to_float64(dt0
, &env
->active_fpu
.fp_status
);
2545 update_fcr31(env
, GETPC());
2549 uint64_t helper_float_cvtl_d(CPUMIPSState
*env
, uint64_t fdt0
)
2553 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2554 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2555 & (float_flag_invalid
| float_flag_overflow
)) {
2556 dt2
= FP_TO_INT64_OVERFLOW
;
2558 update_fcr31(env
, GETPC());
2562 uint64_t helper_float_cvtl_s(CPUMIPSState
*env
, uint32_t fst0
)
2566 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2567 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2568 & (float_flag_invalid
| float_flag_overflow
)) {
2569 dt2
= FP_TO_INT64_OVERFLOW
;
2571 update_fcr31(env
, GETPC());
2575 uint64_t helper_float_cvtps_pw(CPUMIPSState
*env
, uint64_t dt0
)
2580 fst2
= int32_to_float32(dt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
2581 fsth2
= int32_to_float32(dt0
>> 32, &env
->active_fpu
.fp_status
);
2582 update_fcr31(env
, GETPC());
2583 return ((uint64_t)fsth2
<< 32) | fst2
;
2586 uint64_t helper_float_cvtpw_ps(CPUMIPSState
*env
, uint64_t fdt0
)
2592 wt2
= float32_to_int32(fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
2593 excp
= get_float_exception_flags(&env
->active_fpu
.fp_status
);
2594 if (excp
& (float_flag_overflow
| float_flag_invalid
)) {
2595 wt2
= FP_TO_INT32_OVERFLOW
;
2598 set_float_exception_flags(0, &env
->active_fpu
.fp_status
);
2599 wth2
= float32_to_int32(fdt0
>> 32, &env
->active_fpu
.fp_status
);
2600 excph
= get_float_exception_flags(&env
->active_fpu
.fp_status
);
2601 if (excph
& (float_flag_overflow
| float_flag_invalid
)) {
2602 wth2
= FP_TO_INT32_OVERFLOW
;
2605 set_float_exception_flags(excp
| excph
, &env
->active_fpu
.fp_status
);
2606 update_fcr31(env
, GETPC());
2608 return ((uint64_t)wth2
<< 32) | wt2
;
2611 uint32_t helper_float_cvts_d(CPUMIPSState
*env
, uint64_t fdt0
)
2615 fst2
= float64_to_float32(fdt0
, &env
->active_fpu
.fp_status
);
2616 update_fcr31(env
, GETPC());
2620 uint32_t helper_float_cvts_w(CPUMIPSState
*env
, uint32_t wt0
)
2624 fst2
= int32_to_float32(wt0
, &env
->active_fpu
.fp_status
);
2625 update_fcr31(env
, GETPC());
2629 uint32_t helper_float_cvts_l(CPUMIPSState
*env
, uint64_t dt0
)
2633 fst2
= int64_to_float32(dt0
, &env
->active_fpu
.fp_status
);
2634 update_fcr31(env
, GETPC());
2638 uint32_t helper_float_cvts_pl(CPUMIPSState
*env
, uint32_t wt0
)
2643 update_fcr31(env
, GETPC());
2647 uint32_t helper_float_cvts_pu(CPUMIPSState
*env
, uint32_t wth0
)
2652 update_fcr31(env
, GETPC());
2656 uint32_t helper_float_cvtw_s(CPUMIPSState
*env
, uint32_t fst0
)
2660 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2661 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2662 & (float_flag_invalid
| float_flag_overflow
)) {
2663 wt2
= FP_TO_INT32_OVERFLOW
;
2665 update_fcr31(env
, GETPC());
2669 uint32_t helper_float_cvtw_d(CPUMIPSState
*env
, uint64_t fdt0
)
2673 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2674 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2675 & (float_flag_invalid
| float_flag_overflow
)) {
2676 wt2
= FP_TO_INT32_OVERFLOW
;
2678 update_fcr31(env
, GETPC());
2682 uint64_t helper_float_roundl_d(CPUMIPSState
*env
, uint64_t fdt0
)
2686 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2687 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2688 restore_rounding_mode(env
);
2689 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2690 & (float_flag_invalid
| float_flag_overflow
)) {
2691 dt2
= FP_TO_INT64_OVERFLOW
;
2693 update_fcr31(env
, GETPC());
2697 uint64_t helper_float_roundl_s(CPUMIPSState
*env
, uint32_t fst0
)
2701 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2702 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2703 restore_rounding_mode(env
);
2704 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2705 & (float_flag_invalid
| float_flag_overflow
)) {
2706 dt2
= FP_TO_INT64_OVERFLOW
;
2708 update_fcr31(env
, GETPC());
2712 uint32_t helper_float_roundw_d(CPUMIPSState
*env
, uint64_t fdt0
)
2716 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2717 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2718 restore_rounding_mode(env
);
2719 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2720 & (float_flag_invalid
| float_flag_overflow
)) {
2721 wt2
= FP_TO_INT32_OVERFLOW
;
2723 update_fcr31(env
, GETPC());
2727 uint32_t helper_float_roundw_s(CPUMIPSState
*env
, uint32_t fst0
)
2731 set_float_rounding_mode(float_round_nearest_even
, &env
->active_fpu
.fp_status
);
2732 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2733 restore_rounding_mode(env
);
2734 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2735 & (float_flag_invalid
| float_flag_overflow
)) {
2736 wt2
= FP_TO_INT32_OVERFLOW
;
2738 update_fcr31(env
, GETPC());
2742 uint64_t helper_float_truncl_d(CPUMIPSState
*env
, uint64_t fdt0
)
2746 dt2
= float64_to_int64_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
2747 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2748 & (float_flag_invalid
| float_flag_overflow
)) {
2749 dt2
= FP_TO_INT64_OVERFLOW
;
2751 update_fcr31(env
, GETPC());
2755 uint64_t helper_float_truncl_s(CPUMIPSState
*env
, uint32_t fst0
)
2759 dt2
= float32_to_int64_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
2760 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2761 & (float_flag_invalid
| float_flag_overflow
)) {
2762 dt2
= FP_TO_INT64_OVERFLOW
;
2764 update_fcr31(env
, GETPC());
2768 uint32_t helper_float_truncw_d(CPUMIPSState
*env
, uint64_t fdt0
)
2772 wt2
= float64_to_int32_round_to_zero(fdt0
, &env
->active_fpu
.fp_status
);
2773 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2774 & (float_flag_invalid
| float_flag_overflow
)) {
2775 wt2
= FP_TO_INT32_OVERFLOW
;
2777 update_fcr31(env
, GETPC());
2781 uint32_t helper_float_truncw_s(CPUMIPSState
*env
, uint32_t fst0
)
2785 wt2
= float32_to_int32_round_to_zero(fst0
, &env
->active_fpu
.fp_status
);
2786 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2787 & (float_flag_invalid
| float_flag_overflow
)) {
2788 wt2
= FP_TO_INT32_OVERFLOW
;
2790 update_fcr31(env
, GETPC());
2794 uint64_t helper_float_ceill_d(CPUMIPSState
*env
, uint64_t fdt0
)
2798 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2799 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2800 restore_rounding_mode(env
);
2801 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2802 & (float_flag_invalid
| float_flag_overflow
)) {
2803 dt2
= FP_TO_INT64_OVERFLOW
;
2805 update_fcr31(env
, GETPC());
2809 uint64_t helper_float_ceill_s(CPUMIPSState
*env
, uint32_t fst0
)
2813 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2814 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2815 restore_rounding_mode(env
);
2816 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2817 & (float_flag_invalid
| float_flag_overflow
)) {
2818 dt2
= FP_TO_INT64_OVERFLOW
;
2820 update_fcr31(env
, GETPC());
2824 uint32_t helper_float_ceilw_d(CPUMIPSState
*env
, uint64_t fdt0
)
2828 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2829 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2830 restore_rounding_mode(env
);
2831 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2832 & (float_flag_invalid
| float_flag_overflow
)) {
2833 wt2
= FP_TO_INT32_OVERFLOW
;
2835 update_fcr31(env
, GETPC());
2839 uint32_t helper_float_ceilw_s(CPUMIPSState
*env
, uint32_t fst0
)
2843 set_float_rounding_mode(float_round_up
, &env
->active_fpu
.fp_status
);
2844 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2845 restore_rounding_mode(env
);
2846 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2847 & (float_flag_invalid
| float_flag_overflow
)) {
2848 wt2
= FP_TO_INT32_OVERFLOW
;
2850 update_fcr31(env
, GETPC());
2854 uint64_t helper_float_floorl_d(CPUMIPSState
*env
, uint64_t fdt0
)
2858 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
2859 dt2
= float64_to_int64(fdt0
, &env
->active_fpu
.fp_status
);
2860 restore_rounding_mode(env
);
2861 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2862 & (float_flag_invalid
| float_flag_overflow
)) {
2863 dt2
= FP_TO_INT64_OVERFLOW
;
2865 update_fcr31(env
, GETPC());
2869 uint64_t helper_float_floorl_s(CPUMIPSState
*env
, uint32_t fst0
)
2873 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
2874 dt2
= float32_to_int64(fst0
, &env
->active_fpu
.fp_status
);
2875 restore_rounding_mode(env
);
2876 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2877 & (float_flag_invalid
| float_flag_overflow
)) {
2878 dt2
= FP_TO_INT64_OVERFLOW
;
2880 update_fcr31(env
, GETPC());
2884 uint32_t helper_float_floorw_d(CPUMIPSState
*env
, uint64_t fdt0
)
2888 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
2889 wt2
= float64_to_int32(fdt0
, &env
->active_fpu
.fp_status
);
2890 restore_rounding_mode(env
);
2891 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2892 & (float_flag_invalid
| float_flag_overflow
)) {
2893 wt2
= FP_TO_INT32_OVERFLOW
;
2895 update_fcr31(env
, GETPC());
2899 uint32_t helper_float_floorw_s(CPUMIPSState
*env
, uint32_t fst0
)
2903 set_float_rounding_mode(float_round_down
, &env
->active_fpu
.fp_status
);
2904 wt2
= float32_to_int32(fst0
, &env
->active_fpu
.fp_status
);
2905 restore_rounding_mode(env
);
2906 if (get_float_exception_flags(&env
->active_fpu
.fp_status
)
2907 & (float_flag_invalid
| float_flag_overflow
)) {
2908 wt2
= FP_TO_INT32_OVERFLOW
;
2910 update_fcr31(env
, GETPC());
2914 /* unary operations, not modifying fp status */
2915 #define FLOAT_UNOP(name) \
2916 uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
2918 return float64_ ## name(fdt0); \
2920 uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
2922 return float32_ ## name(fst0); \
2924 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
2929 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
2930 wth0 = float32_ ## name(fdt0 >> 32); \
2931 return ((uint64_t)wth0 << 32) | wt0; \
2937 /* MIPS specific unary operations */
2938 uint64_t helper_float_recip_d(CPUMIPSState
*env
, uint64_t fdt0
)
2942 fdt2
= float64_div(float64_one
, fdt0
, &env
->active_fpu
.fp_status
);
2943 update_fcr31(env
, GETPC());
2947 uint32_t helper_float_recip_s(CPUMIPSState
*env
, uint32_t fst0
)
2951 fst2
= float32_div(float32_one
, fst0
, &env
->active_fpu
.fp_status
);
2952 update_fcr31(env
, GETPC());
2956 uint64_t helper_float_rsqrt_d(CPUMIPSState
*env
, uint64_t fdt0
)
2960 fdt2
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
2961 fdt2
= float64_div(float64_one
, fdt2
, &env
->active_fpu
.fp_status
);
2962 update_fcr31(env
, GETPC());
2966 uint32_t helper_float_rsqrt_s(CPUMIPSState
*env
, uint32_t fst0
)
2970 fst2
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
2971 fst2
= float32_div(float32_one
, fst2
, &env
->active_fpu
.fp_status
);
2972 update_fcr31(env
, GETPC());
2976 uint64_t helper_float_recip1_d(CPUMIPSState
*env
, uint64_t fdt0
)
2980 fdt2
= float64_div(float64_one
, fdt0
, &env
->active_fpu
.fp_status
);
2981 update_fcr31(env
, GETPC());
2985 uint32_t helper_float_recip1_s(CPUMIPSState
*env
, uint32_t fst0
)
2989 fst2
= float32_div(float32_one
, fst0
, &env
->active_fpu
.fp_status
);
2990 update_fcr31(env
, GETPC());
2994 uint64_t helper_float_recip1_ps(CPUMIPSState
*env
, uint64_t fdt0
)
2999 fst2
= float32_div(float32_one
, fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
3000 fsth2
= float32_div(float32_one
, fdt0
>> 32, &env
->active_fpu
.fp_status
);
3001 update_fcr31(env
, GETPC());
3002 return ((uint64_t)fsth2
<< 32) | fst2
;
3005 uint64_t helper_float_rsqrt1_d(CPUMIPSState
*env
, uint64_t fdt0
)
3009 fdt2
= float64_sqrt(fdt0
, &env
->active_fpu
.fp_status
);
3010 fdt2
= float64_div(float64_one
, fdt2
, &env
->active_fpu
.fp_status
);
3011 update_fcr31(env
, GETPC());
3015 uint32_t helper_float_rsqrt1_s(CPUMIPSState
*env
, uint32_t fst0
)
3019 fst2
= float32_sqrt(fst0
, &env
->active_fpu
.fp_status
);
3020 fst2
= float32_div(float32_one
, fst2
, &env
->active_fpu
.fp_status
);
3021 update_fcr31(env
, GETPC());
3025 uint64_t helper_float_rsqrt1_ps(CPUMIPSState
*env
, uint64_t fdt0
)
3030 fst2
= float32_sqrt(fdt0
& 0XFFFFFFFF, &env
->active_fpu
.fp_status
);
3031 fsth2
= float32_sqrt(fdt0
>> 32, &env
->active_fpu
.fp_status
);
3032 fst2
= float32_div(float32_one
, fst2
, &env
->active_fpu
.fp_status
);
3033 fsth2
= float32_div(float32_one
, fsth2
, &env
->active_fpu
.fp_status
);
3034 update_fcr31(env
, GETPC());
3035 return ((uint64_t)fsth2
<< 32) | fst2
;
3038 #define FLOAT_RINT(name, bits) \
3039 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3040 uint ## bits ## _t fs) \
3042 uint ## bits ## _t fdret; \
3044 fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
3045 update_fcr31(env, GETPC()); \
3049 FLOAT_RINT(rint_s
, 32)
3050 FLOAT_RINT(rint_d
, 64)
3053 #define FLOAT_CLASS_SIGNALING_NAN 0x001
3054 #define FLOAT_CLASS_QUIET_NAN 0x002
3055 #define FLOAT_CLASS_NEGATIVE_INFINITY 0x004
3056 #define FLOAT_CLASS_NEGATIVE_NORMAL 0x008
3057 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3058 #define FLOAT_CLASS_NEGATIVE_ZERO 0x020
3059 #define FLOAT_CLASS_POSITIVE_INFINITY 0x040
3060 #define FLOAT_CLASS_POSITIVE_NORMAL 0x080
3061 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3062 #define FLOAT_CLASS_POSITIVE_ZERO 0x200
3064 #define FLOAT_CLASS(name, bits) \
3065 uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg) \
3067 if (float ## bits ## _is_signaling_nan(arg)) { \
3068 return FLOAT_CLASS_SIGNALING_NAN; \
3069 } else if (float ## bits ## _is_quiet_nan(arg)) { \
3070 return FLOAT_CLASS_QUIET_NAN; \
3071 } else if (float ## bits ## _is_neg(arg)) { \
3072 if (float ## bits ## _is_infinity(arg)) { \
3073 return FLOAT_CLASS_NEGATIVE_INFINITY; \
3074 } else if (float ## bits ## _is_zero(arg)) { \
3075 return FLOAT_CLASS_NEGATIVE_ZERO; \
3076 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3077 return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \
3079 return FLOAT_CLASS_NEGATIVE_NORMAL; \
3082 if (float ## bits ## _is_infinity(arg)) { \
3083 return FLOAT_CLASS_POSITIVE_INFINITY; \
3084 } else if (float ## bits ## _is_zero(arg)) { \
3085 return FLOAT_CLASS_POSITIVE_ZERO; \
3086 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3087 return FLOAT_CLASS_POSITIVE_SUBNORMAL; \
3089 return FLOAT_CLASS_POSITIVE_NORMAL; \
3094 FLOAT_CLASS(class_s
, 32)
3095 FLOAT_CLASS(class_d
, 64)
3098 /* binary operations */
3099 #define FLOAT_BINOP(name) \
3100 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3101 uint64_t fdt0, uint64_t fdt1) \
3105 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
3106 update_fcr31(env, GETPC()); \
3110 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3111 uint32_t fst0, uint32_t fst1) \
3115 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3116 update_fcr31(env, GETPC()); \
3120 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3124 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3125 uint32_t fsth0 = fdt0 >> 32; \
3126 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3127 uint32_t fsth1 = fdt1 >> 32; \
3131 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3132 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
3133 update_fcr31(env, GETPC()); \
3134 return ((uint64_t)wth2 << 32) | wt2; \
3143 /* MIPS specific binary operations */
3144 uint64_t helper_float_recip2_d(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3146 fdt2
= float64_mul(fdt0
, fdt2
, &env
->active_fpu
.fp_status
);
3147 fdt2
= float64_chs(float64_sub(fdt2
, float64_one
, &env
->active_fpu
.fp_status
));
3148 update_fcr31(env
, GETPC());
3152 uint32_t helper_float_recip2_s(CPUMIPSState
*env
, uint32_t fst0
, uint32_t fst2
)
3154 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3155 fst2
= float32_chs(float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
));
3156 update_fcr31(env
, GETPC());
3160 uint64_t helper_float_recip2_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3162 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3163 uint32_t fsth0
= fdt0
>> 32;
3164 uint32_t fst2
= fdt2
& 0XFFFFFFFF;
3165 uint32_t fsth2
= fdt2
>> 32;
3167 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3168 fsth2
= float32_mul(fsth0
, fsth2
, &env
->active_fpu
.fp_status
);
3169 fst2
= float32_chs(float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
));
3170 fsth2
= float32_chs(float32_sub(fsth2
, float32_one
, &env
->active_fpu
.fp_status
));
3171 update_fcr31(env
, GETPC());
3172 return ((uint64_t)fsth2
<< 32) | fst2
;
3175 uint64_t helper_float_rsqrt2_d(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3177 fdt2
= float64_mul(fdt0
, fdt2
, &env
->active_fpu
.fp_status
);
3178 fdt2
= float64_sub(fdt2
, float64_one
, &env
->active_fpu
.fp_status
);
3179 fdt2
= float64_chs(float64_div(fdt2
, FLOAT_TWO64
, &env
->active_fpu
.fp_status
));
3180 update_fcr31(env
, GETPC());
3184 uint32_t helper_float_rsqrt2_s(CPUMIPSState
*env
, uint32_t fst0
, uint32_t fst2
)
3186 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3187 fst2
= float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
);
3188 fst2
= float32_chs(float32_div(fst2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
3189 update_fcr31(env
, GETPC());
3193 uint64_t helper_float_rsqrt2_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt2
)
3195 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3196 uint32_t fsth0
= fdt0
>> 32;
3197 uint32_t fst2
= fdt2
& 0XFFFFFFFF;
3198 uint32_t fsth2
= fdt2
>> 32;
3200 fst2
= float32_mul(fst0
, fst2
, &env
->active_fpu
.fp_status
);
3201 fsth2
= float32_mul(fsth0
, fsth2
, &env
->active_fpu
.fp_status
);
3202 fst2
= float32_sub(fst2
, float32_one
, &env
->active_fpu
.fp_status
);
3203 fsth2
= float32_sub(fsth2
, float32_one
, &env
->active_fpu
.fp_status
);
3204 fst2
= float32_chs(float32_div(fst2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
3205 fsth2
= float32_chs(float32_div(fsth2
, FLOAT_TWO32
, &env
->active_fpu
.fp_status
));
3206 update_fcr31(env
, GETPC());
3207 return ((uint64_t)fsth2
<< 32) | fst2
;
3210 uint64_t helper_float_addr_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt1
)
3212 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3213 uint32_t fsth0
= fdt0
>> 32;
3214 uint32_t fst1
= fdt1
& 0XFFFFFFFF;
3215 uint32_t fsth1
= fdt1
>> 32;
3219 fst2
= float32_add (fst0
, fsth0
, &env
->active_fpu
.fp_status
);
3220 fsth2
= float32_add (fst1
, fsth1
, &env
->active_fpu
.fp_status
);
3221 update_fcr31(env
, GETPC());
3222 return ((uint64_t)fsth2
<< 32) | fst2
;
3225 uint64_t helper_float_mulr_ps(CPUMIPSState
*env
, uint64_t fdt0
, uint64_t fdt1
)
3227 uint32_t fst0
= fdt0
& 0XFFFFFFFF;
3228 uint32_t fsth0
= fdt0
>> 32;
3229 uint32_t fst1
= fdt1
& 0XFFFFFFFF;
3230 uint32_t fsth1
= fdt1
>> 32;
3234 fst2
= float32_mul (fst0
, fsth0
, &env
->active_fpu
.fp_status
);
3235 fsth2
= float32_mul (fst1
, fsth1
, &env
->active_fpu
.fp_status
);
3236 update_fcr31(env
, GETPC());
3237 return ((uint64_t)fsth2
<< 32) | fst2
;
3240 #define FLOAT_MINMAX(name, bits, minmaxfunc) \
3241 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3242 uint ## bits ## _t fs, \
3243 uint ## bits ## _t ft) \
3245 uint ## bits ## _t fdret; \
3247 fdret = float ## bits ## _ ## minmaxfunc(fs, ft, \
3248 &env->active_fpu.fp_status); \
3249 update_fcr31(env, GETPC()); \
3253 FLOAT_MINMAX(max_s
, 32, maxnum
)
3254 FLOAT_MINMAX(max_d
, 64, maxnum
)
3255 FLOAT_MINMAX(maxa_s
, 32, maxnummag
)
3256 FLOAT_MINMAX(maxa_d
, 64, maxnummag
)
3258 FLOAT_MINMAX(min_s
, 32, minnum
)
3259 FLOAT_MINMAX(min_d
, 64, minnum
)
3260 FLOAT_MINMAX(mina_s
, 32, minnummag
)
3261 FLOAT_MINMAX(mina_d
, 64, minnummag
)
3264 /* ternary operations */
3265 #define UNFUSED_FMA(prefix, a, b, c, flags) \
3267 a = prefix##_mul(a, b, &env->active_fpu.fp_status); \
3268 if ((flags) & float_muladd_negate_c) { \
3269 a = prefix##_sub(a, c, &env->active_fpu.fp_status); \
3271 a = prefix##_add(a, c, &env->active_fpu.fp_status); \
3273 if ((flags) & float_muladd_negate_result) { \
3274 a = prefix##_chs(a); \
3278 /* FMA based operations */
3279 #define FLOAT_FMA(name, type) \
3280 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3281 uint64_t fdt0, uint64_t fdt1, \
3284 UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \
3285 update_fcr31(env, GETPC()); \
3289 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3290 uint32_t fst0, uint32_t fst1, \
3293 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
3294 update_fcr31(env, GETPC()); \
3298 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3299 uint64_t fdt0, uint64_t fdt1, \
3302 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3303 uint32_t fsth0 = fdt0 >> 32; \
3304 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3305 uint32_t fsth1 = fdt1 >> 32; \
3306 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
3307 uint32_t fsth2 = fdt2 >> 32; \
3309 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
3310 UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \
3311 update_fcr31(env, GETPC()); \
3312 return ((uint64_t)fsth0 << 32) | fst0; \
3315 FLOAT_FMA(msub
, float_muladd_negate_c
)
3316 FLOAT_FMA(nmadd
, float_muladd_negate_result
)
3317 FLOAT_FMA(nmsub
, float_muladd_negate_result
| float_muladd_negate_c
)
3320 #define FLOAT_FMADDSUB(name, bits, muladd_arg) \
3321 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3322 uint ## bits ## _t fs, \
3323 uint ## bits ## _t ft, \
3324 uint ## bits ## _t fd) \
3326 uint ## bits ## _t fdret; \
3328 fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg, \
3329 &env->active_fpu.fp_status); \
3330 update_fcr31(env, GETPC()); \
3334 FLOAT_FMADDSUB(maddf_s
, 32, 0)
3335 FLOAT_FMADDSUB(maddf_d
, 64, 0)
3336 FLOAT_FMADDSUB(msubf_s
, 32, float_muladd_negate_product
)
3337 FLOAT_FMADDSUB(msubf_d
, 64, float_muladd_negate_product
)
3338 #undef FLOAT_FMADDSUB
3340 /* compare operations */
3341 #define FOP_COND_D(op, cond) \
3342 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3343 uint64_t fdt1, int cc) \
3347 update_fcr31(env, GETPC()); \
3349 SET_FP_COND(cc, env->active_fpu); \
3351 CLEAR_FP_COND(cc, env->active_fpu); \
3353 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3354 uint64_t fdt1, int cc) \
3357 fdt0 = float64_abs(fdt0); \
3358 fdt1 = float64_abs(fdt1); \
3360 update_fcr31(env, GETPC()); \
3362 SET_FP_COND(cc, env->active_fpu); \
3364 CLEAR_FP_COND(cc, env->active_fpu); \
3367 /* NOTE: the comma operator will make "cond" to eval to false,
3368 * but float64_unordered_quiet() is still called. */
3369 FOP_COND_D(f
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
3370 FOP_COND_D(un
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
))
3371 FOP_COND_D(eq
, float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3372 FOP_COND_D(ueq
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3373 FOP_COND_D(olt
, float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3374 FOP_COND_D(ult
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3375 FOP_COND_D(ole
, float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3376 FOP_COND_D(ule
, float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3377 /* NOTE: the comma operator will make "cond" to eval to false,
3378 * but float64_unordered() is still called. */
3379 FOP_COND_D(sf
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
3380 FOP_COND_D(ngle
,float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
))
3381 FOP_COND_D(seq
, float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3382 FOP_COND_D(ngl
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3383 FOP_COND_D(lt
, float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3384 FOP_COND_D(nge
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3385 FOP_COND_D(le
, float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3386 FOP_COND_D(ngt
, float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
) || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
))
3388 #define FOP_COND_S(op, cond) \
3389 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3390 uint32_t fst1, int cc) \
3394 update_fcr31(env, GETPC()); \
3396 SET_FP_COND(cc, env->active_fpu); \
3398 CLEAR_FP_COND(cc, env->active_fpu); \
3400 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
3401 uint32_t fst1, int cc) \
3404 fst0 = float32_abs(fst0); \
3405 fst1 = float32_abs(fst1); \
3407 update_fcr31(env, GETPC()); \
3409 SET_FP_COND(cc, env->active_fpu); \
3411 CLEAR_FP_COND(cc, env->active_fpu); \
3414 /* NOTE: the comma operator will make "cond" to eval to false,
3415 * but float32_unordered_quiet() is still called. */
3416 FOP_COND_S(f
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
3417 FOP_COND_S(un
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
))
3418 FOP_COND_S(eq
, float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3419 FOP_COND_S(ueq
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3420 FOP_COND_S(olt
, float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3421 FOP_COND_S(ult
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3422 FOP_COND_S(ole
, float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3423 FOP_COND_S(ule
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3424 /* NOTE: the comma operator will make "cond" to eval to false,
3425 * but float32_unordered() is still called. */
3426 FOP_COND_S(sf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
3427 FOP_COND_S(ngle
,float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
))
3428 FOP_COND_S(seq
, float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3429 FOP_COND_S(ngl
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3430 FOP_COND_S(lt
, float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3431 FOP_COND_S(nge
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3432 FOP_COND_S(le
, float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3433 FOP_COND_S(ngt
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
))
3435 #define FOP_COND_PS(op, condl, condh) \
3436 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3437 uint64_t fdt1, int cc) \
3439 uint32_t fst0, fsth0, fst1, fsth1; \
3441 fst0 = fdt0 & 0XFFFFFFFF; \
3442 fsth0 = fdt0 >> 32; \
3443 fst1 = fdt1 & 0XFFFFFFFF; \
3444 fsth1 = fdt1 >> 32; \
3447 update_fcr31(env, GETPC()); \
3449 SET_FP_COND(cc, env->active_fpu); \
3451 CLEAR_FP_COND(cc, env->active_fpu); \
3453 SET_FP_COND(cc + 1, env->active_fpu); \
3455 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3457 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
3458 uint64_t fdt1, int cc) \
3460 uint32_t fst0, fsth0, fst1, fsth1; \
3462 fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
3463 fsth0 = float32_abs(fdt0 >> 32); \
3464 fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
3465 fsth1 = float32_abs(fdt1 >> 32); \
3468 update_fcr31(env, GETPC()); \
3470 SET_FP_COND(cc, env->active_fpu); \
3472 CLEAR_FP_COND(cc, env->active_fpu); \
3474 SET_FP_COND(cc + 1, env->active_fpu); \
3476 CLEAR_FP_COND(cc + 1, env->active_fpu); \
3479 /* NOTE: the comma operator will make "cond" to eval to false,
3480 * but float32_unordered_quiet() is still called. */
3481 FOP_COND_PS(f
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0),
3482 (float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
), 0))
3483 FOP_COND_PS(un
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
),
3484 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
))
3485 FOP_COND_PS(eq
, float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3486 float32_eq_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3487 FOP_COND_PS(ueq
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3488 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_eq_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3489 FOP_COND_PS(olt
, float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3490 float32_lt_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3491 FOP_COND_PS(ult
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3492 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_lt_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3493 FOP_COND_PS(ole
, float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3494 float32_le_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3495 FOP_COND_PS(ule
, float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3496 float32_unordered_quiet(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_le_quiet(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3497 /* NOTE: the comma operator will make "cond" to eval to false,
3498 * but float32_unordered() is still called. */
3499 FOP_COND_PS(sf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0),
3500 (float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
), 0))
3501 FOP_COND_PS(ngle
,float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
),
3502 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
))
3503 FOP_COND_PS(seq
, float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3504 float32_eq(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3505 FOP_COND_PS(ngl
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3506 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_eq(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3507 FOP_COND_PS(lt
, float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3508 float32_lt(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3509 FOP_COND_PS(nge
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3510 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_lt(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3511 FOP_COND_PS(le
, float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3512 float32_le(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3513 FOP_COND_PS(ngt
, float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
) || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
),
3514 float32_unordered(fsth1
, fsth0
, &env
->active_fpu
.fp_status
) || float32_le(fsth0
, fsth1
, &env
->active_fpu
.fp_status
))
3516 /* R6 compare operations */
3517 #define FOP_CONDN_D(op, cond) \
3518 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0, \
3523 update_fcr31(env, GETPC()); \
3531 /* NOTE: the comma operator will make "cond" to eval to false,
3532 * but float64_unordered_quiet() is still called. */
3533 FOP_CONDN_D(af
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
3534 FOP_CONDN_D(un
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)))
3535 FOP_CONDN_D(eq
, (float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3536 FOP_CONDN_D(ueq
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3537 || float64_eq_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3538 FOP_CONDN_D(lt
, (float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3539 FOP_CONDN_D(ult
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3540 || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3541 FOP_CONDN_D(le
, (float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3542 FOP_CONDN_D(ule
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3543 || float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3544 /* NOTE: the comma operator will make "cond" to eval to false,
3545 * but float64_unordered() is still called. */
3546 FOP_CONDN_D(saf
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
), 0))
3547 FOP_CONDN_D(sun
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)))
3548 FOP_CONDN_D(seq
, (float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3549 FOP_CONDN_D(sueq
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3550 || float64_eq(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3551 FOP_CONDN_D(slt
, (float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3552 FOP_CONDN_D(sult
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3553 || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3554 FOP_CONDN_D(sle
, (float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3555 FOP_CONDN_D(sule
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3556 || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3557 FOP_CONDN_D(or, (float64_le_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3558 || float64_le_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3559 FOP_CONDN_D(une
, (float64_unordered_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3560 || float64_lt_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3561 || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3562 FOP_CONDN_D(ne
, (float64_lt_quiet(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3563 || float64_lt_quiet(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3564 FOP_CONDN_D(sor
, (float64_le(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3565 || float64_le(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3566 FOP_CONDN_D(sune
, (float64_unordered(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3567 || float64_lt(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3568 || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3569 FOP_CONDN_D(sne
, (float64_lt(fdt1
, fdt0
, &env
->active_fpu
.fp_status
)
3570 || float64_lt(fdt0
, fdt1
, &env
->active_fpu
.fp_status
)))
3572 #define FOP_CONDN_S(op, cond) \
3573 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0, \
3578 update_fcr31(env, GETPC()); \
3586 /* NOTE: the comma operator will make "cond" to eval to false,
3587 * but float32_unordered_quiet() is still called. */
3588 FOP_CONDN_S(af
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
3589 FOP_CONDN_S(un
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)))
3590 FOP_CONDN_S(eq
, (float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3591 FOP_CONDN_S(ueq
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3592 || float32_eq_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3593 FOP_CONDN_S(lt
, (float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3594 FOP_CONDN_S(ult
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3595 || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3596 FOP_CONDN_S(le
, (float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3597 FOP_CONDN_S(ule
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3598 || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3599 /* NOTE: the comma operator will make "cond" to eval to false,
3600 * but float32_unordered() is still called. */
3601 FOP_CONDN_S(saf
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
), 0))
3602 FOP_CONDN_S(sun
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)))
3603 FOP_CONDN_S(seq
, (float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3604 FOP_CONDN_S(sueq
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3605 || float32_eq(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3606 FOP_CONDN_S(slt
, (float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3607 FOP_CONDN_S(sult
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3608 || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3609 FOP_CONDN_S(sle
, (float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3610 FOP_CONDN_S(sule
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3611 || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3612 FOP_CONDN_S(or, (float32_le_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3613 || float32_le_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3614 FOP_CONDN_S(une
, (float32_unordered_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3615 || float32_lt_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3616 || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3617 FOP_CONDN_S(ne
, (float32_lt_quiet(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3618 || float32_lt_quiet(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3619 FOP_CONDN_S(sor
, (float32_le(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3620 || float32_le(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3621 FOP_CONDN_S(sune
, (float32_unordered(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3622 || float32_lt(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3623 || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3624 FOP_CONDN_S(sne
, (float32_lt(fst1
, fst0
, &env
->active_fpu
.fp_status
)
3625 || float32_lt(fst0
, fst1
, &env
->active_fpu
.fp_status
)))
3628 /* Data format min and max values */
3629 #define DF_BITS(df) (1 << ((df) + 3))
3631 /* Element-by-element access macros */
3632 #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
3634 #if !defined(CONFIG_USER_ONLY)
3635 #define MEMOP_IDX(DF) \
3636 TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
3637 cpu_mmu_index(env));
3639 #define MEMOP_IDX(DF)
3642 #define MSA_LD_DF(DF, TYPE, LD_INSN, ...) \
3643 void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
3644 target_ulong addr) \
3646 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
3650 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
3651 wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__); \
3653 memcpy(pwd, &wx, sizeof(wr_t)); \
3656 #if !defined(CONFIG_USER_ONLY)
3657 MSA_LD_DF(DF_BYTE
, b
, helper_ret_ldub_mmu
, oi
, GETRA())
3658 MSA_LD_DF(DF_HALF
, h
, helper_ret_lduw_mmu
, oi
, GETRA())
3659 MSA_LD_DF(DF_WORD
, w
, helper_ret_ldul_mmu
, oi
, GETRA())
3660 MSA_LD_DF(DF_DOUBLE
, d
, helper_ret_ldq_mmu
, oi
, GETRA())
3662 MSA_LD_DF(DF_BYTE
, b
, cpu_ldub_data
)
3663 MSA_LD_DF(DF_HALF
, h
, cpu_lduw_data
)
3664 MSA_LD_DF(DF_WORD
, w
, cpu_ldl_data
)
3665 MSA_LD_DF(DF_DOUBLE
, d
, cpu_ldq_data
)
3668 #define MSA_PAGESPAN(x) \
3669 ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
3671 static inline void ensure_writable_pages(CPUMIPSState
*env
,
3676 #if !defined(CONFIG_USER_ONLY)
3677 target_ulong page_addr
;
3678 if (unlikely(MSA_PAGESPAN(addr
))) {
3680 probe_write(env
, addr
, mmu_idx
, retaddr
);
3682 page_addr
= (addr
& TARGET_PAGE_MASK
) + TARGET_PAGE_SIZE
;
3683 probe_write(env
, page_addr
, mmu_idx
, retaddr
);
3688 #define MSA_ST_DF(DF, TYPE, ST_INSN, ...) \
3689 void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd, \
3690 target_ulong addr) \
3692 wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
3693 int mmu_idx = cpu_mmu_index(env); \
3696 ensure_writable_pages(env, addr, mmu_idx, GETRA()); \
3697 for (i = 0; i < DF_ELEMENTS(DF); i++) { \
3698 ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__); \
3702 #if !defined(CONFIG_USER_ONLY)
3703 MSA_ST_DF(DF_BYTE
, b
, helper_ret_stb_mmu
, oi
, GETRA())
3704 MSA_ST_DF(DF_HALF
, h
, helper_ret_stw_mmu
, oi
, GETRA())
3705 MSA_ST_DF(DF_WORD
, w
, helper_ret_stl_mmu
, oi
, GETRA())
3706 MSA_ST_DF(DF_DOUBLE
, d
, helper_ret_stq_mmu
, oi
, GETRA())
3708 MSA_ST_DF(DF_BYTE
, b
, cpu_stb_data
)
3709 MSA_ST_DF(DF_HALF
, h
, cpu_stw_data
)
3710 MSA_ST_DF(DF_WORD
, w
, cpu_stl_data
)
3711 MSA_ST_DF(DF_DOUBLE
, d
, cpu_stq_data
)