?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge tag 'v2.4.0-rc3'
[qemu/ar7.git] / hw / net / eepro100.c
blob35f170e82ff5bbe9505bea91cacad2b41a46e59f
1 /*
2 * QEMU i8255x (PRO100) emulation
3 *
4 * Copyright (C) 2006-2011 Stefan Weil
5 *
6 * Portions of the code are copies from grub / etherboot eepro100.c
7 * and linux e100.c.
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 2 of the License, or
12 * (at your option) version 3 or any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 *
22 * Tested features (i82559c):
23 * PXE boot (i386 guest, i386 / ppc host) ok
24 * Linux networking (i386 guest, i386 / ppc / ppc64 host) ok
25 * Linux networking e100 driver (mips / mipsel guest, i386 host) ok
26 * Linux networking eepro100 driver (mipsel guest) not ok
27 * Windows networking (Vista) not ok
28 *
29 * References:
30 *
31 * Intel 8255x 10/100 Mbps Ethernet Controller Family
32 * Open Source Software Developer Manual
33 *
34 * TODO:
35 * * PHY emulation should be separated from nic emulation.
36 * Most nic emulations could share the same phy code.
37 * * i82550 is untested. It is programmed like the i82559.
38 * * i82562 is untested. It is programmed like the i82559.
39 * * Power management (i82558 and later) is not implemented.
40 * * Wake-on-LAN is not implemented.
41 */
42
43 #include <stddef.h> /* offsetof */
44 #include "hw/hw.h"
45 #include "hw/pci/pci.h"
46 #include "net/net.h"
47 #include "hw/nvram/eeprom93xx.h"
48 #include "sysemu/sysemu.h"
49 #include "sysemu/dma.h"
50 #include "qemu/bitops.h"
51
52 /* QEMU sends frames smaller than 60 bytes to ethernet nics.
53 * This should be fixed in the networking code because normally
54 * such frames are rejected by real nics and their emulations.
55 * To avoid this behaviour, other nic emulations pad received
56 * frames. The following definition enables this workaround for
57 * eepro100, too. */
58 #define CONFIG_PAD_RECEIVED_FRAMES
59
60 #define KiB 1024
61
62 /* Debug EEPRO100 card. */
63 #if 0
64 # define DEBUG_EEPRO100
65 #endif
66
67 #ifdef DEBUG_EEPRO100
68 #define logout(fmt, ...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ## __VA_ARGS__)
69 #else
70 #define logout(fmt, ...) ((void)0)
71 #endif
72
73 /* Set flags to 0 to disable debug output. */
74 #define INT 1 /* interrupt related actions */
75 #define MDI 1 /* mdi related actions */
76 #define OTHER 1
77 #define RXTX 1
78 #define EEPROM 1 /* eeprom related actions */
79
80 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
81
82 #define UNEXPECTED() logout("%s:%u unexpected\n", __FILE__, __LINE__)
83
84 #if 0
85 #define missing(text) assert(!"feature is missing in this emulation: " text)
86 #else
87 #define missing(text) logout("feature is missing in this emulation: " text "\n")
88 #endif
89
90 #define MAX_ETH_FRAME_SIZE 1514
91
92 /* This driver supports several different devices which are declared here. */
93 #define i82550 0x82550
94 #define i82551 0x82551
95 #define i82557A 0x82557a
96 #define i82557B 0x82557b
97 #define i82557C 0x82557c
98 #define i82558A 0x82558a
99 #define i82558B 0x82558b
100 #define i82559A 0x82559a
101 #define i82559B 0x82559b
102 #define i82559C 0x82559c
103 #define i82559ER 0x82559e
104 #define i82562 0x82562
105 #define i82801 0x82801
106
107 /* Use 64 word EEPROM. TODO: could be a runtime option. */
108 #define EEPROM_SIZE 64
109
110 #define PCI_MEM_SIZE (4 * KiB)
111 #define PCI_IO_SIZE 64
112 #define PCI_FLASH_SIZE (128 * KiB)
113
114 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
115
116 /* The SCB accepts the following controls for the Tx and Rx units: */
117 #define CU_NOP 0x0000 /* No operation. */
118 #define CU_START 0x0010 /* CU start. */
119 #define CU_RESUME 0x0020 /* CU resume. */
120 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
121 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
122 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
123 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
124 #define CU_SRESUME 0x00a0 /* CU static resume. */
125
126 #define RU_NOP 0x0000
127 #define RX_START 0x0001
128 #define RX_RESUME 0x0002
129 #define RU_ABORT 0x0004
130 #define RX_ADDR_LOAD 0x0006
131 #define RX_RESUMENR 0x0007
132 #define INT_MASK 0x0100
133 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
134
135 typedef struct {
136 const char *name;
137 const char *desc;
138 uint16_t device_id;
139 uint8_t revision;
140 uint16_t subsystem_vendor_id;
141 uint16_t subsystem_id;
142
143 uint32_t device;
144 uint8_t stats_size;
145 bool has_extended_tcb_support;
146 bool power_management;
147 } E100PCIDeviceInfo;
148
149 /* Offsets to the various registers.
150 All accesses need not be longword aligned. */
151 typedef enum {
152 SCBStatus = 0, /* Status Word. */
153 SCBAck = 1,
154 SCBCmd = 2, /* Rx/Command Unit command and status. */
155 SCBIntmask = 3,
156 SCBPointer = 4, /* General purpose pointer. */
157 SCBPort = 8, /* Misc. commands and operands. */
158 SCBflash = 12, /* Flash memory control. */
159 SCBeeprom = 14, /* EEPROM control. */
160 SCBCtrlMDI = 16, /* MDI interface control. */
161 SCBEarlyRx = 20, /* Early receive byte count. */
162 SCBFlow = 24, /* Flow Control. */
163 SCBpmdr = 27, /* Power Management Driver. */
164 SCBgctrl = 28, /* General Control. */
165 SCBgstat = 29, /* General Status. */
166 } E100RegisterOffset;
167
168 /* A speedo3 transmit buffer descriptor with two buffers... */
169 typedef struct {
170 uint16_t status;
171 uint16_t command;
172 uint32_t link; /* void * */
173 uint32_t tbd_array_addr; /* transmit buffer descriptor array address. */
174 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
175 uint8_t tx_threshold; /* transmit threshold */
176 uint8_t tbd_count; /* TBD number */
177 #if 0
178 /* This constitutes two "TBD" entries: hdr and data */
179 uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
180 int32_t tx_buf_size0; /* Length of Tx hdr. */
181 uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
182 int32_t tx_buf_size1; /* Length of Tx data. */
183 #endif
184 } eepro100_tx_t;
185
186 /* Receive frame descriptor. */
187 typedef struct {
188 int16_t status;
189 uint16_t command;
190 uint32_t link; /* struct RxFD * */
191 uint32_t rx_buf_addr; /* void * */
192 uint16_t count;
193 uint16_t size;
194 /* Ethernet frame data follows. */
195 } eepro100_rx_t;
196
197 typedef enum {
198 COMMAND_EL = BIT(15),
199 COMMAND_S = BIT(14),
200 COMMAND_I = BIT(13),
201 COMMAND_NC = BIT(4),
202 COMMAND_SF = BIT(3),
203 COMMAND_CMD = BITS(2, 0),
204 } scb_command_bit;
205
206 typedef enum {
207 STATUS_C = BIT(15),
208 STATUS_OK = BIT(13),
209 } scb_status_bit;
210
211 typedef struct {
212 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
213 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
214 tx_multiple_collisions, tx_total_collisions;
215 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
216 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
217 rx_short_frame_errors;
218 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
219 uint16_t xmt_tco_frames, rcv_tco_frames;
220 /* TODO: i82559 has six reserved statistics but a total of 24 dwords. */
221 uint32_t reserved[4];
222 } eepro100_stats_t;
223
224 typedef enum {
225 cu_idle = 0,
226 cu_suspended = 1,
227 cu_active = 2,
228 cu_lpq_active = 2,
229 cu_hqp_active = 3
230 } cu_state_t;
231
232 typedef enum {
233 ru_idle = 0,
234 ru_suspended = 1,
235 ru_no_resources = 2,
236 ru_ready = 4
237 } ru_state_t;
238
239 typedef struct {
240 PCIDevice dev;
241 /* Hash register (multicast mask array, multiple individual addresses). */
242 uint8_t mult[8];
243 MemoryRegion mmio_bar;
244 MemoryRegion io_bar;
245 MemoryRegion flash_bar;
246 NICState *nic;
247 NICConf conf;
248 uint8_t scb_stat; /* SCB stat/ack byte */
249 uint8_t int_stat; /* PCI interrupt status */
250 /* region must not be saved by nic_save. */
251 uint16_t mdimem[32];
252 eeprom_t *eeprom;
253 uint32_t device; /* device variant */
254 /* (cu_base + cu_offset) address the next command block in the command block list. */
255 uint32_t cu_base; /* CU base address */
256 uint32_t cu_offset; /* CU address offset */
257 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
258 uint32_t ru_base; /* RU base address */
259 uint32_t ru_offset; /* RU address offset */
260 uint32_t statsaddr; /* pointer to eepro100_stats_t */
261
262 /* Temporary status information (no need to save these values),
263 * used while processing CU commands. */
264 eepro100_tx_t tx; /* transmit buffer descriptor */
265 uint32_t cb_address; /* = cu_base + cu_offset */
266
267 /* Statistical counters. Also used for wake-up packet (i82559). */
268 eepro100_stats_t statistics;
269
270 /* Data in mem is always in the byte order of the controller (le).
271 * It must be dword aligned to allow direct access to 32 bit values. */
272 uint8_t mem[PCI_MEM_SIZE] __attribute__((aligned(8)));
273
274 /* Configuration bytes. */
275 uint8_t configuration[22];
276
277 /* vmstate for each particular nic */
278 VMStateDescription *vmstate;
279
280 /* Quasi static device properties (no need to save them). */
281 uint16_t stats_size;
282 bool has_extended_tcb_support;
283 } EEPRO100State;
284
285 /* Word indices in EEPROM. */
286 typedef enum {
287 EEPROM_CNFG_MDIX = 0x03,
288 EEPROM_ID = 0x05,
289 EEPROM_PHY_ID = 0x06,
290 EEPROM_VENDOR_ID = 0x0c,
291 EEPROM_CONFIG_ASF = 0x0d,
292 EEPROM_DEVICE_ID = 0x23,
293 EEPROM_SMBUS_ADDR = 0x90,
294 } EEPROMOffset;
295
296 /* Bit values for EEPROM ID word (offset 0x0a). */
297 typedef enum {
298 EEPROM_ID_MDM = BIT(0), /* Modem */
299 EEPROM_ID_STB = BIT(1), /* Standby Enable */
300 EEPROM_ID_WMR = BIT(2), /* ??? */
301 EEPROM_ID_WOL = BIT(5), /* Wake on LAN */
302 EEPROM_ID_DPD = BIT(6), /* Deep Power Down */
303 EEPROM_ID_ALT = BIT(7), /* */
304 /* BITS(10, 8) device revision */
305 EEPROM_ID_BD = BIT(11), /* boot disable */
306 EEPROM_ID_ID = BIT(13), /* id bit */
307 /* BITS(15, 14) signature */
308 EEPROM_ID_VALID = BIT(14), /* signature for valid eeprom */
309 } eeprom_id_bit;
310
311 /* Default values for MDI (PHY) registers */
312 static const uint16_t eepro100_mdi_default[] = {
313 /* MDI Registers 0 - 6, 7 */
314 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
315 /* MDI Registers 8 - 15 */
316 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
317 /* MDI Registers 16 - 31 */
318 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
319 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
320 };
321
322 /* Readonly mask for MDI (PHY) registers */
323 static const uint16_t eepro100_mdi_mask[] = {
324 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
325 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
326 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
327 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
328 };
329
330 #define POLYNOMIAL 0x04c11db6
331
332 static E100PCIDeviceInfo *eepro100_get_class(EEPRO100State *s);
333
334 /* From FreeBSD (locally modified). */
335 static unsigned e100_compute_mcast_idx(const uint8_t *ep)
336 {
337 uint32_t crc;
338 int carry, i, j;
339 uint8_t b;
340
341 crc = 0xffffffff;
342 for (i = 0; i < 6; i++) {
343 b = *ep++;
344 for (j = 0; j < 8; j++) {
345 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
346 crc <<= 1;
347 b >>= 1;
348 if (carry) {
349 crc = ((crc ^ POLYNOMIAL) | carry);
350 }
351 }
352 }
353 return (crc & BITS(7, 2)) >> 2;
354 }
355
356 /* Read a 16 bit control/status (CSR) register. */
357 static uint16_t e100_read_reg2(EEPRO100State *s, E100RegisterOffset addr)
358 {
359 assert(!((uintptr_t)&s->mem[addr] & 1));
360 return le16_to_cpup((uint16_t *)&s->mem[addr]);
361 }
362
363 /* Read a 32 bit control/status (CSR) register. */
364 static uint32_t e100_read_reg4(EEPRO100State *s, E100RegisterOffset addr)
365 {
366 assert(!((uintptr_t)&s->mem[addr] & 3));
367 return le32_to_cpup((uint32_t *)&s->mem[addr]);
368 }
369
370 /* Write a 16 bit control/status (CSR) register. */
371 static void e100_write_reg2(EEPRO100State *s, E100RegisterOffset addr,
372 uint16_t val)
373 {
374 assert(!((uintptr_t)&s->mem[addr] & 1));
375 cpu_to_le16w((uint16_t *)&s->mem[addr], val);
376 }
377
378 /* Read a 32 bit control/status (CSR) register. */
379 static void e100_write_reg4(EEPRO100State *s, E100RegisterOffset addr,
380 uint32_t val)
381 {
382 assert(!((uintptr_t)&s->mem[addr] & 3));
383 cpu_to_le32w((uint32_t *)&s->mem[addr], val);
384 }
385
386 #if defined(DEBUG_EEPRO100)
387 static const char *nic_dump(const uint8_t * buf, unsigned size)
388 {
389 static char dump[3 * 16 + 1];
390 char *p = &dump[0];
391 if (size > 16) {
392 size = 16;
393 }
394 while (size-- > 0) {
395 p += sprintf(p, " %02x", *buf++);
396 }
397 return dump;
398 }
399 #endif /* DEBUG_EEPRO100 */
400
401 #if 0 /* TODO */
402 enum scb_stat_ack {
403 stat_ack_not_ours = 0x00,
404 stat_ack_sw_gen = 0x04,
405 stat_ack_rnr = 0x10,
406 stat_ack_cu_idle = 0x20,
407 stat_ack_frame_rx = 0x40,
408 stat_ack_cu_cmd_done = 0x80,
409 stat_ack_not_present = 0xFF,
410 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
411 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
412 };
413 #endif
414
415 static void disable_interrupt(EEPRO100State * s)
416 {
417 if (s->int_stat) {
418 TRACE(INT, logout("interrupt disabled\n"));
419 pci_irq_deassert(&s->dev);
420 s->int_stat = 0;
421 }
422 }
423
424 static void enable_interrupt(EEPRO100State * s)
425 {
426 if (!s->int_stat) {
427 TRACE(INT, logout("interrupt enabled\n"));
428 pci_irq_assert(&s->dev);
429 s->int_stat = 1;
430 }
431 }
432
433 static void eepro100_acknowledge(EEPRO100State * s)
434 {
435 s->scb_stat &= ~s->mem[SCBAck];
436 s->mem[SCBAck] = s->scb_stat;
437 if (s->scb_stat == 0) {
438 disable_interrupt(s);
439 }
440 }
441
442 static void eepro100_interrupt(EEPRO100State * s, uint8_t status)
443 {
444 uint8_t mask = ~s->mem[SCBIntmask];
445 s->mem[SCBAck] |= status;
446 status = s->scb_stat = s->mem[SCBAck];
447 status &= (mask | 0x0f);
448 #if 0
449 status &= (~s->mem[SCBIntmask] | 0x0xf);
450 #endif
451 if (status && (mask & 0x01)) {
452 /* SCB mask and SCB Bit M do not disable interrupt. */
453 enable_interrupt(s);
454 } else if (s->int_stat) {
455 disable_interrupt(s);
456 }
457 }
458
459 static void eepro100_cx_interrupt(EEPRO100State * s)
460 {
461 /* CU completed action command. */
462 /* Transmit not ok (82557 only, not in emulation). */
463 eepro100_interrupt(s, 0x80);
464 }
465
466 static void eepro100_cna_interrupt(EEPRO100State * s)
467 {
468 /* CU left the active state. */
469 eepro100_interrupt(s, 0x20);
470 }
471
472 static void eepro100_fr_interrupt(EEPRO100State * s)
473 {
474 /* RU received a complete frame. */
475 eepro100_interrupt(s, 0x40);
476 }
477
478 static void eepro100_rnr_interrupt(EEPRO100State * s)
479 {
480 /* RU is not ready. */
481 eepro100_interrupt(s, 0x10);
482 }
483
484 static void eepro100_mdi_interrupt(EEPRO100State * s)
485 {
486 /* MDI completed read or write cycle. */
487 eepro100_interrupt(s, 0x08);
488 }
489
490 static void eepro100_swi_interrupt(EEPRO100State * s)
491 {
492 /* Software has requested an interrupt. */
493 eepro100_interrupt(s, 0x04);
494 }
495
496 #if 0
497 static void eepro100_fcp_interrupt(EEPRO100State * s)
498 {
499 /* Flow control pause interrupt (82558 and later). */
500 eepro100_interrupt(s, 0x01);
501 }
502 #endif
503
504 static void e100_pci_reset(EEPRO100State * s)
505 {
506 E100PCIDeviceInfo *info = eepro100_get_class(s);
507 uint32_t device = s->device;
508 uint8_t *pci_conf = s->dev.config;
509
510 TRACE(OTHER, logout("%p\n", s));
511
512 /* PCI Status */
513 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM |
514 PCI_STATUS_FAST_BACK);
515 /* PCI Latency Timer */
516 pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */
517 /* Capability Pointer is set by PCI framework. */
518 /* Interrupt Line */
519 /* Interrupt Pin */
520 pci_set_byte(pci_conf + PCI_INTERRUPT_PIN, 1); /* interrupt pin A */
521 /* Minimum Grant */
522 pci_set_byte(pci_conf + PCI_MIN_GNT, 0x08);
523 /* Maximum Latency */
524 pci_set_byte(pci_conf + PCI_MAX_LAT, 0x18);
525
526 s->stats_size = info->stats_size;
527 s->has_extended_tcb_support = info->has_extended_tcb_support;
528
529 switch (device) {
530 case i82550:
531 case i82551:
532 case i82557A:
533 case i82557B:
534 case i82557C:
535 case i82558A:
536 case i82558B:
537 case i82559A:
538 case i82559B:
539 case i82559ER:
540 case i82562:
541 case i82801:
542 case i82559C:
543 break;
544 default:
545 logout("Device %X is undefined!\n", device);
546 }
547
548 /* Standard TxCB. */
549 s->configuration[6] |= BIT(4);
550
551 /* Standard statistical counters. */
552 s->configuration[6] |= BIT(5);
553
554 if (s->stats_size == 80) {
555 /* TODO: check TCO Statistical Counters bit. Documentation not clear. */
556 if (s->configuration[6] & BIT(2)) {
557 /* TCO statistical counters. */
558 assert(s->configuration[6] & BIT(5));
559 } else {
560 if (s->configuration[6] & BIT(5)) {
561 /* No extended statistical counters, i82557 compatible. */
562 s->stats_size = 64;
563 } else {
564 /* i82558 compatible. */
565 s->stats_size = 76;
566 }
567 }
568 } else {
569 if (s->configuration[6] & BIT(5)) {
570 /* No extended statistical counters. */
571 s->stats_size = 64;
572 }
573 }
574 assert(s->stats_size > 0 && s->stats_size <= sizeof(s->statistics));
575
576 if (info->power_management) {
577 /* Power Management Capabilities */
578 int cfg_offset = 0xdc;
579 int r = pci_add_capability(&s->dev, PCI_CAP_ID_PM,
580 cfg_offset, PCI_PM_SIZEOF);
581 assert(r >= 0);
582 pci_set_word(pci_conf + cfg_offset + PCI_PM_PMC, 0x7e21);
583 #if 0 /* TODO: replace dummy code for power management emulation. */
584 /* TODO: Power Management Control / Status. */
585 pci_set_word(pci_conf + cfg_offset + PCI_PM_CTRL, 0x0000);
586 /* TODO: Ethernet Power Consumption Registers (i82559 and later). */
587 pci_set_byte(pci_conf + cfg_offset + PCI_PM_PPB_EXTENSIONS, 0x0000);
588 #endif
589 }
590
591 #if EEPROM_SIZE > 0
592 if (device == i82557C || device == i82558B || device == i82559C) {
593 /*
594 TODO: get vendor id from EEPROM for i82557C or later.
595 TODO: get device id from EEPROM for i82557C or later.
596 TODO: status bit 4 can be disabled by EEPROM for i82558, i82559.
597 TODO: header type is determined by EEPROM for i82559.
598 TODO: get subsystem id from EEPROM for i82557C or later.
599 TODO: get subsystem vendor id from EEPROM for i82557C or later.
600 TODO: exp. rom baddr depends on a bit in EEPROM for i82558 or later.
601 TODO: capability pointer depends on EEPROM for i82558.
602 */
603 logout("Get device id and revision from EEPROM!!!\n");
604 }
605 #endif /* EEPROM_SIZE > 0 */
606 }
607
608 static void nic_selective_reset(EEPRO100State * s)
609 {
610 #if EEPROM_SIZE > 0
611 static const uint16_t eeprom_i82559[] = {
612 /* 0x0000 */ 0x0000, 0x0000, 0x0000, 0x020b,
613 /* 0x0008 */ 0xffff, 0x0201, 0x4701, 0xffff,
614 /* 0x0010 */ 0x7517, 0x6704, 0x50a2, 0x0040,
615 /* 0x0018 */ 0x8086, 0x0064, 0xffff, 0xffff,
616 /* 0x0020 */ 0xffff, 0xffff, 0xffff, 0xffff,
617 /* 0x0028 */ 0xffff, 0xffff, 0xffff, 0xffff,
618 /* 0x0030 */ 0xffff, 0xffff, 0xffff, 0xffff,
619 /* 0x0038 */ 0xffff, 0xffff, 0xffff, 0xffff,
620 /* 0x0040 */ 0xffff, 0xffff, 0xffff, 0x1229,
621 /* 0x0048 */ 0xffff, 0xffff, 0xffff, 0xffff,
622 /* 0x0050 */ 0xffff, 0xffff, 0xffff, 0xffff,
623 /* 0x0058 */ 0xffff, 0xffff, 0xffff, 0xffff,
624 /* 0x0060 */ 0x002c, 0x4000, 0x3003, 0xffff,
625 /* 0x0068 */ 0xffff, 0xffff, 0xffff, 0xffff,
626 /* 0x0070 */ 0xffff, 0xffff, 0xffff, 0xffff,
627 /* 0x0078 */ 0xffff, 0xffff, 0xffff, 0xffff,
628 };
629 size_t i;
630 uint8_t *pci_conf = s->dev.config;
631 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
632 #if 0
633 eeprom93xx_reset(s->eeprom);
634 #endif
635 memcpy(eeprom_contents, eeprom_i82559, EEPROM_SIZE * 2);
636 memcpy(eeprom_contents, s->conf.macaddr.a, 6);
637 #if defined(WORDS_BIGENDIAN)
638 bswap16s(&eeprom_contents[0]);
639 bswap16s(&eeprom_contents[1]);
640 bswap16s(&eeprom_contents[2]);
641 #endif
642 #if 0
643 /* Only needed to set a different vendor id. */
644 memcpy(eeprom_contents + eeprom_vendor_id, pci_conf + PCI_VENDOR_ID, 2);
645 #if defined(WORDS_BIGENDIAN)
646 bswap16s(&eeprom_contents[eeprom_vendor_id]);
647 #endif
648 #endif /* EEPROM_SIZE > 0 */
649 memcpy(eeprom_contents + EEPROM_DEVICE_ID, pci_conf + PCI_DEVICE_ID, 2);
650 #if defined(WORDS_BIGENDIAN)
651 bswap16s(&eeprom_contents[EEPROM_DEVICE_ID]);
652 #endif
653 #if 0
654 /* We might change the phy id here. */
655 eeprom_contents[EEPROM_PHY_ID] =
656 (eeprom_contents[EEPROM_PHY_ID] & 0xff00) + 1;
657 #endif
658 /* TODO: eeprom_id_alt for i82559 */
659 eeprom_contents[EEPROM_ID] |= EEPROM_ID_VALID;
660 if (s->device >= i82557A && s->device <= i82557C) {
661 /* Set revision. */
662 eeprom_contents[EEPROM_ID] |= BIT(8);
663 }
664 /* TODO: source of next statement? */
665 eeprom_contents[0xa] = 0x4000;
666 if (s->device == i82557B || s->device == i82557C)
667 eeprom_contents[5] = 0x0100;
668 eeprom_contents[EEPROM_PHY_ID] = 1;
669 uint16_t sum = 0;
670 for (i = 0; i < EEPROM_SIZE - 1; i++) {
671 sum += eeprom_contents[i];
672 }
673 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
674 TRACE(EEPROM, logout("checksum=0x%04x\n", eeprom_contents[EEPROM_SIZE - 1]));
675 #endif
676
677 memset(s->mem, 0, sizeof(s->mem));
678 e100_write_reg4(s, SCBCtrlMDI, BIT(21));
679
680 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
681 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
682 }
683
684 static void nic_reset(void *opaque)
685 {
686 EEPRO100State *s = opaque;
687 TRACE(OTHER, logout("%p\n", s));
688 /* TODO: Clearing of hash register for selective reset, too? */
689 memset(&s->mult[0], 0, sizeof(s->mult));
690 nic_selective_reset(s);
691 }
692
693 #if defined(DEBUG_EEPRO100)
694 static const char * const e100_reg[PCI_IO_SIZE / 4] = {
695 "Command/Status",
696 "General Pointer",
697 "Port",
698 "EEPROM/Flash Control",
699 "MDI Control",
700 "Receive DMA Byte Count",
701 "Flow Control",
702 "General Status/Control"
703 };
704
705 static char *regname(uint32_t addr)
706 {
707 static char buf[32];
708 if (addr < PCI_IO_SIZE) {
709 const char *r = e100_reg[addr / 4];
710 if (r != 0) {
711 snprintf(buf, sizeof(buf), "%s+%u", r, addr % 4);
712 } else {
713 snprintf(buf, sizeof(buf), "0x%02x", addr);
714 }
715 } else {
716 snprintf(buf, sizeof(buf), "??? 0x%08x", addr);
717 }
718 return buf;
719 }
720 #endif /* DEBUG_EEPRO100 */
721
722 /*****************************************************************************
723 *
724 * Command emulation.
725 *
726 ****************************************************************************/
727
728 #if 0
729 static uint16_t eepro100_read_command(EEPRO100State * s)
730 {
731 uint16_t val = 0xffff;
732 TRACE(OTHER, logout("val=0x%04x\n", val));
733 return val;
734 }
735 #endif
736
737 /* Commands that can be put in a command list entry. */
738 enum commands {
739 CmdNOp = 0,
740 CmdIASetup = 1,
741 CmdConfigure = 2,
742 CmdMulticastList = 3,
743 CmdTx = 4,
744 CmdTDR = 5, /* load microcode */
745 CmdDump = 6,
746 CmdDiagnose = 7,
747
748 /* And some extra flags: */
749 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
750 };
751
752 static cu_state_t get_cu_state(EEPRO100State * s)
753 {
754 return ((s->mem[SCBStatus] & BITS(7, 6)) >> 6);
755 }
756
757 static void set_cu_state(EEPRO100State * s, cu_state_t state)
758 {
759 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(7, 6)) + (state << 6);
760 }
761
762 static ru_state_t get_ru_state(EEPRO100State * s)
763 {
764 return ((s->mem[SCBStatus] & BITS(5, 2)) >> 2);
765 }
766
767 static void set_ru_state(EEPRO100State * s, ru_state_t state)
768 {
769 s->mem[SCBStatus] = (s->mem[SCBStatus] & ~BITS(5, 2)) + (state << 2);
770 }
771
772 static void dump_statistics(EEPRO100State * s)
773 {
774 /* Dump statistical data. Most data is never changed by the emulation
775 * and always 0, so we first just copy the whole block and then those
776 * values which really matter.
777 * Number of data should check configuration!!!
778 */
779 pci_dma_write(&s->dev, s->statsaddr, &s->statistics, s->stats_size);
780 stl_le_pci_dma(&s->dev, s->statsaddr + 0, s->statistics.tx_good_frames);
781 stl_le_pci_dma(&s->dev, s->statsaddr + 36, s->statistics.rx_good_frames);
782 stl_le_pci_dma(&s->dev, s->statsaddr + 48,
783 s->statistics.rx_resource_errors);
784 stl_le_pci_dma(&s->dev, s->statsaddr + 60,
785 s->statistics.rx_short_frame_errors);
786 #if 0
787 stw_le_pci_dma(&s->dev, s->statsaddr + 76, s->statistics.xmt_tco_frames);
788 stw_le_pci_dma(&s->dev, s->statsaddr + 78, s->statistics.rcv_tco_frames);
789 missing("CU dump statistical counters");
790 #endif
791 }
792
793 static void read_cb(EEPRO100State *s)
794 {
795 pci_dma_read(&s->dev, s->cb_address, &s->tx, sizeof(s->tx));
796 s->tx.status = le16_to_cpu(s->tx.status);
797 s->tx.command = le16_to_cpu(s->tx.command);
798 s->tx.link = le32_to_cpu(s->tx.link);
799 s->tx.tbd_array_addr = le32_to_cpu(s->tx.tbd_array_addr);
800 s->tx.tcb_bytes = le16_to_cpu(s->tx.tcb_bytes);
801 }
802
803 static void tx_command(EEPRO100State *s)
804 {
805 uint32_t tbd_array = le32_to_cpu(s->tx.tbd_array_addr);
806 uint16_t tcb_bytes = (le16_to_cpu(s->tx.tcb_bytes) & 0x3fff);
807 /* Sends larger than MAX_ETH_FRAME_SIZE are allowed, up to 2600 bytes. */
808 uint8_t buf[2600];
809 uint16_t size = 0;
810 uint32_t tbd_address = s->cb_address + 0x10;
811 TRACE(RXTX, logout
812 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
813 tbd_array, tcb_bytes, s->tx.tbd_count));
814 assert(!(s->tx.command & COMMAND_NC));
815 assert(tcb_bytes <= sizeof(buf));
816 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
817 logout
818 ("illegal values of TBD array address and TCB byte count!\n");
819 }
820 if (s->tx.command & COMMAND_SF) {
821 /* No simplified mode. TODO: check code in this block. */
822 for (size = 0; size < tcb_bytes; ) {
823 uint32_t tx_buffer_address = ldl_le_pci_dma(&s->dev, tbd_address);
824 uint16_t tx_buffer_size = lduw_le_pci_dma(&s->dev, tbd_address + 4);
825 #if 0
826 uint16_t tx_buffer_el = lduw_le_pci_dma(&s->dev, tbd_address + 6);
827 #endif
828 tbd_address += 8;
829 TRACE(RXTX, logout
830 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
831 tx_buffer_address, tx_buffer_size));
832 if (size + tx_buffer_size > sizeof(buf)) {
833 logout("bad simple TCB with size 0x%04x\n", tx_buffer_size);
834 } else {
835 pci_dma_read(&s->dev, tx_buffer_address, &buf[size],
836 tx_buffer_size);
837 }
838 size += tx_buffer_size;
839 }
840 }
841 if (!(s->tx.command & COMMAND_SF)) {
842 /* Simplified mode. */
843 if (tcb_bytes > sizeof(buf)) {
844 logout("bad TCB byte count 0x%04x (simplified mode)\n", tcb_bytes);
845 } else if (tbd_array != 0xffffffff) {
846 logout("bad TCB array address 0x%04x (simplified mode)\n", tbd_array);
847 UNEXPECTED();
848 } else {
849 cpu_physical_memory_read(tbd_address, &buf[0], tcb_bytes);
850 }
851 } else {
852 /* Flexible mode. */
853 uint8_t tbd_count = 0;
854 if (!(s->configuration[6] & BIT(4))) {
855 /* Extended TxCB. */
856 assert(tcb_bytes == 0);
857 for (; tbd_count < 2 && tbd_count < s->tx.tbd_count; tbd_count++) {
858 uint32_t tx_buffer_address = ldl_le_pci_dma(&s->dev, tbd_address);
859 uint16_t tx_buffer_size = lduw_le_pci_dma(&s->dev, tbd_address + 4);
860 uint16_t tx_buffer_el = lduw_le_pci_dma(&s->dev, tbd_address + 6);
861 tbd_address += 8;
862 TRACE(RXTX, logout
863 ("TBD (extended mode): buffer address 0x%08x, size 0x%04x\n",
864 tx_buffer_address, tx_buffer_size));
865 if (size + tx_buffer_size > sizeof(buf)) {
866 logout("bad extended TCB with size 0x%04x\n", tx_buffer_size);
867 } else if (tx_buffer_size > 0) {
868 assert(tx_buffer_address != 0);
869 pci_dma_read(&s->dev, tx_buffer_address, &buf[size],
870 tx_buffer_size);
871 size += tx_buffer_size;
872 }
873 if (tx_buffer_el & 1) {
874 break;
875 }
876 }
877 }
878 tbd_address = tbd_array;
879 for (; tbd_count < s->tx.tbd_count; tbd_count++) {
880 uint32_t tx_buffer_address = ldl_le_pci_dma(&s->dev, tbd_address);
881 uint16_t tx_buffer_size = lduw_le_pci_dma(&s->dev, tbd_address + 4);
882 uint16_t tx_buffer_el = lduw_le_pci_dma(&s->dev, tbd_address + 6);
883 tbd_address += 8;
884 TRACE(RXTX, logout
885 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
886 tx_buffer_address, tx_buffer_size));
887 if (size + tx_buffer_size > sizeof(buf)) {
888 logout("bad flexible TCB with size 0x%04x\n", tx_buffer_size);
889 } else {
890 pci_dma_read(&s->dev, tx_buffer_address, &buf[size],
891 tx_buffer_size);
892 size += tx_buffer_size;
893 }
894 if (tx_buffer_el & 1) {
895 break;
896 }
897 }
898 }
899 TRACE(RXTX, logout("%p sending frame, len=%d,%s\n", s, size, nic_dump(buf, size)));
900 assert(size <= sizeof(buf));
901 qemu_send_packet(qemu_get_queue(s->nic), buf, size);
902 s->statistics.tx_good_frames++;
903 /* Transmit with bad status would raise an CX/TNO interrupt.
904 * (82557 only). Emulation never has bad status. */
905 #if 0
906 eepro100_cx_interrupt(s);
907 #endif
908 }
909
910 static void set_multicast_list(EEPRO100State *s)
911 {
912 uint16_t multicast_count = s->tx.tbd_array_addr & BITS(13, 0);
913 uint16_t i;
914 memset(&s->mult[0], 0, sizeof(s->mult));
915 TRACE(OTHER, logout("multicast list, multicast count = %u\n", multicast_count));
916 for (i = 0; i < multicast_count; i += 6) {
917 uint8_t multicast_addr[6];
918 pci_dma_read(&s->dev, s->cb_address + 10 + i, multicast_addr, 6);
919 TRACE(OTHER, logout("multicast entry %s\n", nic_dump(multicast_addr, 6)));
920 unsigned mcast_idx = e100_compute_mcast_idx(multicast_addr);
921 assert(mcast_idx < 64);
922 s->mult[mcast_idx >> 3] |= (1 << (mcast_idx & 7));
923 }
924 }
925
926 static void action_command(EEPRO100State *s)
927 {
928 for (;;) {
929 bool bit_el;
930 bool bit_s;
931 bool bit_i;
932 bool bit_nc;
933 uint16_t ok_status = STATUS_OK;
934 s->cb_address = s->cu_base + s->cu_offset;
935 read_cb(s);
936 bit_el = ((s->tx.command & COMMAND_EL) != 0);
937 bit_s = ((s->tx.command & COMMAND_S) != 0);
938 bit_i = ((s->tx.command & COMMAND_I) != 0);
939 bit_nc = ((s->tx.command & COMMAND_NC) != 0);
940 s->cu_offset = s->tx.link;
941 TRACE(OTHER, logout
942 ("val=(cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
943 s->tx.status, s->tx.command, s->cu_offset));
944 switch (s->tx.command & COMMAND_CMD) {
945 case CmdNOp:
946 /* Do nothing. */
947 break;
948 case CmdIASetup:
949 pci_dma_read(&s->dev, s->cb_address + 8, &s->conf.macaddr.a[0], 6);
950 TRACE(OTHER, logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6)));
951 /* TODO: missing code. */
952 break;
953 case CmdConfigure:
954 pci_dma_read(&s->dev, s->cb_address + 8, &s->configuration[0],
955 sizeof(s->configuration));
956 if (!s->has_extended_tcb_support) {
957 /* Force standard TxCB. */
958 s->configuration[6] |= BIT(4);
959 }
960 TRACE(OTHER, logout("configuration: %s\n",
961 nic_dump(&s->configuration[0], 16)));
962 TRACE(OTHER, logout("configuration: %s\n",
963 nic_dump(&s->configuration[16],
964 ARRAY_SIZE(s->configuration) - 16)));
965 if (s->configuration[20] & BIT(6)) {
966 TRACE(OTHER, logout("Multiple IA bit\n"));
967 }
968 break;
969 case CmdMulticastList:
970 set_multicast_list(s);
971 break;
972 case CmdTx:
973 if (bit_nc) {
974 missing("CmdTx: NC = 0");
975 ok_status = 0;
976 break;
977 }
978 tx_command(s);
979 break;
980 case CmdTDR:
981 TRACE(OTHER, logout("load microcode\n"));
982 /* Starting with offset 8, the command contains
983 * 64 dwords microcode which we just ignore here. */
984 break;
985 case CmdDiagnose:
986 TRACE(OTHER, logout("diagnose\n"));
987 /* Make sure error flag is not set. */
988 s->tx.status = 0;
989 break;
990 default:
991 missing("undefined command");
992 ok_status = 0;
993 break;
994 }
995 /* Write new status. */
996 stw_le_pci_dma(&s->dev, s->cb_address,
997 s->tx.status | ok_status | STATUS_C);
998 if (bit_i) {
999 /* CU completed action. */
1000 eepro100_cx_interrupt(s);
1001 }
1002 if (bit_el) {
1003 /* CU becomes idle. Terminate command loop. */
1004 set_cu_state(s, cu_idle);
1005 eepro100_cna_interrupt(s);
1006 break;
1007 } else if (bit_s) {
1008 /* CU becomes suspended. Terminate command loop. */
1009 set_cu_state(s, cu_suspended);
1010 eepro100_cna_interrupt(s);
1011 break;
1012 } else {
1013 /* More entries in list. */
1014 TRACE(OTHER, logout("CU list with at least one more entry\n"));
1015 }
1016 }
1017 TRACE(OTHER, logout("CU list empty\n"));
1018 /* List is empty. Now CU is idle or suspended. */
1019 }
1020
1021 static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
1022 {
1023 cu_state_t cu_state;
1024 switch (val) {
1025 case CU_NOP:
1026 /* No operation. */
1027 break;
1028 case CU_START:
1029 cu_state = get_cu_state(s);
1030 if (cu_state != cu_idle && cu_state != cu_suspended) {
1031 /* Intel documentation says that CU must be idle or suspended
1032 * for the CU start command. */
1033 logout("unexpected CU state is %u\n", cu_state);
1034 }
1035 set_cu_state(s, cu_active);
1036 s->cu_offset = e100_read_reg4(s, SCBPointer);
1037 action_command(s);
1038 break;
1039 case CU_RESUME:
1040 if (get_cu_state(s) != cu_suspended) {
1041 logout("bad CU resume from CU state %u\n", get_cu_state(s));
1042 /* Workaround for bad Linux eepro100 driver which resumes
1043 * from idle state. */
1044 #if 0
1045 missing("cu resume");
1046 #endif
1047 set_cu_state(s, cu_suspended);
1048 }
1049 if (get_cu_state(s) == cu_suspended) {
1050 TRACE(OTHER, logout("CU resuming\n"));
1051 set_cu_state(s, cu_active);
1052 action_command(s);
1053 }
1054 break;
1055 case CU_STATSADDR:
1056 /* Load dump counters address. */
1057 s->statsaddr = e100_read_reg4(s, SCBPointer);
1058 TRACE(OTHER, logout("val=0x%02x (dump counters address)\n", val));
1059 if (s->statsaddr & 3) {
1060 /* Memory must be Dword aligned. */
1061 logout("unaligned dump counters address\n");
1062 /* Handling of misaligned addresses is undefined.
1063 * Here we align the address by ignoring the lower bits. */
1064 /* TODO: Test unaligned dump counter address on real hardware. */
1065 s->statsaddr &= ~3;
1066 }
1067 break;
1068 case CU_SHOWSTATS:
1069 /* Dump statistical counters. */
1070 TRACE(OTHER, logout("val=0x%02x (dump stats)\n", val));
1071 dump_statistics(s);
1072 stl_le_pci_dma(&s->dev, s->statsaddr + s->stats_size, 0xa005);
1073 break;
1074 case CU_CMD_BASE:
1075 /* Load CU base. */
1076 TRACE(OTHER, logout("val=0x%02x (CU base address)\n", val));
1077 s->cu_base = e100_read_reg4(s, SCBPointer);
1078 break;
1079 case CU_DUMPSTATS:
1080 /* Dump and reset statistical counters. */
1081 TRACE(OTHER, logout("val=0x%02x (dump stats and reset)\n", val));
1082 dump_statistics(s);
1083 stl_le_pci_dma(&s->dev, s->statsaddr + s->stats_size, 0xa007);
1084 memset(&s->statistics, 0, sizeof(s->statistics));
1085 break;
1086 case CU_SRESUME:
1087 /* CU static resume. */
1088 missing("CU static resume");
1089 break;
1090 default:
1091 missing("Undefined CU command");
1092 }
1093 }
1094
1095 static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
1096 {
1097 switch (val) {
1098 case RU_NOP:
1099 /* No operation. */
1100 break;
1101 case RX_START:
1102 /* RU start. */
1103 if (get_ru_state(s) != ru_idle) {
1104 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
1105 #if 0
1106 assert(!"wrong RU state");
1107 #endif
1108 }
1109 set_ru_state(s, ru_ready);
1110 s->ru_offset = e100_read_reg4(s, SCBPointer);
1111 qemu_flush_queued_packets(qemu_get_queue(s->nic));
1112 TRACE(OTHER, logout("val=0x%02x (rx start)\n", val));
1113 break;
1114 case RX_RESUME:
1115 /* Restart RU. */
1116 if (get_ru_state(s) != ru_suspended) {
1117 logout("RU state is %u, should be %u\n", get_ru_state(s),
1118 ru_suspended);
1119 #if 0
1120 assert(!"wrong RU state");
1121 #endif
1122 }
1123 set_ru_state(s, ru_ready);
1124 break;
1125 case RU_ABORT:
1126 /* RU abort. */
1127 if (get_ru_state(s) == ru_ready) {
1128 eepro100_rnr_interrupt(s);
1129 }
1130 set_ru_state(s, ru_idle);
1131 break;
1132 case RX_ADDR_LOAD:
1133 /* Load RU base. */
1134 TRACE(OTHER, logout("val=0x%02x (RU base address)\n", val));
1135 s->ru_base = e100_read_reg4(s, SCBPointer);
1136 break;
1137 default:
1138 logout("val=0x%02x (undefined RU command)\n", val);
1139 missing("Undefined RU command");
1140 }
1141 }
1142
1143 static void eepro100_write_command(EEPRO100State * s, uint8_t val)
1144 {
1145 eepro100_ru_command(s, val & 0x0f);
1146 eepro100_cu_command(s, val & 0xf0);
1147 if ((val) == 0) {
1148 TRACE(OTHER, logout("val=0x%02x\n", val));
1149 }
1150 /* Clear command byte after command was accepted. */
1151 s->mem[SCBCmd] = 0;
1152 }
1153
1154 /*****************************************************************************
1155 *
1156 * EEPROM emulation.
1157 *
1158 ****************************************************************************/
1159
1160 #define EEPROM_CS 0x02
1161 #define EEPROM_SK 0x01
1162 #define EEPROM_DI 0x04
1163 #define EEPROM_DO 0x08
1164
1165 static uint16_t eepro100_read_eeprom(EEPRO100State * s)
1166 {
1167 uint16_t val = e100_read_reg2(s, SCBeeprom);
1168 if (eeprom93xx_read(s->eeprom)) {
1169 val |= EEPROM_DO;
1170 } else {
1171 val &= ~EEPROM_DO;
1172 }
1173 TRACE(EEPROM, logout("val=0x%04x\n", val));
1174 return val;
1175 }
1176
1177 static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
1178 {
1179 TRACE(EEPROM, logout("val=0x%02x\n", val));
1180
1181 /* mask unwritable bits */
1182 #if 0
1183 val = SET_MASKED(val, 0x31, eeprom->value);
1184 #endif
1185
1186 int eecs = ((val & EEPROM_CS) != 0);
1187 int eesk = ((val & EEPROM_SK) != 0);
1188 int eedi = ((val & EEPROM_DI) != 0);
1189 eeprom93xx_write(eeprom, eecs, eesk, eedi);
1190 }
1191
1192 /*****************************************************************************
1193 *
1194 * MDI emulation.
1195 *
1196 ****************************************************************************/
1197
1198 #if defined(DEBUG_EEPRO100)
1199 static const char * const mdi_op_name[] = {
1200 "opcode 0",
1201 "write",
1202 "read",
1203 "opcode 3"
1204 };
1205
1206 static const char * const mdi_reg_name[] = {
1207 "Control",
1208 "Status",
1209 "PHY Identification (Word 1)",
1210 "PHY Identification (Word 2)",
1211 "Auto-Negotiation Advertisement",
1212 "Auto-Negotiation Link Partner Ability",
1213 "Auto-Negotiation Expansion"
1214 };
1215
1216 static const char *reg2name(uint8_t reg)
1217 {
1218 static char buffer[10];
1219 const char *p = buffer;
1220 if (reg < ARRAY_SIZE(mdi_reg_name)) {
1221 p = mdi_reg_name[reg];
1222 } else {
1223 snprintf(buffer, sizeof(buffer), "reg=0x%02x", reg);
1224 }
1225 return p;
1226 }
1227 #endif /* DEBUG_EEPRO100 */
1228
1229 static uint32_t eepro100_read_mdi(EEPRO100State * s)
1230 {
1231 uint32_t val = e100_read_reg4(s, SCBCtrlMDI);
1232
1233 #ifdef DEBUG_EEPRO100
1234 uint8_t raiseint = (val & BIT(29)) >> 29;
1235 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1236 uint8_t phy = (val & BITS(25, 21)) >> 21;
1237 uint8_t reg = (val & BITS(20, 16)) >> 16;
1238 uint16_t data = (val & BITS(15, 0));
1239 #endif
1240 /* Emulation takes no time to finish MDI transaction. */
1241 val |= BIT(28);
1242 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1243 val, raiseint, mdi_op_name[opcode], phy,
1244 reg2name(reg), data));
1245 return val;
1246 }
1247
1248 static void eepro100_write_mdi(EEPRO100State *s)
1249 {
1250 uint32_t val = e100_read_reg4(s, SCBCtrlMDI);
1251 uint8_t raiseint = (val & BIT(29)) >> 29;
1252 uint8_t opcode = (val & BITS(27, 26)) >> 26;
1253 uint8_t phy = (val & BITS(25, 21)) >> 21;
1254 uint8_t reg = (val & BITS(20, 16)) >> 16;
1255 uint16_t data = (val & BITS(15, 0));
1256 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1257 val, raiseint, mdi_op_name[opcode], phy, reg2name(reg), data));
1258 if (phy != 1) {
1259 /* Unsupported PHY address. */
1260 #if 0
1261 logout("phy must be 1 but is %u\n", phy);
1262 #endif
1263 data = 0;
1264 } else if (opcode != 1 && opcode != 2) {
1265 /* Unsupported opcode. */
1266 logout("opcode must be 1 or 2 but is %u\n", opcode);
1267 data = 0;
1268 } else if (reg > 6) {
1269 /* Unsupported register. */
1270 logout("register must be 0...6 but is %u\n", reg);
1271 data = 0;
1272 } else {
1273 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1274 val, raiseint, mdi_op_name[opcode], phy,
1275 reg2name(reg), data));
1276 if (opcode == 1) {
1277 /* MDI write */
1278 switch (reg) {
1279 case 0: /* Control Register */
1280 if (data & 0x8000) {
1281 /* Reset status and control registers to default. */
1282 s->mdimem[0] = eepro100_mdi_default[0];
1283 s->mdimem[1] = eepro100_mdi_default[1];
1284 data = s->mdimem[reg];
1285 } else {
1286 /* Restart Auto Configuration = Normal Operation */
1287 data &= ~0x0200;
1288 }
1289 break;
1290 case 1: /* Status Register */
1291 missing("not writable");
1292 break;
1293 case 2: /* PHY Identification Register (Word 1) */
1294 case 3: /* PHY Identification Register (Word 2) */
1295 missing("not implemented");
1296 break;
1297 case 4: /* Auto-Negotiation Advertisement Register */
1298 case 5: /* Auto-Negotiation Link Partner Ability Register */
1299 break;
1300 case 6: /* Auto-Negotiation Expansion Register */
1301 default:
1302 missing("not implemented");
1303 }
1304 s->mdimem[reg] &= eepro100_mdi_mask[reg];
1305 s->mdimem[reg] |= data & ~eepro100_mdi_mask[reg];
1306 } else if (opcode == 2) {
1307 /* MDI read */
1308 switch (reg) {
1309 case 0: /* Control Register */
1310 if (data & 0x8000) {
1311 /* Reset status and control registers to default. */
1312 s->mdimem[0] = eepro100_mdi_default[0];
1313 s->mdimem[1] = eepro100_mdi_default[1];
1314 }
1315 break;
1316 case 1: /* Status Register */
1317 s->mdimem[reg] |= 0x0020;
1318 break;
1319 case 2: /* PHY Identification Register (Word 1) */
1320 case 3: /* PHY Identification Register (Word 2) */
1321 case 4: /* Auto-Negotiation Advertisement Register */
1322 break;
1323 case 5: /* Auto-Negotiation Link Partner Ability Register */
1324 s->mdimem[reg] = 0x41fe;
1325 break;
1326 case 6: /* Auto-Negotiation Expansion Register */
1327 s->mdimem[reg] = 0x0001;
1328 break;
1329 }
1330 data = s->mdimem[reg];
1331 }
1332 /* Emulation takes no time to finish MDI transaction.
1333 * Set MDI bit in SCB status register. */
1334 s->mem[SCBAck] |= 0x08;
1335 val |= BIT(28);
1336 if (raiseint) {
1337 eepro100_mdi_interrupt(s);
1338 }
1339 }
1340 val = (val & 0xffff0000) + data;
1341 e100_write_reg4(s, SCBCtrlMDI, val);
1342 }
1343
1344 /*****************************************************************************
1345 *
1346 * Port emulation.
1347 *
1348 ****************************************************************************/
1349
1350 #define PORT_SOFTWARE_RESET 0
1351 #define PORT_SELFTEST 1
1352 #define PORT_SELECTIVE_RESET 2
1353 #define PORT_DUMP 3
1354 #define PORT_SELECTION_MASK 3
1355
1356 typedef struct {
1357 uint32_t st_sign; /* Self Test Signature */
1358 uint32_t st_result; /* Self Test Results */
1359 } eepro100_selftest_t;
1360
1361 static uint32_t eepro100_read_port(EEPRO100State * s)
1362 {
1363 return 0;
1364 }
1365
1366 static void eepro100_write_port(EEPRO100State *s)
1367 {
1368 uint32_t val = e100_read_reg4(s, SCBPort);
1369 uint32_t address = (val & ~PORT_SELECTION_MASK);
1370 uint8_t selection = (val & PORT_SELECTION_MASK);
1371 switch (selection) {
1372 case PORT_SOFTWARE_RESET:
1373 nic_reset(s);
1374 break;
1375 case PORT_SELFTEST:
1376 TRACE(OTHER, logout("selftest address=0x%08x\n", address));
1377 eepro100_selftest_t data;
1378 pci_dma_read(&s->dev, address, (uint8_t *) &data, sizeof(data));
1379 data.st_sign = 0xffffffff;
1380 data.st_result = 0;
1381 pci_dma_write(&s->dev, address, (uint8_t *) &data, sizeof(data));
1382 break;
1383 case PORT_SELECTIVE_RESET:
1384 TRACE(OTHER, logout("selective reset, selftest address=0x%08x\n", address));
1385 nic_selective_reset(s);
1386 break;
1387 default:
1388 logout("val=0x%08x\n", val);
1389 missing("unknown port selection");
1390 }
1391 }
1392
1393 /*****************************************************************************
1394 *
1395 * General hardware emulation.
1396 *
1397 ****************************************************************************/
1398
1399 static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1400 {
1401 uint8_t val = 0;
1402 assert(addr <= sizeof(s->mem) - sizeof(val));
1403 if (addr <= sizeof(s->mem) - sizeof(val)) {
1404 val = s->mem[addr];
1405 }
1406
1407 switch (addr) {
1408 case SCBStatus:
1409 case SCBAck:
1410 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1411 break;
1412 case SCBCmd:
1413 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1414 #if 0
1415 val = eepro100_read_command(s);
1416 #endif
1417 break;
1418 case SCBIntmask:
1419 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1420 break;
1421 case SCBPort + 3:
1422 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1423 break;
1424 case SCBeeprom:
1425 val = eepro100_read_eeprom(s);
1426 break;
1427 case SCBCtrlMDI:
1428 case SCBCtrlMDI + 1:
1429 case SCBCtrlMDI + 2:
1430 case SCBCtrlMDI + 3:
1431 val = (uint8_t)(eepro100_read_mdi(s) >> (8 * (addr & 3)));
1432 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1433 break;
1434 case SCBpmdr: /* Power Management Driver Register */
1435 val = 0;
1436 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1437 break;
1438 case SCBgctrl: /* General Control Register */
1439 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1440 break;
1441 case SCBgstat: /* General Status Register */
1442 /* 100 Mbps full duplex, valid link */
1443 val = 0x07;
1444 TRACE(OTHER, logout("addr=General Status val=%02x\n", val));
1445 break;
1446 default:
1447 logout("addr=%s val=0x%02x\n", regname(addr), val);
1448 missing("unknown byte read");
1449 }
1450 return val;
1451 }
1452
1453 static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1454 {
1455 uint16_t val = 0;
1456 assert(addr <= sizeof(s->mem) - sizeof(val));
1457 if (addr <= sizeof(s->mem) - sizeof(val)) {
1458 val = e100_read_reg2(s, addr);
1459 }
1460
1461 switch (addr) {
1462 case SCBStatus:
1463 case SCBCmd:
1464 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1465 break;
1466 case SCBeeprom:
1467 val = eepro100_read_eeprom(s);
1468 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1469 break;
1470 case SCBCtrlMDI:
1471 case SCBCtrlMDI + 2:
1472 val = (uint16_t)(eepro100_read_mdi(s) >> (8 * (addr & 3)));
1473 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1474 break;
1475 default:
1476 logout("addr=%s val=0x%04x\n", regname(addr), val);
1477 missing("unknown word read");
1478 }
1479 return val;
1480 }
1481
1482 static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1483 {
1484 uint32_t val = 0;
1485 assert(addr <= sizeof(s->mem) - sizeof(val));
1486 if (addr <= sizeof(s->mem) - sizeof(val)) {
1487 val = e100_read_reg4(s, addr);
1488 }
1489
1490 switch (addr) {
1491 case SCBStatus:
1492 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1493 break;
1494 case SCBPointer:
1495 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1496 break;
1497 case SCBPort:
1498 val = eepro100_read_port(s);
1499 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1500 break;
1501 case SCBflash:
1502 val = eepro100_read_eeprom(s);
1503 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1504 break;
1505 case SCBCtrlMDI:
1506 val = eepro100_read_mdi(s);
1507 break;
1508 default:
1509 logout("addr=%s val=0x%08x\n", regname(addr), val);
1510 missing("unknown longword read");
1511 }
1512 return val;
1513 }
1514
1515 static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1516 {
1517 assert(addr <= sizeof(s->mem) - sizeof(val));
1518 /* SCBStatus is readonly. */
1519 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
1520 s->mem[addr] = val;
1521 }
1522
1523 switch (addr) {
1524 case SCBStatus:
1525 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1526 break;
1527 case SCBAck:
1528 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1529 eepro100_acknowledge(s);
1530 break;
1531 case SCBCmd:
1532 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1533 eepro100_write_command(s, val);
1534 break;
1535 case SCBIntmask:
1536 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1537 if (val & BIT(1)) {
1538 eepro100_swi_interrupt(s);
1539 }
1540 eepro100_interrupt(s, 0);
1541 break;
1542 case SCBPointer:
1543 case SCBPointer + 1:
1544 case SCBPointer + 2:
1545 case SCBPointer + 3:
1546 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1547 break;
1548 case SCBPort:
1549 case SCBPort + 1:
1550 case SCBPort + 2:
1551 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1552 break;
1553 case SCBPort + 3:
1554 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1555 eepro100_write_port(s);
1556 break;
1557 case SCBFlow: /* does not exist on 82557 */
1558 case SCBFlow + 1:
1559 case SCBFlow + 2:
1560 case SCBpmdr: /* does not exist on 82557 */
1561 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1562 break;
1563 case SCBeeprom:
1564 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1565 eepro100_write_eeprom(s->eeprom, val);
1566 break;
1567 case SCBCtrlMDI:
1568 case SCBCtrlMDI + 1:
1569 case SCBCtrlMDI + 2:
1570 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1571 break;
1572 case SCBCtrlMDI + 3:
1573 TRACE(OTHER, logout("addr=%s val=0x%02x\n", regname(addr), val));
1574 eepro100_write_mdi(s);
1575 break;
1576 default:
1577 logout("addr=%s val=0x%02x\n", regname(addr), val);
1578 missing("unknown byte write");
1579 }
1580 }
1581
1582 static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1583 {
1584 assert(addr <= sizeof(s->mem) - sizeof(val));
1585 /* SCBStatus is readonly. */
1586 if (addr > SCBStatus && addr <= sizeof(s->mem) - sizeof(val)) {
1587 e100_write_reg2(s, addr, val);
1588 }
1589
1590 switch (addr) {
1591 case SCBStatus:
1592 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1593 s->mem[SCBAck] = (val >> 8);
1594 eepro100_acknowledge(s);
1595 break;
1596 case SCBCmd:
1597 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1598 eepro100_write_command(s, val);
1599 eepro100_write1(s, SCBIntmask, val >> 8);
1600 break;
1601 case SCBPointer:
1602 case SCBPointer + 2:
1603 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1604 break;
1605 case SCBPort:
1606 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1607 break;
1608 case SCBPort + 2:
1609 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1610 eepro100_write_port(s);
1611 break;
1612 case SCBeeprom:
1613 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1614 eepro100_write_eeprom(s->eeprom, val);
1615 break;
1616 case SCBCtrlMDI:
1617 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1618 break;
1619 case SCBCtrlMDI + 2:
1620 TRACE(OTHER, logout("addr=%s val=0x%04x\n", regname(addr), val));
1621 eepro100_write_mdi(s);
1622 break;
1623 default:
1624 logout("addr=%s val=0x%04x\n", regname(addr), val);
1625 missing("unknown word write");
1626 }
1627 }
1628
1629 static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1630 {
1631 assert(addr <= sizeof(s->mem) - sizeof(val));
1632 if (addr <= sizeof(s->mem) - sizeof(val)) {
1633 e100_write_reg4(s, addr, val);
1634 }
1635
1636 switch (addr) {
1637 case SCBPointer:
1638 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1639 break;
1640 case SCBPort:
1641 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1642 eepro100_write_port(s);
1643 break;
1644 case SCBflash:
1645 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1646 val = val >> 16;
1647 eepro100_write_eeprom(s->eeprom, val);
1648 break;
1649 case SCBCtrlMDI:
1650 TRACE(OTHER, logout("addr=%s val=0x%08x\n", regname(addr), val));
1651 eepro100_write_mdi(s);
1652 break;
1653 default:
1654 logout("addr=%s val=0x%08x\n", regname(addr), val);
1655 missing("unknown longword write");
1656 }
1657 }
1658
1659 static uint64_t eepro100_read(void *opaque, hwaddr addr,
1660 unsigned size)
1661 {
1662 EEPRO100State *s = opaque;
1663
1664 switch (size) {
1665 case 1: return eepro100_read1(s, addr);
1666 case 2: return eepro100_read2(s, addr);
1667 case 4: return eepro100_read4(s, addr);
1668 default: abort();
1669 }
1670 }
1671
1672 static void eepro100_write(void *opaque, hwaddr addr,
1673 uint64_t data, unsigned size)
1674 {
1675 EEPRO100State *s = opaque;
1676
1677 switch (size) {
1678 case 1:
1679 eepro100_write1(s, addr, data);
1680 break;
1681 case 2:
1682 eepro100_write2(s, addr, data);
1683 break;
1684 case 4:
1685 eepro100_write4(s, addr, data);
1686 break;
1687 default:
1688 abort();
1689 }
1690 }
1691
1692 static const MemoryRegionOps eepro100_ops = {
1693 .read = eepro100_read,
1694 .write = eepro100_write,
1695 .endianness = DEVICE_LITTLE_ENDIAN,
1696 };
1697
1698 static ssize_t nic_receive(NetClientState *nc, const uint8_t * buf, size_t size)
1699 {
1700 /* TODO:
1701 * - Magic packets should set bit 30 in power management driver register.
1702 * - Interesting packets should set bit 29 in power management driver register.
1703 */
1704 EEPRO100State *s = qemu_get_nic_opaque(nc);
1705 uint16_t rfd_status = 0xa000;
1706 #if defined(CONFIG_PAD_RECEIVED_FRAMES)
1707 uint8_t min_buf[60];
1708 #endif
1709 static const uint8_t broadcast_macaddr[6] =
1710 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1711
1712 #if defined(CONFIG_PAD_RECEIVED_FRAMES)
1713 /* Pad to minimum Ethernet frame length */
1714 if (size < sizeof(min_buf)) {
1715 memcpy(min_buf, buf, size);
1716 memset(&min_buf[size], 0, sizeof(min_buf) - size);
1717 buf = min_buf;
1718 size = sizeof(min_buf);
1719 }
1720 #endif
1721
1722 if (s->configuration[8] & 0x80) {
1723 /* CSMA is disabled. */
1724 logout("%p received while CSMA is disabled\n", s);
1725 return -1;
1726 #if !defined(CONFIG_PAD_RECEIVED_FRAMES)
1727 } else if (size < 64 && (s->configuration[7] & BIT(0))) {
1728 /* Short frame and configuration byte 7/0 (discard short receive) set:
1729 * Short frame is discarded */
1730 logout("%p received short frame (%zu byte)\n", s, size);
1731 s->statistics.rx_short_frame_errors++;
1732 return -1;
1733 #endif
1734 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & BIT(3))) {
1735 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1736 * Long frames are discarded. */
1737 logout("%p received long frame (%zu byte), ignored\n", s, size);
1738 return -1;
1739 } else if (memcmp(buf, s->conf.macaddr.a, 6) == 0) { /* !!! */
1740 /* Frame matches individual address. */
1741 /* TODO: check configuration byte 15/4 (ignore U/L). */
1742 TRACE(RXTX, logout("%p received frame for me, len=%zu\n", s, size));
1743 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1744 /* Broadcast frame. */
1745 TRACE(RXTX, logout("%p received broadcast, len=%zu\n", s, size));
1746 rfd_status |= 0x0002;
1747 } else if (buf[0] & 0x01) {
1748 /* Multicast frame. */
1749 TRACE(RXTX, logout("%p received multicast, len=%zu,%s\n", s, size, nic_dump(buf, size)));
1750 if (s->configuration[21] & BIT(3)) {
1751 /* Multicast all bit is set, receive all multicast frames. */
1752 } else {
1753 unsigned mcast_idx = e100_compute_mcast_idx(buf);
1754 assert(mcast_idx < 64);
1755 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1756 /* Multicast frame is allowed in hash table. */
1757 } else if (s->configuration[15] & BIT(0)) {
1758 /* Promiscuous: receive all. */
1759 rfd_status |= 0x0004;
1760 } else {
1761 TRACE(RXTX, logout("%p multicast ignored\n", s));
1762 return -1;
1763 }
1764 }
1765 /* TODO: Next not for promiscuous mode? */
1766 rfd_status |= 0x0002;
1767 } else if (s->configuration[15] & BIT(0)) {
1768 /* Promiscuous: receive all. */
1769 TRACE(RXTX, logout("%p received frame in promiscuous mode, len=%zu\n", s, size));
1770 rfd_status |= 0x0004;
1771 } else if (s->configuration[20] & BIT(6)) {
1772 /* Multiple IA bit set. */
1773 unsigned mcast_idx = compute_mcast_idx(buf);
1774 assert(mcast_idx < 64);
1775 if (s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))) {
1776 TRACE(RXTX, logout("%p accepted, multiple IA bit set\n", s));
1777 } else {
1778 TRACE(RXTX, logout("%p frame ignored, multiple IA bit set\n", s));
1779 return -1;
1780 }
1781 } else {
1782 TRACE(RXTX, logout("%p received frame, ignored, len=%zu,%s\n", s, size,
1783 nic_dump(buf, size)));
1784 return size;
1785 }
1786
1787 if (get_ru_state(s) != ru_ready) {
1788 /* No resources available. */
1789 logout("no resources, state=%u\n", get_ru_state(s));
1790 /* TODO: RNR interrupt only at first failed frame? */
1791 eepro100_rnr_interrupt(s);
1792 s->statistics.rx_resource_errors++;
1793 #if 0
1794 assert(!"no resources");
1795 #endif
1796 return -1;
1797 }
1798 /* !!! */
1799 eepro100_rx_t rx;
1800 pci_dma_read(&s->dev, s->ru_base + s->ru_offset, &rx,
1801 sizeof(eepro100_rx_t));
1802 /* !!! */
1803 uint16_t rfd_command = le16_to_cpu(rx.command);
1804 uint16_t rfd_size = le16_to_cpu(rx.size);
1805
1806 if (size > rfd_size) {
1807 /* TODO: does real hardware truncate, too? */
1808 logout("received frame with %zu > %u\n", size, rfd_size);
1809 UNEXPECTED();
1810 size = rfd_size;
1811 }
1812 #if !defined(CONFIG_PAD_RECEIVED_FRAMES)
1813 if (size < 64) {
1814 rfd_status |= 0x0080;
1815 }
1816 #endif
1817 TRACE(OTHER, logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n",
1818 rfd_command, rx.link, rx.rx_buf_addr, rfd_size));
1819 stw_le_pci_dma(&s->dev, s->ru_base + s->ru_offset +
1820 offsetof(eepro100_rx_t, status), rfd_status);
1821 stw_le_pci_dma(&s->dev, s->ru_base + s->ru_offset +
1822 offsetof(eepro100_rx_t, count), size);
1823 /* Early receive interrupt not supported. */
1824 #if 0
1825 eepro100_er_interrupt(s);
1826 #endif
1827 /* Receive CRC Transfer not supported. */
1828 if (s->configuration[18] & BIT(2)) {
1829 missing("Receive CRC Transfer");
1830 return -1;
1831 }
1832 /* TODO: check stripping enable bit. */
1833 #if 0
1834 assert(!(s->configuration[17] & BIT(0)));
1835 #endif
1836 pci_dma_write(&s->dev, s->ru_base + s->ru_offset +
1837 sizeof(eepro100_rx_t), buf, size);
1838 s->statistics.rx_good_frames++;
1839 eepro100_fr_interrupt(s);
1840 s->ru_offset = le32_to_cpu(rx.link);
1841 if (rfd_command & COMMAND_EL) {
1842 /* EL bit is set, so this was the last frame. */
1843 set_ru_state(s, ru_idle);
1844 #if 1
1845 logout("receive: Running out of frames\n");
1846 // TODO: do we need ru_suspended here?
1847 set_ru_state(s, ru_suspended);
1848 #endif
1849 set_ru_state(s, ru_no_resources);
1850 eepro100_rnr_interrupt(s);
1851 }
1852 if (rfd_command & COMMAND_S) {
1853 /* S bit is set. */
1854 set_ru_state(s, ru_suspended);
1855 }
1856 return size;
1857 }
1858
1859 static const VMStateDescription vmstate_eepro100 = {
1860 .version_id = 3,
1861 .minimum_version_id = 2,
1862 .fields = (VMStateField[]) {
1863 VMSTATE_PCI_DEVICE(dev, EEPRO100State),
1864 VMSTATE_UNUSED(32),
1865 VMSTATE_BUFFER(mult, EEPRO100State),
1866 VMSTATE_BUFFER(mem, EEPRO100State),
1867 /* Save all members of struct between scb_stat and mem. */
1868 VMSTATE_UINT8(scb_stat, EEPRO100State),
1869 VMSTATE_UINT8(int_stat, EEPRO100State),
1870 VMSTATE_UNUSED(3*4),
1871 VMSTATE_MACADDR(conf.macaddr, EEPRO100State),
1872 VMSTATE_UNUSED(19*4),
1873 VMSTATE_UINT16_ARRAY(mdimem, EEPRO100State, 32),
1874 /* The eeprom should be saved and restored by its own routines. */
1875 VMSTATE_UINT32(device, EEPRO100State),
1876 /* TODO check device. */
1877 VMSTATE_UINT32(cu_base, EEPRO100State),
1878 VMSTATE_UINT32(cu_offset, EEPRO100State),
1879 VMSTATE_UINT32(ru_base, EEPRO100State),
1880 VMSTATE_UINT32(ru_offset, EEPRO100State),
1881 VMSTATE_UINT32(statsaddr, EEPRO100State),
1882 /* Save eepro100_stats_t statistics. */
1883 VMSTATE_UINT32(statistics.tx_good_frames, EEPRO100State),
1884 VMSTATE_UINT32(statistics.tx_max_collisions, EEPRO100State),
1885 VMSTATE_UINT32(statistics.tx_late_collisions, EEPRO100State),
1886 VMSTATE_UINT32(statistics.tx_underruns, EEPRO100State),
1887 VMSTATE_UINT32(statistics.tx_lost_crs, EEPRO100State),
1888 VMSTATE_UINT32(statistics.tx_deferred, EEPRO100State),
1889 VMSTATE_UINT32(statistics.tx_single_collisions, EEPRO100State),
1890 VMSTATE_UINT32(statistics.tx_multiple_collisions, EEPRO100State),
1891 VMSTATE_UINT32(statistics.tx_total_collisions, EEPRO100State),
1892 VMSTATE_UINT32(statistics.rx_good_frames, EEPRO100State),
1893 VMSTATE_UINT32(statistics.rx_crc_errors, EEPRO100State),
1894 VMSTATE_UINT32(statistics.rx_alignment_errors, EEPRO100State),
1895 VMSTATE_UINT32(statistics.rx_resource_errors, EEPRO100State),
1896 VMSTATE_UINT32(statistics.rx_overrun_errors, EEPRO100State),
1897 VMSTATE_UINT32(statistics.rx_cdt_errors, EEPRO100State),
1898 VMSTATE_UINT32(statistics.rx_short_frame_errors, EEPRO100State),
1899 VMSTATE_UINT32(statistics.fc_xmt_pause, EEPRO100State),
1900 VMSTATE_UINT32(statistics.fc_rcv_pause, EEPRO100State),
1901 VMSTATE_UINT32(statistics.fc_rcv_unsupported, EEPRO100State),
1902 VMSTATE_UINT16(statistics.xmt_tco_frames, EEPRO100State),
1903 VMSTATE_UINT16(statistics.rcv_tco_frames, EEPRO100State),
1904 /* Configuration bytes. */
1905 VMSTATE_BUFFER(configuration, EEPRO100State),
1906 VMSTATE_END_OF_LIST()
1907 }
1908 };
1909
1910 static void pci_nic_uninit(PCIDevice *pci_dev)
1911 {
1912 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1913
1914 vmstate_unregister(&pci_dev->qdev, s->vmstate, s);
1915 eeprom93xx_free(&pci_dev->qdev, s->eeprom);
1916 qemu_del_nic(s->nic);
1917 }
1918
1919 static NetClientInfo net_eepro100_info = {
1920 .type = NET_CLIENT_OPTIONS_KIND_NIC,
1921 .size = sizeof(NICState),
1922 .receive = nic_receive,
1923 };
1924
1925 static void e100_nic_realize(PCIDevice *pci_dev, Error **errp)
1926 {
1927 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, pci_dev);
1928 E100PCIDeviceInfo *info = eepro100_get_class(s);
1929
1930 TRACE(OTHER, logout("\n"));
1931
1932 s->device = info->device;
1933
1934 e100_pci_reset(s);
1935
1936 #if EEPROM_SIZE > 0
1937 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1938 * i82559 and later support 64 or 256 word EEPROM. */
1939 s->eeprom = eeprom93xx_new(&pci_dev->qdev, EEPROM_SIZE);
1940 #endif
1941
1942 /* Handler for memory-mapped I/O */
1943 memory_region_init_io(&s->mmio_bar, OBJECT(s), &eepro100_ops, s,
1944 "eepro100-mmio", PCI_MEM_SIZE);
1945 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->mmio_bar);
1946 memory_region_init_io(&s->io_bar, OBJECT(s), &eepro100_ops, s,
1947 "eepro100-io", PCI_IO_SIZE);
1948 pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
1949 /* FIXME: flash aliases to mmio?! */
1950 memory_region_init_io(&s->flash_bar, OBJECT(s), &eepro100_ops, s,
1951 "eepro100-flash", PCI_FLASH_SIZE);
1952 pci_register_bar(&s->dev, 2, 0, &s->flash_bar);
1953
1954 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1955 logout("macaddr: %s\n", nic_dump(&s->conf.macaddr.a[0], 6));
1956
1957 nic_reset(s);
1958
1959 s->nic = qemu_new_nic(&net_eepro100_info, &s->conf,
1960 object_get_typename(OBJECT(pci_dev)), pci_dev->qdev.id, s);
1961
1962 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
1963 TRACE(OTHER, logout("%s\n", qemu_get_queue(s->nic)->info_str));
1964
1965 qemu_register_reset(nic_reset, s);
1966
1967 s->vmstate = g_malloc(sizeof(vmstate_eepro100));
1968 memcpy(s->vmstate, &vmstate_eepro100, sizeof(vmstate_eepro100));
1969 s->vmstate->name = qemu_get_queue(s->nic)->model;
1970 vmstate_register(&pci_dev->qdev, -1, s->vmstate, s);
1971 }
1972
1973 static void eepro100_instance_init(Object *obj)
1974 {
1975 EEPRO100State *s = DO_UPCAST(EEPRO100State, dev, PCI_DEVICE(obj));
1976 device_add_bootindex_property(obj, &s->conf.bootindex,
1977 "bootindex", "/ethernet-phy@0",
1978 DEVICE(s), NULL);
1979 }
1980
1981 static E100PCIDeviceInfo e100_devices[] = {
1982 {
1983 .name = "i82550",
1984 .desc = "Intel i82550 Ethernet",
1985 .device = i82550,
1986 /* TODO: check device id. */
1987 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
1988 /* Revision ID: 0x0c, 0x0d, 0x0e. */
1989 .revision = 0x0e,
1990 /* TODO: check size of statistical counters. */
1991 .stats_size = 80,
1992 /* TODO: check extended tcb support. */
1993 .has_extended_tcb_support = true,
1994 .power_management = true,
1995 },{
1996 .name = "i82551",
1997 .desc = "Intel i82551 Ethernet",
1998 .device = i82551,
1999 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
2000 /* Revision ID: 0x0f, 0x10. */
2001 .revision = 0x0f,
2002 /* TODO: check size of statistical counters. */
2003 .stats_size = 80,
2004 /* TODO: check extended tcb support. */
2005 .has_extended_tcb_support = true,
2006 .power_management = true,
2007 },{
2008 .name = "i82557a",
2009 .desc = "Intel i82557A Ethernet",
2010 .device = i82557A,
2011 .device_id = PCI_DEVICE_ID_INTEL_82557,
2012 .revision = 0x01,
2013 .power_management = false,
2014 },{
2015 .name = "i82557b",
2016 .desc = "Intel i82557B Ethernet",
2017 .device = i82557B,
2018 .device_id = PCI_DEVICE_ID_INTEL_82557,
2019 .revision = 0x02,
2020 .power_management = false,
2021 },{
2022 .name = "i82557c",
2023 .desc = "Intel i82557C Ethernet",
2024 .device = i82557C,
2025 .device_id = PCI_DEVICE_ID_INTEL_82557,
2026 .revision = 0x03,
2027 .power_management = false,
2028 },{
2029 .name = "i82558a",
2030 .desc = "Intel i82558A Ethernet",
2031 .device = i82558A,
2032 .device_id = PCI_DEVICE_ID_INTEL_82557,
2033 .revision = 0x04,
2034 .stats_size = 76,
2035 .has_extended_tcb_support = true,
2036 .power_management = true,
2037 },{
2038 .name = "i82558b",
2039 .desc = "Intel i82558B Ethernet",
2040 .device = i82558B,
2041 .device_id = PCI_DEVICE_ID_INTEL_82557,
2042 .revision = 0x05,
2043 .stats_size = 76,
2044 .has_extended_tcb_support = true,
2045 .power_management = true,
2046 },{
2047 .name = "i82559a",
2048 .desc = "Intel i82559A Ethernet",
2049 .device = i82559A,
2050 .device_id = PCI_DEVICE_ID_INTEL_82557,
2051 .revision = 0x06,
2052 .stats_size = 80,
2053 .has_extended_tcb_support = true,
2054 .power_management = true,
2055 },{
2056 .name = "i82559b",
2057 .desc = "Intel i82559B Ethernet",
2058 .device = i82559B,
2059 .device_id = PCI_DEVICE_ID_INTEL_82557,
2060 .revision = 0x07,
2061 .stats_size = 80,
2062 .has_extended_tcb_support = true,
2063 .power_management = true,
2064 },{
2065 .name = "i82559c",
2066 .desc = "Intel i82559C Ethernet",
2067 .device = i82559C,
2068 .device_id = PCI_DEVICE_ID_INTEL_82557,
2069 #if 0
2070 .revision = 0x08,
2071 #endif
2072 /* TODO: Windows wants revision id 0x0c. */
2073 .revision = 0x0c,
2074 #if EEPROM_SIZE > 0
2075 .subsystem_vendor_id = PCI_VENDOR_ID_INTEL,
2076 .subsystem_id = 0x0040,
2077 #endif
2078 .stats_size = 80,
2079 .has_extended_tcb_support = true,
2080 .power_management = true,
2081 },{
2082 .name = "i82559er",
2083 .desc = "Intel i82559ER Ethernet",
2084 .device = i82559ER,
2085 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
2086 .revision = 0x09,
2087 .stats_size = 80,
2088 .has_extended_tcb_support = true,
2089 .power_management = true,
2090 },{
2091 .name = "i82562",
2092 .desc = "Intel i82562 Ethernet",
2093 .device = i82562,
2094 /* TODO: check device id. */
2095 .device_id = PCI_DEVICE_ID_INTEL_82551IT,
2096 /* TODO: wrong revision id. */
2097 .revision = 0x0e,
2098 .stats_size = 80,
2099 .has_extended_tcb_support = true,
2100 .power_management = true,
2101 },{
2102 /* Toshiba Tecra 8200. */
2103 .name = "i82801",
2104 .desc = "Intel i82801 Ethernet",
2105 .device = i82801,
2106 .device_id = 0x2449,
2107 .revision = 0x03,
2108 .stats_size = 80,
2109 .has_extended_tcb_support = true,
2110 .power_management = true,
2111 }
2112 };
2113
2114 static E100PCIDeviceInfo *eepro100_get_class_by_name(const char *typename)
2115 {
2116 E100PCIDeviceInfo *info = NULL;
2117 int i;
2118
2119 /* This is admittedly awkward but also temporary. QOM allows for
2120 * parameterized typing and for subclassing both of which would suitable
2121 * handle what's going on here. But class_data is already being used as
2122 * a stop-gap hack to allow incremental qdev conversion so we cannot use it
2123 * right now. Once we merge the final QOM series, we can come back here and
2124 * do this in a much more elegant fashion.
2125 */
2126 for (i = 0; i < ARRAY_SIZE(e100_devices); i++) {
2127 if (strcmp(e100_devices[i].name, typename) == 0) {
2128 info = &e100_devices[i];
2129 break;
2130 }
2131 }
2132 assert(info != NULL);
2133
2134 return info;
2135 }
2136
2137 static E100PCIDeviceInfo *eepro100_get_class(EEPRO100State *s)
2138 {
2139 return eepro100_get_class_by_name(object_get_typename(OBJECT(s)));
2140 }
2141
2142 static Property e100_properties[] = {
2143 DEFINE_NIC_PROPERTIES(EEPRO100State, conf),
2144 DEFINE_PROP_END_OF_LIST(),
2145 };
2146
2147 static void eepro100_class_init(ObjectClass *klass, void *data)
2148 {
2149 DeviceClass *dc = DEVICE_CLASS(klass);
2150 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2151 E100PCIDeviceInfo *info;
2152
2153 info = eepro100_get_class_by_name(object_class_get_name(klass));
2154
2155 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
2156 dc->props = e100_properties;
2157 dc->desc = info->desc;
2158 k->vendor_id = PCI_VENDOR_ID_INTEL;
2159 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
2160 k->romfile = "pxe-eepro100.rom";
2161 k->realize = e100_nic_realize;
2162 k->exit = pci_nic_uninit;
2163 k->device_id = info->device_id;
2164 k->revision = info->revision;
2165 k->subsystem_vendor_id = info->subsystem_vendor_id;
2166 k->subsystem_id = info->subsystem_id;
2167 }
2168
2169 static void eepro100_register_types(void)
2170 {
2171 size_t i;
2172 for (i = 0; i < ARRAY_SIZE(e100_devices); i++) {
2173 TypeInfo type_info = {};
2174 E100PCIDeviceInfo *info = &e100_devices[i];
2175
2176 type_info.name = info->name;
2177 type_info.parent = TYPE_PCI_DEVICE;
2178 type_info.class_init = eepro100_class_init;
2179 type_info.instance_size = sizeof(EEPRO100State);
2180 type_info.instance_init = eepro100_instance_init;
2181
2182 type_register(&type_info);
2183 }
2184 }
2185
2186 type_init(eepro100_register_types)
2187
2188 /* eof */
AR7 emulation for QEMU