m48t59: move ISA ports/memory regions registration to QOM constructor
[qemu/ar7.git] / hw / timer / m48t59.c
blob967a31319f9e1c971ad6a6a274363c93a3c57055
1 /*
2 * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
4 * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
24 #include "hw/hw.h"
25 #include "hw/timer/m48t59.h"
26 #include "qemu/timer.h"
27 #include "sysemu/sysemu.h"
28 #include "hw/sysbus.h"
29 #include "hw/isa/isa.h"
30 #include "exec/address-spaces.h"
32 //#define DEBUG_NVRAM
34 #if defined(DEBUG_NVRAM)
35 #define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
36 #else
37 #define NVRAM_PRINTF(fmt, ...) do { } while (0)
38 #endif
41 * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
42 * alarm and a watchdog timer and related control registers. In the
43 * PPC platform there is also a nvram lock function.
47 * Chipset docs:
48 * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
49 * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
50 * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
53 struct M48t59State {
54 /* Hardware parameters */
55 qemu_irq IRQ;
56 MemoryRegion iomem;
57 uint32_t io_base;
58 uint32_t size;
59 /* RTC management */
60 time_t time_offset;
61 time_t stop_time;
62 /* Alarm & watchdog */
63 struct tm alarm;
64 QEMUTimer *alrm_timer;
65 QEMUTimer *wd_timer;
66 /* NVRAM storage */
67 uint8_t *buffer;
68 /* Model parameters */
69 uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
70 /* NVRAM storage */
71 uint16_t addr;
72 uint8_t lock;
75 #define TYPE_ISA_M48T59 "m48t59_isa"
76 #define ISA_M48T59(obj) \
77 OBJECT_CHECK(M48t59ISAState, (obj), TYPE_ISA_M48T59)
79 typedef struct M48t59ISAState {
80 ISADevice parent_obj;
82 M48t59State state;
83 MemoryRegion io;
84 } M48t59ISAState;
86 #define SYSBUS_M48T59(obj) \
87 OBJECT_CHECK(M48t59SysBusState, (obj), TYPE_SYSBUS_M48T59)
89 typedef struct M48t59SysBusState {
90 SysBusDevice parent_obj;
92 M48t59State state;
93 MemoryRegion io;
94 } M48t59SysBusState;
96 /* Fake timer functions */
98 /* Alarm management */
99 static void alarm_cb (void *opaque)
101 struct tm tm;
102 uint64_t next_time;
103 M48t59State *NVRAM = opaque;
105 qemu_set_irq(NVRAM->IRQ, 1);
106 if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
107 (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
108 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
109 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
110 /* Repeat once a month */
111 qemu_get_timedate(&tm, NVRAM->time_offset);
112 tm.tm_mon++;
113 if (tm.tm_mon == 13) {
114 tm.tm_mon = 1;
115 tm.tm_year++;
117 next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset;
118 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
119 (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
120 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
121 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
122 /* Repeat once a day */
123 next_time = 24 * 60 * 60;
124 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
125 (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
126 (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
127 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
128 /* Repeat once an hour */
129 next_time = 60 * 60;
130 } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
131 (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
132 (NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
133 (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
134 /* Repeat once a minute */
135 next_time = 60;
136 } else {
137 /* Repeat once a second */
138 next_time = 1;
140 timer_mod(NVRAM->alrm_timer, qemu_clock_get_ns(rtc_clock) +
141 next_time * 1000);
142 qemu_set_irq(NVRAM->IRQ, 0);
145 static void set_alarm(M48t59State *NVRAM)
147 int diff;
148 if (NVRAM->alrm_timer != NULL) {
149 timer_del(NVRAM->alrm_timer);
150 diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
151 if (diff > 0)
152 timer_mod(NVRAM->alrm_timer, diff * 1000);
156 /* RTC management helpers */
157 static inline void get_time(M48t59State *NVRAM, struct tm *tm)
159 qemu_get_timedate(tm, NVRAM->time_offset);
162 static void set_time(M48t59State *NVRAM, struct tm *tm)
164 NVRAM->time_offset = qemu_timedate_diff(tm);
165 set_alarm(NVRAM);
168 /* Watchdog management */
169 static void watchdog_cb (void *opaque)
171 M48t59State *NVRAM = opaque;
173 NVRAM->buffer[0x1FF0] |= 0x80;
174 if (NVRAM->buffer[0x1FF7] & 0x80) {
175 NVRAM->buffer[0x1FF7] = 0x00;
176 NVRAM->buffer[0x1FFC] &= ~0x40;
177 /* May it be a hw CPU Reset instead ? */
178 qemu_system_reset_request();
179 } else {
180 qemu_set_irq(NVRAM->IRQ, 1);
181 qemu_set_irq(NVRAM->IRQ, 0);
185 static void set_up_watchdog(M48t59State *NVRAM, uint8_t value)
187 uint64_t interval; /* in 1/16 seconds */
189 NVRAM->buffer[0x1FF0] &= ~0x80;
190 if (NVRAM->wd_timer != NULL) {
191 timer_del(NVRAM->wd_timer);
192 if (value != 0) {
193 interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
194 timer_mod(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
195 ((interval * 1000) >> 4));
200 /* Direct access to NVRAM */
201 void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
203 M48t59State *NVRAM = opaque;
204 struct tm tm;
205 int tmp;
207 if (addr > 0x1FF8 && addr < 0x2000)
208 NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
210 /* check for NVRAM access */
211 if ((NVRAM->model == 2 && addr < 0x7f8) ||
212 (NVRAM->model == 8 && addr < 0x1ff8) ||
213 (NVRAM->model == 59 && addr < 0x1ff0)) {
214 goto do_write;
217 /* TOD access */
218 switch (addr) {
219 case 0x1FF0:
220 /* flags register : read-only */
221 break;
222 case 0x1FF1:
223 /* unused */
224 break;
225 case 0x1FF2:
226 /* alarm seconds */
227 tmp = from_bcd(val & 0x7F);
228 if (tmp >= 0 && tmp <= 59) {
229 NVRAM->alarm.tm_sec = tmp;
230 NVRAM->buffer[0x1FF2] = val;
231 set_alarm(NVRAM);
233 break;
234 case 0x1FF3:
235 /* alarm minutes */
236 tmp = from_bcd(val & 0x7F);
237 if (tmp >= 0 && tmp <= 59) {
238 NVRAM->alarm.tm_min = tmp;
239 NVRAM->buffer[0x1FF3] = val;
240 set_alarm(NVRAM);
242 break;
243 case 0x1FF4:
244 /* alarm hours */
245 tmp = from_bcd(val & 0x3F);
246 if (tmp >= 0 && tmp <= 23) {
247 NVRAM->alarm.tm_hour = tmp;
248 NVRAM->buffer[0x1FF4] = val;
249 set_alarm(NVRAM);
251 break;
252 case 0x1FF5:
253 /* alarm date */
254 tmp = from_bcd(val & 0x3F);
255 if (tmp != 0) {
256 NVRAM->alarm.tm_mday = tmp;
257 NVRAM->buffer[0x1FF5] = val;
258 set_alarm(NVRAM);
260 break;
261 case 0x1FF6:
262 /* interrupts */
263 NVRAM->buffer[0x1FF6] = val;
264 break;
265 case 0x1FF7:
266 /* watchdog */
267 NVRAM->buffer[0x1FF7] = val;
268 set_up_watchdog(NVRAM, val);
269 break;
270 case 0x1FF8:
271 case 0x07F8:
272 /* control */
273 NVRAM->buffer[addr] = (val & ~0xA0) | 0x90;
274 break;
275 case 0x1FF9:
276 case 0x07F9:
277 /* seconds (BCD) */
278 tmp = from_bcd(val & 0x7F);
279 if (tmp >= 0 && tmp <= 59) {
280 get_time(NVRAM, &tm);
281 tm.tm_sec = tmp;
282 set_time(NVRAM, &tm);
284 if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) {
285 if (val & 0x80) {
286 NVRAM->stop_time = time(NULL);
287 } else {
288 NVRAM->time_offset += NVRAM->stop_time - time(NULL);
289 NVRAM->stop_time = 0;
292 NVRAM->buffer[addr] = val & 0x80;
293 break;
294 case 0x1FFA:
295 case 0x07FA:
296 /* minutes (BCD) */
297 tmp = from_bcd(val & 0x7F);
298 if (tmp >= 0 && tmp <= 59) {
299 get_time(NVRAM, &tm);
300 tm.tm_min = tmp;
301 set_time(NVRAM, &tm);
303 break;
304 case 0x1FFB:
305 case 0x07FB:
306 /* hours (BCD) */
307 tmp = from_bcd(val & 0x3F);
308 if (tmp >= 0 && tmp <= 23) {
309 get_time(NVRAM, &tm);
310 tm.tm_hour = tmp;
311 set_time(NVRAM, &tm);
313 break;
314 case 0x1FFC:
315 case 0x07FC:
316 /* day of the week / century */
317 tmp = from_bcd(val & 0x07);
318 get_time(NVRAM, &tm);
319 tm.tm_wday = tmp;
320 set_time(NVRAM, &tm);
321 NVRAM->buffer[addr] = val & 0x40;
322 break;
323 case 0x1FFD:
324 case 0x07FD:
325 /* date (BCD) */
326 tmp = from_bcd(val & 0x3F);
327 if (tmp != 0) {
328 get_time(NVRAM, &tm);
329 tm.tm_mday = tmp;
330 set_time(NVRAM, &tm);
332 break;
333 case 0x1FFE:
334 case 0x07FE:
335 /* month */
336 tmp = from_bcd(val & 0x1F);
337 if (tmp >= 1 && tmp <= 12) {
338 get_time(NVRAM, &tm);
339 tm.tm_mon = tmp - 1;
340 set_time(NVRAM, &tm);
342 break;
343 case 0x1FFF:
344 case 0x07FF:
345 /* year */
346 tmp = from_bcd(val);
347 if (tmp >= 0 && tmp <= 99) {
348 get_time(NVRAM, &tm);
349 if (NVRAM->model == 8) {
350 tm.tm_year = from_bcd(val) + 68; // Base year is 1968
351 } else {
352 tm.tm_year = from_bcd(val);
354 set_time(NVRAM, &tm);
356 break;
357 default:
358 /* Check lock registers state */
359 if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
360 break;
361 if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
362 break;
363 do_write:
364 if (addr < NVRAM->size) {
365 NVRAM->buffer[addr] = val & 0xFF;
367 break;
371 uint32_t m48t59_read (void *opaque, uint32_t addr)
373 M48t59State *NVRAM = opaque;
374 struct tm tm;
375 uint32_t retval = 0xFF;
377 /* check for NVRAM access */
378 if ((NVRAM->model == 2 && addr < 0x078f) ||
379 (NVRAM->model == 8 && addr < 0x1ff8) ||
380 (NVRAM->model == 59 && addr < 0x1ff0)) {
381 goto do_read;
384 /* TOD access */
385 switch (addr) {
386 case 0x1FF0:
387 /* flags register */
388 goto do_read;
389 case 0x1FF1:
390 /* unused */
391 retval = 0;
392 break;
393 case 0x1FF2:
394 /* alarm seconds */
395 goto do_read;
396 case 0x1FF3:
397 /* alarm minutes */
398 goto do_read;
399 case 0x1FF4:
400 /* alarm hours */
401 goto do_read;
402 case 0x1FF5:
403 /* alarm date */
404 goto do_read;
405 case 0x1FF6:
406 /* interrupts */
407 goto do_read;
408 case 0x1FF7:
409 /* A read resets the watchdog */
410 set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
411 goto do_read;
412 case 0x1FF8:
413 case 0x07F8:
414 /* control */
415 goto do_read;
416 case 0x1FF9:
417 case 0x07F9:
418 /* seconds (BCD) */
419 get_time(NVRAM, &tm);
420 retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec);
421 break;
422 case 0x1FFA:
423 case 0x07FA:
424 /* minutes (BCD) */
425 get_time(NVRAM, &tm);
426 retval = to_bcd(tm.tm_min);
427 break;
428 case 0x1FFB:
429 case 0x07FB:
430 /* hours (BCD) */
431 get_time(NVRAM, &tm);
432 retval = to_bcd(tm.tm_hour);
433 break;
434 case 0x1FFC:
435 case 0x07FC:
436 /* day of the week / century */
437 get_time(NVRAM, &tm);
438 retval = NVRAM->buffer[addr] | tm.tm_wday;
439 break;
440 case 0x1FFD:
441 case 0x07FD:
442 /* date */
443 get_time(NVRAM, &tm);
444 retval = to_bcd(tm.tm_mday);
445 break;
446 case 0x1FFE:
447 case 0x07FE:
448 /* month */
449 get_time(NVRAM, &tm);
450 retval = to_bcd(tm.tm_mon + 1);
451 break;
452 case 0x1FFF:
453 case 0x07FF:
454 /* year */
455 get_time(NVRAM, &tm);
456 if (NVRAM->model == 8) {
457 retval = to_bcd(tm.tm_year - 68); // Base year is 1968
458 } else {
459 retval = to_bcd(tm.tm_year);
461 break;
462 default:
463 /* Check lock registers state */
464 if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
465 break;
466 if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
467 break;
468 do_read:
469 if (addr < NVRAM->size) {
470 retval = NVRAM->buffer[addr];
472 break;
474 if (addr > 0x1FF9 && addr < 0x2000)
475 NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
477 return retval;
480 void m48t59_toggle_lock (void *opaque, int lock)
482 M48t59State *NVRAM = opaque;
484 NVRAM->lock ^= 1 << lock;
487 /* IO access to NVRAM */
488 static void NVRAM_writeb(void *opaque, hwaddr addr, uint64_t val,
489 unsigned size)
491 M48t59State *NVRAM = opaque;
493 NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
494 switch (addr) {
495 case 0:
496 NVRAM->addr &= ~0x00FF;
497 NVRAM->addr |= val;
498 break;
499 case 1:
500 NVRAM->addr &= ~0xFF00;
501 NVRAM->addr |= val << 8;
502 break;
503 case 3:
504 m48t59_write(NVRAM, NVRAM->addr, val);
505 NVRAM->addr = 0x0000;
506 break;
507 default:
508 break;
512 static uint64_t NVRAM_readb(void *opaque, hwaddr addr, unsigned size)
514 M48t59State *NVRAM = opaque;
515 uint32_t retval;
517 switch (addr) {
518 case 3:
519 retval = m48t59_read(NVRAM, NVRAM->addr);
520 break;
521 default:
522 retval = -1;
523 break;
525 NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
527 return retval;
530 static void nvram_writeb (void *opaque, hwaddr addr, uint32_t value)
532 M48t59State *NVRAM = opaque;
534 m48t59_write(NVRAM, addr, value & 0xff);
537 static void nvram_writew (void *opaque, hwaddr addr, uint32_t value)
539 M48t59State *NVRAM = opaque;
541 m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
542 m48t59_write(NVRAM, addr + 1, value & 0xff);
545 static void nvram_writel (void *opaque, hwaddr addr, uint32_t value)
547 M48t59State *NVRAM = opaque;
549 m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
550 m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
551 m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
552 m48t59_write(NVRAM, addr + 3, value & 0xff);
555 static uint32_t nvram_readb (void *opaque, hwaddr addr)
557 M48t59State *NVRAM = opaque;
558 uint32_t retval;
560 retval = m48t59_read(NVRAM, addr);
561 return retval;
564 static uint32_t nvram_readw (void *opaque, hwaddr addr)
566 M48t59State *NVRAM = opaque;
567 uint32_t retval;
569 retval = m48t59_read(NVRAM, addr) << 8;
570 retval |= m48t59_read(NVRAM, addr + 1);
571 return retval;
574 static uint32_t nvram_readl (void *opaque, hwaddr addr)
576 M48t59State *NVRAM = opaque;
577 uint32_t retval;
579 retval = m48t59_read(NVRAM, addr) << 24;
580 retval |= m48t59_read(NVRAM, addr + 1) << 16;
581 retval |= m48t59_read(NVRAM, addr + 2) << 8;
582 retval |= m48t59_read(NVRAM, addr + 3);
583 return retval;
586 static const MemoryRegionOps nvram_ops = {
587 .old_mmio = {
588 .read = { nvram_readb, nvram_readw, nvram_readl, },
589 .write = { nvram_writeb, nvram_writew, nvram_writel, },
591 .endianness = DEVICE_NATIVE_ENDIAN,
594 static const VMStateDescription vmstate_m48t59 = {
595 .name = "m48t59",
596 .version_id = 1,
597 .minimum_version_id = 1,
598 .fields = (VMStateField[]) {
599 VMSTATE_UINT8(lock, M48t59State),
600 VMSTATE_UINT16(addr, M48t59State),
601 VMSTATE_VBUFFER_UINT32(buffer, M48t59State, 0, NULL, 0, size),
602 VMSTATE_END_OF_LIST()
606 static void m48t59_reset_common(M48t59State *NVRAM)
608 NVRAM->addr = 0;
609 NVRAM->lock = 0;
610 if (NVRAM->alrm_timer != NULL)
611 timer_del(NVRAM->alrm_timer);
613 if (NVRAM->wd_timer != NULL)
614 timer_del(NVRAM->wd_timer);
617 static void m48t59_reset_isa(DeviceState *d)
619 M48t59ISAState *isa = ISA_M48T59(d);
620 M48t59State *NVRAM = &isa->state;
622 m48t59_reset_common(NVRAM);
625 static void m48t59_reset_sysbus(DeviceState *d)
627 M48t59SysBusState *sys = SYSBUS_M48T59(d);
628 M48t59State *NVRAM = &sys->state;
630 m48t59_reset_common(NVRAM);
633 static const MemoryRegionOps m48t59_io_ops = {
634 .read = NVRAM_readb,
635 .write = NVRAM_writeb,
636 .impl = {
637 .min_access_size = 1,
638 .max_access_size = 1,
640 .endianness = DEVICE_LITTLE_ENDIAN,
643 /* Initialisation routine */
644 M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
645 uint32_t io_base, uint16_t size, int model)
647 DeviceState *dev;
648 SysBusDevice *s;
649 M48t59SysBusState *d;
650 M48t59State *state;
652 dev = qdev_create(NULL, TYPE_SYSBUS_M48T59);
653 qdev_prop_set_uint32(dev, "model", model);
654 qdev_prop_set_uint32(dev, "size", size);
655 qdev_prop_set_uint32(dev, "io_base", io_base);
656 qdev_init_nofail(dev);
657 s = SYS_BUS_DEVICE(dev);
658 d = SYSBUS_M48T59(dev);
659 state = &d->state;
660 sysbus_connect_irq(s, 0, IRQ);
661 if (io_base != 0) {
662 memory_region_add_subregion(get_system_io(), io_base,
663 sysbus_mmio_get_region(dev, 1));
665 if (mem_base != 0) {
666 sysbus_mmio_map(s, 0, mem_base);
669 return state;
672 M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
673 int model)
675 M48t59ISAState *d;
676 ISADevice *isadev;
677 DeviceState *dev;
678 M48t59State *s;
680 isadev = isa_create(bus, TYPE_ISA_M48T59);
681 dev = DEVICE(isadev);
682 qdev_prop_set_uint32(dev, "model", model);
683 qdev_prop_set_uint32(dev, "size", size);
684 qdev_prop_set_uint32(dev, "io_base", io_base);
685 qdev_init_nofail(dev);
686 d = ISA_M48T59(isadev);
687 s = &d->state;
689 return s;
692 static void m48t59_realize_common(M48t59State *s, Error **errp)
694 s->buffer = g_malloc0(s->size);
695 if (s->model == 59) {
696 s->alrm_timer = timer_new_ns(rtc_clock, &alarm_cb, s);
697 s->wd_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &watchdog_cb, s);
699 qemu_get_timedate(&s->alarm, 0);
701 vmstate_register(NULL, -1, &vmstate_m48t59, s);
704 static void m48t59_isa_realize(DeviceState *dev, Error **errp)
706 ISADevice *isadev = ISA_DEVICE(dev);
707 M48t59ISAState *d = ISA_M48T59(dev);
708 M48t59State *s = &d->state;
710 isa_init_irq(isadev, &s->IRQ, 8);
711 m48t59_realize_common(s, errp);
712 memory_region_init_io(&d->io, OBJECT(dev), &m48t59_io_ops, s, "m48t59", 4);
713 if (s->io_base != 0) {
714 isa_register_ioport(isadev, &d->io, s->io_base);
717 return 0;
720 static int m48t59_init1(SysBusDevice *dev)
722 M48t59SysBusState *d = SYSBUS_M48T59(dev);
723 Object *o = OBJECT(dev);
724 M48t59State *s = &d->state;
725 Error *err = NULL;
727 sysbus_init_irq(dev, &s->IRQ);
729 memory_region_init_io(&s->iomem, o, &nvram_ops, s, "m48t59.nvram",
730 s->size);
731 memory_region_init_io(&d->io, o, &m48t59_io_ops, s, "m48t59", 4);
732 sysbus_init_mmio(dev, &s->iomem);
733 sysbus_init_mmio(dev, &d->io);
734 m48t59_realize_common(s, &err);
735 if (err != NULL) {
736 error_free(err);
737 return -1;
740 return 0;
743 static Property m48t59_isa_properties[] = {
744 DEFINE_PROP_UINT32("size", M48t59ISAState, state.size, -1),
745 DEFINE_PROP_UINT32("model", M48t59ISAState, state.model, -1),
746 DEFINE_PROP_UINT32("io_base", M48t59ISAState, state.io_base, 0),
747 DEFINE_PROP_END_OF_LIST(),
750 static void m48t59_isa_class_init(ObjectClass *klass, void *data)
752 DeviceClass *dc = DEVICE_CLASS(klass);
754 dc->realize = m48t59_isa_realize;
755 dc->reset = m48t59_reset_isa;
756 dc->props = m48t59_isa_properties;
759 static const TypeInfo m48t59_isa_info = {
760 .name = TYPE_ISA_M48T59,
761 .parent = TYPE_ISA_DEVICE,
762 .instance_size = sizeof(M48t59ISAState),
763 .class_init = m48t59_isa_class_init,
766 static Property m48t59_properties[] = {
767 DEFINE_PROP_UINT32("size", M48t59SysBusState, state.size, -1),
768 DEFINE_PROP_UINT32("model", M48t59SysBusState, state.model, -1),
769 DEFINE_PROP_UINT32("io_base", M48t59SysBusState, state.io_base, 0),
770 DEFINE_PROP_END_OF_LIST(),
773 static void m48t59_class_init(ObjectClass *klass, void *data)
775 DeviceClass *dc = DEVICE_CLASS(klass);
776 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
778 k->init = m48t59_init1;
779 dc->reset = m48t59_reset_sysbus;
780 dc->props = m48t59_properties;
783 static const TypeInfo m48t59_info = {
784 .name = TYPE_SYSBUS_M48T59,
785 .parent = TYPE_SYS_BUS_DEVICE,
786 .instance_size = sizeof(M48t59SysBusState),
787 .class_init = m48t59_class_init,
790 static void m48t59_register_types(void)
792 type_register_static(&m48t59_info);
793 type_register_static(&m48t59_isa_info);
796 type_init(m48t59_register_types)