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aspeed: Create SRAM name from first CPU index
[qemu/ar7.git] / hw / arm / aspeed_ast10x0.c
blob677699e54c0ad93bed266414bb80566249aea410
1 /*
2 * ASPEED Ast10x0 SoC
3 *
4 * Copyright (C) 2022 ASPEED Technology Inc.
5 *
6 * This code is licensed under the GPL version 2 or later. See
7 * the COPYING file in the top-level directory.
8 *
9 * Implementation extracted from the AST2600 and adapted for Ast10x0.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "exec/address-spaces.h"
15 #include "sysemu/sysemu.h"
16 #include "hw/qdev-clock.h"
17 #include "hw/misc/unimp.h"
18 #include "hw/arm/aspeed_soc.h"
19
20 #define ASPEED_SOC_IOMEM_SIZE 0x00200000
21
22 static const hwaddr aspeed_soc_ast1030_memmap[] = {
23 [ASPEED_DEV_SRAM] = 0x00000000,
24 [ASPEED_DEV_SBC] = 0x79000000,
25 [ASPEED_DEV_IOMEM] = 0x7E600000,
26 [ASPEED_DEV_PWM] = 0x7E610000,
27 [ASPEED_DEV_FMC] = 0x7E620000,
28 [ASPEED_DEV_SPI1] = 0x7E630000,
29 [ASPEED_DEV_SPI2] = 0x7E640000,
30 [ASPEED_DEV_SCU] = 0x7E6E2000,
31 [ASPEED_DEV_ADC] = 0x7E6E9000,
32 [ASPEED_DEV_SBC] = 0x7E6F2000,
33 [ASPEED_DEV_GPIO] = 0x7E780000,
34 [ASPEED_DEV_TIMER1] = 0x7E782000,
35 [ASPEED_DEV_UART1] = 0x7E783000,
36 [ASPEED_DEV_UART2] = 0x7E78D000,
37 [ASPEED_DEV_UART3] = 0x7E78E000,
38 [ASPEED_DEV_UART4] = 0x7E78F000,
39 [ASPEED_DEV_UART5] = 0x7E784000,
40 [ASPEED_DEV_UART6] = 0x7E790000,
41 [ASPEED_DEV_UART7] = 0x7E790100,
42 [ASPEED_DEV_UART8] = 0x7E790200,
43 [ASPEED_DEV_UART9] = 0x7E790300,
44 [ASPEED_DEV_UART10] = 0x7E790400,
45 [ASPEED_DEV_UART11] = 0x7E790500,
46 [ASPEED_DEV_UART12] = 0x7E790600,
47 [ASPEED_DEV_UART13] = 0x7E790700,
48 [ASPEED_DEV_WDT] = 0x7E785000,
49 [ASPEED_DEV_LPC] = 0x7E789000,
50 [ASPEED_DEV_PECI] = 0x7E78B000,
51 [ASPEED_DEV_I2C] = 0x7E7B0000,
52 };
53
54 static const int aspeed_soc_ast1030_irqmap[] = {
55 [ASPEED_DEV_UART1] = 47,
56 [ASPEED_DEV_UART2] = 48,
57 [ASPEED_DEV_UART3] = 49,
58 [ASPEED_DEV_UART4] = 50,
59 [ASPEED_DEV_UART5] = 8,
60 [ASPEED_DEV_UART6] = 57,
61 [ASPEED_DEV_UART7] = 58,
62 [ASPEED_DEV_UART8] = 59,
63 [ASPEED_DEV_UART9] = 60,
64 [ASPEED_DEV_UART10] = 61,
65 [ASPEED_DEV_UART11] = 62,
66 [ASPEED_DEV_UART12] = 63,
67 [ASPEED_DEV_UART13] = 64,
68 [ASPEED_DEV_GPIO] = 11,
69 [ASPEED_DEV_TIMER1] = 16,
70 [ASPEED_DEV_TIMER2] = 17,
71 [ASPEED_DEV_TIMER3] = 18,
72 [ASPEED_DEV_TIMER4] = 19,
73 [ASPEED_DEV_TIMER5] = 20,
74 [ASPEED_DEV_TIMER6] = 21,
75 [ASPEED_DEV_TIMER7] = 22,
76 [ASPEED_DEV_TIMER8] = 23,
77 [ASPEED_DEV_WDT] = 24,
78 [ASPEED_DEV_LPC] = 35,
79 [ASPEED_DEV_PECI] = 38,
80 [ASPEED_DEV_FMC] = 39,
81 [ASPEED_DEV_PWM] = 44,
82 [ASPEED_DEV_ADC] = 46,
83 [ASPEED_DEV_SPI1] = 65,
84 [ASPEED_DEV_SPI2] = 66,
85 [ASPEED_DEV_I2C] = 110, /* 110 ~ 123 */
86 [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */
87 };
88
89 static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev)
90 {
91 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
92
93 return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[dev]);
94 }
95
96 static void aspeed_soc_ast1030_init(Object *obj)
97 {
98 AspeedSoCState *s = ASPEED_SOC(obj);
99 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
100 char socname[8];
101 char typename[64];
102 int i;
103
104 if (sscanf(sc->name, "%7s", socname) != 1) {
105 g_assert_not_reached();
106 }
107
108 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
109
110 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
111
112 snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
113 object_initialize_child(obj, "scu", &s->scu, typename);
114 qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
115
116 object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), "hw-strap1");
117 object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), "hw-strap2");
118
119 snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
120 object_initialize_child(obj, "i2c", &s->i2c, typename);
121
122 snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
123 object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
124
125 snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
126 object_initialize_child(obj, "adc", &s->adc, typename);
127
128 snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
129 object_initialize_child(obj, "fmc", &s->fmc, typename);
130
131 for (i = 0; i < sc->spis_num; i++) {
132 snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
133 object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
134 }
135
136 object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
137
138 object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
139
140 object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC);
141
142 for (i = 0; i < sc->wdts_num; i++) {
143 snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
144 object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
145 }
146
147 snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
148 object_initialize_child(obj, "gpio", &s->gpio, typename);
149
150 object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
151 object_initialize_child(obj, "sbc-unimplemented", &s->sbc_unimplemented,
152 TYPE_UNIMPLEMENTED_DEVICE);
153 }
154
155 static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp)
156 {
157 AspeedSoCState *s = ASPEED_SOC(dev_soc);
158 AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
159 DeviceState *armv7m;
160 Error *err = NULL;
161 int i;
162 g_autofree char *sram_name = NULL;
163
164 if (!clock_has_source(s->sysclk)) {
165 error_setg(errp, "sysclk clock must be wired up by the board code");
166 return;
167 }
168
169 /* General I/O memory space to catch all unimplemented device */
170 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io",
171 sc->memmap[ASPEED_DEV_IOMEM],
172 ASPEED_SOC_IOMEM_SIZE);
173 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->sbc_unimplemented),
174 "aspeed.sbc", sc->memmap[ASPEED_DEV_SBC],
175 0x40000);
176
177 /* AST1030 CPU Core */
178 armv7m = DEVICE(&s->armv7m);
179 qdev_prop_set_uint32(armv7m, "num-irq", 256);
180 qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type);
181 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
182 object_property_set_link(OBJECT(&s->armv7m), "memory",
183 OBJECT(s->memory), &error_abort);
184 sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), &error_abort);
185
186 /* Internal SRAM */
187 sram_name = g_strdup_printf("aspeed.sram.%d",
188 CPU(s->armv7m.cpu)->cpu_index);
189 memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
190 if (err != NULL) {
191 error_propagate(errp, err);
192 return;
193 }
194 memory_region_add_subregion(s->memory,
195 sc->memmap[ASPEED_DEV_SRAM],
196 &s->sram);
197
198 /* SCU */
199 if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
200 return;
201 }
202 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
203
204 /* I2C */
205
206 object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(&s->sram),
207 &error_abort);
208 if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
209 return;
210 }
211 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
212 for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) {
213 qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->armv7m),
214 sc->irqmap[ASPEED_DEV_I2C] + i);
215 /* The AST1030 I2C controller has one IRQ per bus. */
216 sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq);
217 }
218
219 /* PECI */
220 if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
221 return;
222 }
223 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0,
224 sc->memmap[ASPEED_DEV_PECI]);
225 sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
226 aspeed_soc_get_irq(s, ASPEED_DEV_PECI));
227
228 /* LPC */
229 if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
230 return;
231 }
232 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);
233
234 /* Connect the LPC IRQ to the GIC. It is otherwise unused. */
235 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
236 aspeed_soc_get_irq(s, ASPEED_DEV_LPC));
237
238 /*
239 * On the AST1030 LPC subdevice IRQs are connected straight to the GIC.
240 */
241 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
242 qdev_get_gpio_in(DEVICE(&s->armv7m),
243 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
244
245 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
246 qdev_get_gpio_in(DEVICE(&s->armv7m),
247 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
248
249 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
250 qdev_get_gpio_in(DEVICE(&s->armv7m),
251 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
252
253 sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
254 qdev_get_gpio_in(DEVICE(&s->armv7m),
255 sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
256
257 /* UART */
258 aspeed_soc_uart_init(s);
259
260 /* Timer */
261 object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
262 &error_abort);
263 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
264 return;
265 }
266 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0,
267 sc->memmap[ASPEED_DEV_TIMER1]);
268 for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
269 qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
270 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
271 }
272
273 /* ADC */
274 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
275 return;
276 }
277 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
278 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
279 aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
280
281 /* FMC, The number of CS is set at the board level */
282 object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(&s->sram),
283 &error_abort);
284 if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
285 return;
286 }
287 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
288 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1,
289 ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
290 sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
291 aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
292
293 /* SPI */
294 for (i = 0; i < sc->spis_num; i++) {
295 object_property_set_link(OBJECT(&s->spi[i]), "dram",
296 OBJECT(&s->sram), &error_abort);
297 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
298 return;
299 }
300 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0,
301 sc->memmap[ASPEED_DEV_SPI1 + i]);
302 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1,
303 ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
304 }
305
306 /* Secure Boot Controller */
307 if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) {
308 return;
309 }
310 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
311
312 /* Watch dog */
313 for (i = 0; i < sc->wdts_num; i++) {
314 AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
315
316 object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
317 &error_abort);
318 if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
319 return;
320 }
321 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0,
322 sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
323 }
324
325 /* GPIO */
326 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
327 return;
328 }
329 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0,
330 sc->memmap[ASPEED_DEV_GPIO]);
331 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
332 aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
333 }
334
335 static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data)
336 {
337 DeviceClass *dc = DEVICE_CLASS(klass);
338 AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
339
340 dc->realize = aspeed_soc_ast1030_realize;
341
342 sc->name = "ast1030-a1";
343 sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
344 sc->silicon_rev = AST1030_A1_SILICON_REV;
345 sc->sram_size = 0xc0000;
346 sc->spis_num = 2;
347 sc->ehcis_num = 0;
348 sc->wdts_num = 4;
349 sc->macs_num = 1;
350 sc->uarts_num = 13;
351 sc->irqmap = aspeed_soc_ast1030_irqmap;
352 sc->memmap = aspeed_soc_ast1030_memmap;
353 sc->num_cpus = 1;
354 sc->get_irq = aspeed_soc_ast1030_get_irq;
355 }
356
357 static const TypeInfo aspeed_soc_ast1030_type_info = {
358 .name = "ast1030-a1",
359 .parent = TYPE_ASPEED_SOC,
360 .instance_size = sizeof(AspeedSoCState),
361 .instance_init = aspeed_soc_ast1030_init,
362 .class_init = aspeed_soc_ast1030_class_init,
363 .class_size = sizeof(AspeedSoCClass),
364 };
365
366 static void aspeed_soc_register_types(void)
367 {
368 type_register_static(&aspeed_soc_ast1030_type_info);
369 }
370
371 type_init(aspeed_soc_register_types)
AR7 emulation for QEMU