ui: correctly reset framebuffer update state after processing dirty regions
[qemu/ar7.git] / tests / pnv-xscom-test.c
blob89fa6282d3afb3a166b8668c4cf9f70e1247a118
1 /*
2 * QTest testcase for PowerNV XSCOM bus
4 * Copyright (c) 2016, IBM Corporation.
6 * This work is licensed under the terms of the GNU GPL, version 2 or
7 * later. See the COPYING file in the top-level directory.
8 */
9 #include "qemu/osdep.h"
11 #include "libqtest.h"
13 typedef enum PnvChipType {
14 PNV_CHIP_POWER8E, /* AKA Murano (default) */
15 PNV_CHIP_POWER8, /* AKA Venice */
16 PNV_CHIP_POWER8NVL, /* AKA Naples */
17 PNV_CHIP_POWER9, /* AKA Nimbus */
18 } PnvChipType;
20 typedef struct PnvChip {
21 PnvChipType chip_type;
22 const char *cpu_model;
23 uint64_t xscom_base;
24 uint64_t xscom_core_base;
25 uint64_t cfam_id;
26 uint32_t first_core;
27 } PnvChip;
29 static const PnvChip pnv_chips[] = {
31 .chip_type = PNV_CHIP_POWER8,
32 .cpu_model = "POWER8",
33 .xscom_base = 0x0003fc0000000000ull,
34 .xscom_core_base = 0x10000000ull,
35 .cfam_id = 0x220ea04980000000ull,
36 .first_core = 0x1,
37 }, {
38 .chip_type = PNV_CHIP_POWER8NVL,
39 .cpu_model = "POWER8NVL",
40 .xscom_base = 0x0003fc0000000000ull,
41 .xscom_core_base = 0x10000000ull,
42 .cfam_id = 0x120d304980000000ull,
43 .first_core = 0x1,
45 #if 0 /* POWER9 support is not ready yet */
47 .chip_type = PNV_CHIP_POWER9,
48 .cpu_model = "POWER9",
49 .xscom_base = 0x000603fc00000000ull,
50 .xscom_core_base = 0x0ull,
51 .cfam_id = 0x100d104980000000ull,
52 .first_core = 0x20,
54 #endif
57 static uint64_t pnv_xscom_addr(const PnvChip *chip, uint32_t pcba)
59 uint64_t addr = chip->xscom_base;
61 if (chip->chip_type == PNV_CHIP_POWER9) {
62 addr |= ((uint64_t) pcba << 3);
63 } else {
64 addr |= (((uint64_t) pcba << 4) & ~0xffull) |
65 (((uint64_t) pcba << 3) & 0x78);
67 return addr;
70 static uint64_t pnv_xscom_read(const PnvChip *chip, uint32_t pcba)
72 return readq(pnv_xscom_addr(chip, pcba));
75 static void test_xscom_cfam_id(const PnvChip *chip)
77 uint64_t f000f = pnv_xscom_read(chip, 0xf000f);
79 g_assert_cmphex(f000f, ==, chip->cfam_id);
82 static void test_cfam_id(const void *data)
84 const PnvChip *chip = data;
86 global_qtest = qtest_startf("-M powernv,accel=tcg -cpu %s",
87 chip->cpu_model);
88 test_xscom_cfam_id(chip);
89 qtest_quit(global_qtest);
92 #define PNV_XSCOM_EX_CORE_BASE(chip, i) \
93 ((chip)->xscom_core_base | (((uint64_t)i) << 24))
94 #define PNV_XSCOM_EX_DTS_RESULT0 0x50000
96 static void test_xscom_core(const PnvChip *chip)
98 uint32_t first_core_dts0 =
99 PNV_XSCOM_EX_CORE_BASE(chip, chip->first_core) |
100 PNV_XSCOM_EX_DTS_RESULT0;
101 uint64_t dts0 = pnv_xscom_read(chip, first_core_dts0);
103 g_assert_cmphex(dts0, ==, 0x26f024f023f0000ull);
106 static void test_core(const void *data)
108 const PnvChip *chip = data;
110 global_qtest = qtest_startf("-M powernv,accel=tcg -cpu %s",
111 chip->cpu_model);
112 test_xscom_core(chip);
113 qtest_quit(global_qtest);
116 static void add_test(const char *name, void (*test)(const void *data))
118 int i;
120 for (i = 0; i < ARRAY_SIZE(pnv_chips); i++) {
121 char *tname = g_strdup_printf("pnv-xscom/%s/%s", name,
122 pnv_chips[i].cpu_model);
123 qtest_add_data_func(tname, &pnv_chips[i], test);
124 g_free(tname);
128 int main(int argc, char **argv)
130 g_test_init(&argc, &argv, NULL);
132 add_test("cfam_id", test_cfam_id);
133 add_test("core", test_core);
134 return g_test_run();