tcg/tcg.h

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2008 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #ifndef TCG_H
  26 #define TCG_H
  27
  28 #include "qemu-common.h"
  29 #include "cpu.h"
  30 #include "exec/tb-context.h"
  31 #include "qemu/bitops.h"
  32 #include "qemu/queue.h"
  33 #include "tcg-mo.h"
  34 #include "tcg-target.h"
  35 #include "qemu/int128.h"
  36
  37 /* XXX: make safe guess about sizes */
  38 #define MAX_OP_PER_INSTR 266
  39
  40 #if HOST_LONG_BITS == 32
  41 #define MAX_OPC_PARAM_PER_ARG 2
  42 #else
  43 #define MAX_OPC_PARAM_PER_ARG 1
  44 #endif
  45 #define MAX_OPC_PARAM_IARGS 6
  46 #define MAX_OPC_PARAM_OARGS 1
  47 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
  48
  49 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
  50  * and up to 4 + N parameters on 64-bit archs
  51  * (N = number of input arguments + output arguments).  */
  52 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
  53
  54 #define CPU_TEMP_BUF_NLONGS 128
  55
  56 /* Default target word size to pointer size.  */
  57 #ifndef TCG_TARGET_REG_BITS
  58 # if UINTPTR_MAX == UINT32_MAX
  59 #  define TCG_TARGET_REG_BITS 32
  60 # elif UINTPTR_MAX == UINT64_MAX
  61 #  define TCG_TARGET_REG_BITS 64
  62 # else
  63 #  error Unknown pointer size for tcg target
  64 # endif
  65 #endif
  66
  67 #if TCG_TARGET_REG_BITS == 32
  68 typedef int32_t tcg_target_long;
  69 typedef uint32_t tcg_target_ulong;
  70 #define TCG_PRIlx PRIx32
  71 #define TCG_PRIld PRId32
  72 #elif TCG_TARGET_REG_BITS == 64
  73 typedef int64_t tcg_target_long;
  74 typedef uint64_t tcg_target_ulong;
  75 #define TCG_PRIlx PRIx64
  76 #define TCG_PRIld PRId64
  77 #else
  78 #error unsupported
  79 #endif
  80
  81 /* Oversized TCG guests make things like MTTCG hard
  82  * as we can't use atomics for cputlb updates.
  83  */
  84 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
  85 #define TCG_OVERSIZED_GUEST 1
  86 #else
  87 #define TCG_OVERSIZED_GUEST 0
  88 #endif
  89
  90 #if TCG_TARGET_NB_REGS <= 32
  91 typedef uint32_t TCGRegSet;
  92 #elif TCG_TARGET_NB_REGS <= 64
  93 typedef uint64_t TCGRegSet;
  94 #else
  95 #error unsupported
  96 #endif
  97
  98 #if TCG_TARGET_REG_BITS == 32
  99 /* Turn some undef macros into false macros.  */
 100 #define TCG_TARGET_HAS_extrl_i64_i32    0
 101 #define TCG_TARGET_HAS_extrh_i64_i32    0
 102 #define TCG_TARGET_HAS_div_i64          0
 103 #define TCG_TARGET_HAS_rem_i64          0
 104 #define TCG_TARGET_HAS_div2_i64         0
 105 #define TCG_TARGET_HAS_rot_i64          0
 106 #define TCG_TARGET_HAS_ext8s_i64        0
 107 #define TCG_TARGET_HAS_ext16s_i64       0
 108 #define TCG_TARGET_HAS_ext32s_i64       0
 109 #define TCG_TARGET_HAS_ext8u_i64        0
 110 #define TCG_TARGET_HAS_ext16u_i64       0
 111 #define TCG_TARGET_HAS_ext32u_i64       0
 112 #define TCG_TARGET_HAS_bswap16_i64      0
 113 #define TCG_TARGET_HAS_bswap32_i64      0
 114 #define TCG_TARGET_HAS_bswap64_i64      0
 115 #define TCG_TARGET_HAS_neg_i64          0
 116 #define TCG_TARGET_HAS_not_i64          0
 117 #define TCG_TARGET_HAS_andc_i64         0
 118 #define TCG_TARGET_HAS_orc_i64          0
 119 #define TCG_TARGET_HAS_eqv_i64          0
 120 #define TCG_TARGET_HAS_nand_i64         0
 121 #define TCG_TARGET_HAS_nor_i64          0
 122 #define TCG_TARGET_HAS_clz_i64          0
 123 #define TCG_TARGET_HAS_ctz_i64          0
 124 #define TCG_TARGET_HAS_ctpop_i64        0
 125 #define TCG_TARGET_HAS_deposit_i64      0
 126 #define TCG_TARGET_HAS_extract_i64      0
 127 #define TCG_TARGET_HAS_sextract_i64     0
 128 #define TCG_TARGET_HAS_movcond_i64      0
 129 #define TCG_TARGET_HAS_add2_i64         0
 130 #define TCG_TARGET_HAS_sub2_i64         0
 131 #define TCG_TARGET_HAS_mulu2_i64        0
 132 #define TCG_TARGET_HAS_muls2_i64        0
 133 #define TCG_TARGET_HAS_muluh_i64        0
 134 #define TCG_TARGET_HAS_mulsh_i64        0
 135 /* Turn some undef macros into true macros.  */
 136 #define TCG_TARGET_HAS_add2_i32         1
 137 #define TCG_TARGET_HAS_sub2_i32         1
 138 #endif
 139
 140 #ifndef TCG_TARGET_deposit_i32_valid
 141 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1
 142 #endif
 143 #ifndef TCG_TARGET_deposit_i64_valid
 144 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1
 145 #endif
 146 #ifndef TCG_TARGET_extract_i32_valid
 147 #define TCG_TARGET_extract_i32_valid(ofs, len) 1
 148 #endif
 149 #ifndef TCG_TARGET_extract_i64_valid
 150 #define TCG_TARGET_extract_i64_valid(ofs, len) 1
 151 #endif
 152
 153 /* Only one of DIV or DIV2 should be defined.  */
 154 #if defined(TCG_TARGET_HAS_div_i32)
 155 #define TCG_TARGET_HAS_div2_i32         0
 156 #elif defined(TCG_TARGET_HAS_div2_i32)
 157 #define TCG_TARGET_HAS_div_i32          0
 158 #define TCG_TARGET_HAS_rem_i32          0
 159 #endif
 160 #if defined(TCG_TARGET_HAS_div_i64)
 161 #define TCG_TARGET_HAS_div2_i64         0
 162 #elif defined(TCG_TARGET_HAS_div2_i64)
 163 #define TCG_TARGET_HAS_div_i64          0
 164 #define TCG_TARGET_HAS_rem_i64          0
 165 #endif
 166
 167 /* For 32-bit targets, some sort of unsigned widening multiply is required.  */
 168 #if TCG_TARGET_REG_BITS == 32 \
 169     && !(defined(TCG_TARGET_HAS_mulu2_i32) \
 170          || defined(TCG_TARGET_HAS_muluh_i32))
 171 # error "Missing unsigned widening multiply"
 172 #endif
 173
 174 #if !defined(TCG_TARGET_HAS_v64) \
 175     && !defined(TCG_TARGET_HAS_v128) \
 176     && !defined(TCG_TARGET_HAS_v256)
 177 #define TCG_TARGET_MAYBE_vec            0
 178 #define TCG_TARGET_HAS_neg_vec          0
 179 #define TCG_TARGET_HAS_not_vec          0
 180 #define TCG_TARGET_HAS_andc_vec         0
 181 #define TCG_TARGET_HAS_orc_vec          0
 182 #define TCG_TARGET_HAS_shi_vec          0
 183 #define TCG_TARGET_HAS_shs_vec          0
 184 #define TCG_TARGET_HAS_shv_vec          0
 185 #define TCG_TARGET_HAS_mul_vec          0
 186 #else
 187 #define TCG_TARGET_MAYBE_vec            1
 188 #endif
 189 #ifndef TCG_TARGET_HAS_v64
 190 #define TCG_TARGET_HAS_v64              0
 191 #endif
 192 #ifndef TCG_TARGET_HAS_v128
 193 #define TCG_TARGET_HAS_v128             0
 194 #endif
 195 #ifndef TCG_TARGET_HAS_v256
 196 #define TCG_TARGET_HAS_v256             0
 197 #endif
 198
 199 #ifndef TARGET_INSN_START_EXTRA_WORDS
 200 # define TARGET_INSN_START_WORDS 1
 201 #else
 202 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
 203 #endif
 204
 205 typedef enum TCGOpcode {
 206 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name,
 207 #include "tcg-opc.h"
 208 #undef DEF
 209     NB_OPS,
 210 } TCGOpcode;
 211
 212 #define tcg_regset_set_reg(d, r)   ((d) |= (TCGRegSet)1 << (r))
 213 #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r)))
 214 #define tcg_regset_test_reg(d, r)  (((d) >> (r)) & 1)
 215
 216 #ifndef TCG_TARGET_INSN_UNIT_SIZE
 217 # error "Missing TCG_TARGET_INSN_UNIT_SIZE"
 218 #elif TCG_TARGET_INSN_UNIT_SIZE == 1
 219 typedef uint8_t tcg_insn_unit;
 220 #elif TCG_TARGET_INSN_UNIT_SIZE == 2
 221 typedef uint16_t tcg_insn_unit;
 222 #elif TCG_TARGET_INSN_UNIT_SIZE == 4
 223 typedef uint32_t tcg_insn_unit;
 224 #elif TCG_TARGET_INSN_UNIT_SIZE == 8
 225 typedef uint64_t tcg_insn_unit;
 226 #else
 227 /* The port better have done this.  */
 228 #endif
 229
 230
 231 #if defined CONFIG_DEBUG_TCG || defined QEMU_STATIC_ANALYSIS
 232 # define tcg_debug_assert(X) do { assert(X); } while (0)
 233 #else
 234 # define tcg_debug_assert(X) \
 235     do { if (!(X)) { __builtin_unreachable(); } } while (0)
 236 #endif
 237
 238 typedef struct TCGRelocation {
 239     struct TCGRelocation *next;
 240     int type;
 241     tcg_insn_unit *ptr;
 242     intptr_t addend;
 243 } TCGRelocation;
 244
 245 typedef struct TCGLabel {
 246     unsigned has_value : 1;
 247     unsigned id : 31;
 248     union {
 249         uintptr_t value;
 250         tcg_insn_unit *value_ptr;
 251         TCGRelocation *first_reloc;
 252     } u;
 253 } TCGLabel;
 254
 255 typedef struct TCGPool {
 256     struct TCGPool *next;
 257     int size;
 258     uint8_t data[0] __attribute__ ((aligned));
 259 } TCGPool;
 260
 261 #define TCG_POOL_CHUNK_SIZE 32768
 262
 263 #define TCG_MAX_TEMPS 512
 264 #define TCG_MAX_INSNS 512
 265
 266 /* when the size of the arguments of a called function is smaller than
 267    this value, they are statically allocated in the TB stack frame */
 268 #define TCG_STATIC_CALL_ARGS_SIZE 128
 269
 270 typedef enum TCGType {
 271     TCG_TYPE_I32,
 272     TCG_TYPE_I64,
 273
 274     TCG_TYPE_V64,
 275     TCG_TYPE_V128,
 276     TCG_TYPE_V256,
 277
 278     TCG_TYPE_COUNT, /* number of different types */
 279
 280     /* An alias for the size of the host register.  */
 281 #if TCG_TARGET_REG_BITS == 32
 282     TCG_TYPE_REG = TCG_TYPE_I32,
 283 #else
 284     TCG_TYPE_REG = TCG_TYPE_I64,
 285 #endif
 286
 287     /* An alias for the size of the native pointer.  */
 288 #if UINTPTR_MAX == UINT32_MAX
 289     TCG_TYPE_PTR = TCG_TYPE_I32,
 290 #else
 291     TCG_TYPE_PTR = TCG_TYPE_I64,
 292 #endif
 293
 294     /* An alias for the size of the target "long", aka register.  */
 295 #if TARGET_LONG_BITS == 64
 296     TCG_TYPE_TL = TCG_TYPE_I64,
 297 #else
 298     TCG_TYPE_TL = TCG_TYPE_I32,
 299 #endif
 300 } TCGType;
 301
 302 /* Constants for qemu_ld and qemu_st for the Memory Operation field.  */
 303 typedef enum TCGMemOp {
 304     MO_8     = 0,
 305     MO_16    = 1,
 306     MO_32    = 2,
 307     MO_64    = 3,
 308     MO_SIZE  = 3,   /* Mask for the above.  */
 309
 310     MO_SIGN  = 4,   /* Sign-extended, otherwise zero-extended.  */
 311
 312     MO_BSWAP = 8,   /* Host reverse endian.  */
 313 #ifdef HOST_WORDS_BIGENDIAN
 314     MO_LE    = MO_BSWAP,
 315     MO_BE    = 0,
 316 #else
 317     MO_LE    = 0,
 318     MO_BE    = MO_BSWAP,
 319 #endif
 320 #ifdef TARGET_WORDS_BIGENDIAN
 321     MO_TE    = MO_BE,
 322 #else
 323     MO_TE    = MO_LE,
 324 #endif
 325
 326     /* MO_UNALN accesses are never checked for alignment.
 327      * MO_ALIGN accesses will result in a call to the CPU's
 328      * do_unaligned_access hook if the guest address is not aligned.
 329      * The default depends on whether the target CPU defines ALIGNED_ONLY.
 330      *
 331      * Some architectures (e.g. ARMv8) need the address which is aligned
 332      * to a size more than the size of the memory access.
 333      * Some architectures (e.g. SPARCv9) need an address which is aligned,
 334      * but less strictly than the natural alignment.
 335      *
 336      * MO_ALIGN supposes the alignment size is the size of a memory access.
 337      *
 338      * There are three options:
 339      * - unaligned access permitted (MO_UNALN).
 340      * - an alignment to the size of an access (MO_ALIGN);
 341      * - an alignment to a specified size, which may be more or less than
 342      *   the access size (MO_ALIGN_x where 'x' is a size in bytes);
 343      */
 344     MO_ASHIFT = 4,
 345     MO_AMASK = 7 << MO_ASHIFT,
 346 #ifdef ALIGNED_ONLY
 347     MO_ALIGN = 0,
 348     MO_UNALN = MO_AMASK,
 349 #else
 350     MO_ALIGN = MO_AMASK,
 351     MO_UNALN = 0,
 352 #endif
 353     MO_ALIGN_2  = 1 << MO_ASHIFT,
 354     MO_ALIGN_4  = 2 << MO_ASHIFT,
 355     MO_ALIGN_8  = 3 << MO_ASHIFT,
 356     MO_ALIGN_16 = 4 << MO_ASHIFT,
 357     MO_ALIGN_32 = 5 << MO_ASHIFT,
 358     MO_ALIGN_64 = 6 << MO_ASHIFT,
 359
 360     /* Combinations of the above, for ease of use.  */
 361     MO_UB    = MO_8,
 362     MO_UW    = MO_16,
 363     MO_UL    = MO_32,
 364     MO_SB    = MO_SIGN | MO_8,
 365     MO_SW    = MO_SIGN | MO_16,
 366     MO_SL    = MO_SIGN | MO_32,
 367     MO_Q     = MO_64,
 368
 369     MO_LEUW  = MO_LE | MO_UW,
 370     MO_LEUL  = MO_LE | MO_UL,
 371     MO_LESW  = MO_LE | MO_SW,
 372     MO_LESL  = MO_LE | MO_SL,
 373     MO_LEQ   = MO_LE | MO_Q,
 374
 375     MO_BEUW  = MO_BE | MO_UW,
 376     MO_BEUL  = MO_BE | MO_UL,
 377     MO_BESW  = MO_BE | MO_SW,
 378     MO_BESL  = MO_BE | MO_SL,
 379     MO_BEQ   = MO_BE | MO_Q,
 380
 381     MO_TEUW  = MO_TE | MO_UW,
 382     MO_TEUL  = MO_TE | MO_UL,
 383     MO_TESW  = MO_TE | MO_SW,
 384     MO_TESL  = MO_TE | MO_SL,
 385     MO_TEQ   = MO_TE | MO_Q,
 386
 387     MO_SSIZE = MO_SIZE | MO_SIGN,
 388 } TCGMemOp;
 389
 390 /**
 391  * get_alignment_bits
 392  * @memop: TCGMemOp value
 393  *
 394  * Extract the alignment size from the memop.
 395  */
 396 static inline unsigned get_alignment_bits(TCGMemOp memop)
 397 {
 398     unsigned a = memop & MO_AMASK;
 399
 400     if (a == MO_UNALN) {
 401         /* No alignment required.  */
 402         a = 0;
 403     } else if (a == MO_ALIGN) {
 404         /* A natural alignment requirement.  */
 405         a = memop & MO_SIZE;
 406     } else {
 407         /* A specific alignment requirement.  */
 408         a = a >> MO_ASHIFT;
 409     }
 410 #if defined(CONFIG_SOFTMMU)
 411     /* The requested alignment cannot overlap the TLB flags.  */
 412     tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0);
 413 #endif
 414     return a;
 415 }
 416
 417 typedef tcg_target_ulong TCGArg;
 418
 419 /* Define type and accessor macros for TCG variables.
 420
 421    TCG variables are the inputs and outputs of TCG ops, as described
 422    in tcg/README. Target CPU front-end code uses these types to deal
 423    with TCG variables as it emits TCG code via the tcg_gen_* functions.
 424    They come in several flavours:
 425     * TCGv_i32 : 32 bit integer type
 426     * TCGv_i64 : 64 bit integer type
 427     * TCGv_ptr : a host pointer type
 428     * TCGv_vec : a host vector type; the exact size is not exposed
 429                  to the CPU front-end code.
 430     * TCGv : an integer type the same size as target_ulong
 431              (an alias for either TCGv_i32 or TCGv_i64)
 432    The compiler's type checking will complain if you mix them
 433    up and pass the wrong sized TCGv to a function.
 434
 435    Users of tcg_gen_* don't need to know about any of the internal
 436    details of these, and should treat them as opaque types.
 437    You won't be able to look inside them in a debugger either.
 438
 439    Internal implementation details follow:
 440
 441    Note that there is no definition of the structs TCGv_i32_d etc anywhere.
 442    This is deliberate, because the values we store in variables of type
 443    TCGv_i32 are not really pointers-to-structures. They're just small
 444    integers, but keeping them in pointer types like this means that the
 445    compiler will complain if you accidentally pass a TCGv_i32 to a
 446    function which takes a TCGv_i64, and so on. Only the internals of
 447    TCG need to care about the actual contents of the types.  */
 448
 449 typedef struct TCGv_i32_d *TCGv_i32;
 450 typedef struct TCGv_i64_d *TCGv_i64;
 451 typedef struct TCGv_ptr_d *TCGv_ptr;
 452 typedef struct TCGv_vec_d *TCGv_vec;
 453 typedef TCGv_ptr TCGv_env;
 454 #if TARGET_LONG_BITS == 32
 455 #define TCGv TCGv_i32
 456 #elif TARGET_LONG_BITS == 64
 457 #define TCGv TCGv_i64
 458 #else
 459 #error Unhandled TARGET_LONG_BITS value
 460 #endif
 461
 462 /* call flags */
 463 /* Helper does not read globals (either directly or through an exception). It
 464    implies TCG_CALL_NO_WRITE_GLOBALS. */
 465 #define TCG_CALL_NO_READ_GLOBALS    0x0010
 466 /* Helper does not write globals */
 467 #define TCG_CALL_NO_WRITE_GLOBALS   0x0020
 468 /* Helper can be safely suppressed if the return value is not used. */
 469 #define TCG_CALL_NO_SIDE_EFFECTS    0x0040
 470
 471 /* convenience version of most used call flags */
 472 #define TCG_CALL_NO_RWG         TCG_CALL_NO_READ_GLOBALS
 473 #define TCG_CALL_NO_WG          TCG_CALL_NO_WRITE_GLOBALS
 474 #define TCG_CALL_NO_SE          TCG_CALL_NO_SIDE_EFFECTS
 475 #define TCG_CALL_NO_RWG_SE      (TCG_CALL_NO_RWG | TCG_CALL_NO_SE)
 476 #define TCG_CALL_NO_WG_SE       (TCG_CALL_NO_WG | TCG_CALL_NO_SE)
 477
 478 /* Used to align parameters.  See the comment before tcgv_i32_temp.  */
 479 #define TCG_CALL_DUMMY_ARG      ((TCGArg)0)
 480
 481 /* Conditions.  Note that these are laid out for easy manipulation by
 482    the functions below:
 483      bit 0 is used for inverting;
 484      bit 1 is signed,
 485      bit 2 is unsigned,
 486      bit 3 is used with bit 0 for swapping signed/unsigned.  */
 487 typedef enum {
 488     /* non-signed */
 489     TCG_COND_NEVER  = 0 | 0 | 0 | 0,
 490     TCG_COND_ALWAYS = 0 | 0 | 0 | 1,
 491     TCG_COND_EQ     = 8 | 0 | 0 | 0,
 492     TCG_COND_NE     = 8 | 0 | 0 | 1,
 493     /* signed */
 494     TCG_COND_LT     = 0 | 0 | 2 | 0,
 495     TCG_COND_GE     = 0 | 0 | 2 | 1,
 496     TCG_COND_LE     = 8 | 0 | 2 | 0,
 497     TCG_COND_GT     = 8 | 0 | 2 | 1,
 498     /* unsigned */
 499     TCG_COND_LTU    = 0 | 4 | 0 | 0,
 500     TCG_COND_GEU    = 0 | 4 | 0 | 1,
 501     TCG_COND_LEU    = 8 | 4 | 0 | 0,
 502     TCG_COND_GTU    = 8 | 4 | 0 | 1,
 503 } TCGCond;
 504
 505 /* Invert the sense of the comparison.  */
 506 static inline TCGCond tcg_invert_cond(TCGCond c)
 507 {
 508     return (TCGCond)(c ^ 1);
 509 }
 510
 511 /* Swap the operands in a comparison.  */
 512 static inline TCGCond tcg_swap_cond(TCGCond c)
 513 {
 514     return c & 6 ? (TCGCond)(c ^ 9) : c;
 515 }
 516
 517 /* Create an "unsigned" version of a "signed" comparison.  */
 518 static inline TCGCond tcg_unsigned_cond(TCGCond c)
 519 {
 520     return c & 2 ? (TCGCond)(c ^ 6) : c;
 521 }
 522
 523 /* Create a "signed" version of an "unsigned" comparison.  */
 524 static inline TCGCond tcg_signed_cond(TCGCond c)
 525 {
 526     return c & 4 ? (TCGCond)(c ^ 6) : c;
 527 }
 528
 529 /* Must a comparison be considered unsigned?  */
 530 static inline bool is_unsigned_cond(TCGCond c)
 531 {
 532     return (c & 4) != 0;
 533 }
 534
 535 /* Create a "high" version of a double-word comparison.
 536    This removes equality from a LTE or GTE comparison.  */
 537 static inline TCGCond tcg_high_cond(TCGCond c)
 538 {
 539     switch (c) {
 540     case TCG_COND_GE:
 541     case TCG_COND_LE:
 542     case TCG_COND_GEU:
 543     case TCG_COND_LEU:
 544         return (TCGCond)(c ^ 8);
 545     default:
 546         return c;
 547     }
 548 }
 549
 550 typedef enum TCGTempVal {
 551     TEMP_VAL_DEAD,
 552     TEMP_VAL_REG,
 553     TEMP_VAL_MEM,
 554     TEMP_VAL_CONST,
 555 } TCGTempVal;
 556
 557 typedef struct TCGTemp {
 558     TCGReg reg:8;
 559     TCGTempVal val_type:8;
 560     TCGType base_type:8;
 561     TCGType type:8;
 562     unsigned int fixed_reg:1;
 563     unsigned int indirect_reg:1;
 564     unsigned int indirect_base:1;
 565     unsigned int mem_coherent:1;
 566     unsigned int mem_allocated:1;
 567     /* If true, the temp is saved across both basic blocks and
 568        translation blocks.  */
 569     unsigned int temp_global:1;
 570     /* If true, the temp is saved across basic blocks but dead
 571        at the end of translation blocks.  If false, the temp is
 572        dead at the end of basic blocks.  */
 573     unsigned int temp_local:1;
 574     unsigned int temp_allocated:1;
 575
 576     tcg_target_long val;
 577     struct TCGTemp *mem_base;
 578     intptr_t mem_offset;
 579     const char *name;
 580
 581     /* Pass-specific information that can be stored for a temporary.
 582        One word worth of integer data, and one pointer to data
 583        allocated separately.  */
 584     uintptr_t state;
 585     void *state_ptr;
 586 } TCGTemp;
 587
 588 typedef struct TCGContext TCGContext;
 589
 590 typedef struct TCGTempSet {
 591     unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)];
 592 } TCGTempSet;
 593
 594 /* While we limit helpers to 6 arguments, for 32-bit hosts, with padding,
 595    this imples a max of 6*2 (64-bit in) + 2 (64-bit out) = 14 operands.
 596    There are never more than 2 outputs, which means that we can store all
 597    dead + sync data within 16 bits.  */
 598 #define DEAD_ARG  4
 599 #define SYNC_ARG  1
 600 typedef uint16_t TCGLifeData;
 601
 602 /* The layout here is designed to avoid a bitfield crossing of
 603    a 32-bit boundary, which would cause GCC to add extra padding.  */
 604 typedef struct TCGOp {
 605     TCGOpcode opc   : 8;        /*  8 */
 606
 607     /* Parameters for this opcode.  See below.  */
 608     unsigned param1 : 4;        /* 12 */
 609     unsigned param2 : 4;        /* 16 */
 610
 611     /* Lifetime data of the operands.  */
 612     unsigned life   : 16;       /* 32 */
 613
 614     /* Next and previous opcodes.  */
 615     QTAILQ_ENTRY(TCGOp) link;
 616
 617     /* Arguments for the opcode.  */
 618     TCGArg args[MAX_OPC_PARAM];
 619 } TCGOp;
 620
 621 #define TCGOP_CALLI(X)    (X)->param1
 622 #define TCGOP_CALLO(X)    (X)->param2
 623
 624 #define TCGOP_VECL(X)     (X)->param1
 625 #define TCGOP_VECE(X)     (X)->param2
 626
 627 /* Make sure operands fit in the bitfields above.  */
 628 QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8));
 629
 630 typedef struct TCGProfile {
 631     int64_t cpu_exec_time;
 632     int64_t tb_count1;
 633     int64_t tb_count;
 634     int64_t op_count; /* total insn count */
 635     int op_count_max; /* max insn per TB */
 636     int temp_count_max;
 637     int64_t temp_count;
 638     int64_t del_op_count;
 639     int64_t code_in_len;
 640     int64_t code_out_len;
 641     int64_t search_out_len;
 642     int64_t interm_time;
 643     int64_t code_time;
 644     int64_t la_time;
 645     int64_t opt_time;
 646     int64_t restore_count;
 647     int64_t restore_time;
 648     int64_t table_op_count[NB_OPS];
 649 } TCGProfile;
 650
 651 struct TCGContext {
 652     uint8_t *pool_cur, *pool_end;
 653     TCGPool *pool_first, *pool_current, *pool_first_large;
 654     int nb_labels;
 655     int nb_globals;
 656     int nb_temps;
 657     int nb_indirects;
 658     int nb_ops;
 659
 660     /* goto_tb support */
 661     tcg_insn_unit *code_buf;
 662     uint16_t *tb_jmp_reset_offset; /* tb->jmp_reset_offset */
 663     uintptr_t *tb_jmp_insn_offset; /* tb->jmp_target_arg if direct_jump */
 664     uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_arg if !direct_jump */
 665
 666     TCGRegSet reserved_regs;
 667     uint32_t tb_cflags; /* cflags of the current TB */
 668     intptr_t current_frame_offset;
 669     intptr_t frame_start;
 670     intptr_t frame_end;
 671     TCGTemp *frame_temp;
 672
 673     tcg_insn_unit *code_ptr;
 674
 675 #ifdef CONFIG_PROFILER
 676     TCGProfile prof;
 677 #endif
 678
 679 #ifdef CONFIG_DEBUG_TCG
 680     int temps_in_use;
 681     int goto_tb_issue_mask;
 682 #endif
 683
 684     /* Code generation.  Note that we specifically do not use tcg_insn_unit
 685        here, because there's too much arithmetic throughout that relies
 686        on addition and subtraction working on bytes.  Rely on the GCC
 687        extension that allows arithmetic on void*.  */
 688     void *code_gen_prologue;
 689     void *code_gen_epilogue;
 690     void *code_gen_buffer;
 691     size_t code_gen_buffer_size;
 692     void *code_gen_ptr;
 693     void *data_gen_ptr;
 694
 695     /* Threshold to flush the translated code buffer.  */
 696     void *code_gen_highwater;
 697
 698     size_t tb_phys_invalidate_count;
 699
 700     /* Track which vCPU triggers events */
 701     CPUState *cpu;                      /* *_trans */
 702
 703     /* These structures are private to tcg-target.inc.c.  */
 704 #ifdef TCG_TARGET_NEED_LDST_LABELS
 705     QSIMPLEQ_HEAD(ldst_labels, TCGLabelQemuLdst) ldst_labels;
 706 #endif
 707 #ifdef TCG_TARGET_NEED_POOL_LABELS
 708     struct TCGLabelPoolData *pool_labels;
 709 #endif
 710
 711     TCGLabel *exitreq_label;
 712
 713     TCGTempSet free_temps[TCG_TYPE_COUNT * 2];
 714     TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */
 715
 716     QTAILQ_HEAD(TCGOpHead, TCGOp) ops, free_ops;
 717
 718     /* Tells which temporary holds a given register.
 719        It does not take into account fixed registers */
 720     TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS];
 721
 722     uint16_t gen_insn_end_off[TCG_MAX_INSNS];
 723     target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS];
 724 };
 725
 726 extern TCGContext tcg_init_ctx;
 727 extern __thread TCGContext *tcg_ctx;
 728 extern TCGv_env cpu_env;
 729
 730 static inline size_t temp_idx(TCGTemp *ts)
 731 {
 732     ptrdiff_t n = ts - tcg_ctx->temps;
 733     tcg_debug_assert(n >= 0 && n < tcg_ctx->nb_temps);
 734     return n;
 735 }
 736
 737 static inline TCGArg temp_arg(TCGTemp *ts)
 738 {
 739     return (uintptr_t)ts;
 740 }
 741
 742 static inline TCGTemp *arg_temp(TCGArg a)
 743 {
 744     return (TCGTemp *)(uintptr_t)a;
 745 }
 746
 747 /* Using the offset of a temporary, relative to TCGContext, rather than
 748    its index means that we don't use 0.  That leaves offset 0 free for
 749    a NULL representation without having to leave index 0 unused.  */
 750 static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v)
 751 {
 752     uintptr_t o = (uintptr_t)v;
 753     TCGTemp *t = (void *)tcg_ctx + o;
 754     tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) == o);
 755     return t;
 756 }
 757
 758 static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v)
 759 {
 760     return tcgv_i32_temp((TCGv_i32)v);
 761 }
 762
 763 static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v)
 764 {
 765     return tcgv_i32_temp((TCGv_i32)v);
 766 }
 767
 768 static inline TCGTemp *tcgv_vec_temp(TCGv_vec v)
 769 {
 770     return tcgv_i32_temp((TCGv_i32)v);
 771 }
 772
 773 static inline TCGArg tcgv_i32_arg(TCGv_i32 v)
 774 {
 775     return temp_arg(tcgv_i32_temp(v));
 776 }
 777
 778 static inline TCGArg tcgv_i64_arg(TCGv_i64 v)
 779 {
 780     return temp_arg(tcgv_i64_temp(v));
 781 }
 782
 783 static inline TCGArg tcgv_ptr_arg(TCGv_ptr v)
 784 {
 785     return temp_arg(tcgv_ptr_temp(v));
 786 }
 787
 788 static inline TCGArg tcgv_vec_arg(TCGv_vec v)
 789 {
 790     return temp_arg(tcgv_vec_temp(v));
 791 }
 792
 793 static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t)
 794 {
 795     (void)temp_idx(t); /* trigger embedded assert */
 796     return (TCGv_i32)((void *)t - (void *)tcg_ctx);
 797 }
 798
 799 static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t)
 800 {
 801     return (TCGv_i64)temp_tcgv_i32(t);
 802 }
 803
 804 static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t)
 805 {
 806     return (TCGv_ptr)temp_tcgv_i32(t);
 807 }
 808
 809 static inline TCGv_vec temp_tcgv_vec(TCGTemp *t)
 810 {
 811     return (TCGv_vec)temp_tcgv_i32(t);
 812 }
 813
 814 #if TCG_TARGET_REG_BITS == 32
 815 static inline TCGv_i32 TCGV_LOW(TCGv_i64 t)
 816 {
 817     return temp_tcgv_i32(tcgv_i64_temp(t));
 818 }
 819
 820 static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t)
 821 {
 822     return temp_tcgv_i32(tcgv_i64_temp(t) + 1);
 823 }
 824 #endif
 825
 826 static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v)
 827 {
 828     op->args[arg] = v;
 829 }
 830
 831 static inline void tcg_set_insn_start_param(TCGOp *op, int arg, target_ulong v)
 832 {
 833 #if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
 834     tcg_set_insn_param(op, arg, v);
 835 #else
 836     tcg_set_insn_param(op, arg * 2, v);
 837     tcg_set_insn_param(op, arg * 2 + 1, v >> 32);
 838 #endif
 839 }
 840
 841 /* The last op that was emitted.  */
 842 static inline TCGOp *tcg_last_op(void)
 843 {
 844     return QTAILQ_LAST(&tcg_ctx->ops, TCGOpHead);
 845 }
 846
 847 /* Test for whether to terminate the TB for using too many opcodes.  */
 848 static inline bool tcg_op_buf_full(void)
 849 {
 850     /* This is not a hard limit, it merely stops translation when
 851      * we have produced "enough" opcodes.  We want to limit TB size
 852      * such that a RISC host can reasonably use a 16-bit signed
 853      * branch within the TB.  We also need to be mindful of the
 854      * 16-bit unsigned offsets, TranslationBlock.jmp_reset_offset[]
 855      * and TCGContext.gen_insn_end_off[].
 856      */
 857     return tcg_ctx->nb_ops >= 4000;
 858 }
 859
 860 /* pool based memory allocation */
 861
 862 /* user-mode: mmap_lock must be held for tcg_malloc_internal. */
 863 void *tcg_malloc_internal(TCGContext *s, int size);
 864 void tcg_pool_reset(TCGContext *s);
 865 TranslationBlock *tcg_tb_alloc(TCGContext *s);
 866
 867 void tcg_region_init(void);
 868 void tcg_region_reset_all(void);
 869
 870 size_t tcg_code_size(void);
 871 size_t tcg_code_capacity(void);
 872
 873 void tcg_tb_insert(TranslationBlock *tb);
 874 void tcg_tb_remove(TranslationBlock *tb);
 875 size_t tcg_tb_phys_invalidate_count(void);
 876 TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr);
 877 void tcg_tb_foreach(GTraverseFunc func, gpointer user_data);
 878 size_t tcg_nb_tbs(void);
 879
 880 /* user-mode: Called with mmap_lock held.  */
 881 static inline void *tcg_malloc(int size)
 882 {
 883     TCGContext *s = tcg_ctx;
 884     uint8_t *ptr, *ptr_end;
 885
 886     /* ??? This is a weak placeholder for minimum malloc alignment.  */
 887     size = QEMU_ALIGN_UP(size, 8);
 888
 889     ptr = s->pool_cur;
 890     ptr_end = ptr + size;
 891     if (unlikely(ptr_end > s->pool_end)) {
 892         return tcg_malloc_internal(tcg_ctx, size);
 893     } else {
 894         s->pool_cur = ptr_end;
 895         return ptr;
 896     }
 897 }
 898
 899 void tcg_context_init(TCGContext *s);
 900 void tcg_register_thread(void);
 901 void tcg_prologue_init(TCGContext *s);
 902 void tcg_func_start(TCGContext *s);
 903
 904 int tcg_gen_code(TCGContext *s, TranslationBlock *tb);
 905
 906 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);
 907
 908 TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr,
 909                                      intptr_t, const char *);
 910 TCGTemp *tcg_temp_new_internal(TCGType, bool);
 911 void tcg_temp_free_internal(TCGTemp *);
 912 TCGv_vec tcg_temp_new_vec(TCGType type);
 913 TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match);
 914
 915 static inline void tcg_temp_free_i32(TCGv_i32 arg)
 916 {
 917     tcg_temp_free_internal(tcgv_i32_temp(arg));
 918 }
 919
 920 static inline void tcg_temp_free_i64(TCGv_i64 arg)
 921 {
 922     tcg_temp_free_internal(tcgv_i64_temp(arg));
 923 }
 924
 925 static inline void tcg_temp_free_ptr(TCGv_ptr arg)
 926 {
 927     tcg_temp_free_internal(tcgv_ptr_temp(arg));
 928 }
 929
 930 static inline void tcg_temp_free_vec(TCGv_vec arg)
 931 {
 932     tcg_temp_free_internal(tcgv_vec_temp(arg));
 933 }
 934
 935 static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
 936                                               const char *name)
 937 {
 938     TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name);
 939     return temp_tcgv_i32(t);
 940 }
 941
 942 static inline TCGv_i32 tcg_temp_new_i32(void)
 943 {
 944     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, false);
 945     return temp_tcgv_i32(t);
 946 }
 947
 948 static inline TCGv_i32 tcg_temp_local_new_i32(void)
 949 {
 950     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, true);
 951     return temp_tcgv_i32(t);
 952 }
 953
 954 static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset,
 955                                               const char *name)
 956 {
 957     TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name);
 958     return temp_tcgv_i64(t);
 959 }
 960
 961 static inline TCGv_i64 tcg_temp_new_i64(void)
 962 {
 963     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, false);
 964     return temp_tcgv_i64(t);
 965 }
 966
 967 static inline TCGv_i64 tcg_temp_local_new_i64(void)
 968 {
 969     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, true);
 970     return temp_tcgv_i64(t);
 971 }
 972
 973 static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset,
 974                                               const char *name)
 975 {
 976     TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_PTR, reg, offset, name);
 977     return temp_tcgv_ptr(t);
 978 }
 979
 980 static inline TCGv_ptr tcg_temp_new_ptr(void)
 981 {
 982     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, false);
 983     return temp_tcgv_ptr(t);
 984 }
 985
 986 static inline TCGv_ptr tcg_temp_local_new_ptr(void)
 987 {
 988     TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, true);
 989     return temp_tcgv_ptr(t);
 990 }
 991
 992 #if defined(CONFIG_DEBUG_TCG)
 993 /* If you call tcg_clear_temp_count() at the start of a section of
 994  * code which is not supposed to leak any TCG temporaries, then
 995  * calling tcg_check_temp_count() at the end of the section will
 996  * return 1 if the section did in fact leak a temporary.
 997  */
 998 void tcg_clear_temp_count(void);
 999 int tcg_check_temp_count(void);
1000 #else
1001 #define tcg_clear_temp_count() do { } while (0)
1002 #define tcg_check_temp_count() 0
1003 #endif
1004
1005 int64_t tcg_cpu_exec_time(void);
1006 void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf);
1007 void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf);
1008
1009 #define TCG_CT_ALIAS  0x80
1010 #define TCG_CT_IALIAS 0x40
1011 #define TCG_CT_NEWREG 0x20 /* output requires a new register */
1012 #define TCG_CT_REG    0x01
1013 #define TCG_CT_CONST  0x02 /* any constant of register size */
1014
1015 typedef struct TCGArgConstraint {
1016     uint16_t ct;
1017     uint8_t alias_index;
1018     union {
1019         TCGRegSet regs;
1020     } u;
1021 } TCGArgConstraint;
1022
1023 #define TCG_MAX_OP_ARGS 16
1024
1025 /* Bits for TCGOpDef->flags, 8 bits available.  */
1026 enum {
1027     /* Instruction defines the end of a basic block.  */
1028     TCG_OPF_BB_END       = 0x01,
1029     /* Instruction clobbers call registers and potentially update globals.  */
1030     TCG_OPF_CALL_CLOBBER = 0x02,
1031     /* Instruction has side effects: it cannot be removed if its outputs
1032        are not used, and might trigger exceptions.  */
1033     TCG_OPF_SIDE_EFFECTS = 0x04,
1034     /* Instruction operands are 64-bits (otherwise 32-bits).  */
1035     TCG_OPF_64BIT        = 0x08,
1036     /* Instruction is optional and not implemented by the host, or insn
1037        is generic and should not be implemened by the host.  */
1038     TCG_OPF_NOT_PRESENT  = 0x10,
1039     /* Instruction operands are vectors.  */
1040     TCG_OPF_VECTOR       = 0x20,
1041 };
1042
1043 typedef struct TCGOpDef {
1044     const char *name;
1045     uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args;
1046     uint8_t flags;
1047     TCGArgConstraint *args_ct;
1048     int *sorted_args;
1049 #if defined(CONFIG_DEBUG_TCG)
1050     int used;
1051 #endif
1052 } TCGOpDef;
1053
1054 extern TCGOpDef tcg_op_defs[];
1055 extern const size_t tcg_op_defs_max;
1056
1057 typedef struct TCGTargetOpDef {
1058     TCGOpcode op;
1059     const char *args_ct_str[TCG_MAX_OP_ARGS];
1060 } TCGTargetOpDef;
1061
1062 #define tcg_abort() \
1063 do {\
1064     fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\
1065     abort();\
1066 } while (0)
1067
1068 bool tcg_op_supported(TCGOpcode op);
1069
1070 void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args);
1071
1072 TCGOp *tcg_emit_op(TCGOpcode opc);
1073 void tcg_op_remove(TCGContext *s, TCGOp *op);
1074 TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode opc);
1075 TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, TCGOpcode opc);
1076
1077 void tcg_optimize(TCGContext *s);
1078
1079 /* only used for debugging purposes */
1080 void tcg_dump_ops(TCGContext *s);
1081
1082 TCGv_i32 tcg_const_i32(int32_t val);
1083 TCGv_i64 tcg_const_i64(int64_t val);
1084 TCGv_i32 tcg_const_local_i32(int32_t val);
1085 TCGv_i64 tcg_const_local_i64(int64_t val);
1086 TCGv_vec tcg_const_zeros_vec(TCGType);
1087 TCGv_vec tcg_const_ones_vec(TCGType);
1088 TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec);
1089 TCGv_vec tcg_const_ones_vec_matching(TCGv_vec);
1090
1091 #if UINTPTR_MAX == UINT32_MAX
1092 # define tcg_const_ptr(x)        ((TCGv_ptr)tcg_const_i32((intptr_t)(x)))
1093 # define tcg_const_local_ptr(x)  ((TCGv_ptr)tcg_const_local_i32((intptr_t)(x)))
1094 #else
1095 # define tcg_const_ptr(x)        ((TCGv_ptr)tcg_const_i64((intptr_t)(x)))
1096 # define tcg_const_local_ptr(x)  ((TCGv_ptr)tcg_const_local_i64((intptr_t)(x)))
1097 #endif
1098
1099 TCGLabel *gen_new_label(void);
1100
1101 /**
1102  * label_arg
1103  * @l: label
1104  *
1105  * Encode a label for storage in the TCG opcode stream.
1106  */
1107
1108 static inline TCGArg label_arg(TCGLabel *l)
1109 {
1110     return (uintptr_t)l;
1111 }
1112
1113 /**
1114  * arg_label
1115  * @i: value
1116  *
1117  * The opposite of label_arg.  Retrieve a label from the
1118  * encoding of the TCG opcode stream.
1119  */
1120
1121 static inline TCGLabel *arg_label(TCGArg i)
1122 {
1123     return (TCGLabel *)(uintptr_t)i;
1124 }
1125
1126 /**
1127  * tcg_ptr_byte_diff
1128  * @a, @b: addresses to be differenced
1129  *
1130  * There are many places within the TCG backends where we need a byte
1131  * difference between two pointers.  While this can be accomplished
1132  * with local casting, it's easy to get wrong -- especially if one is
1133  * concerned with the signedness of the result.
1134  *
1135  * This version relies on GCC's void pointer arithmetic to get the
1136  * correct result.
1137  */
1138
1139 static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b)
1140 {
1141     return a - b;
1142 }
1143
1144 /**
1145  * tcg_pcrel_diff
1146  * @s: the tcg context
1147  * @target: address of the target
1148  *
1149  * Produce a pc-relative difference, from the current code_ptr
1150  * to the destination address.
1151  */
1152
1153 static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, void *target)
1154 {
1155     return tcg_ptr_byte_diff(target, s->code_ptr);
1156 }
1157
1158 /**
1159  * tcg_current_code_size
1160  * @s: the tcg context
1161  *
1162  * Compute the current code size within the translation block.
1163  * This is used to fill in qemu's data structures for goto_tb.
1164  */
1165
1166 static inline size_t tcg_current_code_size(TCGContext *s)
1167 {
1168     return tcg_ptr_byte_diff(s->code_ptr, s->code_buf);
1169 }
1170
1171 /* Combine the TCGMemOp and mmu_idx parameters into a single value.  */
1172 typedef uint32_t TCGMemOpIdx;
1173
1174 /**
1175  * make_memop_idx
1176  * @op: memory operation
1177  * @idx: mmu index
1178  *
1179  * Encode these values into a single parameter.
1180  */
1181 static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx)
1182 {
1183     tcg_debug_assert(idx <= 15);
1184     return (op << 4) | idx;
1185 }
1186
1187 /**
1188  * get_memop
1189  * @oi: combined op/idx parameter
1190  *
1191  * Extract the memory operation from the combined value.
1192  */
1193 static inline TCGMemOp get_memop(TCGMemOpIdx oi)
1194 {
1195     return oi >> 4;
1196 }
1197
1198 /**
1199  * get_mmuidx
1200  * @oi: combined op/idx parameter
1201  *
1202  * Extract the mmu index from the combined value.
1203  */
1204 static inline unsigned get_mmuidx(TCGMemOpIdx oi)
1205 {
1206     return oi & 15;
1207 }
1208
1209 /**
1210  * tcg_qemu_tb_exec:
1211  * @env: pointer to CPUArchState for the CPU
1212  * @tb_ptr: address of generated code for the TB to execute
1213  *
1214  * Start executing code from a given translation block.
1215  * Where translation blocks have been linked, execution
1216  * may proceed from the given TB into successive ones.
1217  * Control eventually returns only when some action is needed
1218  * from the top-level loop: either control must pass to a TB
1219  * which has not yet been directly linked, or an asynchronous
1220  * event such as an interrupt needs handling.
1221  *
1222  * Return: The return value is the value passed to the corresponding
1223  * tcg_gen_exit_tb() at translation time of the last TB attempted to execute.
1224  * The value is either zero or a 4-byte aligned pointer to that TB combined
1225  * with additional information in its two least significant bits. The
1226  * additional information is encoded as follows:
1227  *  0, 1: the link between this TB and the next is via the specified
1228  *        TB index (0 or 1). That is, we left the TB via (the equivalent
1229  *        of) "goto_tb <index>". The main loop uses this to determine
1230  *        how to link the TB just executed to the next.
1231  *  2:    we are using instruction counting code generation, and we
1232  *        did not start executing this TB because the instruction counter
1233  *        would hit zero midway through it. In this case the pointer
1234  *        returned is the TB we were about to execute, and the caller must
1235  *        arrange to execute the remaining count of instructions.
1236  *  3:    we stopped because the CPU's exit_request flag was set
1237  *        (usually meaning that there is an interrupt that needs to be
1238  *        handled). The pointer returned is the TB we were about to execute
1239  *        when we noticed the pending exit request.
1240  *
1241  * If the bottom two bits indicate an exit-via-index then the CPU
1242  * state is correctly synchronised and ready for execution of the next
1243  * TB (and in particular the guest PC is the address to execute next).
1244  * Otherwise, we gave up on execution of this TB before it started, and
1245  * the caller must fix up the CPU state by calling the CPU's
1246  * synchronize_from_tb() method with the TB pointer we return (falling
1247  * back to calling the CPU's set_pc method with tb->pb if no
1248  * synchronize_from_tb() method exists).
1249  *
1250  * Note that TCG targets may use a different definition of tcg_qemu_tb_exec
1251  * to this default (which just calls the prologue.code emitted by
1252  * tcg_target_qemu_prologue()).
1253  */
1254 #define TB_EXIT_MASK      3
1255 #define TB_EXIT_IDX0      0
1256 #define TB_EXIT_IDX1      1
1257 #define TB_EXIT_IDXMAX    1
1258 #define TB_EXIT_REQUESTED 3
1259
1260 #ifdef HAVE_TCG_QEMU_TB_EXEC
1261 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr);
1262 #else
1263 # define tcg_qemu_tb_exec(env, tb_ptr) \
1264     ((uintptr_t (*)(void *, void *))tcg_ctx->code_gen_prologue)(env, tb_ptr)
1265 #endif
1266
1267 void tcg_register_jit(void *buf, size_t buf_size);
1268
1269 #if TCG_TARGET_MAYBE_vec
1270 /* Return zero if the tuple (opc, type, vece) is unsupportable;
1271    return > 0 if it is directly supportable;
1272    return < 0 if we must call tcg_expand_vec_op.  */
1273 int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned);
1274 #else
1275 static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve)
1276 {
1277     return 0;
1278 }
1279 #endif
1280
1281 /* Expand the tuple (opc, type, vece) on the given arguments.  */
1282 void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...);
1283
1284 /* Replicate a constant C accoring to the log2 of the element size.  */
1285 uint64_t dup_const(unsigned vece, uint64_t c);
1286
1287 #define dup_const(VECE, C)                                         \
1288     (__builtin_constant_p(VECE)                                    \
1289      ? (  (VECE) == MO_8  ? 0x0101010101010101ull * (uint8_t)(C)   \
1290         : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C)  \
1291         : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C)  \
1292         : dup_const(VECE, C))                                      \
1293      : dup_const(VECE, C))
1294
1295
1296 /*
1297  * Memory helpers that will be used by TCG generated code.
1298  */
1299 #ifdef CONFIG_SOFTMMU
1300 /* Value zero-extended to tcg register size.  */
1301 tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
1302                                      TCGMemOpIdx oi, uintptr_t retaddr);
1303 tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
1304                                     TCGMemOpIdx oi, uintptr_t retaddr);
1305 tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
1306                                     TCGMemOpIdx oi, uintptr_t retaddr);
1307 uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
1308                            TCGMemOpIdx oi, uintptr_t retaddr);
1309 tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
1310                                     TCGMemOpIdx oi, uintptr_t retaddr);
1311 tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
1312                                     TCGMemOpIdx oi, uintptr_t retaddr);
1313 uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
1314                            TCGMemOpIdx oi, uintptr_t retaddr);
1315
1316 /* Value sign-extended to tcg register size.  */
1317 tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
1318                                      TCGMemOpIdx oi, uintptr_t retaddr);
1319 tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
1320                                     TCGMemOpIdx oi, uintptr_t retaddr);
1321 tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
1322                                     TCGMemOpIdx oi, uintptr_t retaddr);
1323 tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
1324                                     TCGMemOpIdx oi, uintptr_t retaddr);
1325 tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
1326                                     TCGMemOpIdx oi, uintptr_t retaddr);
1327
1328 void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
1329                         TCGMemOpIdx oi, uintptr_t retaddr);
1330 void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
1331                        TCGMemOpIdx oi, uintptr_t retaddr);
1332 void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
1333                        TCGMemOpIdx oi, uintptr_t retaddr);
1334 void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
1335                        TCGMemOpIdx oi, uintptr_t retaddr);
1336 void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
1337                        TCGMemOpIdx oi, uintptr_t retaddr);
1338 void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
1339                        TCGMemOpIdx oi, uintptr_t retaddr);
1340 void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
1341                        TCGMemOpIdx oi, uintptr_t retaddr);
1342
1343 uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr,
1344                             TCGMemOpIdx oi, uintptr_t retaddr);
1345 uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr,
1346                             TCGMemOpIdx oi, uintptr_t retaddr);
1347 uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr,
1348                             TCGMemOpIdx oi, uintptr_t retaddr);
1349 uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr,
1350                             TCGMemOpIdx oi, uintptr_t retaddr);
1351 uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr,
1352                             TCGMemOpIdx oi, uintptr_t retaddr);
1353 uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr,
1354                             TCGMemOpIdx oi, uintptr_t retaddr);
1355 uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
1356                             TCGMemOpIdx oi, uintptr_t retaddr);
1357
1358 /* Temporary aliases until backends are converted.  */
1359 #ifdef TARGET_WORDS_BIGENDIAN
1360 # define helper_ret_ldsw_mmu  helper_be_ldsw_mmu
1361 # define helper_ret_lduw_mmu  helper_be_lduw_mmu
1362 # define helper_ret_ldsl_mmu  helper_be_ldsl_mmu
1363 # define helper_ret_ldul_mmu  helper_be_ldul_mmu
1364 # define helper_ret_ldl_mmu   helper_be_ldul_mmu
1365 # define helper_ret_ldq_mmu   helper_be_ldq_mmu
1366 # define helper_ret_stw_mmu   helper_be_stw_mmu
1367 # define helper_ret_stl_mmu   helper_be_stl_mmu
1368 # define helper_ret_stq_mmu   helper_be_stq_mmu
1369 # define helper_ret_ldw_cmmu  helper_be_ldw_cmmu
1370 # define helper_ret_ldl_cmmu  helper_be_ldl_cmmu
1371 # define helper_ret_ldq_cmmu  helper_be_ldq_cmmu
1372 #else
1373 # define helper_ret_ldsw_mmu  helper_le_ldsw_mmu
1374 # define helper_ret_lduw_mmu  helper_le_lduw_mmu
1375 # define helper_ret_ldsl_mmu  helper_le_ldsl_mmu
1376 # define helper_ret_ldul_mmu  helper_le_ldul_mmu
1377 # define helper_ret_ldl_mmu   helper_le_ldul_mmu
1378 # define helper_ret_ldq_mmu   helper_le_ldq_mmu
1379 # define helper_ret_stw_mmu   helper_le_stw_mmu
1380 # define helper_ret_stl_mmu   helper_le_stl_mmu
1381 # define helper_ret_stq_mmu   helper_le_stq_mmu
1382 # define helper_ret_ldw_cmmu  helper_le_ldw_cmmu
1383 # define helper_ret_ldl_cmmu  helper_le_ldl_cmmu
1384 # define helper_ret_ldq_cmmu  helper_le_ldq_cmmu
1385 #endif
1386
1387 uint32_t helper_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr,
1388                                     uint32_t cmpv, uint32_t newv,
1389                                     TCGMemOpIdx oi, uintptr_t retaddr);
1390 uint32_t helper_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr,
1391                                        uint32_t cmpv, uint32_t newv,
1392                                        TCGMemOpIdx oi, uintptr_t retaddr);
1393 uint32_t helper_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr,
1394                                        uint32_t cmpv, uint32_t newv,
1395                                        TCGMemOpIdx oi, uintptr_t retaddr);
1396 uint64_t helper_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr,
1397                                        uint64_t cmpv, uint64_t newv,
1398                                        TCGMemOpIdx oi, uintptr_t retaddr);
1399 uint32_t helper_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr,
1400                                        uint32_t cmpv, uint32_t newv,
1401                                        TCGMemOpIdx oi, uintptr_t retaddr);
1402 uint32_t helper_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr,
1403                                        uint32_t cmpv, uint32_t newv,
1404                                        TCGMemOpIdx oi, uintptr_t retaddr);
1405 uint64_t helper_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr,
1406                                        uint64_t cmpv, uint64_t newv,
1407                                        TCGMemOpIdx oi, uintptr_t retaddr);
1408
1409 #define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX)         \
1410 TYPE helper_atomic_ ## NAME ## SUFFIX ## _mmu         \
1411     (CPUArchState *env, target_ulong addr, TYPE val,  \
1412      TCGMemOpIdx oi, uintptr_t retaddr);
1413
1414 #ifdef CONFIG_ATOMIC64
1415 #define GEN_ATOMIC_HELPER_ALL(NAME)          \
1416     GEN_ATOMIC_HELPER(NAME, uint32_t, b)     \
1417     GEN_ATOMIC_HELPER(NAME, uint32_t, w_le)  \
1418     GEN_ATOMIC_HELPER(NAME, uint32_t, w_be)  \
1419     GEN_ATOMIC_HELPER(NAME, uint32_t, l_le)  \
1420     GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)  \
1421     GEN_ATOMIC_HELPER(NAME, uint64_t, q_le)  \
1422     GEN_ATOMIC_HELPER(NAME, uint64_t, q_be)
1423 #else
1424 #define GEN_ATOMIC_HELPER_ALL(NAME)          \
1425     GEN_ATOMIC_HELPER(NAME, uint32_t, b)     \
1426     GEN_ATOMIC_HELPER(NAME, uint32_t, w_le)  \
1427     GEN_ATOMIC_HELPER(NAME, uint32_t, w_be)  \
1428     GEN_ATOMIC_HELPER(NAME, uint32_t, l_le)  \
1429     GEN_ATOMIC_HELPER(NAME, uint32_t, l_be)
1430 #endif
1431
1432 GEN_ATOMIC_HELPER_ALL(fetch_add)
1433 GEN_ATOMIC_HELPER_ALL(fetch_sub)
1434 GEN_ATOMIC_HELPER_ALL(fetch_and)
1435 GEN_ATOMIC_HELPER_ALL(fetch_or)
1436 GEN_ATOMIC_HELPER_ALL(fetch_xor)
1437 GEN_ATOMIC_HELPER_ALL(fetch_smin)
1438 GEN_ATOMIC_HELPER_ALL(fetch_umin)
1439 GEN_ATOMIC_HELPER_ALL(fetch_smax)
1440 GEN_ATOMIC_HELPER_ALL(fetch_umax)
1441
1442 GEN_ATOMIC_HELPER_ALL(add_fetch)
1443 GEN_ATOMIC_HELPER_ALL(sub_fetch)
1444 GEN_ATOMIC_HELPER_ALL(and_fetch)
1445 GEN_ATOMIC_HELPER_ALL(or_fetch)
1446 GEN_ATOMIC_HELPER_ALL(xor_fetch)
1447 GEN_ATOMIC_HELPER_ALL(smin_fetch)
1448 GEN_ATOMIC_HELPER_ALL(umin_fetch)
1449 GEN_ATOMIC_HELPER_ALL(smax_fetch)
1450 GEN_ATOMIC_HELPER_ALL(umax_fetch)
1451
1452 GEN_ATOMIC_HELPER_ALL(xchg)
1453
1454 #undef GEN_ATOMIC_HELPER_ALL
1455 #undef GEN_ATOMIC_HELPER
1456 #endif /* CONFIG_SOFTMMU */
1457
1458 /*
1459  * These aren't really a "proper" helpers because TCG cannot manage Int128.
1460  * However, use the same format as the others, for use by the backends.
1461  *
1462  * The cmpxchg functions are only defined if HAVE_CMPXCHG128;
1463  * the ld/st functions are only defined if HAVE_ATOMIC128,
1464  * as defined by <qemu/atomic128.h>.
1465  */
1466 Int128 helper_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr,
1467                                      Int128 cmpv, Int128 newv,
1468                                      TCGMemOpIdx oi, uintptr_t retaddr);
1469 Int128 helper_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr,
1470                                      Int128 cmpv, Int128 newv,
1471                                      TCGMemOpIdx oi, uintptr_t retaddr);
1472
1473 Int128 helper_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr,
1474                                 TCGMemOpIdx oi, uintptr_t retaddr);
1475 Int128 helper_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr,
1476                                 TCGMemOpIdx oi, uintptr_t retaddr);
1477 void helper_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val,
1478                               TCGMemOpIdx oi, uintptr_t retaddr);
1479 void helper_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val,
1480                               TCGMemOpIdx oi, uintptr_t retaddr);
1481
1482 #endif /* TCG_H */