target-microblaze/cpu.c

   1 /*
   2  * QEMU MicroBlaze CPU
   3  *
   4  * Copyright (c) 2009 Edgar E. Iglesias
   5  * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
   6  * Copyright (c) 2012 SUSE LINUX Products GmbH
   7  * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2.1 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see
  21  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  22  */
  23
  24 #include "cpu.h"
  25 #include "qemu-common.h"
  26 #include "hw/qdev-properties.h"
  27 #include "migration/vmstate.h"
  28
  29
  30 static void mb_cpu_set_pc(CPUState *cs, vaddr value)
  31 {
  32     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
  33
  34     cpu->env.sregs[SR_PC] = value;
  35 }
  36
  37 #ifndef CONFIG_USER_ONLY
  38 static void microblaze_cpu_set_irq(void *opaque, int irq, int level)
  39 {
  40     MicroBlazeCPU *cpu = opaque;
  41     CPUState *cs = CPU(cpu);
  42     int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
  43
  44     if (level) {
  45         cpu_interrupt(cs, type);
  46     } else {
  47         cpu_reset_interrupt(cs, type);
  48     }
  49 }
  50 #endif
  51
  52 /* CPUClass::reset() */
  53 static void mb_cpu_reset(CPUState *s)
  54 {
  55     MicroBlazeCPU *cpu = MICROBLAZE_CPU(s);
  56     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
  57     CPUMBState *env = &cpu->env;
  58
  59     mcc->parent_reset(s);
  60
  61     memset(env, 0, offsetof(CPUMBState, breakpoints));
  62     env->res_addr = RES_ADDR_NONE;
  63     tlb_flush(env, 1);
  64
  65     /* Disable stack protector.  */
  66     env->shr = ~0;
  67
  68     env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
  69                        | PVR0_USE_BARREL_MASK \
  70                        | PVR0_USE_DIV_MASK \
  71                        | PVR0_USE_HW_MUL_MASK \
  72                        | PVR0_USE_EXC_MASK \
  73                        | PVR0_USE_ICACHE_MASK \
  74                        | PVR0_USE_DCACHE_MASK \
  75                        | PVR0_USE_MMU \
  76                        | (0xb << 8);
  77     env->pvr.regs[2] = PVR2_D_OPB_MASK \
  78                         | PVR2_D_LMB_MASK \
  79                         | PVR2_I_OPB_MASK \
  80                         | PVR2_I_LMB_MASK \
  81                         | PVR2_USE_MSR_INSTR \
  82                         | PVR2_USE_PCMP_INSTR \
  83                         | PVR2_USE_BARREL_MASK \
  84                         | PVR2_USE_DIV_MASK \
  85                         | PVR2_USE_HW_MUL_MASK \
  86                         | PVR2_USE_MUL64_MASK \
  87                         | PVR2_USE_FPU_MASK \
  88                         | PVR2_USE_FPU2_MASK \
  89                         | PVR2_FPU_EXC_MASK \
  90                         | 0;
  91     env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family.  */
  92     env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
  93
  94 #if defined(CONFIG_USER_ONLY)
  95     /* start in user mode with interrupts enabled.  */
  96     env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
  97     env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp.  */
  98 #else
  99     env->sregs[SR_MSR] = 0;
 100     mmu_init(&env->mmu);
 101     env->mmu.c_mmu = 3;
 102     env->mmu.c_mmu_tlb_access = 3;
 103     env->mmu.c_mmu_zones = 16;
 104 #endif
 105 }
 106
 107 static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
 108 {
 109     CPUState *cs = CPU(dev);
 110     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
 111
 112     cpu_reset(cs);
 113     qemu_init_vcpu(cs);
 114
 115     mcc->parent_realize(dev, errp);
 116 }
 117
 118 static void mb_cpu_initfn(Object *obj)
 119 {
 120     CPUState *cs = CPU(obj);
 121     MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
 122     CPUMBState *env = &cpu->env;
 123     static bool tcg_initialized;
 124
 125     cs->env_ptr = env;
 126     cpu_exec_init(env);
 127
 128     set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
 129
 130 #ifndef CONFIG_USER_ONLY
 131     /* Inbound IRQ and FIR lines */
 132     qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2);
 133 #endif
 134
 135     if (tcg_enabled() && !tcg_initialized) {
 136         tcg_initialized = true;
 137         mb_tcg_init();
 138     }
 139 }
 140
 141 static const VMStateDescription vmstate_mb_cpu = {
 142     .name = "cpu",
 143     .unmigratable = 1,
 144 };
 145
 146 static Property mb_properties[] = {
 147     DEFINE_PROP_UINT32("xlnx.base-vectors", MicroBlazeCPU, base_vectors, 0),
 148     DEFINE_PROP_END_OF_LIST(),
 149 };
 150
 151 static void mb_cpu_class_init(ObjectClass *oc, void *data)
 152 {
 153     DeviceClass *dc = DEVICE_CLASS(oc);
 154     CPUClass *cc = CPU_CLASS(oc);
 155     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
 156
 157     mcc->parent_realize = dc->realize;
 158     dc->realize = mb_cpu_realizefn;
 159
 160     mcc->parent_reset = cc->reset;
 161     cc->reset = mb_cpu_reset;
 162
 163     cc->do_interrupt = mb_cpu_do_interrupt;
 164     cc->dump_state = mb_cpu_dump_state;
 165     cc->set_pc = mb_cpu_set_pc;
 166     cc->gdb_read_register = mb_cpu_gdb_read_register;
 167     cc->gdb_write_register = mb_cpu_gdb_write_register;
 168 #ifndef CONFIG_USER_ONLY
 169     cc->do_unassigned_access = mb_cpu_unassigned_access;
 170     cc->get_phys_page_debug = mb_cpu_get_phys_page_debug;
 171 #endif
 172     dc->vmsd = &vmstate_mb_cpu;
 173     dc->props = mb_properties;
 174     cc->gdb_num_core_regs = 32 + 5;
 175 }
 176
 177 static const TypeInfo mb_cpu_type_info = {
 178     .name = TYPE_MICROBLAZE_CPU,
 179     .parent = TYPE_CPU,
 180     .instance_size = sizeof(MicroBlazeCPU),
 181     .instance_init = mb_cpu_initfn,
 182     .class_size = sizeof(MicroBlazeCPUClass),
 183     .class_init = mb_cpu_class_init,
 184 };
 185
 186 static void mb_cpu_register_types(void)
 187 {
 188     type_register_static(&mb_cpu_type_info);
 189 }
 190
 191 type_init(mb_cpu_register_types)