hw/pci-host/i440fx.c

   1 /*
   2  * QEMU i440FX PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qemu/range.h"
  27 #include "hw/i386/pc.h"
  28 #include "hw/pci/pci.h"
  29 #include "hw/pci/pci_host.h"
  30 #include "hw/pci-host/i440fx.h"
  31 #include "hw/qdev-properties.h"
  32 #include "hw/sysbus.h"
  33 #include "qapi/error.h"
  34 #include "migration/vmstate.h"
  35 #include "qapi/visitor.h"
  36 #include "qemu/error-report.h"
  37
  38 /*
  39  * I440FX chipset data sheet.
  40  * https://wiki.qemu.org/File:29054901.pdf
  41  */
  42
  43 #define I440FX_PCI_HOST_BRIDGE(obj) \
  44     OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE)
  45
  46 typedef struct I440FXState {
  47     PCIHostState parent_obj;
  48     Range pci_hole;
  49     uint64_t pci_hole64_size;
  50     bool pci_hole64_fix;
  51     uint32_t short_root_bus;
  52 } I440FXState;
  53
  54 #define I440FX_PAM      0x59
  55 #define I440FX_PAM_SIZE 7
  56 #define I440FX_SMRAM    0x72
  57
  58 /* Keep it 2G to comply with older win32 guests */
  59 #define I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 31)
  60
  61 /* Older coreboot versions (4.0 and older) read a config register that doesn't
  62  * exist in real hardware, to get the RAM size from QEMU.
  63  */
  64 #define I440FX_COREBOOT_RAM_SIZE 0x57
  65
  66 static void i440fx_update_memory_mappings(PCII440FXState *d)
  67 {
  68     int i;
  69     PCIDevice *pd = PCI_DEVICE(d);
  70
  71     memory_region_transaction_begin();
  72     for (i = 0; i < ARRAY_SIZE(d->pam_regions); i++) {
  73         pam_update(&d->pam_regions[i], i,
  74                    pd->config[I440FX_PAM + DIV_ROUND_UP(i, 2)]);
  75     }
  76     memory_region_set_enabled(&d->smram_region,
  77                               !(pd->config[I440FX_SMRAM] & SMRAM_D_OPEN));
  78     memory_region_set_enabled(&d->smram,
  79                               pd->config[I440FX_SMRAM] & SMRAM_G_SMRAME);
  80     memory_region_transaction_commit();
  81 }
  82
  83
  84 static void i440fx_write_config(PCIDevice *dev,
  85                                 uint32_t address, uint32_t val, int len)
  86 {
  87     PCII440FXState *d = I440FX_PCI_DEVICE(dev);
  88
  89     /* XXX: implement SMRAM.D_LOCK */
  90     pci_default_write_config(dev, address, val, len);
  91     if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
  92         range_covers_byte(address, len, I440FX_SMRAM)) {
  93         i440fx_update_memory_mappings(d);
  94     }
  95 }
  96
  97 static int i440fx_post_load(void *opaque, int version_id)
  98 {
  99     PCII440FXState *d = opaque;
 100
 101     i440fx_update_memory_mappings(d);
 102     return 0;
 103 }
 104
 105 static const VMStateDescription vmstate_i440fx = {
 106     .name = "I440FX",
 107     .version_id = 3,
 108     .minimum_version_id = 3,
 109     .post_load = i440fx_post_load,
 110     .fields = (VMStateField[]) {
 111         VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
 112         /* Used to be smm_enabled, which was basically always zero because
 113          * SeaBIOS hardly uses SMM.  SMRAM is now handled by CPU code.
 114          */
 115         VMSTATE_UNUSED(1),
 116         VMSTATE_END_OF_LIST()
 117     }
 118 };
 119
 120 static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v,
 121                                               const char *name, void *opaque,
 122                                               Error **errp)
 123 {
 124     I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
 125     uint64_t val64;
 126     uint32_t value;
 127
 128     val64 = range_is_empty(&s->pci_hole) ? 0 : range_lob(&s->pci_hole);
 129     value = val64;
 130     assert(value == val64);
 131     visit_type_uint32(v, name, &value, errp);
 132 }
 133
 134 static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v,
 135                                             const char *name, void *opaque,
 136                                             Error **errp)
 137 {
 138     I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
 139     uint64_t val64;
 140     uint32_t value;
 141
 142     val64 = range_is_empty(&s->pci_hole) ? 0 : range_upb(&s->pci_hole) + 1;
 143     value = val64;
 144     assert(value == val64);
 145     visit_type_uint32(v, name, &value, errp);
 146 }
 147
 148 /*
 149  * The 64bit PCI hole start is set by the Guest firmware
 150  * as the address of the first 64bit PCI MEM resource.
 151  * If no PCI device has resources on the 64bit area,
 152  * the 64bit PCI hole will start after "over 4G RAM" and the
 153  * reserved space for memory hotplug if any.
 154  */
 155 static uint64_t i440fx_pcihost_get_pci_hole64_start_value(Object *obj)
 156 {
 157     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 158     I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
 159     Range w64;
 160     uint64_t value;
 161
 162     pci_bus_get_w64_range(h->bus, &w64);
 163     value = range_is_empty(&w64) ? 0 : range_lob(&w64);
 164     if (!value && s->pci_hole64_fix) {
 165         value = pc_pci_hole64_start();
 166     }
 167     return value;
 168 }
 169
 170 static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v,
 171                                                 const char *name,
 172                                                 void *opaque, Error **errp)
 173 {
 174     uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj);
 175
 176     visit_type_uint64(v, name, &hole64_start, errp);
 177 }
 178
 179 /*
 180  * The 64bit PCI hole end is set by the Guest firmware
 181  * as the address of the last 64bit PCI MEM resource.
 182  * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE
 183  * that can be configured by the user.
 184  */
 185 static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,
 186                                               const char *name, void *opaque,
 187                                               Error **errp)
 188 {
 189     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 190     I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
 191     uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj);
 192     Range w64;
 193     uint64_t value, hole64_end;
 194
 195     pci_bus_get_w64_range(h->bus, &w64);
 196     value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1;
 197     hole64_end = ROUND_UP(hole64_start + s->pci_hole64_size, 1ULL << 30);
 198     if (s->pci_hole64_fix && value < hole64_end) {
 199         value = hole64_end;
 200     }
 201     visit_type_uint64(v, name, &value, errp);
 202 }
 203
 204 static void i440fx_pcihost_initfn(Object *obj)
 205 {
 206     PCIHostState *s = PCI_HOST_BRIDGE(obj);
 207
 208     memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s,
 209                           "pci-conf-idx", 4);
 210     memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s,
 211                           "pci-conf-data", 4);
 212
 213     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32",
 214                         i440fx_pcihost_get_pci_hole_start,
 215                         NULL, NULL, NULL, NULL);
 216
 217     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32",
 218                         i440fx_pcihost_get_pci_hole_end,
 219                         NULL, NULL, NULL, NULL);
 220
 221     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64",
 222                         i440fx_pcihost_get_pci_hole64_start,
 223                         NULL, NULL, NULL, NULL);
 224
 225     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64",
 226                         i440fx_pcihost_get_pci_hole64_end,
 227                         NULL, NULL, NULL, NULL);
 228 }
 229
 230 static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
 231 {
 232     PCIHostState *s = PCI_HOST_BRIDGE(dev);
 233     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 234
 235     sysbus_add_io(sbd, 0xcf8, &s->conf_mem);
 236     sysbus_init_ioports(sbd, 0xcf8, 4);
 237
 238     sysbus_add_io(sbd, 0xcfc, &s->data_mem);
 239     sysbus_init_ioports(sbd, 0xcfc, 4);
 240
 241     /* register i440fx 0xcf8 port as coalesced pio */
 242     memory_region_set_flush_coalesced(&s->data_mem);
 243     memory_region_add_coalescing(&s->conf_mem, 0, 4);
 244 }
 245
 246 static void i440fx_realize(PCIDevice *dev, Error **errp)
 247 {
 248     dev->config[I440FX_SMRAM] = 0x02;
 249
 250     if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) {
 251         warn_report("i440fx doesn't support emulated iommu");
 252     }
 253 }
 254
 255 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
 256                     PCII440FXState **pi440fx_state,
 257                     MemoryRegion *address_space_mem,
 258                     MemoryRegion *address_space_io,
 259                     ram_addr_t ram_size,
 260                     ram_addr_t below_4g_mem_size,
 261                     ram_addr_t above_4g_mem_size,
 262                     MemoryRegion *pci_address_space,
 263                     MemoryRegion *ram_memory)
 264 {
 265     DeviceState *dev;
 266     PCIBus *b;
 267     PCIDevice *d;
 268     PCIHostState *s;
 269     PCII440FXState *f;
 270     unsigned i;
 271     I440FXState *i440fx;
 272
 273     dev = qdev_create(NULL, host_type);
 274     s = PCI_HOST_BRIDGE(dev);
 275     b = pci_root_bus_new(dev, NULL, pci_address_space,
 276                          address_space_io, 0, TYPE_PCI_BUS);
 277     s->bus = b;
 278     object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
 279     qdev_init_nofail(dev);
 280
 281     d = pci_create_simple(b, 0, pci_type);
 282     *pi440fx_state = I440FX_PCI_DEVICE(d);
 283     f = *pi440fx_state;
 284     f->system_memory = address_space_mem;
 285     f->pci_address_space = pci_address_space;
 286     f->ram_memory = ram_memory;
 287
 288     i440fx = I440FX_PCI_HOST_BRIDGE(dev);
 289     range_set_bounds(&i440fx->pci_hole, below_4g_mem_size,
 290                      IO_APIC_DEFAULT_ADDRESS - 1);
 291
 292     /* setup pci memory mapping */
 293     pc_pci_as_mapping_init(OBJECT(f), f->system_memory,
 294                            f->pci_address_space);
 295
 296     /* if *disabled* show SMRAM to all CPUs */
 297     memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region",
 298                              f->pci_address_space, 0xa0000, 0x20000);
 299     memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
 300                                         &f->smram_region, 1);
 301     memory_region_set_enabled(&f->smram_region, true);
 302
 303     /* smram, as seen by SMM CPUs */
 304     memory_region_init(&f->smram, OBJECT(d), "smram", 1ull << 32);
 305     memory_region_set_enabled(&f->smram, true);
 306     memory_region_init_alias(&f->low_smram, OBJECT(d), "smram-low",
 307                              f->ram_memory, 0xa0000, 0x20000);
 308     memory_region_set_enabled(&f->low_smram, true);
 309     memory_region_add_subregion(&f->smram, 0xa0000, &f->low_smram);
 310     object_property_add_const_link(qdev_get_machine(), "smram",
 311                                    OBJECT(&f->smram), &error_abort);
 312
 313     init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
 314              &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
 315     for (i = 0; i < ARRAY_SIZE(f->pam_regions) - 1; ++i) {
 316         init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
 317                  &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
 318                  PAM_EXPAN_SIZE);
 319     }
 320
 321     ram_size = ram_size / 8 / 1024 / 1024;
 322     if (ram_size > 255) {
 323         ram_size = 255;
 324     }
 325     d->config[I440FX_COREBOOT_RAM_SIZE] = ram_size;
 326
 327     i440fx_update_memory_mappings(f);
 328
 329     return b;
 330 }
 331
 332 PCIBus *find_i440fx(void)
 333 {
 334     PCIHostState *s = OBJECT_CHECK(PCIHostState,
 335                                    object_resolve_path("/machine/i440fx", NULL),
 336                                    TYPE_PCI_HOST_BRIDGE);
 337     return s ? s->bus : NULL;
 338 }
 339
 340 static void i440fx_class_init(ObjectClass *klass, void *data)
 341 {
 342     DeviceClass *dc = DEVICE_CLASS(klass);
 343     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 344
 345     k->realize = i440fx_realize;
 346     k->config_write = i440fx_write_config;
 347     k->vendor_id = PCI_VENDOR_ID_INTEL;
 348     k->device_id = PCI_DEVICE_ID_INTEL_82441;
 349     k->revision = 0x02;
 350     k->class_id = PCI_CLASS_BRIDGE_HOST;
 351     dc->desc = "Host bridge";
 352     dc->vmsd = &vmstate_i440fx;
 353     /*
 354      * PCI-facing part of the host bridge, not usable without the
 355      * host-facing part, which can't be device_add'ed, yet.
 356      */
 357     dc->user_creatable = false;
 358     dc->hotpluggable   = false;
 359 }
 360
 361 static const TypeInfo i440fx_info = {
 362     .name          = TYPE_I440FX_PCI_DEVICE,
 363     .parent        = TYPE_PCI_DEVICE,
 364     .instance_size = sizeof(PCII440FXState),
 365     .class_init    = i440fx_class_init,
 366     .interfaces = (InterfaceInfo[]) {
 367         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 368         { },
 369     },
 370 };
 371
 372 static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
 373                                                 PCIBus *rootbus)
 374 {
 375     I440FXState *s = I440FX_PCI_HOST_BRIDGE(host_bridge);
 376
 377     /* For backwards compat with old device paths */
 378     if (s->short_root_bus) {
 379         return "0000";
 380     }
 381     return "0000:00";
 382 }
 383
 384 static Property i440fx_props[] = {
 385     DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState,
 386                      pci_hole64_size, I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT),
 387     DEFINE_PROP_UINT32("short_root_bus", I440FXState, short_root_bus, 0),
 388     DEFINE_PROP_BOOL("x-pci-hole64-fix", I440FXState, pci_hole64_fix, true),
 389     DEFINE_PROP_END_OF_LIST(),
 390 };
 391
 392 static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
 393 {
 394     DeviceClass *dc = DEVICE_CLASS(klass);
 395     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
 396
 397     hc->root_bus_path = i440fx_pcihost_root_bus_path;
 398     dc->realize = i440fx_pcihost_realize;
 399     dc->fw_name = "pci";
 400     device_class_set_props(dc, i440fx_props);
 401     /* Reason: needs to be wired up by pc_init1 */
 402     dc->user_creatable = false;
 403 }
 404
 405 static const TypeInfo i440fx_pcihost_info = {
 406     .name          = TYPE_I440FX_PCI_HOST_BRIDGE,
 407     .parent        = TYPE_PCI_HOST_BRIDGE,
 408     .instance_size = sizeof(I440FXState),
 409     .instance_init = i440fx_pcihost_initfn,
 410     .class_init    = i440fx_pcihost_class_init,
 411 };
 412
 413 static void i440fx_register_types(void)
 414 {
 415     type_register_static(&i440fx_info);
 416     type_register_static(&i440fx_pcihost_info);
 417 }
 418
 419 type_init(i440fx_register_types)