target-microblaze/cpu.c

   1 /*
   2  * QEMU MicroBlaze CPU
   3  *
   4  * Copyright (c) 2009 Edgar E. Iglesias
   5  * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
   6  * Copyright (c) 2012 SUSE LINUX Products GmbH
   7  * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2.1 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see
  21  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  22  */
  23
  24 #include "cpu.h"
  25 #include "qemu-common.h"
  26 #include "hw/qdev-properties.h"
  27 #include "migration/vmstate.h"
  28
  29 static const struct {
  30     const char *name;
  31     uint8_t version_id;
  32 } mb_cpu_lookup[] = {
  33     /* These key value are as per MBV field in PVR0 */
  34     {"5.00.a", 0x01},
  35     {"5.00.b", 0x02},
  36     {"5.00.c", 0x03},
  37     {"6.00.a", 0x04},
  38     {"6.00.b", 0x06},
  39     {"7.00.a", 0x05},
  40     {"7.00.b", 0x07},
  41     {"7.10.a", 0x08},
  42     {"7.10.b", 0x09},
  43     {"7.10.c", 0x0a},
  44     {"7.10.d", 0x0b},
  45     {"7.20.a", 0x0c},
  46     {"7.20.b", 0x0d},
  47     {"7.20.c", 0x0e},
  48     {"7.20.d", 0x0f},
  49     {"7.30.a", 0x10},
  50     {"7.30.b", 0x11},
  51     {"8.00.a", 0x12},
  52     {"8.00.b", 0x13},
  53     {"8.10.a", 0x14},
  54     {"8.20.a", 0x15},
  55     {"8.20.b", 0x16},
  56     {"8.30.a", 0x17},
  57     {"8.40.a", 0x18},
  58     {"8.40.b", 0x19},
  59     {"8.50.a", 0x1A},
  60     {"9.0", 0x1B},
  61     {"9.1", 0x1D},
  62     {"9.2", 0x1F},
  63     {"9.3", 0x20},
  64     {NULL, 0},
  65 };
  66
  67 static void mb_cpu_set_pc(CPUState *cs, vaddr value)
  68 {
  69     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
  70
  71     cpu->env.sregs[SR_PC] = value;
  72 }
  73
  74 static bool mb_cpu_has_work(CPUState *cs)
  75 {
  76     return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
  77 }
  78
  79 #ifndef CONFIG_USER_ONLY
  80 static void microblaze_cpu_set_irq(void *opaque, int irq, int level)
  81 {
  82     MicroBlazeCPU *cpu = opaque;
  83     CPUState *cs = CPU(cpu);
  84     int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
  85
  86     if (level) {
  87         cpu_interrupt(cs, type);
  88     } else {
  89         cpu_reset_interrupt(cs, type);
  90     }
  91 }
  92 #endif
  93
  94 /* CPUClass::reset() */
  95 static void mb_cpu_reset(CPUState *s)
  96 {
  97     MicroBlazeCPU *cpu = MICROBLAZE_CPU(s);
  98     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
  99     CPUMBState *env = &cpu->env;
 100
 101     mcc->parent_reset(s);
 102
 103     memset(env, 0, offsetof(CPUMBState, pvr));
 104     env->res_addr = RES_ADDR_NONE;
 105     tlb_flush(s, 1);
 106
 107     /* Disable stack protector.  */
 108     env->shr = ~0;
 109
 110 #if defined(CONFIG_USER_ONLY)
 111     /* start in user mode with interrupts enabled.  */
 112     env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
 113 #else
 114     env->sregs[SR_MSR] = 0;
 115     mmu_init(&env->mmu);
 116     env->mmu.c_mmu = 3;
 117     env->mmu.c_mmu_tlb_access = 3;
 118     env->mmu.c_mmu_zones = 16;
 119 #endif
 120 }
 121
 122 static void mb_disas_set_info(CPUState *cpu, disassemble_info *info)
 123 {
 124     info->mach = bfd_arch_microblaze;
 125     info->print_insn = print_insn_microblaze;
 126 }
 127
 128 static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
 129 {
 130     CPUState *cs = CPU(dev);
 131     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
 132     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 133     CPUMBState *env = &cpu->env;
 134     uint8_t version_code = 0;
 135     int i = 0;
 136
 137     qemu_init_vcpu(cs);
 138
 139     env->pvr.regs[0] = PVR0_USE_BARREL_MASK \
 140                        | PVR0_USE_DIV_MASK \
 141                        | PVR0_USE_HW_MUL_MASK \
 142                        | PVR0_USE_EXC_MASK \
 143                        | PVR0_USE_ICACHE_MASK \
 144                        | PVR0_USE_DCACHE_MASK \
 145                        | (0xb << 8);
 146     env->pvr.regs[2] = PVR2_D_OPB_MASK \
 147                         | PVR2_D_LMB_MASK \
 148                         | PVR2_I_OPB_MASK \
 149                         | PVR2_I_LMB_MASK \
 150                         | PVR2_USE_MSR_INSTR \
 151                         | PVR2_USE_PCMP_INSTR \
 152                         | PVR2_USE_BARREL_MASK \
 153                         | PVR2_USE_DIV_MASK \
 154                         | PVR2_USE_HW_MUL_MASK \
 155                         | PVR2_USE_MUL64_MASK \
 156                         | PVR2_FPU_EXC_MASK \
 157                         | 0;
 158
 159     for (i = 0; mb_cpu_lookup[i].name && cpu->cfg.version; i++) {
 160         if (strcmp(mb_cpu_lookup[i].name, cpu->cfg.version) == 0) {
 161             version_code = mb_cpu_lookup[i].version_id;
 162             break;
 163         }
 164     }
 165
 166     if (!version_code) {
 167         qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version);
 168     }
 169
 170     env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
 171                         (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
 172                         (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
 173                         (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
 174                         (version_code << 16) |
 175                         (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0);
 176
 177     env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
 178                         (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
 179
 180     env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
 181                                         PVR5_DCACHE_WRITEBACK_MASK : 0;
 182
 183     env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family.  */
 184     env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
 185
 186     env->sregs[SR_PC] = cpu->cfg.base_vectors;
 187
 188     mcc->parent_realize(dev, errp);
 189 }
 190
 191 static void mb_cpu_initfn(Object *obj)
 192 {
 193     CPUState *cs = CPU(obj);
 194     MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
 195     CPUMBState *env = &cpu->env;
 196     static bool tcg_initialized;
 197
 198     cs->env_ptr = env;
 199     cpu_exec_init(cs, &error_abort);
 200
 201     set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
 202
 203 #ifndef CONFIG_USER_ONLY
 204     /* Inbound IRQ and FIR lines */
 205     qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2);
 206 #endif
 207
 208     if (tcg_enabled() && !tcg_initialized) {
 209         tcg_initialized = true;
 210         mb_tcg_init();
 211     }
 212 }
 213
 214 static const VMStateDescription vmstate_mb_cpu = {
 215     .name = "cpu",
 216     .unmigratable = 1,
 217 };
 218
 219 static Property mb_properties[] = {
 220     DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
 221     DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
 222                      false),
 223     /* If use-fpu > 0 - FPU is enabled
 224      * If use-fpu = 2 - Floating point conversion and square root instructions
 225      *                  are enabled
 226      */
 227     DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
 228     DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
 229     DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
 230                      false),
 231     DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
 232     DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
 233     DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
 234     DEFINE_PROP_END_OF_LIST(),
 235 };
 236
 237 static void mb_cpu_class_init(ObjectClass *oc, void *data)
 238 {
 239     DeviceClass *dc = DEVICE_CLASS(oc);
 240     CPUClass *cc = CPU_CLASS(oc);
 241     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
 242
 243     mcc->parent_realize = dc->realize;
 244     dc->realize = mb_cpu_realizefn;
 245
 246     mcc->parent_reset = cc->reset;
 247     cc->reset = mb_cpu_reset;
 248
 249     cc->has_work = mb_cpu_has_work;
 250     cc->do_interrupt = mb_cpu_do_interrupt;
 251     cc->cpu_exec_interrupt = mb_cpu_exec_interrupt;
 252     cc->dump_state = mb_cpu_dump_state;
 253     cc->set_pc = mb_cpu_set_pc;
 254     cc->gdb_read_register = mb_cpu_gdb_read_register;
 255     cc->gdb_write_register = mb_cpu_gdb_write_register;
 256 #ifdef CONFIG_USER_ONLY
 257     cc->handle_mmu_fault = mb_cpu_handle_mmu_fault;
 258 #else
 259     cc->do_unassigned_access = mb_cpu_unassigned_access;
 260     cc->get_phys_page_debug = mb_cpu_get_phys_page_debug;
 261 #endif
 262     dc->vmsd = &vmstate_mb_cpu;
 263     dc->props = mb_properties;
 264     cc->gdb_num_core_regs = 32 + 5;
 265
 266     cc->disas_set_info = mb_disas_set_info;
 267 }
 268
 269 static const TypeInfo mb_cpu_type_info = {
 270     .name = TYPE_MICROBLAZE_CPU,
 271     .parent = TYPE_CPU,
 272     .instance_size = sizeof(MicroBlazeCPU),
 273     .instance_init = mb_cpu_initfn,
 274     .class_size = sizeof(MicroBlazeCPUClass),
 275     .class_init = mb_cpu_class_init,
 276 };
 277
 278 static void mb_cpu_register_types(void)
 279 {
 280     type_register_static(&mb_cpu_type_info);
 281 }
 282
 283 type_init(mb_cpu_register_types)