hw/arm_sysctl: Handle SYS_CFGCTRL in a more structured way
[qemu/ar7.git] / hw / arm_sysctl.c
blob05a3200c632eb8e0e6943fb4b16632819895f376
1 /*
2 * Status and system control registers for ARM RealView/Versatile boards.
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
8 */
10 #include "hw/hw.h"
11 #include "qemu/timer.h"
12 #include "qemu/bitops.h"
13 #include "hw/sysbus.h"
14 #include "hw/primecell.h"
15 #include "sysemu/sysemu.h"
17 #define LOCK_VALUE 0xa05f
19 typedef struct {
20 SysBusDevice busdev;
21 MemoryRegion iomem;
22 qemu_irq pl110_mux_ctrl;
24 uint32_t sys_id;
25 uint32_t leds;
26 uint16_t lockval;
27 uint32_t cfgdata1;
28 uint32_t cfgdata2;
29 uint32_t flags;
30 uint32_t nvflags;
31 uint32_t resetlevel;
32 uint32_t proc_id;
33 uint32_t sys_mci;
34 uint32_t sys_cfgdata;
35 uint32_t sys_cfgctrl;
36 uint32_t sys_cfgstat;
37 uint32_t sys_clcd;
38 } arm_sysctl_state;
40 static const VMStateDescription vmstate_arm_sysctl = {
41 .name = "realview_sysctl",
42 .version_id = 3,
43 .minimum_version_id = 1,
44 .fields = (VMStateField[]) {
45 VMSTATE_UINT32(leds, arm_sysctl_state),
46 VMSTATE_UINT16(lockval, arm_sysctl_state),
47 VMSTATE_UINT32(cfgdata1, arm_sysctl_state),
48 VMSTATE_UINT32(cfgdata2, arm_sysctl_state),
49 VMSTATE_UINT32(flags, arm_sysctl_state),
50 VMSTATE_UINT32(nvflags, arm_sysctl_state),
51 VMSTATE_UINT32(resetlevel, arm_sysctl_state),
52 VMSTATE_UINT32_V(sys_mci, arm_sysctl_state, 2),
53 VMSTATE_UINT32_V(sys_cfgdata, arm_sysctl_state, 2),
54 VMSTATE_UINT32_V(sys_cfgctrl, arm_sysctl_state, 2),
55 VMSTATE_UINT32_V(sys_cfgstat, arm_sysctl_state, 2),
56 VMSTATE_UINT32_V(sys_clcd, arm_sysctl_state, 3),
57 VMSTATE_END_OF_LIST()
61 /* The PB926 actually uses a different format for
62 * its SYS_ID register. Fortunately the bits which are
63 * board type on later boards are distinct.
65 #define BOARD_ID_PB926 0x100
66 #define BOARD_ID_EB 0x140
67 #define BOARD_ID_PBA8 0x178
68 #define BOARD_ID_PBX 0x182
69 #define BOARD_ID_VEXPRESS 0x190
71 static int board_id(arm_sysctl_state *s)
73 /* Extract the board ID field from the SYS_ID register value */
74 return (s->sys_id >> 16) & 0xfff;
77 static void arm_sysctl_reset(DeviceState *d)
79 arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, SYS_BUS_DEVICE(d));
81 s->leds = 0;
82 s->lockval = 0;
83 s->cfgdata1 = 0;
84 s->cfgdata2 = 0;
85 s->flags = 0;
86 s->resetlevel = 0;
87 if (board_id(s) == BOARD_ID_VEXPRESS) {
88 /* On VExpress this register will RAZ/WI */
89 s->sys_clcd = 0;
90 } else {
91 /* All others: CLCDID 0x1f, indicating VGA */
92 s->sys_clcd = 0x1f00;
96 static uint64_t arm_sysctl_read(void *opaque, hwaddr offset,
97 unsigned size)
99 arm_sysctl_state *s = (arm_sysctl_state *)opaque;
101 switch (offset) {
102 case 0x00: /* ID */
103 return s->sys_id;
104 case 0x04: /* SW */
105 /* General purpose hardware switches.
106 We don't have a useful way of exposing these to the user. */
107 return 0;
108 case 0x08: /* LED */
109 return s->leds;
110 case 0x20: /* LOCK */
111 return s->lockval;
112 case 0x0c: /* OSC0 */
113 case 0x10: /* OSC1 */
114 case 0x14: /* OSC2 */
115 case 0x18: /* OSC3 */
116 case 0x1c: /* OSC4 */
117 case 0x24: /* 100HZ */
118 /* ??? Implement these. */
119 return 0;
120 case 0x28: /* CFGDATA1 */
121 return s->cfgdata1;
122 case 0x2c: /* CFGDATA2 */
123 return s->cfgdata2;
124 case 0x30: /* FLAGS */
125 return s->flags;
126 case 0x38: /* NVFLAGS */
127 return s->nvflags;
128 case 0x40: /* RESETCTL */
129 if (board_id(s) == BOARD_ID_VEXPRESS) {
130 /* reserved: RAZ/WI */
131 return 0;
133 return s->resetlevel;
134 case 0x44: /* PCICTL */
135 return 1;
136 case 0x48: /* MCI */
137 return s->sys_mci;
138 case 0x4c: /* FLASH */
139 return 0;
140 case 0x50: /* CLCD */
141 return s->sys_clcd;
142 case 0x54: /* CLCDSER */
143 return 0;
144 case 0x58: /* BOOTCS */
145 return 0;
146 case 0x5c: /* 24MHz */
147 return muldiv64(qemu_get_clock_ns(vm_clock), 24000000, get_ticks_per_sec());
148 case 0x60: /* MISC */
149 return 0;
150 case 0x84: /* PROCID0 */
151 return s->proc_id;
152 case 0x88: /* PROCID1 */
153 return 0xff000000;
154 case 0x64: /* DMAPSR0 */
155 case 0x68: /* DMAPSR1 */
156 case 0x6c: /* DMAPSR2 */
157 case 0x70: /* IOSEL */
158 case 0x74: /* PLDCTL */
159 case 0x80: /* BUSID */
160 case 0x8c: /* OSCRESET0 */
161 case 0x90: /* OSCRESET1 */
162 case 0x94: /* OSCRESET2 */
163 case 0x98: /* OSCRESET3 */
164 case 0x9c: /* OSCRESET4 */
165 case 0xc0: /* SYS_TEST_OSC0 */
166 case 0xc4: /* SYS_TEST_OSC1 */
167 case 0xc8: /* SYS_TEST_OSC2 */
168 case 0xcc: /* SYS_TEST_OSC3 */
169 case 0xd0: /* SYS_TEST_OSC4 */
170 return 0;
171 case 0xa0: /* SYS_CFGDATA */
172 if (board_id(s) != BOARD_ID_VEXPRESS) {
173 goto bad_reg;
175 return s->sys_cfgdata;
176 case 0xa4: /* SYS_CFGCTRL */
177 if (board_id(s) != BOARD_ID_VEXPRESS) {
178 goto bad_reg;
180 return s->sys_cfgctrl;
181 case 0xa8: /* SYS_CFGSTAT */
182 if (board_id(s) != BOARD_ID_VEXPRESS) {
183 goto bad_reg;
185 return s->sys_cfgstat;
186 default:
187 bad_reg:
188 qemu_log_mask(LOG_GUEST_ERROR,
189 "arm_sysctl_read: Bad register offset 0x%x\n",
190 (int)offset);
191 return 0;
195 /* SYS_CFGCTRL functions */
196 #define SYS_CFG_OSC 1
197 #define SYS_CFG_VOLT 2
198 #define SYS_CFG_AMP 3
199 #define SYS_CFG_TEMP 4
200 #define SYS_CFG_RESET 5
201 #define SYS_CFG_SCC 6
202 #define SYS_CFG_MUXFPGA 7
203 #define SYS_CFG_SHUTDOWN 8
204 #define SYS_CFG_REBOOT 9
205 #define SYS_CFG_DVIMODE 11
206 #define SYS_CFG_POWER 12
207 #define SYS_CFG_ENERGY 13
209 /* SYS_CFGCTRL site field values */
210 #define SYS_CFG_SITE_MB 0
211 #define SYS_CFG_SITE_DB1 1
212 #define SYS_CFG_SITE_DB2 2
215 * vexpress_cfgctrl_read:
216 * @s: arm_sysctl_state pointer
217 * @dcc, @function, @site, @position, @device: split out values from
218 * SYS_CFGCTRL register
219 * @val: pointer to where to put the read data on success
221 * Handle a VExpress SYS_CFGCTRL register read. On success, return true and
222 * write the read value to *val. On failure, return false (and val may
223 * or may not be written to).
225 static bool vexpress_cfgctrl_read(arm_sysctl_state *s, unsigned int dcc,
226 unsigned int function, unsigned int site,
227 unsigned int position, unsigned int device,
228 uint32_t *val)
230 /* We don't support anything other than DCC 0, board stack position 0
231 * or sites other than motherboard/daughterboard:
233 if (dcc != 0 || position != 0 ||
234 (site != SYS_CFG_SITE_MB && site != SYS_CFG_SITE_DB1)) {
235 goto cfgctrl_unimp;
238 switch (function) {
239 default:
240 break;
243 cfgctrl_unimp:
244 qemu_log_mask(LOG_UNIMP,
245 "arm_sysctl: Unimplemented SYS_CFGCTRL read of function "
246 "0x%x DCC 0x%x site 0x%x position 0x%x device 0x%x\n",
247 function, dcc, site, position, device);
248 return false;
252 * vexpress_cfgctrl_write:
253 * @s: arm_sysctl_state pointer
254 * @dcc, @function, @site, @position, @device: split out values from
255 * SYS_CFGCTRL register
256 * @val: data to write
258 * Handle a VExpress SYS_CFGCTRL register write. On success, return true.
259 * On failure, return false.
261 static bool vexpress_cfgctrl_write(arm_sysctl_state *s, unsigned int dcc,
262 unsigned int function, unsigned int site,
263 unsigned int position, unsigned int device,
264 uint32_t val)
266 /* We don't support anything other than DCC 0, board stack position 0
267 * or sites other than motherboard/daughterboard:
269 if (dcc != 0 || position != 0 ||
270 (site != SYS_CFG_SITE_MB && site != SYS_CFG_SITE_DB1)) {
271 goto cfgctrl_unimp;
274 switch (function) {
275 case SYS_CFG_SHUTDOWN:
276 if (site == SYS_CFG_SITE_MB && device == 0) {
277 qemu_system_shutdown_request();
278 return true;
280 break;
281 case SYS_CFG_REBOOT:
282 if (site == SYS_CFG_SITE_MB && device == 0) {
283 qemu_system_reset_request();
284 return true;
286 break;
287 default:
288 break;
291 cfgctrl_unimp:
292 qemu_log_mask(LOG_UNIMP,
293 "arm_sysctl: Unimplemented SYS_CFGCTRL write of function "
294 "0x%x DCC 0x%x site 0x%x position 0x%x device 0x%x\n",
295 function, dcc, site, position, device);
296 return false;
299 static void arm_sysctl_write(void *opaque, hwaddr offset,
300 uint64_t val, unsigned size)
302 arm_sysctl_state *s = (arm_sysctl_state *)opaque;
304 switch (offset) {
305 case 0x08: /* LED */
306 s->leds = val;
307 break;
308 case 0x0c: /* OSC0 */
309 case 0x10: /* OSC1 */
310 case 0x14: /* OSC2 */
311 case 0x18: /* OSC3 */
312 case 0x1c: /* OSC4 */
313 /* ??? */
314 break;
315 case 0x20: /* LOCK */
316 if (val == LOCK_VALUE)
317 s->lockval = val;
318 else
319 s->lockval = val & 0x7fff;
320 break;
321 case 0x28: /* CFGDATA1 */
322 /* ??? Need to implement this. */
323 s->cfgdata1 = val;
324 break;
325 case 0x2c: /* CFGDATA2 */
326 /* ??? Need to implement this. */
327 s->cfgdata2 = val;
328 break;
329 case 0x30: /* FLAGSSET */
330 s->flags |= val;
331 break;
332 case 0x34: /* FLAGSCLR */
333 s->flags &= ~val;
334 break;
335 case 0x38: /* NVFLAGSSET */
336 s->nvflags |= val;
337 break;
338 case 0x3c: /* NVFLAGSCLR */
339 s->nvflags &= ~val;
340 break;
341 case 0x40: /* RESETCTL */
342 switch (board_id(s)) {
343 case BOARD_ID_PB926:
344 if (s->lockval == LOCK_VALUE) {
345 s->resetlevel = val;
346 if (val & 0x100) {
347 qemu_system_reset_request();
350 break;
351 case BOARD_ID_PBX:
352 case BOARD_ID_PBA8:
353 if (s->lockval == LOCK_VALUE) {
354 s->resetlevel = val;
355 if (val & 0x04) {
356 qemu_system_reset_request();
359 break;
360 case BOARD_ID_VEXPRESS:
361 case BOARD_ID_EB:
362 default:
363 /* reserved: RAZ/WI */
364 break;
366 break;
367 case 0x44: /* PCICTL */
368 /* nothing to do. */
369 break;
370 case 0x4c: /* FLASH */
371 break;
372 case 0x50: /* CLCD */
373 switch (board_id(s)) {
374 case BOARD_ID_PB926:
375 /* On 926 bits 13:8 are R/O, bits 1:0 control
376 * the mux that defines how to interpret the PL110
377 * graphics format, and other bits are r/w but we
378 * don't implement them to do anything.
380 s->sys_clcd &= 0x3f00;
381 s->sys_clcd |= val & ~0x3f00;
382 qemu_set_irq(s->pl110_mux_ctrl, val & 3);
383 break;
384 case BOARD_ID_EB:
385 /* The EB is the same except that there is no mux since
386 * the EB has a PL111.
388 s->sys_clcd &= 0x3f00;
389 s->sys_clcd |= val & ~0x3f00;
390 break;
391 case BOARD_ID_PBA8:
392 case BOARD_ID_PBX:
393 /* On PBA8 and PBX bit 7 is r/w and all other bits
394 * are either r/o or RAZ/WI.
396 s->sys_clcd &= (1 << 7);
397 s->sys_clcd |= val & ~(1 << 7);
398 break;
399 case BOARD_ID_VEXPRESS:
400 default:
401 /* On VExpress this register is unimplemented and will RAZ/WI */
402 break;
404 break;
405 case 0x54: /* CLCDSER */
406 case 0x64: /* DMAPSR0 */
407 case 0x68: /* DMAPSR1 */
408 case 0x6c: /* DMAPSR2 */
409 case 0x70: /* IOSEL */
410 case 0x74: /* PLDCTL */
411 case 0x80: /* BUSID */
412 case 0x84: /* PROCID0 */
413 case 0x88: /* PROCID1 */
414 case 0x8c: /* OSCRESET0 */
415 case 0x90: /* OSCRESET1 */
416 case 0x94: /* OSCRESET2 */
417 case 0x98: /* OSCRESET3 */
418 case 0x9c: /* OSCRESET4 */
419 break;
420 case 0xa0: /* SYS_CFGDATA */
421 if (board_id(s) != BOARD_ID_VEXPRESS) {
422 goto bad_reg;
424 s->sys_cfgdata = val;
425 return;
426 case 0xa4: /* SYS_CFGCTRL */
427 if (board_id(s) != BOARD_ID_VEXPRESS) {
428 goto bad_reg;
430 /* Undefined bits [19:18] are RAZ/WI, and writing to
431 * the start bit just triggers the action; it always reads
432 * as zero.
434 s->sys_cfgctrl = val & ~((3 << 18) | (1 << 31));
435 if (val & (1 << 31)) {
436 /* Start bit set -- actually do something */
437 unsigned int dcc = extract32(s->sys_cfgctrl, 26, 4);
438 unsigned int function = extract32(s->sys_cfgctrl, 20, 6);
439 unsigned int site = extract32(s->sys_cfgctrl, 16, 2);
440 unsigned int position = extract32(s->sys_cfgctrl, 12, 4);
441 unsigned int device = extract32(s->sys_cfgctrl, 0, 12);
442 s->sys_cfgstat = 1; /* complete */
443 if (s->sys_cfgctrl & (1 << 30)) {
444 if (!vexpress_cfgctrl_write(s, dcc, function, site, position,
445 device, s->sys_cfgdata)) {
446 s->sys_cfgstat |= 2; /* error */
448 } else {
449 uint32_t val;
450 if (!vexpress_cfgctrl_read(s, dcc, function, site, position,
451 device, &val)) {
452 s->sys_cfgstat |= 2; /* error */
453 } else {
454 s->sys_cfgdata = val;
458 s->sys_cfgctrl &= ~(1 << 31);
459 return;
460 case 0xa8: /* SYS_CFGSTAT */
461 if (board_id(s) != BOARD_ID_VEXPRESS) {
462 goto bad_reg;
464 s->sys_cfgstat = val & 3;
465 return;
466 default:
467 bad_reg:
468 qemu_log_mask(LOG_GUEST_ERROR,
469 "arm_sysctl_write: Bad register offset 0x%x\n",
470 (int)offset);
471 return;
475 static const MemoryRegionOps arm_sysctl_ops = {
476 .read = arm_sysctl_read,
477 .write = arm_sysctl_write,
478 .endianness = DEVICE_NATIVE_ENDIAN,
481 static void arm_sysctl_gpio_set(void *opaque, int line, int level)
483 arm_sysctl_state *s = (arm_sysctl_state *)opaque;
484 switch (line) {
485 case ARM_SYSCTL_GPIO_MMC_WPROT:
487 /* For PB926 and EB write-protect is bit 2 of SYS_MCI;
488 * for all later boards it is bit 1.
490 int bit = 2;
491 if ((board_id(s) == BOARD_ID_PB926) || (board_id(s) == BOARD_ID_EB)) {
492 bit = 4;
494 s->sys_mci &= ~bit;
495 if (level) {
496 s->sys_mci |= bit;
498 break;
500 case ARM_SYSCTL_GPIO_MMC_CARDIN:
501 s->sys_mci &= ~1;
502 if (level) {
503 s->sys_mci |= 1;
505 break;
509 static int arm_sysctl_init(SysBusDevice *dev)
511 arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev);
513 memory_region_init_io(&s->iomem, &arm_sysctl_ops, s, "arm-sysctl", 0x1000);
514 sysbus_init_mmio(dev, &s->iomem);
515 qdev_init_gpio_in(&s->busdev.qdev, arm_sysctl_gpio_set, 2);
516 qdev_init_gpio_out(&s->busdev.qdev, &s->pl110_mux_ctrl, 1);
517 return 0;
520 static Property arm_sysctl_properties[] = {
521 DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0),
522 DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0),
523 DEFINE_PROP_END_OF_LIST(),
526 static void arm_sysctl_class_init(ObjectClass *klass, void *data)
528 DeviceClass *dc = DEVICE_CLASS(klass);
529 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
531 k->init = arm_sysctl_init;
532 dc->reset = arm_sysctl_reset;
533 dc->vmsd = &vmstate_arm_sysctl;
534 dc->props = arm_sysctl_properties;
537 static const TypeInfo arm_sysctl_info = {
538 .name = "realview_sysctl",
539 .parent = TYPE_SYS_BUS_DEVICE,
540 .instance_size = sizeof(arm_sysctl_state),
541 .class_init = arm_sysctl_class_init,
544 static void arm_sysctl_register_types(void)
546 type_register_static(&arm_sysctl_info);
549 type_init(arm_sysctl_register_types)