hw/display/pl110.c

   1 /*
   2  * Arm PrimeCell PL110 Color LCD Controller
   3  *
   4  * Copyright (c) 2005-2009 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GNU LGPL
   8  */
   9
  10 #include "hw/sysbus.h"
  11 #include "ui/console.h"
  12 #include "framebuffer.h"
  13 #include "ui/pixel_ops.h"
  14
  15 #define PL110_CR_EN   0x001
  16 #define PL110_CR_BGR  0x100
  17 #define PL110_CR_BEBO 0x200
  18 #define PL110_CR_BEPO 0x400
  19 #define PL110_CR_PWR  0x800
  20
  21 enum pl110_bppmode
  22 {
  23     BPP_1,
  24     BPP_2,
  25     BPP_4,
  26     BPP_8,
  27     BPP_16,
  28     BPP_32,
  29     BPP_16_565, /* PL111 only */
  30     BPP_12      /* PL111 only */
  31 };
  32
  33
  34 /* The Versatile/PB uses a slightly modified PL110 controller.  */
  35 enum pl110_version
  36 {
  37     PL110,
  38     PL110_VERSATILE,
  39     PL111
  40 };
  41
  42 #define TYPE_PL110 "pl110"
  43 #define PL110(obj) OBJECT_CHECK(PL110State, (obj), TYPE_PL110)
  44
  45 typedef struct PL110State {
  46     SysBusDevice parent_obj;
  47
  48     MemoryRegion iomem;
  49     QemuConsole *con;
  50
  51     int version;
  52     uint32_t timing[4];
  53     uint32_t cr;
  54     uint32_t upbase;
  55     uint32_t lpbase;
  56     uint32_t int_status;
  57     uint32_t int_mask;
  58     int cols;
  59     int rows;
  60     enum pl110_bppmode bpp;
  61     int invalidate;
  62     uint32_t mux_ctrl;
  63     uint32_t palette[256];
  64     uint32_t raw_palette[128];
  65     qemu_irq irq;
  66 } PL110State;
  67
  68 static int vmstate_pl110_post_load(void *opaque, int version_id);
  69
  70 static const VMStateDescription vmstate_pl110 = {
  71     .name = "pl110",
  72     .version_id = 2,
  73     .minimum_version_id = 1,
  74     .post_load = vmstate_pl110_post_load,
  75     .fields = (VMStateField[]) {
  76         VMSTATE_INT32(version, PL110State),
  77         VMSTATE_UINT32_ARRAY(timing, PL110State, 4),
  78         VMSTATE_UINT32(cr, PL110State),
  79         VMSTATE_UINT32(upbase, PL110State),
  80         VMSTATE_UINT32(lpbase, PL110State),
  81         VMSTATE_UINT32(int_status, PL110State),
  82         VMSTATE_UINT32(int_mask, PL110State),
  83         VMSTATE_INT32(cols, PL110State),
  84         VMSTATE_INT32(rows, PL110State),
  85         VMSTATE_UINT32(bpp, PL110State),
  86         VMSTATE_INT32(invalidate, PL110State),
  87         VMSTATE_UINT32_ARRAY(palette, PL110State, 256),
  88         VMSTATE_UINT32_ARRAY(raw_palette, PL110State, 128),
  89         VMSTATE_UINT32_V(mux_ctrl, PL110State, 2),
  90         VMSTATE_END_OF_LIST()
  91     }
  92 };
  93
  94 static const unsigned char pl110_id[] =
  95 { 0x10, 0x11, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
  96
  97 static const unsigned char pl111_id[] = {
  98     0x11, 0x11, 0x24, 0x00, 0x0d, 0xf0, 0x05, 0xb1
  99 };
 100
 101
 102 /* Indexed by pl110_version */
 103 static const unsigned char *idregs[] = {
 104     pl110_id,
 105     /* The ARM documentation (DDI0224C) says the CLCDC on the Versatile board
 106      * has a different ID (0x93, 0x10, 0x04, 0x00, ...). However the hardware
 107      * itself has the same ID values as a stock PL110, and guests (in
 108      * particular Linux) rely on this. We emulate what the hardware does,
 109      * rather than what the docs claim it ought to do.
 110      */
 111     pl110_id,
 112     pl111_id
 113 };
 114
 115 #define BITS 8
 116 #include "pl110_template.h"
 117 #define BITS 15
 118 #include "pl110_template.h"
 119 #define BITS 16
 120 #include "pl110_template.h"
 121 #define BITS 24
 122 #include "pl110_template.h"
 123 #define BITS 32
 124 #include "pl110_template.h"
 125
 126 static int pl110_enabled(PL110State *s)
 127 {
 128   return (s->cr & PL110_CR_EN) && (s->cr & PL110_CR_PWR);
 129 }
 130
 131 static void pl110_update_display(void *opaque)
 132 {
 133     PL110State *s = (PL110State *)opaque;
 134     SysBusDevice *sbd;
 135     DisplaySurface *surface = qemu_console_surface(s->con);
 136     drawfn* fntable;
 137     drawfn fn;
 138     int dest_width;
 139     int src_width;
 140     int bpp_offset;
 141     int first;
 142     int last;
 143
 144     if (!pl110_enabled(s)) {
 145         return;
 146     }
 147
 148     sbd = SYS_BUS_DEVICE(s);
 149
 150     switch (surface_bits_per_pixel(surface)) {
 151     case 0:
 152         return;
 153     case 8:
 154         fntable = pl110_draw_fn_8;
 155         dest_width = 1;
 156         break;
 157     case 15:
 158         fntable = pl110_draw_fn_15;
 159         dest_width = 2;
 160         break;
 161     case 16:
 162         fntable = pl110_draw_fn_16;
 163         dest_width = 2;
 164         break;
 165     case 24:
 166         fntable = pl110_draw_fn_24;
 167         dest_width = 3;
 168         break;
 169     case 32:
 170         fntable = pl110_draw_fn_32;
 171         dest_width = 4;
 172         break;
 173     default:
 174         fprintf(stderr, "pl110: Bad color depth\n");
 175         exit(1);
 176     }
 177     if (s->cr & PL110_CR_BGR)
 178         bpp_offset = 0;
 179     else
 180         bpp_offset = 24;
 181
 182     if ((s->version != PL111) && (s->bpp == BPP_16)) {
 183         /* The PL110's native 16 bit mode is 5551; however
 184          * most boards with a PL110 implement an external
 185          * mux which allows bits to be reshuffled to give
 186          * 565 format. The mux is typically controlled by
 187          * an external system register.
 188          * This is controlled by a GPIO input pin
 189          * so boards can wire it up to their register.
 190          *
 191          * The PL111 straightforwardly implements both
 192          * 5551 and 565 under control of the bpp field
 193          * in the LCDControl register.
 194          */
 195         switch (s->mux_ctrl) {
 196         case 3: /* 565 BGR */
 197             bpp_offset = (BPP_16_565 - BPP_16);
 198             break;
 199         case 1: /* 5551 */
 200             break;
 201         case 0: /* 888; also if we have loaded vmstate from an old version */
 202         case 2: /* 565 RGB */
 203         default:
 204             /* treat as 565 but honour BGR bit */
 205             bpp_offset += (BPP_16_565 - BPP_16);
 206             break;
 207         }
 208     }
 209
 210     if (s->cr & PL110_CR_BEBO)
 211         fn = fntable[s->bpp + 8 + bpp_offset];
 212     else if (s->cr & PL110_CR_BEPO)
 213         fn = fntable[s->bpp + 16 + bpp_offset];
 214     else
 215         fn = fntable[s->bpp + bpp_offset];
 216
 217     src_width = s->cols;
 218     switch (s->bpp) {
 219     case BPP_1:
 220         src_width >>= 3;
 221         break;
 222     case BPP_2:
 223         src_width >>= 2;
 224         break;
 225     case BPP_4:
 226         src_width >>= 1;
 227         break;
 228     case BPP_8:
 229         break;
 230     case BPP_16:
 231     case BPP_16_565:
 232     case BPP_12:
 233         src_width <<= 1;
 234         break;
 235     case BPP_32:
 236         src_width <<= 2;
 237         break;
 238     }
 239     dest_width *= s->cols;
 240     first = 0;
 241     framebuffer_update_display(surface, sysbus_address_space(sbd),
 242                                s->upbase, s->cols, s->rows,
 243                                src_width, dest_width, 0,
 244                                s->invalidate,
 245                                fn, s->palette,
 246                                &first, &last);
 247     if (first >= 0) {
 248         dpy_gfx_update(s->con, 0, first, s->cols, last - first + 1);
 249     }
 250     s->invalidate = 0;
 251 }
 252
 253 static void pl110_invalidate_display(void * opaque)
 254 {
 255     PL110State *s = (PL110State *)opaque;
 256     s->invalidate = 1;
 257     if (pl110_enabled(s)) {
 258         qemu_console_resize(s->con, s->cols, s->rows);
 259     }
 260 }
 261
 262 static void pl110_update_palette(PL110State *s, int n)
 263 {
 264     DisplaySurface *surface = qemu_console_surface(s->con);
 265     int i;
 266     uint32_t raw;
 267     unsigned int r, g, b;
 268
 269     raw = s->raw_palette[n];
 270     n <<= 1;
 271     for (i = 0; i < 2; i++) {
 272         r = (raw & 0x1f) << 3;
 273         raw >>= 5;
 274         g = (raw & 0x1f) << 3;
 275         raw >>= 5;
 276         b = (raw & 0x1f) << 3;
 277         /* The I bit is ignored.  */
 278         raw >>= 6;
 279         switch (surface_bits_per_pixel(surface)) {
 280         case 8:
 281             s->palette[n] = rgb_to_pixel8(r, g, b);
 282             break;
 283         case 15:
 284             s->palette[n] = rgb_to_pixel15(r, g, b);
 285             break;
 286         case 16:
 287             s->palette[n] = rgb_to_pixel16(r, g, b);
 288             break;
 289         case 24:
 290         case 32:
 291             s->palette[n] = rgb_to_pixel32(r, g, b);
 292             break;
 293         }
 294         n++;
 295     }
 296 }
 297
 298 static void pl110_resize(PL110State *s, int width, int height)
 299 {
 300     if (width != s->cols || height != s->rows) {
 301         if (pl110_enabled(s)) {
 302             qemu_console_resize(s->con, width, height);
 303         }
 304     }
 305     s->cols = width;
 306     s->rows = height;
 307 }
 308
 309 /* Update interrupts.  */
 310 static void pl110_update(PL110State *s)
 311 {
 312   /* TODO: Implement interrupts.  */
 313 }
 314
 315 static uint64_t pl110_read(void *opaque, hwaddr offset,
 316                            unsigned size)
 317 {
 318     PL110State *s = (PL110State *)opaque;
 319
 320     if (offset >= 0xfe0 && offset < 0x1000) {
 321         return idregs[s->version][(offset - 0xfe0) >> 2];
 322     }
 323     if (offset >= 0x200 && offset < 0x400) {
 324         return s->raw_palette[(offset - 0x200) >> 2];
 325     }
 326     switch (offset >> 2) {
 327     case 0: /* LCDTiming0 */
 328         return s->timing[0];
 329     case 1: /* LCDTiming1 */
 330         return s->timing[1];
 331     case 2: /* LCDTiming2 */
 332         return s->timing[2];
 333     case 3: /* LCDTiming3 */
 334         return s->timing[3];
 335     case 4: /* LCDUPBASE */
 336         return s->upbase;
 337     case 5: /* LCDLPBASE */
 338         return s->lpbase;
 339     case 6: /* LCDIMSC */
 340         if (s->version != PL110) {
 341             return s->cr;
 342         }
 343         return s->int_mask;
 344     case 7: /* LCDControl */
 345         if (s->version != PL110) {
 346             return s->int_mask;
 347         }
 348         return s->cr;
 349     case 8: /* LCDRIS */
 350         return s->int_status;
 351     case 9: /* LCDMIS */
 352         return s->int_status & s->int_mask;
 353     case 11: /* LCDUPCURR */
 354         /* TODO: Implement vertical refresh.  */
 355         return s->upbase;
 356     case 12: /* LCDLPCURR */
 357         return s->lpbase;
 358     default:
 359         qemu_log_mask(LOG_GUEST_ERROR,
 360                       "pl110_read: Bad offset %x\n", (int)offset);
 361         return 0;
 362     }
 363 }
 364
 365 static void pl110_write(void *opaque, hwaddr offset,
 366                         uint64_t val, unsigned size)
 367 {
 368     PL110State *s = (PL110State *)opaque;
 369     int n;
 370
 371     /* For simplicity invalidate the display whenever a control register
 372        is written to.  */
 373     s->invalidate = 1;
 374     if (offset >= 0x200 && offset < 0x400) {
 375         /* Palette.  */
 376         n = (offset - 0x200) >> 2;
 377         s->raw_palette[(offset - 0x200) >> 2] = val;
 378         pl110_update_palette(s, n);
 379         return;
 380     }
 381     switch (offset >> 2) {
 382     case 0: /* LCDTiming0 */
 383         s->timing[0] = val;
 384         n = ((val & 0xfc) + 4) * 4;
 385         pl110_resize(s, n, s->rows);
 386         break;
 387     case 1: /* LCDTiming1 */
 388         s->timing[1] = val;
 389         n = (val & 0x3ff) + 1;
 390         pl110_resize(s, s->cols, n);
 391         break;
 392     case 2: /* LCDTiming2 */
 393         s->timing[2] = val;
 394         break;
 395     case 3: /* LCDTiming3 */
 396         s->timing[3] = val;
 397         break;
 398     case 4: /* LCDUPBASE */
 399         s->upbase = val;
 400         break;
 401     case 5: /* LCDLPBASE */
 402         s->lpbase = val;
 403         break;
 404     case 6: /* LCDIMSC */
 405         if (s->version != PL110) {
 406             goto control;
 407         }
 408     imsc:
 409         s->int_mask = val;
 410         pl110_update(s);
 411         break;
 412     case 7: /* LCDControl */
 413         if (s->version != PL110) {
 414             goto imsc;
 415         }
 416     control:
 417         s->cr = val;
 418         s->bpp = (val >> 1) & 7;
 419         if (pl110_enabled(s)) {
 420             qemu_console_resize(s->con, s->cols, s->rows);
 421         }
 422         break;
 423     case 10: /* LCDICR */
 424         s->int_status &= ~val;
 425         pl110_update(s);
 426         break;
 427     default:
 428         qemu_log_mask(LOG_GUEST_ERROR,
 429                       "pl110_write: Bad offset %x\n", (int)offset);
 430     }
 431 }
 432
 433 static const MemoryRegionOps pl110_ops = {
 434     .read = pl110_read,
 435     .write = pl110_write,
 436     .endianness = DEVICE_NATIVE_ENDIAN,
 437 };
 438
 439 static void pl110_mux_ctrl_set(void *opaque, int line, int level)
 440 {
 441     PL110State *s = (PL110State *)opaque;
 442     s->mux_ctrl = level;
 443 }
 444
 445 static int vmstate_pl110_post_load(void *opaque, int version_id)
 446 {
 447     PL110State *s = opaque;
 448     /* Make sure we redraw, and at the right size */
 449     pl110_invalidate_display(s);
 450     return 0;
 451 }
 452
 453 static const GraphicHwOps pl110_gfx_ops = {
 454     .invalidate  = pl110_invalidate_display,
 455     .gfx_update  = pl110_update_display,
 456 };
 457
 458 static int pl110_initfn(SysBusDevice *sbd)
 459 {
 460     DeviceState *dev = DEVICE(sbd);
 461     PL110State *s = PL110(dev);
 462
 463     memory_region_init_io(&s->iomem, OBJECT(s), &pl110_ops, s, "pl110", 0x1000);
 464     sysbus_init_mmio(sbd, &s->iomem);
 465     sysbus_init_irq(sbd, &s->irq);
 466     qdev_init_gpio_in(dev, pl110_mux_ctrl_set, 1);
 467     s->con = graphic_console_init(dev, 0, &pl110_gfx_ops, s);
 468     return 0;
 469 }
 470
 471 static void pl110_init(Object *obj)
 472 {
 473     PL110State *s = PL110(obj);
 474
 475     s->version = PL110;
 476 }
 477
 478 static void pl110_versatile_init(Object *obj)
 479 {
 480     PL110State *s = PL110(obj);
 481
 482     s->version = PL110_VERSATILE;
 483 }
 484
 485 static void pl111_init(Object *obj)
 486 {
 487     PL110State *s = PL110(obj);
 488
 489     s->version = PL111;
 490 }
 491
 492 static void pl110_class_init(ObjectClass *klass, void *data)
 493 {
 494     DeviceClass *dc = DEVICE_CLASS(klass);
 495     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 496
 497     k->init = pl110_initfn;
 498     set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
 499     dc->vmsd = &vmstate_pl110;
 500 }
 501
 502 static const TypeInfo pl110_info = {
 503     .name          = TYPE_PL110,
 504     .parent        = TYPE_SYS_BUS_DEVICE,
 505     .instance_size = sizeof(PL110State),
 506     .instance_init = pl110_init,
 507     .class_init    = pl110_class_init,
 508 };
 509
 510 static const TypeInfo pl110_versatile_info = {
 511     .name          = "pl110_versatile",
 512     .parent        = TYPE_PL110,
 513     .instance_init = pl110_versatile_init,
 514 };
 515
 516 static const TypeInfo pl111_info = {
 517     .name          = "pl111",
 518     .parent        = TYPE_PL110,
 519     .instance_init = pl111_init,
 520 };
 521
 522 static void pl110_register_types(void)
 523 {
 524     type_register_static(&pl110_info);
 525     type_register_static(&pl110_versatile_info);
 526     type_register_static(&pl111_info);
 527 }
 528
 529 type_init(pl110_register_types)