4 * Copyright (c) 2005-2007 CodeSourcery, LLC
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "qemu/main-loop.h"
23 #include "exec/helper-proto.h"
24 #include "internals.h"
25 #include "exec/exec-all.h"
26 #include "exec/cpu_ldst.h"
28 #define SIGNBIT (uint32_t)0x80000000
29 #define SIGNBIT64 ((uint64_t)1 << 63)
31 static void QEMU_NORETURN
32 raise_exception(CPUARMState
*env
, uint32_t excp
,
33 uint32_t syndrome
, uint32_t target_el
)
35 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
37 assert(!excp_is_internal(excp
));
38 cs
->exception_index
= excp
;
39 env
->exception
.syndrome
= syndrome
;
40 env
->exception
.target_el
= target_el
;
44 static int exception_target_el(CPUARMState
*env
)
46 int target_el
= MAX(1, arm_current_el(env
));
48 /* No such thing as secure EL1 if EL3 is aarch32, so update the target EL
49 * to EL3 in this case.
51 if (arm_is_secure(env
) && !arm_el_is_aa64(env
, 3) && target_el
== 1) {
58 uint32_t HELPER(neon_tbl
)(CPUARMState
*env
, uint32_t ireg
, uint32_t def
,
59 uint32_t rn
, uint32_t maxindex
)
66 table
= (uint64_t *)&env
->vfp
.regs
[rn
];
68 for (shift
= 0; shift
< 32; shift
+= 8) {
69 index
= (ireg
>> shift
) & 0xff;
70 if (index
< maxindex
) {
71 tmp
= (table
[index
>> 3] >> ((index
& 7) << 3)) & 0xff;
74 val
|= def
& (0xff << shift
);
80 #if !defined(CONFIG_USER_ONLY)
82 static inline uint32_t merge_syn_data_abort(uint32_t template_syn
,
83 unsigned int target_el
,
85 bool s1ptw
, bool is_write
,
90 /* ISV is only set for data aborts routed to EL2 and
91 * never for stage-1 page table walks faulting on stage 2.
93 * Furthermore, ISV is only set for certain kinds of load/stores.
94 * If the template syndrome does not have ISV set, we should leave
97 * See ARMv8 specs, D7-1974:
98 * ISS encoding for an exception from a Data Abort, the
101 if (!(template_syn
& ARM_EL_ISV
) || target_el
!= 2 || s1ptw
) {
102 syn
= syn_data_abort_no_iss(same_el
,
103 0, 0, s1ptw
, is_write
, fsc
);
105 /* Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template
106 * syndrome created at translation time.
107 * Now we create the runtime syndrome with the remaining fields.
109 syn
= syn_data_abort_with_iss(same_el
,
111 0, 0, s1ptw
, is_write
, fsc
,
113 /* Merge the runtime syndrome with the template syndrome. */
119 /* try to fill the TLB and return an exception if error. If retaddr is
120 * NULL, it means that the function was called in C code (i.e. not
121 * from generated code or from helper.c)
123 void tlb_fill(CPUState
*cs
, target_ulong addr
, MMUAccessType access_type
,
124 int mmu_idx
, uintptr_t retaddr
)
128 ARMMMUFaultInfo fi
= {};
130 ret
= arm_tlb_fill(cs
, addr
, access_type
, mmu_idx
, &fsr
, &fi
);
132 ARMCPU
*cpu
= ARM_CPU(cs
);
133 CPUARMState
*env
= &cpu
->env
;
134 uint32_t syn
, exc
, fsc
;
135 unsigned int target_el
;
139 /* now we have a real cpu fault */
140 cpu_restore_state(cs
, retaddr
);
143 target_el
= exception_target_el(env
);
146 env
->cp15
.hpfar_el2
= extract64(fi
.s2addr
, 12, 47) << 4;
148 same_el
= arm_current_el(env
) == target_el
;
150 if (fsr
& (1 << 9)) {
151 /* LPAE format fault status register : bottom 6 bits are
152 * status code in the same form as needed for syndrome
154 fsc
= extract32(fsr
, 0, 6);
156 /* Short format FSR : this fault will never actually be reported
157 * to an EL that uses a syndrome register. Check that here,
158 * and use a (currently) reserved FSR code in case the constructed
159 * syndrome does leak into the guest somehow.
161 assert(target_el
!= 2 && !arm_el_is_aa64(env
, target_el
));
165 /* For insn and data aborts we assume there is no instruction syndrome
166 * information; this is always true for exceptions reported to EL1.
168 if (access_type
== MMU_INST_FETCH
) {
169 syn
= syn_insn_abort(same_el
, 0, fi
.s1ptw
, fsc
);
170 exc
= EXCP_PREFETCH_ABORT
;
172 syn
= merge_syn_data_abort(env
->exception
.syndrome
, target_el
,
174 access_type
== MMU_DATA_STORE
, fsc
);
175 if (access_type
== MMU_DATA_STORE
176 && arm_feature(env
, ARM_FEATURE_V6
)) {
179 exc
= EXCP_DATA_ABORT
;
182 env
->exception
.vaddress
= addr
;
183 env
->exception
.fsr
= fsr
;
184 raise_exception(env
, exc
, syn
, target_el
);
188 /* Raise a data fault alignment exception for the specified virtual address */
189 void arm_cpu_do_unaligned_access(CPUState
*cs
, vaddr vaddr
,
190 MMUAccessType access_type
,
191 int mmu_idx
, uintptr_t retaddr
)
193 ARMCPU
*cpu
= ARM_CPU(cs
);
194 CPUARMState
*env
= &cpu
->env
;
198 ARMMMUIdx arm_mmu_idx
= core_to_arm_mmu_idx(env
, mmu_idx
);
201 /* now we have a real cpu fault */
202 cpu_restore_state(cs
, retaddr
);
205 target_el
= exception_target_el(env
);
206 same_el
= (arm_current_el(env
) == target_el
);
208 env
->exception
.vaddress
= vaddr
;
210 /* the DFSR for an alignment fault depends on whether we're using
211 * the LPAE long descriptor format, or the short descriptor format
213 if (arm_s1_regime_using_lpae_format(env
, arm_mmu_idx
)) {
214 env
->exception
.fsr
= (1 << 9) | 0x21;
216 env
->exception
.fsr
= 0x1;
219 if (access_type
== MMU_DATA_STORE
&& arm_feature(env
, ARM_FEATURE_V6
)) {
220 env
->exception
.fsr
|= (1 << 11);
223 syn
= merge_syn_data_abort(env
->exception
.syndrome
, target_el
,
224 same_el
, 0, access_type
== MMU_DATA_STORE
,
226 raise_exception(env
, EXCP_DATA_ABORT
, syn
, target_el
);
229 #endif /* !defined(CONFIG_USER_ONLY) */
231 uint32_t HELPER(add_setq
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
233 uint32_t res
= a
+ b
;
234 if (((res
^ a
) & SIGNBIT
) && !((a
^ b
) & SIGNBIT
))
239 uint32_t HELPER(add_saturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
241 uint32_t res
= a
+ b
;
242 if (((res
^ a
) & SIGNBIT
) && !((a
^ b
) & SIGNBIT
)) {
244 res
= ~(((int32_t)a
>> 31) ^ SIGNBIT
);
249 uint32_t HELPER(sub_saturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
251 uint32_t res
= a
- b
;
252 if (((res
^ a
) & SIGNBIT
) && ((a
^ b
) & SIGNBIT
)) {
254 res
= ~(((int32_t)a
>> 31) ^ SIGNBIT
);
259 uint32_t HELPER(double_saturate
)(CPUARMState
*env
, int32_t val
)
262 if (val
>= 0x40000000) {
265 } else if (val
<= (int32_t)0xc0000000) {
274 uint32_t HELPER(add_usaturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
276 uint32_t res
= a
+ b
;
284 uint32_t HELPER(sub_usaturate
)(CPUARMState
*env
, uint32_t a
, uint32_t b
)
286 uint32_t res
= a
- b
;
294 /* Signed saturation. */
295 static inline uint32_t do_ssat(CPUARMState
*env
, int32_t val
, int shift
)
301 mask
= (1u << shift
) - 1;
305 } else if (top
< -1) {
312 /* Unsigned saturation. */
313 static inline uint32_t do_usat(CPUARMState
*env
, int32_t val
, int shift
)
317 max
= (1u << shift
) - 1;
321 } else if (val
> max
) {
328 /* Signed saturate. */
329 uint32_t HELPER(ssat
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
331 return do_ssat(env
, x
, shift
);
334 /* Dual halfword signed saturate. */
335 uint32_t HELPER(ssat16
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
339 res
= (uint16_t)do_ssat(env
, (int16_t)x
, shift
);
340 res
|= do_ssat(env
, ((int32_t)x
) >> 16, shift
) << 16;
344 /* Unsigned saturate. */
345 uint32_t HELPER(usat
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
347 return do_usat(env
, x
, shift
);
350 /* Dual halfword unsigned saturate. */
351 uint32_t HELPER(usat16
)(CPUARMState
*env
, uint32_t x
, uint32_t shift
)
355 res
= (uint16_t)do_usat(env
, (int16_t)x
, shift
);
356 res
|= do_usat(env
, ((int32_t)x
) >> 16, shift
) << 16;
360 void HELPER(setend
)(CPUARMState
*env
)
362 env
->uncached_cpsr
^= CPSR_E
;
365 /* Function checks whether WFx (WFI/WFE) instructions are set up to be trapped.
366 * The function returns the target EL (1-3) if the instruction is to be trapped;
367 * otherwise it returns 0 indicating it is not trapped.
369 static inline int check_wfx_trap(CPUARMState
*env
, bool is_wfe
)
371 int cur_el
= arm_current_el(env
);
374 /* If we are currently in EL0 then we need to check if SCTLR is set up for
375 * WFx instructions being trapped to EL1. These trap bits don't exist in v7.
377 if (cur_el
< 1 && arm_feature(env
, ARM_FEATURE_V8
)) {
380 mask
= is_wfe
? SCTLR_nTWE
: SCTLR_nTWI
;
381 if (arm_is_secure_below_el3(env
) && !arm_el_is_aa64(env
, 3)) {
382 /* Secure EL0 and Secure PL1 is at EL3 */
388 if (!(env
->cp15
.sctlr_el
[target_el
] & mask
)) {
393 /* We are not trapping to EL1; trap to EL2 if HCR_EL2 requires it
394 * No need for ARM_FEATURE check as if HCR_EL2 doesn't exist the
395 * bits will be zero indicating no trap.
397 if (cur_el
< 2 && !arm_is_secure(env
)) {
398 mask
= (is_wfe
) ? HCR_TWE
: HCR_TWI
;
399 if (env
->cp15
.hcr_el2
& mask
) {
404 /* We are not trapping to EL1 or EL2; trap to EL3 if SCR_EL3 requires it */
406 mask
= (is_wfe
) ? SCR_TWE
: SCR_TWI
;
407 if (env
->cp15
.scr_el3
& mask
) {
415 void HELPER(wfi
)(CPUARMState
*env
)
417 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
418 int target_el
= check_wfx_trap(env
, false);
420 if (cpu_has_work(cs
)) {
421 /* Don't bother to go into our "low power state" if
422 * we would just wake up immediately.
429 raise_exception(env
, EXCP_UDEF
, syn_wfx(1, 0xe, 0), target_el
);
432 cs
->exception_index
= EXCP_HLT
;
437 void QEMU_NORETURN
HELPER(wfe
)(CPUARMState
*env
)
439 /* This is a hint instruction that is semantically different
440 * from YIELD even though we currently implement it identically.
441 * Don't actually halt the CPU, just yield back to top
442 * level loop. This is not going into a "low power state"
443 * (ie halting until some event occurs), so we never take
444 * a configurable trap to a different exception level.
449 void QEMU_NORETURN
HELPER(yield
)(CPUARMState
*env
)
451 ARMCPU
*cpu
= arm_env_get_cpu(env
);
452 CPUState
*cs
= CPU(cpu
);
454 /* When running in MTTCG we don't generate jumps to the yield and
455 * WFE helpers as it won't affect the scheduling of other vCPUs.
456 * If we wanted to more completely model WFE/SEV so we don't busy
457 * spin unnecessarily we would need to do something more involved.
459 g_assert(!parallel_cpus
);
461 /* This is a non-trappable hint instruction that generally indicates
462 * that the guest is currently busy-looping. Yield control back to the
463 * top level loop so that a more deserving VCPU has a chance to run.
465 cs
->exception_index
= EXCP_YIELD
;
469 /* Raise an internal-to-QEMU exception. This is limited to only
470 * those EXCP values which are special cases for QEMU to interrupt
471 * execution and not to be used for exceptions which are passed to
472 * the guest (those must all have syndrome information and thus should
473 * use exception_with_syndrome).
475 void QEMU_NORETURN
HELPER(exception_internal
)(CPUARMState
*env
, uint32_t excp
)
477 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
479 assert(excp_is_internal(excp
));
480 cs
->exception_index
= excp
;
484 /* Raise an exception with the specified syndrome register value */
486 HELPER(exception_with_syndrome
)(CPUARMState
*env
, uint32_t excp
,
487 uint32_t syndrome
, uint32_t target_el
)
489 raise_exception(env
, excp
, syndrome
, target_el
);
492 uint32_t HELPER(cpsr_read
)(CPUARMState
*env
)
494 return cpsr_read(env
) & ~(CPSR_EXEC
| CPSR_RESERVED
);
497 void HELPER(cpsr_write
)(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
499 cpsr_write(env
, val
, mask
, CPSRWriteByInstr
);
502 /* Write the CPSR for a 32-bit exception return */
503 void HELPER(cpsr_write_eret
)(CPUARMState
*env
, uint32_t val
)
505 cpsr_write(env
, val
, CPSR_ERET_MASK
, CPSRWriteExceptionReturn
);
507 /* Generated code has already stored the new PC value, but
508 * without masking out its low bits, because which bits need
509 * masking depends on whether we're returning to Thumb or ARM
510 * state. Do the masking now.
512 env
->regs
[15] &= (env
->thumb
? ~1 : ~3);
514 qemu_mutex_lock_iothread();
515 arm_call_el_change_hook(arm_env_get_cpu(env
));
516 qemu_mutex_unlock_iothread();
519 /* Access to user mode registers from privileged modes. */
520 uint32_t HELPER(get_user_reg
)(CPUARMState
*env
, uint32_t regno
)
525 val
= env
->banked_r13
[BANK_USRSYS
];
526 } else if (regno
== 14) {
527 val
= env
->banked_r14
[BANK_USRSYS
];
528 } else if (regno
>= 8
529 && (env
->uncached_cpsr
& 0x1f) == ARM_CPU_MODE_FIQ
) {
530 val
= env
->usr_regs
[regno
- 8];
532 val
= env
->regs
[regno
];
537 void HELPER(set_user_reg
)(CPUARMState
*env
, uint32_t regno
, uint32_t val
)
540 env
->banked_r13
[BANK_USRSYS
] = val
;
541 } else if (regno
== 14) {
542 env
->banked_r14
[BANK_USRSYS
] = val
;
543 } else if (regno
>= 8
544 && (env
->uncached_cpsr
& 0x1f) == ARM_CPU_MODE_FIQ
) {
545 env
->usr_regs
[regno
- 8] = val
;
547 env
->regs
[regno
] = val
;
551 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
553 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
556 env
->banked_r13
[bank_number(mode
)] = val
;
560 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
562 if ((env
->uncached_cpsr
& CPSR_M
) == ARM_CPU_MODE_SYS
) {
563 /* SRS instruction is UNPREDICTABLE from System mode; we UNDEF.
564 * Other UNPREDICTABLE and UNDEF cases were caught at translate time.
566 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
567 exception_target_el(env
));
570 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
571 return env
->regs
[13];
573 return env
->banked_r13
[bank_number(mode
)];
577 static void msr_mrs_banked_exc_checks(CPUARMState
*env
, uint32_t tgtmode
,
580 /* Raise an exception if the requested access is one of the UNPREDICTABLE
581 * cases; otherwise return. This broadly corresponds to the pseudocode
582 * BankedRegisterAccessValid() and SPSRAccessValid(),
583 * except that we have already handled some cases at translate time.
585 int curmode
= env
->uncached_cpsr
& CPSR_M
;
587 if (curmode
== tgtmode
) {
591 if (tgtmode
== ARM_CPU_MODE_USR
) {
594 if (curmode
!= ARM_CPU_MODE_FIQ
) {
599 if (curmode
== ARM_CPU_MODE_SYS
) {
604 if (curmode
== ARM_CPU_MODE_HYP
|| curmode
== ARM_CPU_MODE_SYS
) {
613 if (tgtmode
== ARM_CPU_MODE_HYP
) {
615 case 17: /* ELR_Hyp */
616 if (curmode
!= ARM_CPU_MODE_HYP
&& curmode
!= ARM_CPU_MODE_MON
) {
621 if (curmode
!= ARM_CPU_MODE_MON
) {
631 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
632 exception_target_el(env
));
635 void HELPER(msr_banked
)(CPUARMState
*env
, uint32_t value
, uint32_t tgtmode
,
638 msr_mrs_banked_exc_checks(env
, tgtmode
, regno
);
642 env
->banked_spsr
[bank_number(tgtmode
)] = value
;
644 case 17: /* ELR_Hyp */
645 env
->elr_el
[2] = value
;
648 env
->banked_r13
[bank_number(tgtmode
)] = value
;
651 env
->banked_r14
[bank_number(tgtmode
)] = value
;
655 case ARM_CPU_MODE_USR
:
656 env
->usr_regs
[regno
- 8] = value
;
658 case ARM_CPU_MODE_FIQ
:
659 env
->fiq_regs
[regno
- 8] = value
;
662 g_assert_not_reached();
666 g_assert_not_reached();
670 uint32_t HELPER(mrs_banked
)(CPUARMState
*env
, uint32_t tgtmode
, uint32_t regno
)
672 msr_mrs_banked_exc_checks(env
, tgtmode
, regno
);
676 return env
->banked_spsr
[bank_number(tgtmode
)];
677 case 17: /* ELR_Hyp */
678 return env
->elr_el
[2];
680 return env
->banked_r13
[bank_number(tgtmode
)];
682 return env
->banked_r14
[bank_number(tgtmode
)];
685 case ARM_CPU_MODE_USR
:
686 return env
->usr_regs
[regno
- 8];
687 case ARM_CPU_MODE_FIQ
:
688 return env
->fiq_regs
[regno
- 8];
690 g_assert_not_reached();
693 g_assert_not_reached();
697 void HELPER(access_check_cp_reg
)(CPUARMState
*env
, void *rip
, uint32_t syndrome
,
700 const ARMCPRegInfo
*ri
= rip
;
703 if (arm_feature(env
, ARM_FEATURE_XSCALE
) && ri
->cp
< 14
704 && extract32(env
->cp15
.c15_cpar
, ri
->cp
, 1) == 0) {
705 raise_exception(env
, EXCP_UDEF
, syndrome
, exception_target_el(env
));
712 switch (ri
->accessfn(env
, ri
, isread
)) {
716 target_el
= exception_target_el(env
);
718 case CP_ACCESS_TRAP_EL2
:
719 /* Requesting a trap to EL2 when we're in EL3 or S-EL0/1 is
720 * a bug in the access function.
722 assert(!arm_is_secure(env
) && arm_current_el(env
) != 3);
725 case CP_ACCESS_TRAP_EL3
:
728 case CP_ACCESS_TRAP_UNCATEGORIZED
:
729 target_el
= exception_target_el(env
);
730 syndrome
= syn_uncategorized();
732 case CP_ACCESS_TRAP_UNCATEGORIZED_EL2
:
734 syndrome
= syn_uncategorized();
736 case CP_ACCESS_TRAP_UNCATEGORIZED_EL3
:
738 syndrome
= syn_uncategorized();
740 case CP_ACCESS_TRAP_FP_EL2
:
742 /* Since we are an implementation that takes exceptions on a trapped
743 * conditional insn only if the insn has passed its condition code
744 * check, we take the IMPDEF choice to always report CV=1 COND=0xe
745 * (which is also the required value for AArch64 traps).
747 syndrome
= syn_fp_access_trap(1, 0xe, false);
749 case CP_ACCESS_TRAP_FP_EL3
:
751 syndrome
= syn_fp_access_trap(1, 0xe, false);
754 g_assert_not_reached();
757 raise_exception(env
, EXCP_UDEF
, syndrome
, target_el
);
760 void HELPER(set_cp_reg
)(CPUARMState
*env
, void *rip
, uint32_t value
)
762 const ARMCPRegInfo
*ri
= rip
;
764 if (ri
->type
& ARM_CP_IO
) {
765 qemu_mutex_lock_iothread();
766 ri
->writefn(env
, ri
, value
);
767 qemu_mutex_unlock_iothread();
769 ri
->writefn(env
, ri
, value
);
773 uint32_t HELPER(get_cp_reg
)(CPUARMState
*env
, void *rip
)
775 const ARMCPRegInfo
*ri
= rip
;
778 if (ri
->type
& ARM_CP_IO
) {
779 qemu_mutex_lock_iothread();
780 res
= ri
->readfn(env
, ri
);
781 qemu_mutex_unlock_iothread();
783 res
= ri
->readfn(env
, ri
);
789 void HELPER(set_cp_reg64
)(CPUARMState
*env
, void *rip
, uint64_t value
)
791 const ARMCPRegInfo
*ri
= rip
;
793 if (ri
->type
& ARM_CP_IO
) {
794 qemu_mutex_lock_iothread();
795 ri
->writefn(env
, ri
, value
);
796 qemu_mutex_unlock_iothread();
798 ri
->writefn(env
, ri
, value
);
802 uint64_t HELPER(get_cp_reg64
)(CPUARMState
*env
, void *rip
)
804 const ARMCPRegInfo
*ri
= rip
;
807 if (ri
->type
& ARM_CP_IO
) {
808 qemu_mutex_lock_iothread();
809 res
= ri
->readfn(env
, ri
);
810 qemu_mutex_unlock_iothread();
812 res
= ri
->readfn(env
, ri
);
818 void HELPER(msr_i_pstate
)(CPUARMState
*env
, uint32_t op
, uint32_t imm
)
820 /* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set.
821 * Note that SPSel is never OK from EL0; we rely on handle_msr_i()
822 * to catch that case at translate time.
824 if (arm_current_el(env
) == 0 && !(env
->cp15
.sctlr_el
[1] & SCTLR_UMA
)) {
825 uint32_t syndrome
= syn_aa64_sysregtrap(0, extract32(op
, 0, 3),
826 extract32(op
, 3, 3), 4,
828 raise_exception(env
, EXCP_UDEF
, syndrome
, exception_target_el(env
));
832 case 0x05: /* SPSel */
833 update_spsel(env
, imm
);
835 case 0x1e: /* DAIFSet */
836 env
->daif
|= (imm
<< 6) & PSTATE_DAIF
;
838 case 0x1f: /* DAIFClear */
839 env
->daif
&= ~((imm
<< 6) & PSTATE_DAIF
);
842 g_assert_not_reached();
846 void HELPER(clear_pstate_ss
)(CPUARMState
*env
)
848 env
->pstate
&= ~PSTATE_SS
;
851 void HELPER(pre_hvc
)(CPUARMState
*env
)
853 ARMCPU
*cpu
= arm_env_get_cpu(env
);
854 int cur_el
= arm_current_el(env
);
855 /* FIXME: Use actual secure state. */
859 if (arm_is_psci_call(cpu
, EXCP_HVC
)) {
860 /* If PSCI is enabled and this looks like a valid PSCI call then
861 * that overrides the architecturally mandated HVC behaviour.
866 if (!arm_feature(env
, ARM_FEATURE_EL2
)) {
867 /* If EL2 doesn't exist, HVC always UNDEFs */
869 } else if (arm_feature(env
, ARM_FEATURE_EL3
)) {
870 /* EL3.HCE has priority over EL2.HCD. */
871 undef
= !(env
->cp15
.scr_el3
& SCR_HCE
);
873 undef
= env
->cp15
.hcr_el2
& HCR_HCD
;
876 /* In ARMv7 and ARMv8/AArch32, HVC is undef in secure state.
877 * For ARMv8/AArch64, HVC is allowed in EL3.
878 * Note that we've already trapped HVC from EL0 at translation
881 if (secure
&& (!is_a64(env
) || cur_el
== 1)) {
886 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
887 exception_target_el(env
));
891 void HELPER(pre_smc
)(CPUARMState
*env
, uint32_t syndrome
)
893 ARMCPU
*cpu
= arm_env_get_cpu(env
);
894 int cur_el
= arm_current_el(env
);
895 bool secure
= arm_is_secure(env
);
896 bool smd
= env
->cp15
.scr_el3
& SCR_SMD
;
897 /* On ARMv8 with EL3 AArch64, SMD applies to both S and NS state.
898 * On ARMv8 with EL3 AArch32, or ARMv7 with the Virtualization
899 * extensions, SMD only applies to NS state.
900 * On ARMv7 without the Virtualization extensions, the SMD bit
901 * doesn't exist, but we forbid the guest to set it to 1 in scr_write(),
902 * so we need not special case this here.
904 bool undef
= arm_feature(env
, ARM_FEATURE_AARCH64
) ? smd
: smd
&& !secure
;
906 if (arm_is_psci_call(cpu
, EXCP_SMC
)) {
907 /* If PSCI is enabled and this looks like a valid PSCI call then
908 * that overrides the architecturally mandated SMC behaviour.
913 if (!arm_feature(env
, ARM_FEATURE_EL3
)) {
914 /* If we have no EL3 then SMC always UNDEFs */
916 } else if (!secure
&& cur_el
== 1 && (env
->cp15
.hcr_el2
& HCR_TSC
)) {
917 /* In NS EL1, HCR controlled routing to EL2 has priority over SMD. */
918 raise_exception(env
, EXCP_HYP_TRAP
, syndrome
, 2);
922 raise_exception(env
, EXCP_UDEF
, syn_uncategorized(),
923 exception_target_el(env
));
927 static int el_from_spsr(uint32_t spsr
)
929 /* Return the exception level that this SPSR is requesting a return to,
930 * or -1 if it is invalid (an illegal return)
932 if (spsr
& PSTATE_nRW
) {
933 switch (spsr
& CPSR_M
) {
934 case ARM_CPU_MODE_USR
:
936 case ARM_CPU_MODE_HYP
:
938 case ARM_CPU_MODE_FIQ
:
939 case ARM_CPU_MODE_IRQ
:
940 case ARM_CPU_MODE_SVC
:
941 case ARM_CPU_MODE_ABT
:
942 case ARM_CPU_MODE_UND
:
943 case ARM_CPU_MODE_SYS
:
945 case ARM_CPU_MODE_MON
:
946 /* Returning to Mon from AArch64 is never possible,
947 * so this is an illegal return.
953 if (extract32(spsr
, 1, 1)) {
954 /* Return with reserved M[1] bit set */
957 if (extract32(spsr
, 0, 4) == 1) {
958 /* return to EL0 with M[0] bit set */
961 return extract32(spsr
, 2, 2);
965 void HELPER(exception_return
)(CPUARMState
*env
)
967 int cur_el
= arm_current_el(env
);
968 unsigned int spsr_idx
= aarch64_banked_spsr_index(cur_el
);
969 uint32_t spsr
= env
->banked_spsr
[spsr_idx
];
971 bool return_to_aa64
= (spsr
& PSTATE_nRW
) == 0;
973 aarch64_save_sp(env
, cur_el
);
975 env
->exclusive_addr
= -1;
977 /* We must squash the PSTATE.SS bit to zero unless both of the
979 * 1. debug exceptions are currently disabled
980 * 2. singlestep will be active in the EL we return to
981 * We check 1 here and 2 after we've done the pstate/cpsr write() to
982 * transition to the EL we're going to.
984 if (arm_generate_debug_exceptions(env
)) {
988 new_el
= el_from_spsr(spsr
);
993 || (new_el
== 2 && !arm_feature(env
, ARM_FEATURE_EL2
))) {
994 /* Disallow return to an EL which is unimplemented or higher
995 * than the current one.
1000 if (new_el
!= 0 && arm_el_is_aa64(env
, new_el
) != return_to_aa64
) {
1001 /* Return to an EL which is configured for a different register width */
1002 goto illegal_return
;
1005 if (new_el
== 2 && arm_is_secure_below_el3(env
)) {
1006 /* Return to the non-existent secure-EL2 */
1007 goto illegal_return
;
1010 if (new_el
== 1 && (env
->cp15
.hcr_el2
& HCR_TGE
)
1011 && !arm_is_secure_below_el3(env
)) {
1012 goto illegal_return
;
1015 if (!return_to_aa64
) {
1017 /* We do a raw CPSR write because aarch64_sync_64_to_32()
1018 * will sort the register banks out for us, and we've already
1019 * caught all the bad-mode cases in el_from_spsr().
1021 cpsr_write(env
, spsr
, ~0, CPSRWriteRaw
);
1022 if (!arm_singlestep_active(env
)) {
1023 env
->uncached_cpsr
&= ~PSTATE_SS
;
1025 aarch64_sync_64_to_32(env
);
1027 if (spsr
& CPSR_T
) {
1028 env
->regs
[15] = env
->elr_el
[cur_el
] & ~0x1;
1030 env
->regs
[15] = env
->elr_el
[cur_el
] & ~0x3;
1032 qemu_log_mask(CPU_LOG_INT
, "Exception return from AArch64 EL%d to "
1033 "AArch32 EL%d PC 0x%" PRIx32
"\n",
1034 cur_el
, new_el
, env
->regs
[15]);
1037 pstate_write(env
, spsr
);
1038 if (!arm_singlestep_active(env
)) {
1039 env
->pstate
&= ~PSTATE_SS
;
1041 aarch64_restore_sp(env
, new_el
);
1042 env
->pc
= env
->elr_el
[cur_el
];
1043 qemu_log_mask(CPU_LOG_INT
, "Exception return from AArch64 EL%d to "
1044 "AArch64 EL%d PC 0x%" PRIx64
"\n",
1045 cur_el
, new_el
, env
->pc
);
1048 qemu_mutex_lock_iothread();
1049 arm_call_el_change_hook(arm_env_get_cpu(env
));
1050 qemu_mutex_unlock_iothread();
1055 /* Illegal return events of various kinds have architecturally
1056 * mandated behaviour:
1057 * restore NZCV and DAIF from SPSR_ELx
1059 * restore PC from ELR_ELx
1060 * no change to exception level, execution state or stack pointer
1062 env
->pstate
|= PSTATE_IL
;
1063 env
->pc
= env
->elr_el
[cur_el
];
1064 spsr
&= PSTATE_NZCV
| PSTATE_DAIF
;
1065 spsr
|= pstate_read(env
) & ~(PSTATE_NZCV
| PSTATE_DAIF
);
1066 pstate_write(env
, spsr
);
1067 if (!arm_singlestep_active(env
)) {
1068 env
->pstate
&= ~PSTATE_SS
;
1070 qemu_log_mask(LOG_GUEST_ERROR
, "Illegal exception return at EL%d: "
1071 "resuming execution at 0x%" PRIx64
"\n", cur_el
, env
->pc
);
1074 /* Return true if the linked breakpoint entry lbn passes its checks */
1075 static bool linked_bp_matches(ARMCPU
*cpu
, int lbn
)
1077 CPUARMState
*env
= &cpu
->env
;
1078 uint64_t bcr
= env
->cp15
.dbgbcr
[lbn
];
1079 int brps
= extract32(cpu
->dbgdidr
, 24, 4);
1080 int ctx_cmps
= extract32(cpu
->dbgdidr
, 20, 4);
1082 uint32_t contextidr
;
1084 /* Links to unimplemented or non-context aware breakpoints are
1085 * CONSTRAINED UNPREDICTABLE: either behave as if disabled, or
1086 * as if linked to an UNKNOWN context-aware breakpoint (in which
1087 * case DBGWCR<n>_EL1.LBN must indicate that breakpoint).
1088 * We choose the former.
1090 if (lbn
> brps
|| lbn
< (brps
- ctx_cmps
)) {
1094 bcr
= env
->cp15
.dbgbcr
[lbn
];
1096 if (extract64(bcr
, 0, 1) == 0) {
1097 /* Linked breakpoint disabled : generate no events */
1101 bt
= extract64(bcr
, 20, 4);
1103 /* We match the whole register even if this is AArch32 using the
1104 * short descriptor format (in which case it holds both PROCID and ASID),
1105 * since we don't implement the optional v7 context ID masking.
1107 contextidr
= extract64(env
->cp15
.contextidr_el
[1], 0, 32);
1110 case 3: /* linked context ID match */
1111 if (arm_current_el(env
) > 1) {
1112 /* Context matches never fire in EL2 or (AArch64) EL3 */
1115 return (contextidr
== extract64(env
->cp15
.dbgbvr
[lbn
], 0, 32));
1116 case 5: /* linked address mismatch (reserved in AArch64) */
1117 case 9: /* linked VMID match (reserved if no EL2) */
1118 case 11: /* linked context ID and VMID match (reserved if no EL2) */
1120 /* Links to Unlinked context breakpoints must generate no
1121 * events; we choose to do the same for reserved values too.
1129 static bool bp_wp_matches(ARMCPU
*cpu
, int n
, bool is_wp
)
1131 CPUARMState
*env
= &cpu
->env
;
1133 int pac
, hmc
, ssc
, wt
, lbn
;
1134 /* Note that for watchpoints the check is against the CPU security
1135 * state, not the S/NS attribute on the offending data access.
1137 bool is_secure
= arm_is_secure(env
);
1138 int access_el
= arm_current_el(env
);
1141 CPUWatchpoint
*wp
= env
->cpu_watchpoint
[n
];
1143 if (!wp
|| !(wp
->flags
& BP_WATCHPOINT_HIT
)) {
1146 cr
= env
->cp15
.dbgwcr
[n
];
1147 if (wp
->hitattrs
.user
) {
1148 /* The LDRT/STRT/LDT/STT "unprivileged access" instructions should
1149 * match watchpoints as if they were accesses done at EL0, even if
1150 * the CPU is at EL1 or higher.
1155 uint64_t pc
= is_a64(env
) ? env
->pc
: env
->regs
[15];
1157 if (!env
->cpu_breakpoint
[n
] || env
->cpu_breakpoint
[n
]->pc
!= pc
) {
1160 cr
= env
->cp15
.dbgbcr
[n
];
1162 /* The WATCHPOINT_HIT flag guarantees us that the watchpoint is
1163 * enabled and that the address and access type match; for breakpoints
1164 * we know the address matched; check the remaining fields, including
1165 * linked breakpoints. We rely on WCR and BCR having the same layout
1166 * for the LBN, SSC, HMC, PAC/PMC and is-linked fields.
1167 * Note that some combinations of {PAC, HMC, SSC} are reserved and
1168 * must act either like some valid combination or as if the watchpoint
1169 * were disabled. We choose the former, and use this together with
1170 * the fact that EL3 must always be Secure and EL2 must always be
1171 * Non-Secure to simplify the code slightly compared to the full
1172 * table in the ARM ARM.
1174 pac
= extract64(cr
, 1, 2);
1175 hmc
= extract64(cr
, 13, 1);
1176 ssc
= extract64(cr
, 14, 2);
1194 switch (access_el
) {
1202 if (extract32(pac
, 0, 1) == 0) {
1207 if (extract32(pac
, 1, 1) == 0) {
1212 g_assert_not_reached();
1215 wt
= extract64(cr
, 20, 1);
1216 lbn
= extract64(cr
, 16, 4);
1218 if (wt
&& !linked_bp_matches(cpu
, lbn
)) {
1225 static bool check_watchpoints(ARMCPU
*cpu
)
1227 CPUARMState
*env
= &cpu
->env
;
1230 /* If watchpoints are disabled globally or we can't take debug
1231 * exceptions here then watchpoint firings are ignored.
1233 if (extract32(env
->cp15
.mdscr_el1
, 15, 1) == 0
1234 || !arm_generate_debug_exceptions(env
)) {
1238 for (n
= 0; n
< ARRAY_SIZE(env
->cpu_watchpoint
); n
++) {
1239 if (bp_wp_matches(cpu
, n
, true)) {
1246 static bool check_breakpoints(ARMCPU
*cpu
)
1248 CPUARMState
*env
= &cpu
->env
;
1251 /* If breakpoints are disabled globally or we can't take debug
1252 * exceptions here then breakpoint firings are ignored.
1254 if (extract32(env
->cp15
.mdscr_el1
, 15, 1) == 0
1255 || !arm_generate_debug_exceptions(env
)) {
1259 for (n
= 0; n
< ARRAY_SIZE(env
->cpu_breakpoint
); n
++) {
1260 if (bp_wp_matches(cpu
, n
, false)) {
1267 void HELPER(check_breakpoints
)(CPUARMState
*env
)
1269 ARMCPU
*cpu
= arm_env_get_cpu(env
);
1271 if (check_breakpoints(cpu
)) {
1272 HELPER(exception_internal(env
, EXCP_DEBUG
));
1276 bool arm_debug_check_watchpoint(CPUState
*cs
, CPUWatchpoint
*wp
)
1278 /* Called by core code when a CPU watchpoint fires; need to check if this
1279 * is also an architectural watchpoint match.
1281 ARMCPU
*cpu
= ARM_CPU(cs
);
1283 return check_watchpoints(cpu
);
1286 vaddr
arm_adjust_watchpoint_address(CPUState
*cs
, vaddr addr
, int len
)
1288 ARMCPU
*cpu
= ARM_CPU(cs
);
1289 CPUARMState
*env
= &cpu
->env
;
1291 /* In BE32 system mode, target memory is stored byteswapped (on a
1292 * little-endian host system), and by the time we reach here (via an
1293 * opcode helper) the addresses of subword accesses have been adjusted
1294 * to account for that, which means that watchpoints will not match.
1295 * Undo the adjustment here.
1297 if (arm_sctlr_b(env
)) {
1300 } else if (len
== 2) {
1308 void arm_debug_excp_handler(CPUState
*cs
)
1310 /* Called by core code when a watchpoint or breakpoint fires;
1311 * need to check which one and raise the appropriate exception.
1313 ARMCPU
*cpu
= ARM_CPU(cs
);
1314 CPUARMState
*env
= &cpu
->env
;
1315 CPUWatchpoint
*wp_hit
= cs
->watchpoint_hit
;
1318 if (wp_hit
->flags
& BP_CPU
) {
1319 bool wnr
= (wp_hit
->flags
& BP_WATCHPOINT_HIT_WRITE
) != 0;
1320 bool same_el
= arm_debug_target_el(env
) == arm_current_el(env
);
1322 cs
->watchpoint_hit
= NULL
;
1324 if (extended_addresses_enabled(env
)) {
1325 env
->exception
.fsr
= (1 << 9) | 0x22;
1327 env
->exception
.fsr
= 0x2;
1329 env
->exception
.vaddress
= wp_hit
->hitaddr
;
1330 raise_exception(env
, EXCP_DATA_ABORT
,
1331 syn_watchpoint(same_el
, 0, wnr
),
1332 arm_debug_target_el(env
));
1335 uint64_t pc
= is_a64(env
) ? env
->pc
: env
->regs
[15];
1336 bool same_el
= (arm_debug_target_el(env
) == arm_current_el(env
));
1338 /* (1) GDB breakpoints should be handled first.
1339 * (2) Do not raise a CPU exception if no CPU breakpoint has fired,
1340 * since singlestep is also done by generating a debug internal
1343 if (cpu_breakpoint_test(cs
, pc
, BP_GDB
)
1344 || !cpu_breakpoint_test(cs
, pc
, BP_CPU
)) {
1348 if (extended_addresses_enabled(env
)) {
1349 env
->exception
.fsr
= (1 << 9) | 0x22;
1351 env
->exception
.fsr
= 0x2;
1353 /* FAR is UNKNOWN, so doesn't need setting */
1354 raise_exception(env
, EXCP_PREFETCH_ABORT
,
1355 syn_breakpoint(same_el
),
1356 arm_debug_target_el(env
));
1360 /* ??? Flag setting arithmetic is awkward because we need to do comparisons.
1361 The only way to do that in TCG is a conditional branch, which clobbers
1362 all our temporaries. For now implement these as helper functions. */
1364 /* Similarly for variable shift instructions. */
1366 uint32_t HELPER(shl_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
1368 int shift
= i
& 0xff;
1375 } else if (shift
!= 0) {
1376 env
->CF
= (x
>> (32 - shift
)) & 1;
1382 uint32_t HELPER(shr_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
1384 int shift
= i
& 0xff;
1387 env
->CF
= (x
>> 31) & 1;
1391 } else if (shift
!= 0) {
1392 env
->CF
= (x
>> (shift
- 1)) & 1;
1398 uint32_t HELPER(sar_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
1400 int shift
= i
& 0xff;
1402 env
->CF
= (x
>> 31) & 1;
1403 return (int32_t)x
>> 31;
1404 } else if (shift
!= 0) {
1405 env
->CF
= (x
>> (shift
- 1)) & 1;
1406 return (int32_t)x
>> shift
;
1411 uint32_t HELPER(ror_cc
)(CPUARMState
*env
, uint32_t x
, uint32_t i
)
1415 shift
= shift1
& 0x1f;
1418 env
->CF
= (x
>> 31) & 1;
1421 env
->CF
= (x
>> (shift
- 1)) & 1;
1422 return ((uint32_t)x
>> shift
) | (x
<< (32 - shift
));