1 #include "qemu/osdep.h"
2 #include "qemu-common.h"
6 #include "qemu/error-report.h"
7 #include "sysemu/kvm.h"
10 #include "migration/cpu.h"
12 static bool vfp_needed(void *opaque
)
15 CPUARMState
*env
= &cpu
->env
;
17 return arm_feature(env
, ARM_FEATURE_VFP
);
20 static int get_fpscr(QEMUFile
*f
, void *opaque
, size_t size
,
24 CPUARMState
*env
= &cpu
->env
;
25 uint32_t val
= qemu_get_be32(f
);
27 vfp_set_fpscr(env
, val
);
31 static int put_fpscr(QEMUFile
*f
, void *opaque
, size_t size
,
32 VMStateField
*field
, QJSON
*vmdesc
)
35 CPUARMState
*env
= &cpu
->env
;
37 qemu_put_be32(f
, vfp_get_fpscr(env
));
41 static const VMStateInfo vmstate_fpscr
= {
47 static const VMStateDescription vmstate_vfp
= {
50 .minimum_version_id
= 3,
52 .fields
= (VMStateField
[]) {
53 VMSTATE_FLOAT64_ARRAY(env
.vfp
.regs
, ARMCPU
, 64),
54 /* The xregs array is a little awkward because element 1 (FPSCR)
55 * requires a specific accessor, so we have to split it up in
58 VMSTATE_UINT32(env
.vfp
.xregs
[0], ARMCPU
),
59 VMSTATE_UINT32_SUB_ARRAY(env
.vfp
.xregs
, ARMCPU
, 2, 14),
63 .size
= sizeof(uint32_t),
64 .info
= &vmstate_fpscr
,
72 static bool iwmmxt_needed(void *opaque
)
75 CPUARMState
*env
= &cpu
->env
;
77 return arm_feature(env
, ARM_FEATURE_IWMMXT
);
80 static const VMStateDescription vmstate_iwmmxt
= {
83 .minimum_version_id
= 1,
84 .needed
= iwmmxt_needed
,
85 .fields
= (VMStateField
[]) {
86 VMSTATE_UINT64_ARRAY(env
.iwmmxt
.regs
, ARMCPU
, 16),
87 VMSTATE_UINT32_ARRAY(env
.iwmmxt
.cregs
, ARMCPU
, 16),
92 static bool m_needed(void *opaque
)
95 CPUARMState
*env
= &cpu
->env
;
97 return arm_feature(env
, ARM_FEATURE_M
);
100 static const VMStateDescription vmstate_m
= {
103 .minimum_version_id
= 4,
105 .fields
= (VMStateField
[]) {
106 VMSTATE_UINT32(env
.v7m
.vecbase
, ARMCPU
),
107 VMSTATE_UINT32(env
.v7m
.basepri
, ARMCPU
),
108 VMSTATE_UINT32(env
.v7m
.control
, ARMCPU
),
109 VMSTATE_UINT32(env
.v7m
.ccr
, ARMCPU
),
110 VMSTATE_UINT32(env
.v7m
.cfsr
, ARMCPU
),
111 VMSTATE_UINT32(env
.v7m
.hfsr
, ARMCPU
),
112 VMSTATE_UINT32(env
.v7m
.dfsr
, ARMCPU
),
113 VMSTATE_UINT32(env
.v7m
.mmfar
, ARMCPU
),
114 VMSTATE_UINT32(env
.v7m
.bfar
, ARMCPU
),
115 VMSTATE_UINT32(env
.v7m
.mpu_ctrl
, ARMCPU
),
116 VMSTATE_INT32(env
.v7m
.exception
, ARMCPU
),
117 VMSTATE_END_OF_LIST()
121 static bool thumb2ee_needed(void *opaque
)
123 ARMCPU
*cpu
= opaque
;
124 CPUARMState
*env
= &cpu
->env
;
126 return arm_feature(env
, ARM_FEATURE_THUMB2EE
);
129 static const VMStateDescription vmstate_thumb2ee
= {
130 .name
= "cpu/thumb2ee",
132 .minimum_version_id
= 1,
133 .needed
= thumb2ee_needed
,
134 .fields
= (VMStateField
[]) {
135 VMSTATE_UINT32(env
.teecr
, ARMCPU
),
136 VMSTATE_UINT32(env
.teehbr
, ARMCPU
),
137 VMSTATE_END_OF_LIST()
141 static bool pmsav7_needed(void *opaque
)
143 ARMCPU
*cpu
= opaque
;
144 CPUARMState
*env
= &cpu
->env
;
146 return arm_feature(env
, ARM_FEATURE_PMSA
) &&
147 arm_feature(env
, ARM_FEATURE_V7
);
150 static bool pmsav7_rgnr_vmstate_validate(void *opaque
, int version_id
)
152 ARMCPU
*cpu
= opaque
;
154 return cpu
->env
.pmsav7
.rnr
< cpu
->pmsav7_dregion
;
157 static const VMStateDescription vmstate_pmsav7
= {
158 .name
= "cpu/pmsav7",
160 .minimum_version_id
= 1,
161 .needed
= pmsav7_needed
,
162 .fields
= (VMStateField
[]) {
163 VMSTATE_VARRAY_UINT32(env
.pmsav7
.drbar
, ARMCPU
, pmsav7_dregion
, 0,
164 vmstate_info_uint32
, uint32_t),
165 VMSTATE_VARRAY_UINT32(env
.pmsav7
.drsr
, ARMCPU
, pmsav7_dregion
, 0,
166 vmstate_info_uint32
, uint32_t),
167 VMSTATE_VARRAY_UINT32(env
.pmsav7
.dracr
, ARMCPU
, pmsav7_dregion
, 0,
168 vmstate_info_uint32
, uint32_t),
169 VMSTATE_VALIDATE("rgnr is valid", pmsav7_rgnr_vmstate_validate
),
170 VMSTATE_END_OF_LIST()
174 static bool pmsav7_rnr_needed(void *opaque
)
176 ARMCPU
*cpu
= opaque
;
177 CPUARMState
*env
= &cpu
->env
;
179 /* For R profile cores pmsav7.rnr is migrated via the cpreg
180 * "RGNR" definition in helper.h. For M profile we have to
181 * migrate it separately.
183 return arm_feature(env
, ARM_FEATURE_M
);
186 static const VMStateDescription vmstate_pmsav7_rnr
= {
187 .name
= "cpu/pmsav7-rnr",
189 .minimum_version_id
= 1,
190 .needed
= pmsav7_rnr_needed
,
191 .fields
= (VMStateField
[]) {
192 VMSTATE_UINT32(env
.pmsav7
.rnr
, ARMCPU
),
193 VMSTATE_END_OF_LIST()
197 static int get_cpsr(QEMUFile
*f
, void *opaque
, size_t size
,
200 ARMCPU
*cpu
= opaque
;
201 CPUARMState
*env
= &cpu
->env
;
202 uint32_t val
= qemu_get_be32(f
);
204 env
->aarch64
= ((val
& PSTATE_nRW
) == 0);
207 pstate_write(env
, val
);
211 cpsr_write(env
, val
, 0xffffffff, CPSRWriteRaw
);
215 static int put_cpsr(QEMUFile
*f
, void *opaque
, size_t size
,
216 VMStateField
*field
, QJSON
*vmdesc
)
218 ARMCPU
*cpu
= opaque
;
219 CPUARMState
*env
= &cpu
->env
;
223 val
= pstate_read(env
);
225 val
= cpsr_read(env
);
228 qemu_put_be32(f
, val
);
232 static const VMStateInfo vmstate_cpsr
= {
238 static int get_power(QEMUFile
*f
, void *opaque
, size_t size
,
241 ARMCPU
*cpu
= opaque
;
242 bool powered_off
= qemu_get_byte(f
);
243 cpu
->power_state
= powered_off
? PSCI_OFF
: PSCI_ON
;
247 static int put_power(QEMUFile
*f
, void *opaque
, size_t size
,
248 VMStateField
*field
, QJSON
*vmdesc
)
250 ARMCPU
*cpu
= opaque
;
252 /* Migration should never happen while we transition power states */
254 if (cpu
->power_state
== PSCI_ON
||
255 cpu
->power_state
== PSCI_OFF
) {
256 bool powered_off
= (cpu
->power_state
== PSCI_OFF
) ? true : false;
257 qemu_put_byte(f
, powered_off
);
264 static const VMStateInfo vmstate_powered_off
= {
265 .name
= "powered_off",
270 static void cpu_pre_save(void *opaque
)
272 ARMCPU
*cpu
= opaque
;
275 if (!write_kvmstate_to_list(cpu
)) {
276 /* This should never fail */
280 if (!write_cpustate_to_list(cpu
)) {
281 /* This should never fail. */
286 cpu
->cpreg_vmstate_array_len
= cpu
->cpreg_array_len
;
287 memcpy(cpu
->cpreg_vmstate_indexes
, cpu
->cpreg_indexes
,
288 cpu
->cpreg_array_len
* sizeof(uint64_t));
289 memcpy(cpu
->cpreg_vmstate_values
, cpu
->cpreg_values
,
290 cpu
->cpreg_array_len
* sizeof(uint64_t));
293 static int cpu_post_load(void *opaque
, int version_id
)
295 ARMCPU
*cpu
= opaque
;
298 /* Update the values list from the incoming migration data.
299 * Anything in the incoming data which we don't know about is
300 * a migration failure; anything we know about but the incoming
301 * data doesn't specify retains its current (reset) value.
302 * The indexes list remains untouched -- we only inspect the
303 * incoming migration index list so we can match the values array
304 * entries with the right slots in our own values array.
307 for (i
= 0, v
= 0; i
< cpu
->cpreg_array_len
308 && v
< cpu
->cpreg_vmstate_array_len
; i
++) {
309 if (cpu
->cpreg_vmstate_indexes
[v
] > cpu
->cpreg_indexes
[i
]) {
310 /* register in our list but not incoming : skip it */
313 if (cpu
->cpreg_vmstate_indexes
[v
] < cpu
->cpreg_indexes
[i
]) {
314 /* register in their list but not ours: fail migration */
317 /* matching register, copy the value over */
318 cpu
->cpreg_values
[i
] = cpu
->cpreg_vmstate_values
[v
];
323 if (!write_list_to_kvmstate(cpu
, KVM_PUT_FULL_STATE
)) {
326 /* Note that it's OK for the TCG side not to know about
327 * every register in the list; KVM is authoritative if
330 write_list_to_cpustate(cpu
);
332 if (!write_list_to_cpustate(cpu
)) {
337 hw_breakpoint_update_all(cpu
);
338 hw_watchpoint_update_all(cpu
);
343 const VMStateDescription vmstate_arm_cpu
= {
346 .minimum_version_id
= 22,
347 .pre_save
= cpu_pre_save
,
348 .post_load
= cpu_post_load
,
349 .fields
= (VMStateField
[]) {
350 VMSTATE_UINT32_ARRAY(env
.regs
, ARMCPU
, 16),
351 VMSTATE_UINT64_ARRAY(env
.xregs
, ARMCPU
, 32),
352 VMSTATE_UINT64(env
.pc
, ARMCPU
),
356 .size
= sizeof(uint32_t),
357 .info
= &vmstate_cpsr
,
361 VMSTATE_UINT32(env
.spsr
, ARMCPU
),
362 VMSTATE_UINT64_ARRAY(env
.banked_spsr
, ARMCPU
, 8),
363 VMSTATE_UINT32_ARRAY(env
.banked_r13
, ARMCPU
, 8),
364 VMSTATE_UINT32_ARRAY(env
.banked_r14
, ARMCPU
, 8),
365 VMSTATE_UINT32_ARRAY(env
.usr_regs
, ARMCPU
, 5),
366 VMSTATE_UINT32_ARRAY(env
.fiq_regs
, ARMCPU
, 5),
367 VMSTATE_UINT64_ARRAY(env
.elr_el
, ARMCPU
, 4),
368 VMSTATE_UINT64_ARRAY(env
.sp_el
, ARMCPU
, 4),
369 /* The length-check must come before the arrays to avoid
370 * incoming data possibly overflowing the array.
372 VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len
, ARMCPU
),
373 VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes
, ARMCPU
,
374 cpreg_vmstate_array_len
,
375 0, vmstate_info_uint64
, uint64_t),
376 VMSTATE_VARRAY_INT32(cpreg_vmstate_values
, ARMCPU
,
377 cpreg_vmstate_array_len
,
378 0, vmstate_info_uint64
, uint64_t),
379 VMSTATE_UINT64(env
.exclusive_addr
, ARMCPU
),
380 VMSTATE_UINT64(env
.exclusive_val
, ARMCPU
),
381 VMSTATE_UINT64(env
.exclusive_high
, ARMCPU
),
382 VMSTATE_UINT64(env
.features
, ARMCPU
),
383 VMSTATE_UINT32(env
.exception
.syndrome
, ARMCPU
),
384 VMSTATE_UINT32(env
.exception
.fsr
, ARMCPU
),
385 VMSTATE_UINT64(env
.exception
.vaddress
, ARMCPU
),
386 VMSTATE_TIMER_PTR(gt_timer
[GTIMER_PHYS
], ARMCPU
),
387 VMSTATE_TIMER_PTR(gt_timer
[GTIMER_VIRT
], ARMCPU
),
389 .name
= "power_state",
391 .size
= sizeof(bool),
392 .info
= &vmstate_powered_off
,
396 VMSTATE_END_OF_LIST()
398 .subsections
= (const VMStateDescription
*[]) {
403 /* pmsav7_rnr must come before pmsav7 so that we have the
404 * region number before we test it in the VMSTATE_VALIDATE