2 * QEMU ARM CPU -- internal functions and types
4 * Copyright (c) 2014 Linaro Ltd
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
20 * This header defines functions, types, etc which need to be shared
21 * between different source files within target/arm/ but which are
22 * private to it and not required by the rest of QEMU.
25 #ifndef TARGET_ARM_INTERNALS_H
26 #define TARGET_ARM_INTERNALS_H
28 #include "hw/registerfields.h"
30 /* register banks for CPU modes */
40 static inline bool excp_is_internal(int excp
)
42 /* Return true if this exception number represents a QEMU-internal
43 * exception that will not be passed to the guest.
45 return excp
== EXCP_INTERRUPT
48 || excp
== EXCP_HALTED
49 || excp
== EXCP_EXCEPTION_EXIT
50 || excp
== EXCP_KERNEL_TRAP
51 || excp
== EXCP_SEMIHOST
;
54 /* Scale factor for generic timers, ie number of ns per tick.
55 * This gives a 62.5MHz timer.
57 #define GTIMER_SCALE 16
59 /* Bit definitions for the v7M CONTROL register */
60 FIELD(V7M_CONTROL
, NPRIV
, 0, 1)
61 FIELD(V7M_CONTROL
, SPSEL
, 1, 1)
62 FIELD(V7M_CONTROL
, FPCA
, 2, 1)
65 * For AArch64, map a given EL to an index in the banked_spsr array.
66 * Note that this mapping and the AArch32 mapping defined in bank_number()
67 * must agree such that the AArch64<->AArch32 SPSRs have the architecturally
68 * mandated mapping between each other.
70 static inline unsigned int aarch64_banked_spsr_index(unsigned int el
)
72 static const unsigned int map
[4] = {
73 [1] = BANK_SVC
, /* EL1. */
74 [2] = BANK_HYP
, /* EL2. */
75 [3] = BANK_MON
, /* EL3. */
77 assert(el
>= 1 && el
<= 3);
81 /* Map CPU modes onto saved register banks. */
82 static inline int bank_number(int mode
)
85 case ARM_CPU_MODE_USR
:
86 case ARM_CPU_MODE_SYS
:
88 case ARM_CPU_MODE_SVC
:
90 case ARM_CPU_MODE_ABT
:
92 case ARM_CPU_MODE_UND
:
94 case ARM_CPU_MODE_IRQ
:
96 case ARM_CPU_MODE_FIQ
:
98 case ARM_CPU_MODE_HYP
:
100 case ARM_CPU_MODE_MON
:
103 g_assert_not_reached();
106 void switch_mode(CPUARMState
*, int);
107 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
);
108 void arm_translate_init(void);
110 enum arm_fprounding
{
119 int arm_rmode_to_sf(int rmode
);
121 static inline void aarch64_save_sp(CPUARMState
*env
, int el
)
123 if (env
->pstate
& PSTATE_SP
) {
124 env
->sp_el
[el
] = env
->xregs
[31];
126 env
->sp_el
[0] = env
->xregs
[31];
130 static inline void aarch64_restore_sp(CPUARMState
*env
, int el
)
132 if (env
->pstate
& PSTATE_SP
) {
133 env
->xregs
[31] = env
->sp_el
[el
];
135 env
->xregs
[31] = env
->sp_el
[0];
139 static inline void update_spsel(CPUARMState
*env
, uint32_t imm
)
141 unsigned int cur_el
= arm_current_el(env
);
142 /* Update PSTATE SPSel bit; this requires us to update the
143 * working stack pointer in xregs[31].
145 if (!((imm
^ env
->pstate
) & PSTATE_SP
)) {
148 aarch64_save_sp(env
, cur_el
);
149 env
->pstate
= deposit32(env
->pstate
, 0, 1, imm
);
151 /* We rely on illegal updates to SPsel from EL0 to get trapped
152 * at translation time.
154 assert(cur_el
>= 1 && cur_el
<= 3);
155 aarch64_restore_sp(env
, cur_el
);
162 * Returns the implementation defined bit-width of physical addresses.
163 * The ARMv8 reference manuals refer to this as PAMax().
165 static inline unsigned int arm_pamax(ARMCPU
*cpu
)
167 static const unsigned int pamax_map
[] = {
175 unsigned int parange
= extract32(cpu
->id_aa64mmfr0
, 0, 4);
177 /* id_aa64mmfr0 is a read-only register so values outside of the
178 * supported mappings can be considered an implementation error. */
179 assert(parange
< ARRAY_SIZE(pamax_map
));
180 return pamax_map
[parange
];
183 /* Return true if extended addresses are enabled.
184 * This is always the case if our translation regime is 64 bit,
185 * but depends on TTBCR.EAE for 32 bit.
187 static inline bool extended_addresses_enabled(CPUARMState
*env
)
189 TCR
*tcr
= &env
->cp15
.tcr_el
[arm_is_secure(env
) ? 3 : 1];
190 return arm_el_is_aa64(env
, 1) ||
191 (arm_feature(env
, ARM_FEATURE_LPAE
) && (tcr
->raw_tcr
& TTBCR_EAE
));
194 /* Valid Syndrome Register EC field values */
195 enum arm_exception_class
{
196 EC_UNCATEGORIZED
= 0x00,
198 EC_CP15RTTRAP
= 0x03,
199 EC_CP15RRTTRAP
= 0x04,
200 EC_CP14RTTRAP
= 0x05,
201 EC_CP14DTTRAP
= 0x06,
202 EC_ADVSIMDFPACCESSTRAP
= 0x07,
204 EC_CP14RRTTRAP
= 0x0c,
205 EC_ILLEGALSTATE
= 0x0e,
212 EC_SYSTEMREGISTERTRAP
= 0x18,
214 EC_INSNABORT_SAME_EL
= 0x21,
215 EC_PCALIGNMENT
= 0x22,
217 EC_DATAABORT_SAME_EL
= 0x25,
218 EC_SPALIGNMENT
= 0x26,
219 EC_AA32_FPTRAP
= 0x28,
220 EC_AA64_FPTRAP
= 0x2c,
222 EC_BREAKPOINT
= 0x30,
223 EC_BREAKPOINT_SAME_EL
= 0x31,
224 EC_SOFTWARESTEP
= 0x32,
225 EC_SOFTWARESTEP_SAME_EL
= 0x33,
226 EC_WATCHPOINT
= 0x34,
227 EC_WATCHPOINT_SAME_EL
= 0x35,
229 EC_VECTORCATCH
= 0x3a,
233 #define ARM_EL_EC_SHIFT 26
234 #define ARM_EL_IL_SHIFT 25
235 #define ARM_EL_ISV_SHIFT 24
236 #define ARM_EL_IL (1 << ARM_EL_IL_SHIFT)
237 #define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT)
239 /* Utility functions for constructing various kinds of syndrome value.
240 * Note that in general we follow the AArch64 syndrome values; in a
241 * few cases the value in HSR for exceptions taken to AArch32 Hyp
242 * mode differs slightly, so if we ever implemented Hyp mode then the
243 * syndrome value would need some massaging on exception entry.
244 * (One example of this is that AArch64 defaults to IL bit set for
245 * exceptions which don't specifically indicate information about the
246 * trapping instruction, whereas AArch32 defaults to IL bit clear.)
248 static inline uint32_t syn_uncategorized(void)
250 return (EC_UNCATEGORIZED
<< ARM_EL_EC_SHIFT
) | ARM_EL_IL
;
253 static inline uint32_t syn_aa64_svc(uint32_t imm16
)
255 return (EC_AA64_SVC
<< ARM_EL_EC_SHIFT
) | ARM_EL_IL
| (imm16
& 0xffff);
258 static inline uint32_t syn_aa64_hvc(uint32_t imm16
)
260 return (EC_AA64_HVC
<< ARM_EL_EC_SHIFT
) | ARM_EL_IL
| (imm16
& 0xffff);
263 static inline uint32_t syn_aa64_smc(uint32_t imm16
)
265 return (EC_AA64_SMC
<< ARM_EL_EC_SHIFT
) | ARM_EL_IL
| (imm16
& 0xffff);
268 static inline uint32_t syn_aa32_svc(uint32_t imm16
, bool is_16bit
)
270 return (EC_AA32_SVC
<< ARM_EL_EC_SHIFT
) | (imm16
& 0xffff)
271 | (is_16bit
? 0 : ARM_EL_IL
);
274 static inline uint32_t syn_aa32_hvc(uint32_t imm16
)
276 return (EC_AA32_HVC
<< ARM_EL_EC_SHIFT
) | ARM_EL_IL
| (imm16
& 0xffff);
279 static inline uint32_t syn_aa32_smc(void)
281 return (EC_AA32_SMC
<< ARM_EL_EC_SHIFT
) | ARM_EL_IL
;
284 static inline uint32_t syn_aa64_bkpt(uint32_t imm16
)
286 return (EC_AA64_BKPT
<< ARM_EL_EC_SHIFT
) | ARM_EL_IL
| (imm16
& 0xffff);
289 static inline uint32_t syn_aa32_bkpt(uint32_t imm16
, bool is_16bit
)
291 return (EC_AA32_BKPT
<< ARM_EL_EC_SHIFT
) | (imm16
& 0xffff)
292 | (is_16bit
? 0 : ARM_EL_IL
);
295 static inline uint32_t syn_aa64_sysregtrap(int op0
, int op1
, int op2
,
296 int crn
, int crm
, int rt
,
299 return (EC_SYSTEMREGISTERTRAP
<< ARM_EL_EC_SHIFT
) | ARM_EL_IL
300 | (op0
<< 20) | (op2
<< 17) | (op1
<< 14) | (crn
<< 10) | (rt
<< 5)
301 | (crm
<< 1) | isread
;
304 static inline uint32_t syn_cp14_rt_trap(int cv
, int cond
, int opc1
, int opc2
,
305 int crn
, int crm
, int rt
, int isread
,
308 return (EC_CP14RTTRAP
<< ARM_EL_EC_SHIFT
)
309 | (is_16bit
? 0 : ARM_EL_IL
)
310 | (cv
<< 24) | (cond
<< 20) | (opc2
<< 17) | (opc1
<< 14)
311 | (crn
<< 10) | (rt
<< 5) | (crm
<< 1) | isread
;
314 static inline uint32_t syn_cp15_rt_trap(int cv
, int cond
, int opc1
, int opc2
,
315 int crn
, int crm
, int rt
, int isread
,
318 return (EC_CP15RTTRAP
<< ARM_EL_EC_SHIFT
)
319 | (is_16bit
? 0 : ARM_EL_IL
)
320 | (cv
<< 24) | (cond
<< 20) | (opc2
<< 17) | (opc1
<< 14)
321 | (crn
<< 10) | (rt
<< 5) | (crm
<< 1) | isread
;
324 static inline uint32_t syn_cp14_rrt_trap(int cv
, int cond
, int opc1
, int crm
,
325 int rt
, int rt2
, int isread
,
328 return (EC_CP14RRTTRAP
<< ARM_EL_EC_SHIFT
)
329 | (is_16bit
? 0 : ARM_EL_IL
)
330 | (cv
<< 24) | (cond
<< 20) | (opc1
<< 16)
331 | (rt2
<< 10) | (rt
<< 5) | (crm
<< 1) | isread
;
334 static inline uint32_t syn_cp15_rrt_trap(int cv
, int cond
, int opc1
, int crm
,
335 int rt
, int rt2
, int isread
,
338 return (EC_CP15RRTTRAP
<< ARM_EL_EC_SHIFT
)
339 | (is_16bit
? 0 : ARM_EL_IL
)
340 | (cv
<< 24) | (cond
<< 20) | (opc1
<< 16)
341 | (rt2
<< 10) | (rt
<< 5) | (crm
<< 1) | isread
;
344 static inline uint32_t syn_fp_access_trap(int cv
, int cond
, bool is_16bit
)
346 return (EC_ADVSIMDFPACCESSTRAP
<< ARM_EL_EC_SHIFT
)
347 | (is_16bit
? 0 : ARM_EL_IL
)
348 | (cv
<< 24) | (cond
<< 20);
351 static inline uint32_t syn_insn_abort(int same_el
, int ea
, int s1ptw
, int fsc
)
353 return (EC_INSNABORT
<< ARM_EL_EC_SHIFT
) | (same_el
<< ARM_EL_EC_SHIFT
)
354 | ARM_EL_IL
| (ea
<< 9) | (s1ptw
<< 7) | fsc
;
357 static inline uint32_t syn_data_abort_no_iss(int same_el
,
358 int ea
, int cm
, int s1ptw
,
361 return (EC_DATAABORT
<< ARM_EL_EC_SHIFT
) | (same_el
<< ARM_EL_EC_SHIFT
)
363 | (ea
<< 9) | (cm
<< 8) | (s1ptw
<< 7) | (wnr
<< 6) | fsc
;
366 static inline uint32_t syn_data_abort_with_iss(int same_el
,
367 int sas
, int sse
, int srt
,
369 int ea
, int cm
, int s1ptw
,
373 return (EC_DATAABORT
<< ARM_EL_EC_SHIFT
) | (same_el
<< ARM_EL_EC_SHIFT
)
374 | (is_16bit
? 0 : ARM_EL_IL
)
375 | ARM_EL_ISV
| (sas
<< 22) | (sse
<< 21) | (srt
<< 16)
376 | (sf
<< 15) | (ar
<< 14)
377 | (ea
<< 9) | (cm
<< 8) | (s1ptw
<< 7) | (wnr
<< 6) | fsc
;
380 static inline uint32_t syn_swstep(int same_el
, int isv
, int ex
)
382 return (EC_SOFTWARESTEP
<< ARM_EL_EC_SHIFT
) | (same_el
<< ARM_EL_EC_SHIFT
)
383 | ARM_EL_IL
| (isv
<< 24) | (ex
<< 6) | 0x22;
386 static inline uint32_t syn_watchpoint(int same_el
, int cm
, int wnr
)
388 return (EC_WATCHPOINT
<< ARM_EL_EC_SHIFT
) | (same_el
<< ARM_EL_EC_SHIFT
)
389 | ARM_EL_IL
| (cm
<< 8) | (wnr
<< 6) | 0x22;
392 static inline uint32_t syn_breakpoint(int same_el
)
394 return (EC_BREAKPOINT
<< ARM_EL_EC_SHIFT
) | (same_el
<< ARM_EL_EC_SHIFT
)
398 static inline uint32_t syn_wfx(int cv
, int cond
, int ti
)
400 return (EC_WFX_TRAP
<< ARM_EL_EC_SHIFT
) |
401 (cv
<< 24) | (cond
<< 20) | ti
;
404 /* Update a QEMU watchpoint based on the information the guest has set in the
405 * DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers.
407 void hw_watchpoint_update(ARMCPU
*cpu
, int n
);
408 /* Update the QEMU watchpoints for every guest watchpoint. This does a
409 * complete delete-and-reinstate of the QEMU watchpoint list and so is
410 * suitable for use after migration or on reset.
412 void hw_watchpoint_update_all(ARMCPU
*cpu
);
413 /* Update a QEMU breakpoint based on the information the guest has set in the
414 * DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers.
416 void hw_breakpoint_update(ARMCPU
*cpu
, int n
);
417 /* Update the QEMU breakpoints for every guest breakpoint. This does a
418 * complete delete-and-reinstate of the QEMU breakpoint list and so is
419 * suitable for use after migration or on reset.
421 void hw_breakpoint_update_all(ARMCPU
*cpu
);
423 /* Callback function for checking if a watchpoint should trigger. */
424 bool arm_debug_check_watchpoint(CPUState
*cs
, CPUWatchpoint
*wp
);
426 /* Adjust addresses (in BE32 mode) before testing against watchpoint
429 vaddr
arm_adjust_watchpoint_address(CPUState
*cs
, vaddr addr
, int len
);
431 /* Callback function for when a watchpoint or breakpoint triggers. */
432 void arm_debug_excp_handler(CPUState
*cs
);
434 #ifdef CONFIG_USER_ONLY
435 static inline bool arm_is_psci_call(ARMCPU
*cpu
, int excp_type
)
440 /* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */
441 bool arm_is_psci_call(ARMCPU
*cpu
, int excp_type
);
442 /* Actually handle a PSCI call */
443 void arm_handle_psci_call(ARMCPU
*cpu
);
447 * ARMMMUFaultInfo: Information describing an ARM MMU Fault
448 * @s2addr: Address that caused a fault at stage 2
449 * @stage2: True if we faulted at stage 2
450 * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk
452 typedef struct ARMMMUFaultInfo ARMMMUFaultInfo
;
453 struct ARMMMUFaultInfo
{
459 /* Do a page table walk and add page to TLB if possible */
460 bool arm_tlb_fill(CPUState
*cpu
, vaddr address
, int rw
, int mmu_idx
,
461 uint32_t *fsr
, ARMMMUFaultInfo
*fi
);
463 /* Return true if the stage 1 translation regime is using LPAE format page
465 bool arm_s1_regime_using_lpae_format(CPUARMState
*env
, ARMMMUIdx mmu_idx
);
467 /* Raise a data fault alignment exception for the specified virtual address */
468 void arm_cpu_do_unaligned_access(CPUState
*cs
, vaddr vaddr
,
469 MMUAccessType access_type
,
470 int mmu_idx
, uintptr_t retaddr
);
472 /* Call the EL change hook if one has been registered */
473 static inline void arm_call_el_change_hook(ARMCPU
*cpu
)
475 if (cpu
->el_change_hook
) {
476 cpu
->el_change_hook(cpu
, cpu
->el_change_hook_opaque
);