hw/ppc/ppc4xx_pci.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License, version 2, as
   4  * published by the Free Software Foundation.
   5  *
   6  * This program is distributed in the hope that it will be useful,
   7  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  * GNU General Public License for more details.
  10  *
  11  * You should have received a copy of the GNU General Public License
  12  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  13  *
  14  * Copyright IBM Corp. 2008
  15  *
  16  * Authors: Hollis Blanchard <hollisb@us.ibm.com>
  17  */
  18
  19 /* This file implements emulation of the 32-bit PCI controller found in some
  20  * 4xx SoCs, such as the 440EP. */
  21
  22 #include "hw/hw.h"
  23 #include "hw/ppc/ppc.h"
  24 #include "hw/ppc/ppc4xx.h"
  25 #include "hw/pci/pci.h"
  26 #include "hw/pci/pci_host.h"
  27 #include "exec/address-spaces.h"
  28
  29 #undef DEBUG
  30 #ifdef DEBUG
  31 #define DPRINTF(fmt, ...) do { printf(fmt, ## __VA_ARGS__); } while (0)
  32 #else
  33 #define DPRINTF(fmt, ...)
  34 #endif /* DEBUG */
  35
  36 struct PCIMasterMap {
  37     uint32_t la;
  38     uint32_t ma;
  39     uint32_t pcila;
  40     uint32_t pciha;
  41 };
  42
  43 struct PCITargetMap {
  44     uint32_t ms;
  45     uint32_t la;
  46 };
  47
  48 #define PPC4xx_PCI_HOST_BRIDGE(obj) \
  49     OBJECT_CHECK(PPC4xxPCIState, (obj), TYPE_PPC4xx_PCI_HOST_BRIDGE)
  50
  51 #define PPC4xx_PCI_NR_PMMS 3
  52 #define PPC4xx_PCI_NR_PTMS 2
  53
  54 struct PPC4xxPCIState {
  55     PCIHostState parent_obj;
  56
  57     struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS];
  58     struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS];
  59     qemu_irq irq[4];
  60
  61     MemoryRegion container;
  62     MemoryRegion iomem;
  63 };
  64 typedef struct PPC4xxPCIState PPC4xxPCIState;
  65
  66 #define PCIC0_CFGADDR       0x0
  67 #define PCIC0_CFGDATA       0x4
  68
  69 /* PLB Memory Map (PMM) registers specify which PLB addresses are translated to
  70  * PCI accesses. */
  71 #define PCIL0_PMM0LA        0x0
  72 #define PCIL0_PMM0MA        0x4
  73 #define PCIL0_PMM0PCILA     0x8
  74 #define PCIL0_PMM0PCIHA     0xc
  75 #define PCIL0_PMM1LA        0x10
  76 #define PCIL0_PMM1MA        0x14
  77 #define PCIL0_PMM1PCILA     0x18
  78 #define PCIL0_PMM1PCIHA     0x1c
  79 #define PCIL0_PMM2LA        0x20
  80 #define PCIL0_PMM2MA        0x24
  81 #define PCIL0_PMM2PCILA     0x28
  82 #define PCIL0_PMM2PCIHA     0x2c
  83
  84 /* PCI Target Map (PTM) registers specify which PCI addresses are translated to
  85  * PLB accesses. */
  86 #define PCIL0_PTM1MS        0x30
  87 #define PCIL0_PTM1LA        0x34
  88 #define PCIL0_PTM2MS        0x38
  89 #define PCIL0_PTM2LA        0x3c
  90 #define PCI_REG_BASE        0x800000
  91 #define PCI_REG_SIZE        0x40
  92
  93 #define PCI_ALL_SIZE        (PCI_REG_BASE + PCI_REG_SIZE)
  94
  95 static void ppc4xx_pci_reg_write4(void *opaque, hwaddr offset,
  96                                   uint64_t value, unsigned size)
  97 {
  98     struct PPC4xxPCIState *pci = opaque;
  99
 100     /* We ignore all target attempts at PCI configuration, effectively
 101      * assuming a bidirectional 1:1 mapping of PLB and PCI space. */
 102
 103     switch (offset) {
 104     case PCIL0_PMM0LA:
 105         pci->pmm[0].la = value;
 106         break;
 107     case PCIL0_PMM0MA:
 108         pci->pmm[0].ma = value;
 109         break;
 110     case PCIL0_PMM0PCIHA:
 111         pci->pmm[0].pciha = value;
 112         break;
 113     case PCIL0_PMM0PCILA:
 114         pci->pmm[0].pcila = value;
 115         break;
 116
 117     case PCIL0_PMM1LA:
 118         pci->pmm[1].la = value;
 119         break;
 120     case PCIL0_PMM1MA:
 121         pci->pmm[1].ma = value;
 122         break;
 123     case PCIL0_PMM1PCIHA:
 124         pci->pmm[1].pciha = value;
 125         break;
 126     case PCIL0_PMM1PCILA:
 127         pci->pmm[1].pcila = value;
 128         break;
 129
 130     case PCIL0_PMM2LA:
 131         pci->pmm[2].la = value;
 132         break;
 133     case PCIL0_PMM2MA:
 134         pci->pmm[2].ma = value;
 135         break;
 136     case PCIL0_PMM2PCIHA:
 137         pci->pmm[2].pciha = value;
 138         break;
 139     case PCIL0_PMM2PCILA:
 140         pci->pmm[2].pcila = value;
 141         break;
 142
 143     case PCIL0_PTM1MS:
 144         pci->ptm[0].ms = value;
 145         break;
 146     case PCIL0_PTM1LA:
 147         pci->ptm[0].la = value;
 148         break;
 149     case PCIL0_PTM2MS:
 150         pci->ptm[1].ms = value;
 151         break;
 152     case PCIL0_PTM2LA:
 153         pci->ptm[1].la = value;
 154         break;
 155
 156     default:
 157         printf("%s: unhandled PCI internal register 0x%lx\n", __func__,
 158                (unsigned long)offset);
 159         break;
 160     }
 161 }
 162
 163 static uint64_t ppc4xx_pci_reg_read4(void *opaque, hwaddr offset,
 164                                      unsigned size)
 165 {
 166     struct PPC4xxPCIState *pci = opaque;
 167     uint32_t value;
 168
 169     switch (offset) {
 170     case PCIL0_PMM0LA:
 171         value = pci->pmm[0].la;
 172         break;
 173     case PCIL0_PMM0MA:
 174         value = pci->pmm[0].ma;
 175         break;
 176     case PCIL0_PMM0PCIHA:
 177         value = pci->pmm[0].pciha;
 178         break;
 179     case PCIL0_PMM0PCILA:
 180         value = pci->pmm[0].pcila;
 181         break;
 182
 183     case PCIL0_PMM1LA:
 184         value = pci->pmm[1].la;
 185         break;
 186     case PCIL0_PMM1MA:
 187         value = pci->pmm[1].ma;
 188         break;
 189     case PCIL0_PMM1PCIHA:
 190         value = pci->pmm[1].pciha;
 191         break;
 192     case PCIL0_PMM1PCILA:
 193         value = pci->pmm[1].pcila;
 194         break;
 195
 196     case PCIL0_PMM2LA:
 197         value = pci->pmm[2].la;
 198         break;
 199     case PCIL0_PMM2MA:
 200         value = pci->pmm[2].ma;
 201         break;
 202     case PCIL0_PMM2PCIHA:
 203         value = pci->pmm[2].pciha;
 204         break;
 205     case PCIL0_PMM2PCILA:
 206         value = pci->pmm[2].pcila;
 207         break;
 208
 209     case PCIL0_PTM1MS:
 210         value = pci->ptm[0].ms;
 211         break;
 212     case PCIL0_PTM1LA:
 213         value = pci->ptm[0].la;
 214         break;
 215     case PCIL0_PTM2MS:
 216         value = pci->ptm[1].ms;
 217         break;
 218     case PCIL0_PTM2LA:
 219         value = pci->ptm[1].la;
 220         break;
 221
 222     default:
 223         printf("%s: invalid PCI internal register 0x%lx\n", __func__,
 224                (unsigned long)offset);
 225         value = 0;
 226     }
 227
 228     return value;
 229 }
 230
 231 static const MemoryRegionOps pci_reg_ops = {
 232     .read = ppc4xx_pci_reg_read4,
 233     .write = ppc4xx_pci_reg_write4,
 234     .endianness = DEVICE_LITTLE_ENDIAN,
 235 };
 236
 237 static void ppc4xx_pci_reset(void *opaque)
 238 {
 239     struct PPC4xxPCIState *pci = opaque;
 240
 241     memset(pci->pmm, 0, sizeof(pci->pmm));
 242     memset(pci->ptm, 0, sizeof(pci->ptm));
 243 }
 244
 245 /* On Bamboo, all pins from each slot are tied to a single board IRQ. This
 246  * may need further refactoring for other boards. */
 247 static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
 248 {
 249     int slot = pci_dev->devfn >> 3;
 250
 251     DPRINTF("%s: devfn %x irq %d -> %d\n", __func__,
 252             pci_dev->devfn, irq_num, slot);
 253
 254     return slot - 1;
 255 }
 256
 257 static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level)
 258 {
 259     qemu_irq *pci_irqs = opaque;
 260
 261     DPRINTF("%s: PCI irq %d\n", __func__, irq_num);
 262     if (irq_num < 0) {
 263         fprintf(stderr, "%s: PCI irq %d\n", __func__, irq_num);
 264         return;
 265     }
 266     qemu_set_irq(pci_irqs[irq_num], level);
 267 }
 268
 269 static const VMStateDescription vmstate_pci_master_map = {
 270     .name = "pci_master_map",
 271     .version_id = 0,
 272     .minimum_version_id = 0,
 273     .fields = (VMStateField[]) {
 274         VMSTATE_UINT32(la, struct PCIMasterMap),
 275         VMSTATE_UINT32(ma, struct PCIMasterMap),
 276         VMSTATE_UINT32(pcila, struct PCIMasterMap),
 277         VMSTATE_UINT32(pciha, struct PCIMasterMap),
 278         VMSTATE_END_OF_LIST()
 279     }
 280 };
 281
 282 static const VMStateDescription vmstate_pci_target_map = {
 283     .name = "pci_target_map",
 284     .version_id = 0,
 285     .minimum_version_id = 0,
 286     .fields = (VMStateField[]) {
 287         VMSTATE_UINT32(ms, struct PCITargetMap),
 288         VMSTATE_UINT32(la, struct PCITargetMap),
 289         VMSTATE_END_OF_LIST()
 290     }
 291 };
 292
 293 static const VMStateDescription vmstate_ppc4xx_pci = {
 294     .name = "ppc4xx_pci",
 295     .version_id = 1,
 296     .minimum_version_id = 1,
 297     .fields = (VMStateField[]) {
 298         VMSTATE_STRUCT_ARRAY(pmm, PPC4xxPCIState, PPC4xx_PCI_NR_PMMS, 1,
 299                              vmstate_pci_master_map,
 300                              struct PCIMasterMap),
 301         VMSTATE_STRUCT_ARRAY(ptm, PPC4xxPCIState, PPC4xx_PCI_NR_PTMS, 1,
 302                              vmstate_pci_target_map,
 303                              struct PCITargetMap),
 304         VMSTATE_END_OF_LIST()
 305     }
 306 };
 307
 308 /* XXX Interrupt acknowledge cycles not supported. */
 309 static int ppc4xx_pcihost_initfn(SysBusDevice *dev)
 310 {
 311     PPC4xxPCIState *s;
 312     PCIHostState *h;
 313     PCIBus *b;
 314     int i;
 315
 316     h = PCI_HOST_BRIDGE(dev);
 317     s = PPC4xx_PCI_HOST_BRIDGE(dev);
 318
 319     for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
 320         sysbus_init_irq(dev, &s->irq[i]);
 321     }
 322
 323     b = pci_register_bus(DEVICE(dev), NULL, ppc4xx_pci_set_irq,
 324                          ppc4xx_pci_map_irq, s->irq, get_system_memory(),
 325                          get_system_io(), 0, 4, TYPE_PCI_BUS);
 326     h->bus = b;
 327
 328     pci_create_simple(b, 0, "ppc4xx-host-bridge");
 329
 330     /* XXX split into 2 memory regions, one for config space, one for regs */
 331     memory_region_init(&s->container, OBJECT(s), "pci-container", PCI_ALL_SIZE);
 332     memory_region_init_io(&h->conf_mem, OBJECT(s), &pci_host_conf_le_ops, h,
 333                           "pci-conf-idx", 4);
 334     memory_region_init_io(&h->data_mem, OBJECT(s), &pci_host_data_le_ops, h,
 335                           "pci-conf-data", 4);
 336     memory_region_init_io(&s->iomem, OBJECT(s), &pci_reg_ops, s,
 337                           "pci.reg", PCI_REG_SIZE);
 338     memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem);
 339     memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem);
 340     memory_region_add_subregion(&s->container, PCI_REG_BASE, &s->iomem);
 341     sysbus_init_mmio(dev, &s->container);
 342     qemu_register_reset(ppc4xx_pci_reset, s);
 343
 344     return 0;
 345 }
 346
 347 static void ppc4xx_host_bridge_class_init(ObjectClass *klass, void *data)
 348 {
 349     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 350     DeviceClass *dc = DEVICE_CLASS(klass);
 351
 352     dc->desc        = "Host bridge";
 353     k->vendor_id    = PCI_VENDOR_ID_IBM;
 354     k->device_id    = PCI_DEVICE_ID_IBM_440GX;
 355     k->class_id     = PCI_CLASS_BRIDGE_OTHER;
 356     /*
 357      * PCI-facing part of the host bridge, not usable without the
 358      * host-facing part, which can't be device_add'ed, yet.
 359      */
 360     dc->cannot_instantiate_with_device_add_yet = true;
 361 }
 362
 363 static const TypeInfo ppc4xx_host_bridge_info = {
 364     .name          = "ppc4xx-host-bridge",
 365     .parent        = TYPE_PCI_DEVICE,
 366     .instance_size = sizeof(PCIDevice),
 367     .class_init    = ppc4xx_host_bridge_class_init,
 368 };
 369
 370 static void ppc4xx_pcihost_class_init(ObjectClass *klass, void *data)
 371 {
 372     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 373     DeviceClass *dc = DEVICE_CLASS(klass);
 374
 375     k->init = ppc4xx_pcihost_initfn;
 376     dc->vmsd = &vmstate_ppc4xx_pci;
 377 }
 378
 379 static const TypeInfo ppc4xx_pcihost_info = {
 380     .name          = TYPE_PPC4xx_PCI_HOST_BRIDGE,
 381     .parent        = TYPE_PCI_HOST_BRIDGE,
 382     .instance_size = sizeof(PPC4xxPCIState),
 383     .class_init    = ppc4xx_pcihost_class_init,
 384 };
 385
 386 static void ppc4xx_pci_register_types(void)
 387 {
 388     type_register_static(&ppc4xx_pcihost_info);
 389     type_register_static(&ppc4xx_host_bridge_info);
 390 }
 391
 392 type_init(ppc4xx_pci_register_types)